A clock optimization method and clock device

Abstract

The present application discloses a clock optimization method and a clock device, which obtains a target reference clock source signal; if the target reference clock source signal meets the target condition, the base station phase-locked loop is adjusted based on the target reference clock source signal to obtain a base station clock synchronization signal; if the target reference clock source signal does not meet the target condition, the clock source signal is obtained based on the clock holding module of the base station, and the clock holding module is a module that is tamed based on the base station clock synchronization signal when the target reference clock source signal meets the target condition; the clock source signal is input into the base station phase-locked loop to obtain the base station clock synchronization signal. The present application can perform clock calibration through the clock holding module, and realizes the stability and reliability of the base station system clock when the external reference source is abnormal.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and more specifically to a clock optimization method and a clock device. Background Art

[0002] In the communication system, in order to meet the requirements of wireless air interface time synchronization, the base station system should meet the requirements of ±50ppb frequency synchronization and ±1.5us phase synchronization. The base station side is usually designed to support multiple reference source tracking forms to ensure synchronization indicators. The reference source can include GNSS (Global Navigation Satellite System), syncE+1588 (Synchronous Ethernet, used to transmit frequency synchronization) and cascaded upstream clocks.

[0003] However, when the reference source is abnormally lost, for example, when the GNSS signal is weak and the reference source is invalid, the base station clock will be abnormal and affect the base station. Summary of the invention

[0004] In view of this, this application provides the following technical solutions:

[0005] A clock optimization method, comprising:

[0006] Obtain target reference clock source signal;

[0007] If the target reference clock source signal meets the target condition, a phase-locked loop of the base station is adjusted based on the target reference source signal to obtain a base station clock synchronization signal;

[0008] If the target reference clock source signal does not meet the target condition, a clock source signal is obtained based on a clock holding module of the base station, wherein the clock holding module is a module obtained by taming based on the clock synchronization signal of the base station when the target reference clock source signal meets the target condition;

[0009] The clock signal is input into the phase-locked loop of the base station to obtain a base station clock synchronization signal.

[0010] Optionally, the method further comprises:

[0011] If the target reference clock source signal meets the target condition, the base station clock synchronization signal is input into the clock holding module to implement clock signal training of the clock holding module based on the real-time clock synchronization signal and the obtained ambient temperature data during the training period.

[0012] Optionally, the method further comprises:

[0013] In response to the clock source signal being acquired by the clock holding module based on the base station, detecting whether the target reference clock source signal meets the target condition;

[0014] If yes, the target reference clock source signal is input into the phase locked loop of the base station.

[0015] Optionally, the method further comprises:

[0016] In response to inputting the target reference clock source signal into the phase-locked loop of the base station, the base station clock synchronization signal is simultaneously input into the clock holding module, so that the clock holding module continues to perform clock discipline based on the target reference clock source signal.

[0017] Optionally, acquiring a target reference clock source signal includes:

[0018] If there is at least one reference clock source, obtain characteristic information and application scenario characteristics of each reference clock source;

[0019] Determine the priority of each reference clock source based on the characteristic information of each reference clock source and the characteristics of the application scenario;

[0020] According to the priorities of the reference clock sources, the target reference clock source signal is determined.

[0021] Optionally, the clock signal source is obtained based on the clock holding module of the base station, and does not include:

[0022] Obtain the taming time of the clock holding module of the base station;

[0023] If the taming time is longer than the target time threshold, a clock source signal of the clock holding module is obtained.

[0024] A clock device, which is applied to a base station and comprises: a clock synchronization module and a clock holding module;

[0025] The clock synchronization module is used to obtain a target reference clock source signal; if the target reference clock source signal meets the target condition, the base station phase-locked loop is adjusted based on the target reference clock source signal to obtain a base station clock synchronization signal;

[0026] The clock holding module is used to obtain the base station clock synchronization signal output by the clock synchronization module; and perform clock training based on the base station clock synchronization signal;

[0027] The clock synchronization module is also used to obtain a clock source signal based on the clock holding module of the base station if the target reference clock source signal does not meet the target condition, and input the clock source signal into the phase-locked loop of the base station to obtain a base station clock synchronization signal.

[0028] Optionally, the clock synchronization module includes: a phase-locked loop submodule and a control submodule, wherein:

[0029] The phase-locked loop submodule is used to perform phase-locked loop adjustment based on the target reference clock source signal to obtain a base station clock synchronization signal; send the base station clock synchronization signal to the application device to synchronize the clock of the application device; and send the base station clock synchronization signal to the clock holding module to tame the clock of the clock holding module;

[0030] The control submodule is used to control the base station clock synchronization signal to be sent to the clock holding module if the target reference clock source signal meets the target condition; or, if the target reference clock source signal does not meet the target condition, control the clock holding module to send the clock source signal to the clock synchronization module.

[0031] Optionally, the phase-locked loop submodule includes a first interface, a second interface, a third interface and a processing submodule, wherein a target reference clock signal of a reference source is obtained through the first interface, the base station clock synchronization signal is sent to the application device through the second interface, and the base station clock synchronization signal is sent to a clock holding module through the third interface, and the processing submodule is used to perform phase-locked loop adjustment based on the target reference clock source signal to obtain a base station clock synchronization signal;

[0032] The clock holding module includes a first analog switch, a second analog switch, a fourth interface, a fifth interface and a timekeeping clock submodule, wherein the first analog switch is respectively connected to the control submodule of the clock synchronization module and the fourth interface, the second analog switch is respectively connected to the control submodule of the clock synchronization module and the fifth interface, and the timekeeping clock submodule is respectively used for connecting the fourth interface and the fifth interface;

[0033] Wherein, the first analog switch is used to receive the control instruction of the control submodule, and if the control instruction is to open, connect the fourth interface with the second interface; if the control instruction is to close, disconnect the connection between the fourth interface and the second interface;

[0034] The second analog switch is used to receive a control instruction from the control submodule, and if the control instruction is to open, connect the fifth interface with the first interface; if the control instruction is to close, disconnect the connection between the fifth interface and the first interface;

[0035] The timekeeping clock submodule is used to perform clock signal training based on the base station clock synchronization signal obtained in real time during the training period and the obtained ambient temperature data.

[0036] Optionally, the clock holding module further includes:

[0037] An Ethernet interface connected to the second analog switch, the Ethernet interface being used to obtain a synchronous Ethernet signal carried in the Ethernet information, so that the timekeeping clock submodule performs clock signal training based on the synchronous Ethernet signal.

[0038] Through the above technical solutions, it can be known that the present application discloses a clock optimization method and clock device, which obtains a target reference clock source signal; if the target reference clock source signal meets the target condition, the base station phase-locked loop is adjusted based on the target reference clock source signal to obtain a base station clock synchronization signal; if the target reference clock source signal does not meet the target condition, the clock source signal is obtained based on the clock holding module of the base station, and the clock holding module is a module that is tamed based on the base station clock synchronization signal when the target reference clock source signal meets the target condition; the clock source signal is input into the phase-locked loop of the base station to obtain the base station clock synchronization signal. The present application can perform clock calibration through the clock holding module, and realizes the stability and reliability of the base station system clock when the external reference source is abnormal. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0040] Figure 1 A flowchart of a clock optimization method provided in an embodiment of the present application;

[0041] Figure 2 A schematic diagram of the structure of a clock device in a clock taming process provided by an embodiment of the present application;

[0042] Figure 3 A schematic diagram of the structure of a clock device in a clock taming process provided by an embodiment of the present application;

[0043] Figure 4 A schematic diagram of the structure of a clock device in the process of restoring taming provided by an embodiment of the present application;

[0044] Figure 5 A schematic diagram of the structure of another clock device in the process of restoring taming provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0046] In the communication system, in order to meet the wireless air interface time synchronization, the base station system should meet the ±50ppb frequency synchronization and ±1.5us phase synchronization requirements. Inside the device, the clock signal is generated by a crystal oscillator. Due to the characteristics of the crystal oscillator, as the crystal oscillator ages over time, the clock signal it generates will also deviate. Therefore, in the embodiment of the present application, the clock device uses a clock holding module for timekeeping, which ensures the stability and reliability of the base station system clock when the external reference source is abnormal.

[0047] See also Figure 1 , is a flow chart of a clock optimization method provided in an embodiment of the present application, the method may include the following steps:

[0048] S101. Obtain a target reference clock source signal.

[0049] The method is applied to a clock device, and the target reference clock source signal is a signal generated by an external clock source corresponding to the clock device. The external clock source can be a 1588 protocol, a GPS (Global Positioning System) protocol, and a SyncE (Synchronous Ethernet) signal carried in Ethernet information.

[0050] For example, the clock synchronization module of the current clock device supports three reference sources: GNSS (Global Navigation Satellite System), SyncE+1588 (Synchronous Ethernet), and 1PPS+TOD. Usually, the clock source signal generated by any one of the reference sources can be obtained as the target clock source, or the target reference clock source signal can be determined in combination with the current application scenario.

[0051] In one implementation of the embodiments of the present application, obtaining the target reference clock source signal includes: if there is at least one reference clock source, obtaining characteristic information and application scenario characteristics of each reference clock source; based on the characteristic information and application scenario characteristics of each reference clock source, determining the priority of each reference clock source; and determining the target reference clock source signal according to the priority of each reference clock source.

[0052] The characteristic information of the reference clock source may include at least one of the location information, signal strength information, and signal quality parameters of the reference clock source. The application scenario characteristics may include the characteristics of the environment in which the clock device is located, the interface characteristics, the accuracy range characteristics, etc. The clock synchronization module of the current clock device supports three reference sources as references: GNSS (Global Navigation Satellite System), SyncE+1588 (Synchronous Ethernet), and 1PPS+TOD. Based on the above characteristics, the priority of these three reference sources can be set to GNSS>1PPS+TOD>SyncE+1588. That is, the current target reference clock source signal is the GNSS reference source signal with the highest priority.

[0053] S102: If the target reference clock source signal meets the target condition, a phase-locked loop of the base station is adjusted based on the target reference clock source signal to obtain a base station clock synchronization signal.

[0054] S103: If the target reference clock source signal does not meet the target condition, a clock source signal is acquired based on a clock holding module of the base station.

[0055] S104: Input the clock source signal to the phase-locked loop of the base station to obtain a base station clock synchronization signal.

[0056] In the embodiment of the present application, the clock optimization method can be applied to the clock device of the base station, and the clock device in the present application includes a clock synchronization module and a clock holding module. The clock synchronization module mainly adjusts the phase-locked loop of the base station based on the clock source signal to obtain the base station clock synchronization signal; and the clock holding module is a module that is tamed based on the base station clock synchronization signal when the target reference clock source signal meets the target conditions.

[0057] The target reference clock source signal is a signal generated by an external clock source. When it is input into the phase-locked loop of the clock synchronization module, the phase-locked loop can use the input signal as a reference to correct the clock signal generated by the crystal oscillator and output the corrected clock signal. The target condition refers to the condition that the error range of the phase-locked loop after outputting the clock signal based on the target reference clock source signal is within the target range. For example, taking the 1pps (1PulsePerSecond, pulse per second) generated by the phase-locked loop as an example, when the phase-locked loop tracks the external reference source, the 1pps output of the phase-locked loop will follow the 1pps input (that is, the target reference clock source signal as input) to perform phase synchronization and frequency synchronization. At this time, if the error between the 1pps output of the phase-locked loop and the 1pps input of the reference external reference clock source (that is, the target reference clock signal) is within the target range (such as ±1.5us), it means that the target reference clock source signal is normal and can be used for base station phase-locked loop adjustment to obtain the base station clock synchronization signal.

[0058] If the target reference clock source signal does not meet the target condition, it means that the external reference source is abnormal and the clock synchronization cannot be performed through the external reference source. In the embodiment of the present application, if the target reference source signal does not meet the target condition, the clock source signal is obtained based on the clock holding module of the base station. Among them, the clock holding module includes a punctual clock submodule, and the clock holding module is a module obtained by taming based on the base station clock synchronization signal when the target reference clock signal meets the target condition. That is, when the clock device of the base station has an external reference clock source tracking, the 1pps phase stability of its phase-locked loop output is high, and its corresponding control submodule (such as MCU microcontroller unit) controls the 1pps output of its phase-locked loop to be input to the punctual clock submodule, and the submodule is tamed. After taming for a certain time, the punctual clock submodule can output 1pps to the outside according to the 1pps phase data and after calibration and smoothing of the target processing mode, that is, output the clock source signal. So that when the external clock source is lost or abnormal, the base station clock synchronization can be performed according to the clock source signal output by the clock holding module to obtain the base station clock synchronization signal. The base station clock synchronization signal can be used to input into the application device so that the application device performs clock synchronization.

[0059] Based on the embodiment of the present application, the base station clock is calibrated through the clock holding module of the base station, which can solve the problem of insufficient local crystal oscillator holding ability, can quickly meet the ±1.5us / 24h phase synchronization requirements, and avoid the long development time and difficulty of the clock calibration algorithm.

[0060] Specifically, in order to ensure the accuracy of the clock module training, in one implementation of the embodiment of the present application, if the target reference clock source signal meets the target condition, the base station clock synchronization signal is input to the clock holding module to implement the clock signal training of the clock holding module based on the base station clock synchronization signal obtained in real time and the obtained ambient temperature data in the training device. Among them, the ambient temperature will affect the training process of the clock holding module. Therefore, the correspondence between the clock signal training and the base station clock synchronization signal and the ambient temperature information can be pre-stored, and the target processing mode can be obtained, so that when training is performed, the corresponding target processing mode is called according to the current ambient temperature data for processing, and the training of the clock holding module is completed.

[0061] In the process of acquiring the clock source signal based on the clock holding module of the base station and performing clock synchronization of the base station, it is also possible to monitor whether the target reference clock source signal meets the target condition. If so, the target reference clock source signal is input into the phase-locked loop of the base station. When clock synchronization is performed through the clock holding module, it is necessary to monitor the signal state of the external reference source. If it meets the target condition, that is, the error is within the target range, the clock synchronization can continue based on the external reference source, that is, the clock source signal provided by the clock holding module is switched to the target reference clock source signal obtained through the external reference source.

[0062] Furthermore, in response to inputting the target reference clock source signal into the phase-locked loop of the base station, the base station clock synchronization signal is simultaneously input into the clock holding module, so that the clock holding module continues to perform clock training based on the target reference clock source signal. When the external reference source returns to normal, the base station performs clock synchronization through the target reference clock signal corresponding to the external reference source, and continues to input its clock synchronization signal into the clock holding module to ensure the continued training of the clock holding module, so that it can prepare to output an accurate clock source signal in real time.

[0063] In one implementation, in order to ensure the taming accuracy of the clock holding module, only after the taming of the clock holding module reaches the target condition, for example, the taming reaches a certain duration, can the clock holding module be switched to output the clock synchronization signal. Specifically, the clock holding module based on the base station obtains the clock source signal, including: obtaining the taming duration of the clock holding module of the base station; if the taming duration is greater than the target duration threshold, obtaining the clock source signal of the clock holding module.

[0064] Furthermore, in the embodiment of the present application, the taming duration can be implemented in the form of a taming cycle, and the clock source signal can be provided by the clock holding module only after each taming cycle is completed. Specifically, the taming duration must be greater than the target duration threshold. The target duration threshold for taming the clock holding module can be determined by collecting the application scenario characteristics of clock optimization and the configuration characteristics of the clock device, wherein the application scenario characteristics include the device characteristics of the application device to be calibrated, such as device attribute characteristics, device allowable error characteristics, etc. The configuration characteristics of the clock device may include the setting information of the components and circuits of the clock holding module, the correction error information of each component, etc., as well as the overall required accuracy information. Therefore, the target duration threshold is determined based on this information to ensure that the taming duration of the clock holding module is greater than the target duration threshold, thereby ensuring the accuracy of the clock source signal provided by the clock holding module.

[0065] In the embodiment of the present application, a clock device applied to a base station is also provided, see Figure 2 , which shows a schematic diagram of the structure of a clock device in the clock holding module taming process provided by an embodiment of the present application. Correspondingly, the clock device includes a clock synchronization module 20 and a clock holding module 21.

[0066] Specifically, the clock synchronization module 20 is used to obtain a target reference clock source signal; if the target reference clock source signal meets the target condition, the base station phase-locked loop is adjusted based on the target reference clock source signal to obtain a base station clock synchronization signal;

[0067] The clock holding module 20 is used to obtain the base station clock synchronization signal output by the clock synchronization module 21; and perform clock training based on the base station clock synchronization signal;

[0068] The clock synchronization module 20 is also used to obtain the clock source signal based on the clock holding module of the base station if the target reference clock source signal does not meet the target condition, and input the clock source signal into the phase-locked loop of the base station to obtain the base station clock synchronization signal.

[0069] Further, the clock synchronization module includes: a phase-locked loop submodule 201 and a control submodule 202, wherein the phase-locked loop submodule 201 can be a phase-locked loop system, which is a negative feedback control system that uses the voltage generated by phase synchronization to tune the voltage oscillator to generate a target frequency. The frequency and phase of the oscillation signal inside the loop are controlled by an external reference signal to achieve automatic tracking of the output signal frequency to the input signal frequency, which is generally used in a closed-loop tracking circuit. The control submodule 202 can be composed of an FPGA (Field Programmable Gate Array, programmable logic array), or it can be a single MCU (Microcontroller Unit, a control unit) in an FPGA.

[0070] Correspondingly, the phase-locked loop submodule 201 is used to adjust the phase-locked loop based on the target reference clock source signal to obtain a base station clock synchronization signal; send the base station clock synchronization signal to the application device to synchronize the clock of the application device; and send the base station clock synchronization signal to the clock holding module 21 to tame the clock of the clock holding module 21.

[0071] The control submodule 202 is used to control the base station clock synchronization signal to be sent to the clock holding module 21 if the target reference clock source signal meets the target condition; or, if the target reference clock source signal does not meet the target condition, control the clock holding module to send the clock source signal to the clock synchronization module 20.

[0072] Specifically, the phase-locked loop submodule 201 includes a first interface 2011, a second interface 2012, a third interface 2013 and a processing submodule 2014, wherein the target reference clock signal of the reference source is obtained through the first interface 2011, the base station clock synchronization signal is sent to the application device through the second interface 2012, and the base station clock synchronization signal is sent to the clock holding module 21 through the third interface 2013, and the processing submodule 2014 is used to perform phase-locked loop adjustment based on the target reference clock source signal to obtain the base station clock synchronization signal.

[0073] The clock holding module 21 includes a first analog switch 2101, a second analog switch 2102, a fourth interface 2103, a fifth interface 2104 and a timekeeping clock submodule 2105. The first analog switch 2101, the second analog switch 2102, the fourth interface 2103, the fifth interface 2104 and the timekeeping clock submodule 2105, the first analog switch 2101 is respectively connected to the control submodule 202 and the fourth interface 2103 of the clock synchronization module 20, the second analog switch 2102 is respectively connected to the control submodule 202 and the fifth interface 2104 of the clock synchronization module 20, and the timekeeping clock submodule 2105 is respectively used for connecting the fourth interface 2103 and the fifth interface 2104;

[0074] The first analog switch 2101 is used to receive a control instruction from the control submodule 202. If the control instruction is to open, the fourth interface 2103 and the second interface 2012 are connected; if the control instruction is to close, the connection with the fourth interface 2103 and the second interface 2102 is disconnected.

[0075] The second analog switch 2102 is used to receive a control instruction from the control submodule 202 . If the control instruction is to open, the fifth interface 2104 and the first interface 2011 are connected. If the control instruction is to close, the connection between the fifth interface 2104 and the first interface 2011 is disconnected.

[0076] The timekeeping clock submodule 2105 is used to perform clock signal training based on the base station clock synchronization signal obtained in real time during the training period and the obtained ambient temperature data.

[0077] The following is specific Figure 2 In this application scenario, the clock synchronization module 20 supports three reference sources as references: GNSS (Global Navigation Satellite System), SyncE+1588 (Synchronous Ethernet), and 1PPS+TOD. The reference source priorities of the three can be set, for example, the order of priority is GNSS>1PPS+TOD>SyncE+1588.

[0078] When the clock synchronization module 20 tracks three valid reference sources, the second interface 2012 (i.e., 1PPS out) of the phase-locked loop submodule 201 follows the first interface 2021 (i.e., 1PPS in) to perform phase synchronization and frequency synchronization. At this time, if the output of the second interface and the reference GPS 1pps error meet the target condition, the output signal of the second interface 2012 can be transmitted to the application device so that the application device performs clock synchronization based on this. At this time, the output of the third interface 2013 of the phase-locked loop submodule 201 is used as the signal input of the punctual clock submodule 2105 of the clock holding module 21 to tame the punctual clock submodule 2105. The punctual clock submodule 2105 will collect the historical data and ambient temperature corresponding to the clock source signal output by the clock synchronization module through the fourth interface 2103, and obtain the clock source signal according to the target processing mode, which can be output through the fifth interface 2104.

[0079] Correspondingly, see Figure 3 , which shows a structural schematic diagram of a clock device in a clock holding process provided by an embodiment of the present application.

[0080] When the GNSS, SyncE+1588, and 1PPS+TOD (RJ45) sources are all invalid, the clock holding module 21 will switch from the taming state to the holding (Holdover) state, and the control submodule 202 of the clock synchronization module controls the first analog switch 2101 to close the 1PPS Out of the phase-locked loop submodule 201 through the third interface 2013 and input it to the 1PPS in of the punctual clock submodule through the fourth interface 2103, thereby stopping the taming of the punctual clock submodule 2105. Control the second analog switch 2102 to open the 1PPS Out output by the punctual clock submodule through the fifth interface 2104, and input it to the first interface 2011 of the phase-locked loop submodule for 1PPS In, so that the phase-locked loop tracks the 1PPS output by the punctual clock submodule after taming. Taming time, the taming time of the punctual clock submodule needs to be greater than the target time threshold, and the target time threshold can be determined according to the specific application scenario and the configuration information and component accuracy of the clock submodule. For example, if the target duration threshold is set to 7 days, the timekeeping clock submodule is recommended to be trained for more than 7 days to ensure that sufficient historical data is captured to meet the ±1.5us / 24h requirement of the phase-locked loop 1PPS Out and the reference GPS 1PPS. That is, after the timekeeping clock module has been trained for 7 days, the DPLL only follows the 1PPS Out of the timekeeping clock module within 24 hours after the clock synchronization module disconnects all reference sources such as GNSS, SyncE+1588, and 1PPS+TOD (RJ45), which can ensure that the DPLL 1PPS Out and the reference GPS 1PPS meet the ±1.5us / 24h requirement.

[0081] Correspondingly, see Figure 4 The schematic diagram of the structure of the clock device in the recovery training process is shown. When either the GNSS or SyncE+1588 source is valid, the clock holding module 21 will switch from the holding state to the training state, and the control submodule 202 will control the first analog switch 2101 to re-input the DPLL 1PPS Out into the 1PPS in of the punctual clock module to train the punctual clock module; the 1PPS output by GNSS or SyncE+1588S is input into the 1PPS In of the DPLL, and the second analog switch 2102 is controlled to turn off the 1PPS Out output by the punctual clock module.

[0082] In one implementation, the clock holding module further includes:

[0083] The Ethernet interface 2106 connected to the second analog switch is used to obtain the synchronous Ethernet signal carried in the Ethernet information, so that the timekeeping clock submodule performs clock signal training based on the synchronous Ethernet signal.

[0084] For further information, see Figure 5 When GNSS and SyncE+1588 are invalid and 1PPS+TOD (RJ45) source is valid, the clock holding module 21 will switch from the holding state to the taming state, and the control submodule 202 controls the first analog switch to re-input the DPLL 1PPS Out into the 1PPS in of the timekeeping clock module to tame the timekeeping clock module; the 1PPS In is input into the 1PPS In of the DPLL through the Ethernet interface 2106 such as RJ45, and the reference source 1PPS In of the DPLL is switched to the external reference source RJ45.

[0085] In the clock device provided in the embodiment of the present application, if the target reference clock source signal does not meet the target condition, the clock source signal is obtained based on the clock holding module of the base station, and the clock holding module is a module obtained by taming based on the clock synchronization signal of the base station when the target reference clock source signal meets the target condition; the clock source signal is input into the phase-locked loop of the base station to obtain the clock synchronization signal of the base station. The present application can perform clock calibration through the clock holding module, and realizes the stability and reliability of the base station system clock when the external reference source is abnormal.

[0086] It should be noted that the specific implementation of each module and sub-module in this embodiment can refer to the corresponding content in the previous text and will not be described in detail here.

[0087] In another embodiment of the present application, a readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, each step of the clock optimization method as described in any one of the above items is implemented.

[0088] In another embodiment of the present application, an electronic device is further provided, and the electronic device may include:

[0089] A memory, used to store applications and data generated by the operation of the applications;

[0090] A processor is used to execute the application program to implement the clock optimization method as described in any one of the above items.

[0091] It should be noted that the specific implementation of the processor in this embodiment can refer to the corresponding content in the previous text and will not be described in detail here.

[0092] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0093] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0094] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0095] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A clock optimization method, comprising: The clock synchronization module obtains the target reference clock source signal; If the target reference clock source signal meets the target condition, a phase-locked loop of the base station is adjusted based on the target reference clock source signal to obtain a base station clock synchronization signal; If the target reference clock source signal does not meet the target condition, the clock source signal is obtained based on the clock holding module of the base station, and the clock holding module is a module obtained by training based on the base station clock synchronization signal when the target reference clock source signal meets the target condition; the clock holding module includes a first analog switch, a second analog switch, a fourth interface, a fifth interface and a punctual clock submodule, and the punctual clock submodule is used for connecting the fourth interface and the fifth interface respectively; wherein, the first analog switch is used to control the on-off between the interface for outputting the base station clock synchronization signal in the clock synchronization module and the fourth interface, and the second analog switch is used to control the on-off between the interface for obtaining the clock source signal in the clock synchronization module and the fifth interface, and the punctual clock submodule is used to train the clock signal based on the base station clock synchronization signal obtained in real time and the obtained ambient temperature data during the training period; The clock source signal is input into the phase-locked loop of the base station to obtain a base station clock synchronization signal.

2. The method according to claim 1, further comprising: If the target reference clock source signal meets the target condition, the base station clock synchronization signal is input into the clock holding module to implement clock signal training of the clock holding module based on the base station clock synchronization signal obtained in real time and the obtained ambient temperature data during the training period.

3. The method according to claim 1, further comprising: In response to the clock source signal being acquired by the clock holding module based on the base station, monitoring whether the target reference clock source signal meets the target condition; If yes, the target reference clock source signal is input into the phase locked loop of the base station.

4. The method according to claim 3, further comprising: In response to inputting the target reference clock source signal into the phase-locked loop of the base station, the base station clock synchronization signal is simultaneously input into the clock holding module, so that the clock holding module continues to perform clock discipline based on the target reference clock source signal.

5. The method according to claim 1, wherein obtaining a target reference clock source signal comprises: If there is at least one reference clock source, obtain characteristic information and application scenario characteristics of each reference clock source; Determine the priority of each reference clock source based on the characteristic information of each reference clock source and the characteristics of the application scenario; According to the priorities of the reference clock sources, the target reference clock source signal is determined.

6. The method according to claim 1, wherein the clock holding module based on the base station obtains the clock source signal, comprising: Obtain the taming time of the clock holding module of the base station; If the taming time is greater than the target time threshold, a clock source signal of the clock holding module is obtained.

7. A clock device, applied to a base station, comprising: Clock synchronization module and clock holding module; The clock synchronization module is used to obtain a target reference clock source signal; If the target reference clock source signal meets the target condition, a phase-locked loop of the base station is adjusted based on the target reference clock source signal to obtain a base station clock synchronization signal; The clock holding module is used to obtain the base station clock synchronization signal output by the clock synchronization module; When the target reference clock source signal meets the target condition, clock taming is performed based on the base station clock synchronization signal; the clock holding module includes a first analog switch, a second analog switch, a fourth interface, a fifth interface and a punctual clock submodule, and the punctual clock submodule is used for connecting the fourth interface and the fifth interface respectively; wherein, the first analog switch is used to control the on-off between the interface for outputting the base station clock synchronization signal in the clock synchronization module and the fourth interface, the second analog switch is used to control the on-off between the interface for obtaining the clock source signal in the clock synchronization module and the fifth interface, and the punctual clock submodule is used to perform clock signal taming based on the base station clock synchronization signal obtained in real time and the obtained ambient temperature data during the taming period; The clock synchronization module is also used to obtain a clock source signal based on the clock holding module of the base station if the target reference clock source signal does not meet the target condition, and input the clock source signal into the phase-locked loop of the base station to obtain a base station clock synchronization signal.

8. The clock device according to claim 7, wherein the clock synchronization module comprises: Phase-locked loop submodule and control submodule, wherein, The phase-locked loop submodule is used to perform phase-locked loop adjustment based on the target reference clock source signal to obtain a base station clock synchronization signal; send the base station clock synchronization signal to the application device to synchronize the clock of the application device; and send the base station clock synchronization signal to the clock holding module to tame the clock of the clock holding module; The control submodule is used to control the base station clock synchronization signal to be sent to the clock holding module if the target reference clock source signal meets the target condition; or, if the target reference clock source signal does not meet the target condition, control the clock holding module to send the clock source signal to the clock synchronization module.

9. The clock device according to claim 8, wherein the phase-locked loop submodule comprises a first interface, a second interface, a third interface and a processing submodule, wherein: Obtain a target reference clock signal of a reference source through the first interface, send the base station clock synchronization signal to the application device through the second interface, send the base station clock synchronization signal to a clock holding module through the third interface, and the processing submodule is used to perform phase-locked loop adjustment based on the target reference clock source signal to obtain a base station clock synchronization signal; The first analog switch is connected to the control submodule of the clock synchronization module and the fourth interface respectively, the second analog switch is connected to the control submodule of the clock synchronization module and the fifth interface respectively, and the punctual clock submodule is used for connecting the fourth interface and the fifth interface respectively; Wherein, the first analog switch is used to receive the control instruction of the control submodule, and if the control instruction is to open, connect the fourth interface with the third interface; if the control instruction is to close, disconnect the connection between the fourth interface and the third interface; The second analog switch is used to receive a control instruction from the control submodule, and if the control instruction is to open, connect the fifth interface with the first interface; if the control instruction is to close, disconnect the connection between the fifth interface and the first interface.

10. The clock device according to claim 9, wherein the clock holding module further comprises: An Ethernet interface connected to the second analog switch, the Ethernet interface being used to obtain a synchronous Ethernet signal carried in the Ethernet information, so that the punctual clock submodule performs clock signal training based on the synchronous Ethernet signal.

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