A circuit board and a method for manufacturing a circuit board
By setting blind holes and forming vias on the etched layer of the circuit board, the problem of poor heat dissipation performance of the circuit board is solved, the heat of the components is directly conducted, and the heat dissipation efficiency of the circuit board is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENNAN CIRCUITS
- Filing Date
- 2021-06-30
- Publication Date
- 2026-05-15
AI Technical Summary
The poor heat dissipation performance of existing circuit boards results in a long heat transfer path for components, affecting the performance and reliability of electronic products.
Blind vias are set on the etched layer of the circuit board to form through-holes, which directly conduct the heat generated by the components to the surface of the circuit board, avoiding the heat transfer through the additional circuit layer. The etched layer is formed by mixing photocuring and thermocuring materials, and the through-holes are formed by electroplating.
It shortens the heat transfer path, improves the heat dissipation performance of the circuit board, and enhances the heat dissipation efficiency of components.
Smart Images
Figure CN115551171B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electronic technology, and in particular to a circuit board and a method for manufacturing the same. Background Technology
[0002] As electronic products rapidly develop towards being lighter, thinner, smaller, higher-density, and more multifunctional, the size of electronic components and logic circuits has shrunk dramatically, and the density of components in circuit boards has increased significantly. Consequently, the heat dissipation problem of circuit boards urgently needs to be improved. Summary of the Invention
[0003] The main technical problem solved by this invention is to provide a circuit board and a method for manufacturing the circuit board, thereby solving the problem of poor heat dissipation performance of circuit boards in the prior art.
[0004] To solve the above-mentioned technical problems, the first technical solution adopted by the present invention is: to provide a circuit board, the circuit board comprising: a board body, the board body having a groove; components disposed in the groove; a first etched layer disposed on the side surface of the board body having the groove, the first etched layer having a window, the components being disposed corresponding to the window; a second etched layer disposed on the side surface of the first etched layer away from the board body, and partly located within the window; the second etched layer having a blind hole, the blind hole penetrating the portion of the second etched layer corresponding to the window; wherein, the inner diameter of the blind hole is smaller than the inner diameter of the window, the blind hole having an electroplated layer, so that the blind hole forms a through hole, the through hole connecting the components.
[0005] The first etched layer is formed by curing a mixture of photocurable and thermocurable materials.
[0006] The second etched layer is formed by curing a mixture of photocurable and thermocurable materials.
[0007] The second etched layer is a prepreg or resin.
[0008] The circuit board also includes a first circuit layer, which is disposed between the first etch layer and the second etch layer and extends to the inner wall of the window and the surface of the components, and is connected to the vias and the pins of the components.
[0009] The circuit board also includes a second circuit layer, which is disposed on the side of the second etched layer away from the board body. The second circuit layer is connected to the portion of the first circuit layer whose pins are not connected through vias.
[0010] To solve the above-mentioned technical problems, the second technical solution adopted by the present invention is: providing a method for manufacturing a circuit board, the method comprising: obtaining a board body in which components are embedded; setting a first etching layer on the surface of the exposed components on the board body; exposing the first etching layer to photocuring and crosslinking; performing a development process to form a window on the first etching layer to expose the components through the window; setting a second etching layer on the side of the first etching layer away from the board body, such that a portion of the second etching layer is set in the window; forming a blind hole in the portion of the second etching layer set in the window to expose a portion of the components through the blind hole; and forming a via in the blind hole to connect the components.
[0011] The step of forming a window on the first etched layer by performing a developing process to expose the components through the window further includes: heating the first etched layer to thermally cure and crosslink it.
[0012] The process of forming a window on the first etched layer by performing development treatment also includes forming a first seed layer within the window.
[0013] The step of forming a first seed layer in the window includes: forming a first seed layer in the window and on the surface of the first etched layer away from the board by means of copper plating or sputtering; before the step of forming a via in the blind hole, the step includes: forming a second seed layer in the blind hole and on the surface of the second etched layer away from the first etched layer by means of copper plating or sputtering.
[0014] The step of forming a first seed layer in the window and on the surface of the first etched layer away from the board by means of copper plating or sputtering further includes: covering the first seed layer in the window with a first protective layer; opening a through hole in the first protective layer to expose a portion of the first seed layer through the through hole; etching the exposed first seed layer to expose a portion of the surface between the pins of the component and a portion of the surface of the pin and / or a portion of the pin; and removing the first protective layer to form a first circuit layer from the first seed layer, wherein the first circuit layer is connected to a portion of the pin and / or a portion of the surface of the pin.
[0015] The step of forming a first seed layer inside the window and on the surface of the first etched layer away from the board by means of copper plating or sputtering further includes: electroplating on the first seed layer to form a first metal layer at least on the exposed components in the window; covering the surface of the first metal layer away from the components with a first protective layer; opening through holes in the first protective layer to expose a portion of the first metal layer through the through holes; etching the exposed first metal layer to expose the surfaces between the pins of the components and a portion of the pins and / or a portion of the pin surfaces; removing the first protective layer, and the first metal layer forming a first circuit layer.
[0016] The step of forming a first seed layer in the window and on the surface of the first etched layer away from the board by means of copper plating or sputtering further includes: covering the surface of the first seed layer away from the board with a first protective layer; opening through holes in the first protective layer to expose the first seed layer covering a portion of the pins and / or a portion of the pin surfaces through the through holes; using electroplating to form a first metal layer in the through holes; removing the first protective layer to expose the unplated portion of the first seed layer; etching the exposed first seed layer to expose the surfaces of a portion of the components and a portion of the pins and / or a portion of the pin surfaces, and the first metal layer forming a first circuit layer.
[0017] The step of etching the exposed first seed layer includes: removing the exposed first seed layer by differential etching.
[0018] The step of forming a second seed layer in the blind via and on the side of the second etched layer away from the first etched layer by means of copper plating or sputtering further includes forming a second circuit layer on the side of the second etched layer away from the first etched layer.
[0019] The material of the first etched layer is a photosensitive resin.
[0020] The second etched layer is a prepreg or resin; the step of forming blind holes in the portion of the second etched layer that is located in the window to expose some components through the blind holes includes: forming blind holes in the portion of the second etched layer that is located in the window by laser drilling to expose some pins and / or some surfaces of the pins on the components that are not connected to the first circuit layer through the blind holes.
[0021] The second etched layer is made of a mixture of photocurable and thermocurable materials. The step of forming blind holes in the portion of the second etched layer that is located in the window to expose some components through the blind holes includes: processing the second etched layer by exposure and development to form blind holes in the portion of the second etched layer that is located in the window, so that the pins and / or the surface of the pins that are not connected to the first circuit layer on the component are exposed through the blind holes.
[0022] The step of electroplating to form a via in the blind hole includes: generating a metal conductor in the blind hole by electroplating, so that the metal conductor extends the portion of the pin not connected to the first circuit layer and / or the portion of the surface of the pin not connected to the first circuit layer to the side surface of the second etched layer away from the board body.
[0023] The beneficial effects of this invention are as follows: Unlike the prior art, this invention provides a circuit board and a method for manufacturing the same. In the circuit board provided by this application, a second etching layer is provided on a first etching layer, and a portion of the second etching layer is disposed within a window formed by the first etching layer. A blind hole is formed in the portion of the second etching layer disposed in the window, and a via is formed by electroplating. This facilitates the direct conduction of heat generated by components to the surface of the circuit board through the via, without the need for an additional circuit layer between the first and second etching layers. This shortens the heat transfer path and improves the heat dissipation performance of the circuit board. Attached Figure Description
[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0025] Figure 1 This is a schematic diagram of a circuit board according to an embodiment of the present invention;
[0026] Figure 2 This is a flowchart illustrating the first embodiment of the circuit board manufacturing method provided by the present invention;
[0027] Figures 3(a) to 3(m) yes Figure 2 A schematic diagram of the structure corresponding to the steps in the provided circuit board manufacturing method;
[0028] Figure 4 This is a flowchart illustrating the second embodiment of the circuit board manufacturing method provided by the present invention;
[0029] Figures 5(a) to 5(e) yes Figure 4 A schematic diagram of the structure corresponding to the steps in the provided circuit board manufacturing method;
[0030] Figure 6 This is a flowchart illustrating the third embodiment of the circuit board manufacturing method provided by the present invention;
[0031] Figures 7(a) to 7(d) yes Figure 6 A schematic diagram of the structure corresponding to the steps in the provided electroplating method. Detailed Implementation
[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0033] The terms "first," "second," and "third" used in this invention are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this invention are only used to explain the relative positional relationships and movement of components in a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications will also change accordingly. The terms "comprising" and "having," and any variations thereof, in the embodiments of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or components inherent to these processes, methods, products, or devices.
[0034] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of phrases in various places throughout the specification does not necessarily refer to the same embodiment, nor are they independent or alternative embodiments mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0035] Currently, the heat generated by components in a circuit board needs to be transferred outward layer by layer through the circuit layers connected to them. This means that heat needs to be transferred laterally to each circuit layer before being transferred longitudinally away from the components. As a result, the heat transfer path generated by the components is long, leading to poor heat dissipation performance of the circuit board.
[0036] Please see Figure 1 , Figure 1This is a schematic diagram of a circuit board according to an embodiment of the present invention. This embodiment provides a circuit board 1, which includes a board body 10, components 102, a first etching layer 20, and a second etching layer 60. Both the first etching layer 20 and the second etching layer 60 are layers on which patterns, through-holes, or blind holes can be etched using an exposure and development process. The board body 10 can be one or more core boards, or a semi-finished circuit board, a finished circuit board, etc.
[0037] At least one surface of the plate 10 is provided with a groove 101. There can be one or more grooves 101. Multiple grooves 101 can be located on the same surface of the plate 10 or on opposite surfaces of the plate 10. In another optional embodiment, the groove 101 can be a through groove. When there are multiple grooves 101, they can be spaced apart.
[0038] Component 102 is disposed within recess 101, with its pins 103 positioned away from the bottom surface of recess 101. Pins 103 on the surface of component 102 may be flush with one side surface of the recess 101 on the board 10. In another optional embodiment, pins 103 on the surface of component 102 may be lower or higher than one side surface of the recess 101 on the board 10. In this embodiment, one component 102 is disposed in one recess 101. In another optional embodiment, multiple components 102 are disposed in one recess 101, with the multiple components 102 spaced apart. Component 102 may be at least one of a chip, capacitor, resistor, inductor, and power supply device.
[0039] A first etched layer 20 is disposed on the side surface of the plate 10 where the groove 101 is located, and a window 201 is provided on the first etched layer 20. The window 201 penetrates the first etched layer 20, and the component 102 is disposed corresponding to the window 201. The first etched layer 20 is formed by curing a mixture of a photocurable material and a thermocurable material. In one specific embodiment, the material of the first etched layer 20 is a resin containing a photosensitizer. In an optional embodiment, the second etched layer 60 is formed by curing a mixture of a photocurable material and a thermocurable material. In another optional embodiment, the second etched layer 60 may also be a prepreg or a resin.
[0040] In an optional embodiment, the circuit board 1 further includes a first circuit layer 50. The first circuit layer 50 is disposed between the first etch layer 20 and the second etch layer 60, and a portion of the first circuit layer 50 extends to the inner wall of the window 201 and the surface of the component 102, so that the first circuit layer 50 is connected to a portion of the pins 103 of the component 102, thereby allowing the heat generated by the component 102 to be transferred and diffused through the portion of the pins 103 connected to the first circuit layer 50. Further, the first circuit layer 50 may also be connected to a portion of the surface of the pins 103 of the component 102, thereby allowing the heat generated by the component 102 to be transferred and diffused through the portion of the surface of the pins 103 connected to the first circuit layer 50.
[0041] The second etched layer 60 is disposed on the surface of the first etched layer 20 away from the board body 10, and a portion of the second etched layer 60 is disposed in the window 201 on the first etched layer 20. At least the portion of the second etched layer 60 disposed in the window 201 is provided with a blind via 601. The position of the blind via 601 corresponds to the portion of the pin 103 that is not connected to the first circuit layer 50. Further, the position of the blind via 601 corresponds to the portion of the surface of the pin 103 that is not connected to the first circuit layer 50. The blind via 601 penetrates the portion of the second etched layer 60 corresponding to the window 201. Since both the first etched layer 20 and the second etched layer 60 are layers that can be etched by exposure and development processes to form patterns, through holes, or blind vias, the blind via 601 can have a sufficiently small inner diameter, for example, greater than or equal to 25 micrometers and less than 50 micrometers. The smaller the inner diameter of the blind via 601, the larger the wiring space in the circuit board 1, and the higher the wiring density. Due to the small size of the blind via 601, wiring space is saved, thereby enabling a high-density distribution of the circuit. The inner diameter of the blind via 601 can be set according to the needs of the circuit board 1. For example, the inner diameter of the blind via 601 can be greater than or equal to 50 micrometers. In this embodiment, the inner diameter of the blind via 601 is smaller than the inner diameter of the window 201, and the inner diameter of the blind via 601 is also smaller than the pad diameter of the pin 103. The blind via 601 has a metal conductor 702 to form a through hole 701. The through hole 701 connects the part of the pin 103 of the component 102 that is not connected to the first circuit layer 50, or the part of the surface of the pin 103 that is not connected to the first circuit layer 50. Furthermore, the through hole 701 directly extends the part of the pin 103 of the component 102 or the part of the surface of the pin 103 to the side of the second etched layer 60 away from the first etched layer 20. Since the pins 103 of component 102 are directly connected to the via 701, the heat transfer path of component 102 can be shortened, so that the heat generated by component 102 can be directly conducted to the surface of circuit board 1 without passing through the first circuit layer 50, thereby improving the heat dissipation performance of circuit board 1.
[0042] In another optional embodiment, the circuit board 1 further includes a second circuit layer 90, which is disposed on the surface of the second etched layer 60 away from the board body 10. The second circuit layer 90 is connected to the portion of the pins 103 of the component 102 that are not connected to the first circuit layer 50, or the portion of the surface of the pins 103 that are not connected to the first circuit layer 50, through a via 701. This allows heat generated by the component 102 to be conducted to the second circuit layer 90 through the pins 103 connected to the component 102 and the via 701. Thus, the first circuit layer 50 and the second circuit layer 90 simultaneously dissipate heat generated on the component 102, eliminating the need to transfer heat from the component 102 to the second circuit layer 90 through the first circuit layer 50, shortening the heat transfer path and improving the heat dissipation performance of the circuit board 1. In another optional embodiment, the first circuit layer 50 on the first etched layer 20 is connected to the second circuit layer 90 through a via 701.
[0043] In the circuit board provided in this embodiment, a second etching layer is provided on the first etching layer, and the second etching layer is partially disposed within the window formed by the first etching layer. A blind hole is formed in the part of the second etching layer disposed in the window and electroplated to form a through hole. This facilitates the direct conduction of heat generated by the components to the surface of the circuit board through the through hole, without the need for an additional circuit layer between the first and second etching layers, thereby shortening the heat transfer path and improving the heat dissipation performance of the circuit board.
[0044] Please see Figure 2 and Figures 3(a) to 3(m) , Figure 2 This is a flowchart illustrating the first embodiment of the circuit board manufacturing method provided by the present invention; Figures 3(a) to 3(m) yes Figure 2 The provided circuit board manufacturing method includes a structural schematic diagram corresponding to the steps. This embodiment provides a method for manufacturing circuit board 1, which includes the following steps.
[0045] S101: Obtain the board body, which contains embedded components.
[0046] Specifically, referring to Figure 3(a), a board 10 and a component 102 are obtained, and a groove 101 is formed on the board 10; the component 102 is embedded in the groove 101 of the board 10, and the pins 103 of the component 102 are positioned away from the bottom of the groove 101. The material of the board 10 can be polytetrafluoroethylene or polyimide. The groove 101 can be a blind groove or a through groove.
[0047] In one optional embodiment, a dielectric layer is laminated onto the surface of the plate 10 away from the side where the blind slot is located, and a conductive layer may be laminated onto the side of the dielectric layer away from the plate 10. In another optional embodiment, a dielectric layer is laminated onto one side surface of the plate 10 so that the dielectric layer covers one end of the through slot, and a conductive layer may be laminated onto the side of the dielectric layer away from the plate 10. In a specific embodiment, the dielectric layer may be a prepreg, which is in a semi-fluid state during lamination and can fill the gap between the component 102 and the inner wall of the groove 101, thereby fixing the component 102 to the plate 10. The leads 103 of the component 102 are exposed from the plate 10.
[0048] S102: A first etched layer is applied to the surface of the exposed components on the board.
[0049] Specifically, referring to Figure 3(b), a first etching layer 20 is provided on one side of the opening of the groove 101 in the board 10. The first etching layer 20 covers the surface of the board 10 where the groove 101 is located and also covers the pins 103 of the component 102. In a specific embodiment, the first etching layer 20 is provided on the side of the board 10 away from the dielectric layer, so that the first etching layer 20 covers the side surface of the board 10 where the groove 101 is located. The material of the first etching layer 20 is a photosensitive resin. The first etching layer 20 is formed by mixing and curing a photocurable material and a thermocurable material. That is, the material of the first etching layer 20 contains both photosensitive reactive groups and thermosensitive reactive groups. The thickness of the first etching layer 20 is no greater than 50 micrometers.
[0050] S103: Expose the first etched layer to allow it to undergo photocuring and crosslinking.
[0051] Specifically, a mask is placed over the side of the first etched layer 20 away from the plate 10, and ultraviolet light is irradiated onto the first etched layer 20. The portion of the first etched layer 20 that needs to be retained is irradiated with ultraviolet light, while the portion that needs to be removed is excluded from ultraviolet light irradiation. When the first etched layer 20 receives ultraviolet light irradiation, the photosensitive groups in the first etched layer 20 undergo cross-linking, resulting in the first curing of the first etched layer 20. In other words, the portion of the first etched layer 20 that needs to be retained undergoes photocuring cross-linking under ultraviolet light irradiation, while the portion that is not irradiated does not undergo photocuring cross-linking. The mask is then removed.
[0052] S104: Perform a development process to form a window on the first etched layer so that the components are exposed through the window.
[0053] Specifically, referring to Figure 3(c), the unexposed portions of the first etched layer 20 are removed using a developer. The developer washes away the uncured cross-linked portions of the first etched layer 20 to form a window 201 on the first etched layer 20. Specifically, a portion of the surface of the board 10 is exposed through the window 201. The pins 103 of the component 102 can be exposed through the window 201. The size of the window 201 is larger than the size of the pins 103 of the component 102.
[0054] S105: The first etched layer is heated to thermally cure and crosslink it.
[0055] Specifically, the first etched layer 20 obtained in step S104 is baked to allow the remaining portion of the first etched layer 20 to undergo thermosetting cross-linking during baking, thus achieving a second curing of the first etched layer 20. During baking, the thermosensitive groups in the first etched layer 20 undergo cross-linking and curing, resulting in more thorough curing of the first etched layer 20 and achieving the required strength for filler layering. Simultaneously, the thermosensitive groups in the first etched layer 20 can cross-link with groups on the surface of the plate 10, thereby improving the bonding strength between the first etched layer 20 and the plate 10.
[0056] Of course, step S105 can also be omitted.
[0057] S106: Form the first seed layer within the window.
[0058] Specifically, referring to Figure 3(d), a first seed layer 30 is formed within the window 201 and on the surface of the first etched layer 20 away from the substrate 10 by means of copper plating or sputtering. The material of the first seed layer 30 is metallic copper or gold.
[0059] S107: Cover the first protective layer on the first seed layer within the window.
[0060] Specifically, referring to Figure 3(e), a first protective layer 40 is covered on the first seed layer 30 disposed on the surface of the first etched layer 20 away from the plate 10. The first protective layer 40 completely covers the surface of the first seed layer 30 away from the first etched layer 20. The first protective layer 40 can be a dry film or a photoresist. For example, the material of the first protective layer 40 is a photosensitive resin, and the material of the first protective layer 40 contains photosensitive reactive groups. In an optional embodiment, the first protective layer 40 can also be filled into the first seed layer 30 disposed within the window 201.
[0061] S108: A through-hole is made in the first protective layer so that a portion of the first seed layer is exposed through the through-hole.
[0062] Specifically, referring to Figure 3(f), since the material of the first protective layer 40 is a photosensitive resin, through-holes 401 can be formed on the first protective layer 40 by exposure and development, so that a portion of the first seed layer 30 disposed on the first etched layer 20 is exposed through the through-holes 401. The positions of the through-holes 401 in the first protective layer 40 outside the window 201 are spaced apart from the position of the window 201, so that a portion of the first seed layer 30 covered on the first etched layer 20 is exposed through the window 201. The positions of the through-holes 401 in the first protective layer 40 inside the window 201 are between two adjacent pins 103, so that a portion of the first seed layer 30 covering the pins 103 of the component 102 inside the window 201 is exposed through the through-holes 401. In an optional embodiment, the position of the through-holes 401 can correspond to the position of a portion of the pins 103, so that the first seed layer 30 covering a portion of the pins 103 of the component 102 inside the window 201 is exposed through the through-holes 401. In another alternative embodiment, the via 401 may be positioned to correspond to a portion of the surface of the pin 103, so that the first seed layer 30 covering the portion of the surface of the pin 103 is exposed through the via 401.
[0063] S109: Etch the first seed layer to expose a portion of the surface between the pins of the component and a portion of the surface of the pins and / or a portion of the pins.
[0064] Specifically, referring to Figure 3(g), the first seed layer 30 exposed through the via 401 is etched using a wet chemical etching method to expose a portion of the first etched layer 20, a portion of the surface of the component 102, and a portion of the surface of the pin 103. Alternatively, the first seed layer 30 exposed through the via 401 can be removed by plasma etching to expose a portion of the first etched layer 20, a portion of the surface of the component 102, and a portion of the surface of the pin 103.
[0065] S110: Remove the first protective layer so that the first seed layer forms the first circuit layer.
[0066] Specifically, referring to Figure 3(h), the first protective layer 40 is removed to expose the portion of the first seed layer 30 covered by the first protective layer 40. The first seed layer 30, after the above steps, forms the first circuit layer 50. That is, after removing the first protective layer 40, the first seed layer 30 on the surface of the first etched layer 20 and the first seed layer 30 on the surface of the component 102 are patterned to form the first circuit layer 50. The first circuit layer 50 is connected to a portion of the pins 103 and / or a portion of the surface of the pins 103. Heat generated by the component 102 can be transferred and diffused through the first circuit layer 50.
[0067] S111: A second etching layer is provided on the side of the first etching layer away from the board body, so that a portion of the second etching layer is provided in the window.
[0068] Specifically, referring to Figure 3(i), a second etched layer 60 is disposed on the surface of the first etched layer 20 where the first circuit layer 50 is located, and the second etched layer 60 completely covers the first etched layer 20. That is, the first circuit layer 50 on the first etched layer 20 is completely covered by the second etched layer 60. Part of the second etched layer 60 is disposed in the window 201 and covers the first circuit layer 50 and the gaps between the circuits. In an optional embodiment, the second etched layer 60 can be a prepreg. In another optional embodiment, the material of the second etched layer 60 can also be the same as the material of the first etched layer 20. In this embodiment, the surface of the second etched layer 60 away from the first etched layer 20 is parallel to the surface of the board 10.
[0069] S112: A blind hole is formed in the portion of the window in the second etch layer so that some components are exposed through the blind hole.
[0070] Specifically, the second etched layer 60 is made of a mixture of photocurable and thermocurable materials. Referring to Figure 3(j), the second etched layer 60 is processed by exposure and development to form blind vias 601 in the portion of the second etched layer 60 disposed in window 201, exposing the pins 103 and / or the surfaces of pins 103 not connected to the first circuit layer 50 through the blind vias 601. In a preferred embodiment, the second etched layer 60 is heat-treated to thermally cure and cross-link. Specifically, because both the first etched layer 20 and the second etched layer 60 are layers that can be etched by patterning, forming through-holes or blind vias through exposure and development processes, the blind vias 601 can achieve a sufficiently small inner diameter, for example, greater than or equal to 25 micrometers and less than 50 micrometers. The smaller the inner diameter of the blind vias 601, the larger the wiring space in the circuit board 1, and the higher the wiring density. Due to the small size of the blind vias 601, wiring space is saved, thereby enabling a high-density distribution of circuits. The inner diameter of the blind via 601 can be set according to the needs of the circuit board 1. For example, the inner diameter of the blind via 601 can be greater than or equal to 50 micrometers.
[0071] In another alternative embodiment, the second etched layer 60 is a prepreg or resin. A blind via 601 can be formed directly in the portion of the second etched layer 60 located in the window 201 by laser ablation, so that the pins 103 not connected to the first circuit layer 50 and / or the surfaces of pins 103 not connected to the first circuit layer 50 are exposed through the blind via 601.
[0072] S113: A second seed layer is formed in the blind hole and on the side of the second etch layer away from the first etch layer by means of copper plating or sputtering.
[0073] Specifically, referring to Figure 3(k), a second seed layer 70 is formed on the inner wall of the blind via 601 and on the surface of the second etched layer 60 away from the first etched layer 20 by means of copper plating or sputtering. The material of the second seed layer 70 can be the same as or different from the material of the first seed layer 30, as long as it can achieve conductivity. The thickness of the second seed layer 70 can be the same as the thickness of the first seed layer 30, or it can be slightly thinner than the thickness of the first seed layer 30.
[0074] S114: A through hole is formed in the blind hole, and the through hole connects to the component.
[0075] Specifically, referring to Figure 3(l), a metal conductor 702 is generated in the blind hole 601 by electroplating, so that the metal conductor 702 extends the portion of the pin 103 not connected to the first circuit layer 50 and / or the portion of the surface of the pin 103 not connected to the first circuit layer 50 to the side surface of the second etched layer 60 away from the board body 10.
[0076] In one specific embodiment, a metal conductor 702 is formed within the blind via 601 covered by the second seed layer 70 through electroplating, thereby transforming the blind via 601 into a via 701. The end of the via 701 near the board 10 is connected to a portion of the pin 103 not connected to the first circuit layer 50, or a portion of the surface of the pin 103 not connected to the first circuit layer 50. The metal conductor 702 in the blind via 601 directly connects to the portion of the pin 103 and / or the portion of the surface of the pin 103 not connected to the first circuit layer 50 of the component 102. This allows the heat generated by the component 102 to be dissipated through the first circuit layer 50 or directly transferred through the via 701, improving the heat dissipation performance of the circuit board 1. Furthermore, the inner diameter of the blind via 601 is smaller than the diameter of the pad of the pin 103.
[0077] S115: A second circuit layer is formed on the surface of the second etch layer away from the first etch layer.
[0078] Specifically, referring to Figure 3(m), a second metal layer 703 is formed on the surface of the second etched layer 60 away from the first etched layer 20 by electroplating. The metal conductor 702 can be a metal layer or a metal pillar.
[0079] In one specific embodiment, a second protective layer (not shown) is covered on the surface of the second metal layer 703 away from the second etch layer 60, and the second protective layer completely covers the second metal layer 703. A notch (not shown) is created in the second protective layer by exposure and development to expose a portion of the second metal layer 703. The exposed portion of the second metal layer 703 is etched by chemical etching to expose the portion of the second etch layer 60 covered by the second metal layer 703. The second protective layer is removed to expose the second circuit layer 90 formed by the second metal layer 703. A portion of the second circuit layer 90 is connected to the end of the via 701 away from the component 102. The via 701 allows direct communication between the pin 103 of the component 102 and the second circuit layer 90.
[0080] In another alternative embodiment, a second protective layer is directly applied to the surface of the second seed layer 70 away from the second etch layer 60, completely covering the second seed layer 70. A notch is created in the second protective layer by exposure and development to expose a portion of the second seed layer 70. The exposed portion of the second seed layer 70 is etched by chemical etching to expose the portion of the second etch layer 60 covered by the second seed layer 70. The second protective layer is then removed to expose the second circuit layer 90 formed by the second seed layer 70. A portion of the second circuit layer 90 is connected to the end of the via 701 away from the component 102. The via 701 allows direct communication between the pin 103 of the component 102 and the second circuit layer 90.
[0081] In another alternative embodiment, a second protective layer is applied to the surface of the second seed layer 70 away from the second etch layer 60, completely covering the second seed layer 70. A notch is created in the second protective layer by exposure and development to expose the second seed layer 70 within the blind via 601. Electroplating is used to form a metal conductor 702 within the blind via 601 to create a via 701, and filler metal is electroplated into the notch to form a second metal layer 703 on the surface of the second etch layer 60 away from the first etch layer 20. The second protective layer is then removed to expose the portion of the second seed layer 70 covered by the second protective layer. The exposed portion of the second seed layer 70 is etched by chemical etching to expose the portion of the second etch layer 60 covered by the second seed layer 70, allowing the second metal layer 703 to form the second circuit layer 90. A portion of the second circuit layer 90 is connected to the end of the via 701 away from the component 102. The via 701 allows direct communication between the pin 103 of the component 102 and the second circuit layer 90.
[0082] This embodiment provides a method for manufacturing a circuit board. By setting a second etch layer on a first etch layer, with the second etch layer partially disposed within a window formed by the first etch layer, the first circuit layer is connected to a portion of the pins and / or the surface of the pins of a component. A blind via is formed in the portion of the second etch layer disposed within the window, and a via is formed by electroplating. This allows the via to connect to the pins and / or the surface of the pins of the component that are not connected to the first circuit layer. This enables the second circuit layer to connect to the pins of the component through the via, allowing heat generated by the component to be conducted directly to the second circuit layer through the via and dissipated without needing to pass through the first circuit layer. This shortens the heat transfer path and improves the heat dissipation performance of the circuit board.
[0083] Please see Figure 4 and Figures 5(a) to 5(e) , Figure 4 This is a flowchart illustrating the second embodiment of the circuit board manufacturing method provided by the present invention; Figures 5(a) to 5(e) yes Figure 4 The provided circuit board manufacturing method includes a structural schematic diagram corresponding to the steps. This embodiment provides a method for manufacturing circuit board 1, which includes the following steps.
[0084] S201: Obtain the board body, which contains embedded components.
[0085] S202: A first etched layer is applied to the surface of the exposed components on the board.
[0086] S203: Expose the first etched layer to allow it to undergo photocuring and crosslinking.
[0087] S204: Perform a development process to form a window on the first etched layer so that components are exposed through the window.
[0088] S205: The first etched layer is heated to thermally cure and crosslink it.
[0089] S206: Form the first seed layer within the window.
[0090] Specifically, the specific implementation methods of steps S201 to S206 are the same as those of steps S101 to S106 in the above embodiments, and will not be repeated here.
[0091] S207: Electroplating is performed on the first seed layer to form a first metal layer at least on the exposed components of the window.
[0092] Specifically, referring to Figure 5(a), electroplating is used to cover the surface of the first etched layer 20 away from the board 10 and the surface of the component 102 exposed through the window 201 with electroplated metal, thereby forming a first metal layer 301 on the surface of the exposed component 102 and the surface of the first etched layer 20. In an optional embodiment, the surface of the first metal layer 301 away from the first etched layer 20 is flush-treated so that the surface of the first metal layer 301 away from the first etched layer 20 is parallel to the surface of the first etched layer 20. The thickness of the first metal layer 301 is less than the thickness of the first etched layer 20.
[0093] S208: A first protective layer is covered on the surface of the first metal layer away from the component.
[0094] Specifically, referring to Figure 5(b), a first protective layer 40 is applied to the surface of the first metal layer 301 away from the first etched layer 20 and the surface of the first metal layer 301 away from the component 102. The first protective layer 40 completely covers the first metal layer 301 and the surface of the first metal layer 301 in the window 201 away from the component 102. The first protective layer 40 can be a dry film or a photoresist. The material of the first protective layer 40 is a photosensitive resin, and the material of the first protective layer 40 contains photosensitive reactive groups. In an optional embodiment, the first protective layer 40 can also be filled into the first metal layer 301 disposed within the window 201.
[0095] S209: A through-hole is formed in the first protective layer so that a portion of the first metal layer is exposed through the through-hole.
[0096] Specifically, referring to Figure 5(c), since the material of the first protective layer 40 is a photosensitive resin, through-holes 401 can be formed on the first protective layer 40 by exposure and development, so that a portion of the first metal layer 301 disposed on the first etched layer 20 is exposed through the through-holes 401. Specifically, the through-holes 401 in the first protective layer 40 outside the window 201 are spaced apart from the window 201, so that a portion of the first seed layer 30 covered on the first etched layer 20 is exposed through the window 201. The through-holes 401 in the first protective layer 40 inside the window 201 are located between two adjacent pins 103, so that a portion of the first metal layer 301 covering the pins 103 of the component 102 inside the window 201 is exposed through the through-holes 401. In an optional embodiment, the position of the through-hole 401 can correspond to the position of a portion of the pins 103, so that the first metal layer 301 covering a portion of the pins 103 of the component 102 inside the window 201 is exposed through the through-holes 401. In another alternative embodiment, the via 401 may be positioned to correspond to a portion of the surface of the pin 103, so that the first metal layer 301 covering the portion of the surface of the pin 103 is exposed through the via 401.
[0097] S210: Etch the first metal layer to expose the surfaces between the pins of the component and parts of the pins and / or parts of the pin surfaces.
[0098] Specifically, referring to Figure 5(d), the first metal layer 301 exposed through the via 401 is etched using a wet chemical etching method to expose a portion of the first etched layer 20, a portion of the surface of the component 102, and a portion of the surface of the pin 103 and / or the pin 103 covered by the first metal layer 301. Alternatively, the first metal layer 301 exposed through the via 401 can be removed by plasma etching to expose a portion of the first etched layer 20, a portion of the surface of the component 102, and a portion of the surface of the pin 103 and / or the pin 103 covered by the first metal layer 301.
[0099] S211: Remove the first protective layer, and the first metal layer forms the first circuit layer.
[0100] Specifically, referring to Figure 5(e), the first protective layer 40 is removed to expose a portion of the first metal layer 301 covered by the first protective layer 40. The first metal layer 301, after the above steps, forms the first circuit layer 50. That is, after removing the first protective layer 40, the first metal layer 301 on the surface of the first etched layer 20 and the first metal layer 301 on the surface of the component 102 are patterned to form the first circuit layer 50. The first circuit layer 50 is connected to a portion of the pins 103 and / or a portion of the surface of the pins 103. Heat generated by the component 102 can be transferred and diffused through the first circuit layer 50.
[0101] S212: A second etching layer is provided on the side of the first etching layer away from the board body, so that a portion of the second etching layer is provided in the window.
[0102] S213: A blind hole is formed in the portion of the window in the second etch layer so that some components are exposed through the blind hole.
[0103] S214: A second seed layer is formed in the blind hole and on the side of the second etch layer away from the first etch layer by means of copper plating or sputtering.
[0104] S215: A through hole is formed in a blind hole, and the through hole connects to the component.
[0105] S216: A second circuit layer is formed on the surface of the second etch layer away from the first etch layer.
[0106] Specifically, the specific implementation methods of steps S212 to S216 are the same as those of steps S111 to S115 in the above embodiments, and will not be repeated here.
[0107] This embodiment provides a method for manufacturing a circuit board. By setting a second etch layer on a first etch layer, with the second etch layer partially disposed within a window formed by the first etch layer, the first circuit layer is connected to a portion of the pins and / or the surface of the pins of a component. A blind via is formed in the portion of the second etch layer disposed within the window, and a via is formed by electroplating. This allows the via to connect to the pins and / or the surface of the pins of the component that are not connected to the first circuit layer. This enables the second circuit layer to connect to the pins of the component through the via, allowing heat generated by the component to be conducted directly to the second circuit layer through the via and dissipated without needing to pass through the first circuit layer. This shortens the heat transfer path and improves the heat dissipation performance of the circuit board.
[0108] Please see Figure 6 and Figures 7(a) to 7(d) , Figure 6 This is a flowchart illustrating the third embodiment of the circuit board manufacturing method provided by the present invention; Figures 7(a) to 7(d) yes Figure 6 The provided electroplating method includes a structural schematic diagram corresponding to each step. This embodiment provides a method for manufacturing a circuit board 1, which includes the following steps.
[0109] S301: Obtain the board body, which contains embedded components.
[0110] S302: A first etched layer is applied to the surface of exposed components on the board.
[0111] S303: Expose the first etched layer to allow it to undergo photocuring and crosslinking.
[0112] S304: Perform a development process to form a window on the first etched layer so that components are exposed through the window.
[0113] S305: The first etched layer is heated to thermally cure and crosslink it.
[0114] S306: Form the first seed layer within the window.
[0115] S307: Cover the first protective layer on the first seed layer within the window.
[0116] Specifically, the specific implementation methods of steps S301 to S307 are the same as those of steps S101 to S107 in the above embodiments, and will not be repeated here.
[0117] S308: A through-hole is formed in the first protective layer so that the first seed layer covering a portion of the pin or a portion of the pin surface is exposed through the through-hole.
[0118] Specifically, referring to Figure 7(a), since the material of the first protective layer 40 is a photosensitive resin, through-holes 401 can be formed on the first protective layer 40 by exposure and development, so that a portion of the first seed layer 30 disposed on the first etched layer 20 is exposed through the through-holes 401. The positions of the through-holes 401 in the first protective layer 40 outside the window 201 are spaced apart from the position of the window 201, so that a portion of the first seed layer 30 covered on the first etched layer 20 is exposed through the window 201. The positions of the through-holes 401 in the first protective layer 40 inside the window 201 correspond to a portion of the pin 103 or a portion of the surface of the pin 103 of the component 102, so that a portion of the first seed layer 30 covering a portion of the pin 103 or a portion of the surface of the pin 103 of the component 102 inside the window 201 is exposed through the through-holes 401.
[0119] S309: Electroplating is used to form a first metal layer in the through hole.
[0120] Specifically, referring to Figure 7(b), electroplated metal is filled into the via 401 to form a first metal layer 301 on a portion of the pins 103 or a portion of the surface of the pins 103 of the component 102 covered by the exposed first seed layer 30. In an optional embodiment, the surface of the first metal layer 301 away from the first etch layer 20 is flush-treated so that the surface of the first metal layer 301 away from the first etch layer 20 is parallel to the surface of the first etch layer 20. The thickness of the first metal layer 301 is less than the thickness of the first etch layer 20.
[0121] S310: Remove the first protective layer to expose the first seed layer of the unplated portion.
[0122] Specifically, referring to Figure 7(c), the first protective layer 40 is removed to expose the portion of the first seed layer 30 covered by the first protective layer 40. That is, the first metal layer 301 is covered on a portion of the first etched layer 20 and the surface of a portion of the pin 103 or the surface of the pin 103 of the component 102, while the remaining portion is covered by the first seed layer 30, and the first seed layer 30 and the first metal layer 301 are alternately disposed on the surface of the first etched layer 20 and the component 102.
[0123] S311: Etching exposes the first seed layer, exposing the surface of some components and some pins or part of the pin surface, and the first metal layer forms the first circuit layer.
[0124] Specifically, referring to Figure 7(d), the exposed first seed layer 30 is removed by differential etching. The exposed first seed layer 30 is removed to form the first circuit layer 50 on the surface of the first etched layer 20 and the component 102. That is, the exposed first seed layer 30 is etched to expose the surface between the first etched layer 20 covered by the first seed layer 30 and the pins 103 of the component 102, as well as a portion of the pins 103 and / or a portion of the surface of the pins 103 on the component 102. The first etched layer 20 and the first metal layer 301 on the surface of the component form the first circuit layer 50.
[0125] S312: A second etching layer is provided on the side of the first etching layer away from the board body, so that a portion of the second etching layer is provided in the window.
[0126] S313: A blind hole is formed in the portion of the window in the second etch layer so that some components are exposed through the blind hole.
[0127] S314: A second seed layer is formed in the blind hole and on the side of the second etch layer away from the first etch layer by means of copper plating or sputtering.
[0128] S315: A through hole is formed in a blind via, and the through hole connects to components.
[0129] S316: A second circuit layer is formed on the surface of the second etch layer away from the first etch layer.
[0130] Specifically, the specific implementation methods of steps S312 to S316 are the same as those of steps S111 to S115 in the above embodiments, and will not be repeated here.
[0131] This embodiment provides a method for manufacturing a circuit board. By setting a second etch layer on a first etch layer, with the second etch layer partially disposed within a window formed by the first etch layer, the first circuit layer is connected to a portion of the pins and / or the surface of the pins of a component. A blind via is formed in the portion of the second etch layer disposed within the window, and a via is formed by electroplating. This allows the via to connect to the pins and / or the surface of the pins of the component that are not connected to the first circuit layer. This enables the second circuit layer to connect to the pins of the component through the via, allowing heat generated by the component to be conducted directly to the second circuit layer through the via and dissipated without needing to pass through the first circuit layer. This shortens the heat transfer path and improves the heat dissipation performance of the circuit board.
[0132] The above description is merely an embodiment of the present invention and does not limit the scope of patent protection of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.
Claims
1. A circuit board, characterized in that, The circuit board includes: The plate body has grooves on it; A component is disposed in the groove, the component has a back surface and a bottom surface disposed opposite to the back surface, and the bottom surface of the component is provided with pins; A first etched layer is disposed on the side surface of the plate body where the groove is located. A window is provided on the first etched layer, and the components are disposed corresponding to the window. The first etched layer is formed by mixing and curing a photocurable material and a thermocurable material. The second etched layer is disposed on the side of the first etched layer away from the board body, and is partially located within the window; the second etched layer is provided with blind holes, which penetrate the portion of the second etched layer corresponding to the window; the second etched layer, the first etched layer, and the pins of the component are disposed on the same side of the board body, and the second etched layer is a prepreg or resin; The inner diameter of the blind hole is smaller than the inner diameter of the window and smaller than the diameter of the pin pad on the component. The blind hole has an electroplated layer to form a through hole. The through hole connects to the pin of the component and is used to directly dissipate the heat at the pin of the component to the outside.
2. The circuit board according to claim 1, characterized in that, The circuit board further includes a first circuit layer disposed between the first etched layer and the second etched layer. The circuit board also includes a second circuit layer disposed on the surface of the second etched layer away from the board body. The second circuit layer is connected to the portion of the pin that is not connected to the first circuit layer through the via.
3. A method for manufacturing a circuit board, characterized in that, The manufacturing method includes: Obtain a board body, wherein components are embedded in the board body; A first etching layer is provided on the surface of the exposed component on the board. The component has a back surface and a bottom surface opposite to the back surface. The bottom surface of the component is provided with pins. The first etched layer is exposed to allow it to undergo photocuring and cross-linking. A development process is performed to form a window on the first etched layer, so that the bottom surface of the component is exposed through the window; the first etched layer is then subjected to a heat treatment to thermally cure and crosslink the first etched layer, wherein the material of the first etched layer is a photosensitive resin. A second etching layer is provided on the side of the first etching layer away from the board body, so that a portion of the second etching layer is provided in the window; the second etching layer, the first etching layer, and the pins of the component are provided on the same side of the board body, and the second etching layer is a prepreg or resin; The circuit board further includes a first circuit layer disposed between the first etch layer and the second etch layer; blind vias are formed in the portion of the second etch layer disposed in the window by laser drilling, so that the portion of the pins of the component not connected to the first circuit layer and / or the portion of the surface of the pins are exposed through the blind vias; or, the second etch layer is processed by exposure and development to form the blind vias in the portion of the second etch layer disposed in the window, so that the portion of the pins of the component not connected to the first circuit layer and / or the portion of the surface of the pins are exposed through the blind vias. A via is formed in the blind via, the via is connected to the pin of the component, and the via is used to directly dissipate the heat at the pin of the component to the outside.
4. The method for manufacturing a circuit board according to claim 3, characterized in that, The steps preceding the formation of the via in the blind hole include: A second seed layer is formed inside the blind via and on the side of the second etched layer away from the first etched layer by means of copper plating or sputtering.
5. The method for manufacturing a circuit board according to claim 4, characterized in that, Following the step of forming a second seed layer within the blind via and on the side of the second etched layer away from the first etched layer by means of copper plating or sputtering, the method further includes: A second circuit layer is formed on the surface of the second etched layer that is away from the first etched layer.