A circuit board and a method for manufacturing a circuit board

Abstract

This invention discloses a circuit board and a method for manufacturing the same. The method includes: providing a board body with a metal block embedded within it; opening a first blind hole on the surface of the board body corresponding to the position of the metal block, allowing the metal block to be exposed through the first blind hole; and forming a first metal conductor within the first blind hole, the first metal conductor connecting to the metal block and exposed on one side of the board body. This invention improves the manufacturing process of the circuit board by pre-embedding a metal block within the board body, opening a first blind hole on the surface of the board body corresponding to the position of the metal block, and generating a first metal conductor within the first blind hole, thereby achieving conductivity between the metal block and the first metal conductor, and also enhancing the heat dissipation performance of the circuit board.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and in particular to a circuit board and a method for manufacturing the same. Background Technology

[0002] As electronic products rapidly develop towards being lighter, thinner, smaller, higher-density, and more multifunctional, the size of electronic components and logic circuits has shrunk dramatically, and the vias in circuit boards have become smaller and smaller.

[0003] However, since vias are generally formed by electroplating inside the hole, the electroplating process becomes increasingly difficult as the hole diameter becomes smaller and smaller. Summary of the Invention

[0004] The main technical problem solved by this invention is to provide a circuit board and a method for manufacturing the circuit board, thereby solving the technical problem of how to form vias in circuit boards in the prior art.

[0005] To solve the above-mentioned technical problems, the first technical solution adopted by the present invention is: to provide a method for manufacturing a circuit board, the method comprising: providing a board body, wherein a metal block is embedded in the board body; opening a first blind hole on the surface of the board body corresponding to the position of the metal block, so that the metal block is exposed through the first blind hole; forming a first metal conductor in the first blind hole, wherein the first metal conductor connects to the metal block and is exposed on one side of the board body.

[0006] The step of opening a first blind hole on the surface of the plate corresponding to the metal block position includes: opening a first blind hole on the surface of the plate corresponding to the metal block position by laser drilling, wherein the diameter of the first blind hole is smaller than the length or width of the metal block.

[0007] The formation of the first metal conductor in the first blind hole includes: forming the first metal conductor in the first blind hole by electroplating, wherein the first metal conductor is connected to the metal block and the circuit layer on the outer side of the board.

[0008] The step of providing a plate body with a metal block embedded in it includes: providing a carrier; sequentially stacking and pressing a first sub-dielectric layer, a first sub-metal layer, and a second sub-metal layer on the carrier; generating a metal block on the surface of the second sub-metal layer away from the first sub-metal layer; stacking and pressing a second sub-dielectric layer and a third sub-metal layer on the side surface of the second sub-metal layer where the metal block is formed; separating the plate from the second sub-metal layer and the first sub-metal layer; and removing the third sub-metal layer and the second sub-metal layer from both sides of the second sub-dielectric layer.

[0009] The step of providing a plate body and embedding a metal block in the plate body further includes: pressing a first dielectric layer and a second dielectric layer on opposite sides of the second sub-dielectric layer in which the metal block is embedded; setting a first metal layer and a second metal layer on the opposite side of the first dielectric layer and the second dielectric layer from the second sub-dielectric layer; or pressing a first core plate and a second core plate on opposite sides of the second sub-dielectric layer in which the metal block is embedded, wherein the first dielectric layer of the first core plate and the second dielectric layer of the second core plate are respectively connected to the surface of the second sub-dielectric layer.

[0010] The method includes: opening a second blind hole on the side of the plate opposite to the first blind hole; forming a second metal conductor in the second blind hole, the second metal conductor being connected to a metal block and exposed on one side of the plate; wherein the first blind hole penetrates the first dielectric layer, the second blind hole penetrates the second dielectric layer, the first metal conductor is connected to the first metal layer, and the second metal conductor is connected to the second metal layer.

[0011] To solve the above-mentioned technical problems, the second technical solution adopted by the present invention is: to provide a circuit board, the circuit board comprising: a board body; a metal block embedded in the board body; wherein, at least one surface of the board body is provided with a blind hole, a metal conductor is provided in the blind hole, the metal conductor is connected to the metal block and exposed in the blind hole.

[0012] The plate body includes a stacked core plate and a dielectric layer. A metal block is disposed in the core plate, with one side of the metal block exposed on one side of the core plate. The exposed side of the metal block is covered by the dielectric layer. The diameter of the blind hole is smaller than the length or width of the metal block.

[0013] In this design, a metal layer is disposed on the surface of the dielectric layer away from the core board, and a metal conductor is connected to the metal layer.

[0014] Among them, the metallic conductor is a conductive pillar.

[0015] The core board is made of at least one of epoxy resin, polyimide, and molding compound, and the dielectric layer is made of a semi-cured material or resin.

[0016] The beneficial effects of the present invention are as follows: Unlike the prior art, this application pre-embeds a metal block in the circuit board and then opens a first blind hole on the surface of the board corresponding to the position of the metal block to generate a first metal conductor. Therefore, it is not necessary to form a through hole for the entire thickness of the board. It is only necessary to form a through hole on one side of the metal block. This facilitates the electroplating process with smaller hole diameter, achieves smaller through hole spacing and higher precision, and improves the heat dissipation performance of the circuit board. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic flowchart of an embodiment of the circuit board manufacturing method provided by the present invention;

[0019] Figures 2 to 16 yes Figure 1 A schematic diagram of step S11 in the provided circuit board manufacturing method;

[0020] Figures 17-19 yes Figure 1 A schematic diagram of step S12 in the provided circuit board manufacturing method;

[0021] Figures 20-22 yes Figure 1 A schematic diagram of step S13 in the provided circuit board manufacturing method;

[0022] Figure 23 This is a schematic diagram of a circuit board embodiment provided by the present invention. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0024] The terms "first," "second," and "third" used in this invention are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this invention are only used to explain the relative positional relationships and movement of components in a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications will also change accordingly. The terms "comprising" and "having," and any variations thereof, in the embodiments of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or components inherent to these processes, methods, products, or devices.

[0025] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of phrases in various places throughout the specification does not necessarily refer to the same embodiment, nor are they independent or alternative embodiments mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0026] As electronic products rapidly develop towards being lighter, thinner, smaller, higher-density, and more multifunctional, the size of electronic components and logic circuits has shrunk dramatically, while operating frequencies have increased dramatically and power consumption has continued to rise. This has led to a change in the operating environment of components towards higher temperatures, placing increasingly higher demands on the heat dissipation of circuit boards. If there is no good heat dissipation method to remove the heat generated by electrons, these excessively high temperatures will cause phenomena such as electron ionization and thermal stress in electronic components, resulting in reduced overall stability and shortened lifespan of the electronic components themselves.

[0027] Currently, through-holes are directly drilled on the printed circuit board, and a copper layer is formed on the inner wall of the through-holes to achieve electrical conduction between board layers or to solve the heat dissipation problem of the circuit board. However, electroplating across the entire board thickness is difficult, and the heat dissipation capacity of the copper layer on the inner wall of the through-holes is limited, resulting in a minimal improvement in the heat dissipation of the circuit board.

[0028] Please see Figure 1 , Figure 1 This is a schematic flowchart of an embodiment of the circuit board manufacturing method provided by the present invention. In this embodiment, the circuit board manufacturing method includes the following steps.

[0029] S11: Provides a plate body, in which a metal block is embedded.

[0030] Please see Figures 2 to 16 , Figures 2 to 16 yes Figure 1 A schematic diagram of step S11 in the provided circuit board manufacturing method. For details, please refer to... Figures 2 to 10 A carrier 113 is provided, on which a first sub-dielectric layer 114, a first sub-metal layer 115, and a second sub-metal layer 116 are sequentially stacked and pressed together. A cover layer 117 is formed on the surface of the second sub-metal layer 116 away from the first sub-metal layer 115. A window 111 is formed on the cover layer 117 by exposure and development to expose a portion of the second sub-metal layer 116 through the window 111. A metal block 2 is formed in the window 111 by electroplating, and the exposed surface of the metal block 2 is flush with the surface of the cover layer 117 away from the second sub-metal layer 116. The cover layer 117 is then removed to expose the portion of the second sub-metal layer 116 covered by the cover layer 117. A second sub-dielectric layer 11 and a third sub-metal layer 118 are sequentially stacked and pressed together on one side surface of the metal block 2 formed in the second sub-metal layer 116. The metal block 2 is embedded in the second sub-dielectric layer 11, and one side surface of the second sub-metal layer 116 with the metal block 2 is connected to the second sub-dielectric layer 11. A separation is performed between the second sub-metal layer 116 and the first sub-metal layer 115. The third sub-metal layer 118 and the second sub-metal layer 116 on both sides of the second sub-dielectric layer 11 are removed by etching. The carrier 113 can be a core board, a glass plate, or a steel plate. The thickness of the second sub-dielectric layer 11 with the embedded metal block 2 can be adjusted arbitrarily according to the thickness of the metal block 2 and the second sub-dielectric layer 11, without being limited by the material. The increased area of ​​the metal block 2 facilitates heat dissipation. The first sub-dielectric layer 114 and the second sub-dielectric layer 11 are made of prepreg, and the first sub-metal layer 115, the second sub-metal layer 116, and the third sub-metal layer 118 can all be made of copper foil.

[0031] In another alternative embodiment, please refer to Figure 11 Mounting holes 112 are provided on the second sub-medium layer 11, wherein the mounting holes 112 are spaced apart from the metal block 2.

[0032] Please see Figure 12 An adhesive layer 16 is adhered to one surface of the second sub-dielectric layer 11 so that the adhesive layer 16 completely covers the mounting hole 112. The adhesive layer 16 is adhered to the surface of the second sub-dielectric layer 11 opposite to the metal block 2; alternatively, the adhesive layer 16 can be adhered to the surface of the second sub-dielectric layer 11 that is also adjacent to the metal block 2. Please refer to [link to relevant documentation]. Figure 13A component 3 is placed inside the mounting hole 112 so that the pins 31 on the component 3 are bonded to the adhesive layer 16 to fix the position of the component 3 within the mounting hole 112 and prevent the component 3 from drifting during the pressing process. The adhesive layer 16 can be adhesive tape.

[0033] Please see Figure 14 A first core board is stacked on the surface of the second sub-dielectric layer 11 away from the adhesive layer 16. The first core board includes a first dielectric layer 12 and a first metal layer 14 disposed on one surface of the first dielectric layer 12. The surface of the first dielectric layer 12 away from the first metal layer 14 is connected to the surface of the second sub-dielectric layer 11. In one specific embodiment, the surface of the first dielectric layer 12 away from the first metal layer 14 contacts the surface of the metal block 2 and the surface of the component 3 away from the pin 31. The material of the first dielectric layer 12 is a prepreg or resin. During the lamination process, the first dielectric layer 12 exhibits a fluid dynamic under high temperature conditions, which can fill the gap between the component 3 and the second sub-dielectric layer 11.

[0034] Please see Figure 15 Remove the adhesive layer 16 on the second sub-dielectric layer 11 to expose the pin 31 to the surface of the second sub-dielectric layer 11.

[0035] Please see Figure 16 A second core board is stacked and laminated on the surface of the exposed pins 31 of the second sub-dielectric layer 11. The second core board includes a second dielectric layer 13 and a second metal layer 15 disposed on one surface of the second dielectric layer 13. The surface of the second dielectric layer 13 away from the second metal layer 15 is connected to the surface of the second sub-dielectric layer 11. The material of the second dielectric layer 13 is a prepreg or resin. During the lamination process, the second dielectric layer 13 exhibits a fluid dynamic under high temperature conditions, which can fill the gaps between the pins 31 of the component 3.

[0036] S12: A first blind hole is made on the surface of the plate corresponding to the position of the metal block, so that the metal block is exposed through the first blind hole.

[0037] Please see Figures 17 to 19 , Figures 17-19 yes Figure 1 A schematic diagram of step S12 in the provided circuit board manufacturing method. Specifically, a first blind hole 121 is formed on the surface of the board 1 corresponding to the position of the metal block 2 by laser drilling. Optionally, the diameter of the first blind hole 121 is smaller than the length or width of the metal block 2; of course, it can also be equal to the length or width of the metal block 2, depending on the situation.

[0038] In another specific embodiment, protective layers are respectively applied to the surfaces of the first metal layer 14 and the second metal layer 15 away from the second sub-dielectric layer 11. Specifically, please refer to... Figure 11 and Figure 12A first protective layer 123 is applied to the first metal layer 14. A first window 124 is formed on the first protective layer 123 by exposure and development, so that a portion of the first metal layer 14 is exposed through the first window 124. The exposed portion of the first metal layer 14 corresponds to the position of the metal block 2. Please refer to... Figure 13 The exposed portion of the first metal layer 14 is removed by etching, exposing a portion of the first dielectric layer 12 through the window. Specifically, the exposed first metal layer 14 can be removed by chemical etching to expose a portion of the first dielectric layer 12; alternatively, the exposed portion of the first metal layer 14 can be removed by plasma etching to expose a portion of the first dielectric layer 12. The exposed portion of the first dielectric layer 12 is then removed by laser drilling to expose the surface of the metal block 2, thereby forming a first blind via 121. That is, the first blind via 121 penetrates the first dielectric layer 12, and the surface of the metal block 2 is exposed through the first blind via 121.

[0039] A second protective layer 133 is applied to the second metal layer 15. A second window 134 is formed on the second protective layer 133 by exposure and development, exposing a portion of the second metal layer 15 through the second window 134. The exposed portion of the second metal layer 15 corresponds to the position of the metal block 2. The exposed portion of the second metal layer 15 is removed by etching, exposing a portion of the second dielectric layer 13 through the second window 134. Specifically, the exposed second metal layer 15 can be removed by chemical etching, exposing a portion of the second dielectric layer 13; alternatively, the exposed portion of the second metal layer 15 can be removed by plasma etching, exposing a portion of the second dielectric layer 13. The exposed portion of the second dielectric layer 13 is removed by laser drilling, exposing the surface of the metal block 2, thereby forming a second blind via 131. That is, the surface of the metal block 2 is exposed through the second blind via 131. The second blind via 131 penetrates the second dielectric layer 13. The dimensions of the second blind via 131 and the first blind via 121 may be the same or different. The diameter of the second blind hole 131 only needs to be smaller than the length or width of the metal block 2. In an optional embodiment, the central axes of the first blind hole 121, the second blind hole 131, and the metal block 2 can coincide; or the central axes of the first blind hole 121, the second blind hole 131, and the metal block 2 can be independent of each other. The central axis of the second blind hole 131 can coincide with the central axis of the first blind hole 121, resulting in faster heat dissipation. The central axis of the second blind hole 131 can also not coincide with the central axis of the first blind hole 121, resulting in more balanced heat dissipation throughout the circuit board 100.

[0040] The positions of the first blind via 121 and the second blind via 131 are determined by chemical etching or plasma etching of the first metal layer 14 and / or the second metal layer 15, thereby improving the positional accuracy of the first blind via 121 and the second blind via 131.

[0041] In another optional embodiment, a third window 135 is formed on the second protective layer 133 by exposure and development, so that a portion of the second metal layer 15 is exposed through the third window 135, and the exposed portion of the second metal layer 15 corresponds to the position of the pin 31 of the component 3. The portion of the second metal layer 15 exposed through the third window 135 is removed by etching, so that a portion of the second dielectric layer 13 is exposed through the third window 135. Specifically, the second metal layer 15 exposed through the third window 135 can be removed by chemical etching, so that a portion of the second dielectric layer 13 is exposed; or the portion of the second metal layer 15 exposed through the third window 135 can be removed by plasma etching, so that a portion of the second dielectric layer 13 is exposed. The exposed portion of the second dielectric layer 13 is removed by laser drilling, so that the pin 31 of the component 3 is exposed, thereby forming a third blind via 136. That is, the third blind via 136 penetrates the second dielectric layer 13, and the pin 31 of the component 3 is exposed through the third blind via 136.

[0042] S13: A first metal conductor is formed in the first blind hole, the first metal conductor is connected to the metal block and exposed on one side of the plate.

[0043] Please see Figures 20 to 22 , Figures 20-22 yes Figure 1 A schematic diagram of step S13 in the provided circuit board manufacturing method. For details, please refer to... Figure 20 A first metal conductor 122 is formed in the first blind via 121 by electroplating. The first metal conductor 122 is conductive to both the metal block 2 and the outer circuit layer of the board 1. The first metal conductor 122 is formed in the first blind via 121 by electroplating, so that one end of the first metal conductor 122 is conductive to the metal block 2 and the other end is conductive to the first metal layer 14. In an optional embodiment, the surface of the first metal conductor 122 away from the metal block 2 is flush with the surface of the protective layer away from the first metal layer 14; or the surface of the first metal conductor 122 away from the metal block 2 is flush with the surface of the protective layer connected to the first metal layer 14. A second metal conductor 132 is formed in the second blind via 131 by electroplating, so that one end of the second metal conductor 132 is conductive to the metal block 2 and the other end is conductive to the second metal layer 15. A third metal conductor 137 is formed in the third blind via 136, so that one end of the third metal conductor 137 is conductive to the pin 31 of the component 3 and the other end is conductive to the second metal layer 15. In one optional embodiment, the surface of the second metal conductor 132 away from the metal block 2 is flush with the surface of the protective layer away from the second metal layer 15; or the surface of the second metal conductor 132 away from the metal block 2 is flush with the surface of the protective layer connected to the second metal layer 15. The first metal conductor 122 can be a metal layer or a metal pillar.

[0044] In another alternative embodiment, please refer to Figure 21 and Figure 22 The first protective layer 123 and the second protective layer 133 are removed, and the first metal conductor 122 is flushed so that the surface of the first metal conductor 122 away from the metal block 2 is flush with the surface of the first metal layer 14 away from the second sub-dielectric layer 11. The second metal conductor 132 and the third metal conductor 137 are flushed so that the end face of the second metal conductor 132 away from the metal block 2 and the end face of the third metal conductor 137 away from the pin 31 of the component 3 are flush with the surface of the second metal layer 15 away from the second sub-dielectric layer 11.

[0045] In an alternative embodiment, the first metal layer 14 and / or the second metal layer 15 are patterned to form a circuit layer.

[0046] This embodiment provides a method for manufacturing a circuit board. By pre-embedding a metal block in the circuit board and then opening a first blind hole on the surface of the board corresponding to the position of the metal block to generate a first metal conductor, it is not necessary to form a through hole for the entire thickness of the board. Only a through hole needs to be formed on one side of the metal block. This facilitates electroplating processes with smaller hole diameters, achieves smaller through hole spacing and higher precision, and improves the heat dissipation performance of the circuit board.

[0047] Please see Figure 23 , Figure 23 This is a schematic diagram of a circuit board according to an embodiment of the present invention. The circuit board 100 provided in this embodiment includes a board body 1 and a metal block 2. The metal block 2 is embedded in the board body 1, and at least one surface of the board body 1 is provided with a blind hole. A metal conductor is provided in the blind hole, and the metal conductor is connected to the metal block 2 and exposed in the blind hole.

[0048] In one specific embodiment, the plate body 1 includes a core plate 11 stacked together and a first dielectric layer 12 and / or a second dielectric layer 13 disposed on the surface of the core plate 11. A first metal layer 14 is disposed on the surface of the first dielectric layer 12 away from the core plate 11, and a second metal layer 15 is disposed on the surface of the second dielectric layer 13 away from the core plate 11. A metal block 2 is embedded in the core plate 11 and exposed on one surface of the core plate 11.

[0049] In one embodiment, a first dielectric layer 12 is disposed on the surface of the exposed metal block 2 of the core board 11, and the dielectric layer completely covers the surface of the exposed metal block 2 of the core board 11. In another embodiment, a second dielectric layer 13 is disposed on the surface of the core board 11 away from the first dielectric layer 12. In one embodiment, the material of the core board 11 is at least one of organic materials such as epoxy resin, polyimide, and molding compound.

[0050] In an optional embodiment, a first blind hole 121 is provided on one surface of the board 1. The first blind hole 121 is filled with a first metal conductor 122, and one end of the first metal conductor 122 is connected to the metal block 2. The position of the first blind hole 121 corresponds to the position of the metal block 2. A second blind hole 131 is provided on the surface of the board 1 away from the first blind hole 121. The second blind hole 131 is filled with a second metal conductor 132, and one end of the second metal conductor 132 is connected to the metal block 2. That is, the metal block 2 connects the first metal conductor 122 and the second metal conductor 132 to achieve conductivity between the two surfaces of the circuit board 100. The first metal conductor 122 and the second metal conductor 132 can be at least one of a metal layer or a metal pillar. The diameter of both the first blind hole 121 and the second blind hole 131 is smaller than the length or width of the metal block 2. The diameter of the first blind hole 121 can be the same as or different from the diameter of the second blind hole 131. The first dielectric layer 12 and the second dielectric layer 13 are made of at least one of prepreg and resin. A first blind via 121 penetrates the first dielectric layer 12. A second blind via 131 penetrates the second dielectric layer 13.

[0051] In another optional embodiment, a component 3 is embedded in the board 1. The component 3 is embedded in the core board 11 and spaced apart from the metal block 2. The pins 31 of the component 3 are in contact with the surface of the second dielectric layer 13 away from the second metal layer 15. A third blind via 136 is provided on the board 1, and a third metal conductor 137 is disposed in the third blind via 136. One end of the third metal conductor 137 is connected to the pin 31, and the other end is connected to the second metal layer 15. The third blind via 136 is spaced apart from the second blind via 131. The third blind via 136 penetrates the second dielectric layer 13.

[0052] The circuit board provided in this embodiment includes a board body with a metal block embedded in it. At least one surface of the board body has a blind hole containing a metal conductor that connects to the metal block and is exposed within the blind hole. Specifically, by embedding the metal block within the board body and forming a first metal conductor and a second metal conductor on the corresponding surfaces of the board body and the metal block, the first and second metal conductors are made conductive to the opposite surfaces of the metal block, thereby achieving conductivity between the upper and lower surfaces of the board body and improving heat dissipation performance. The diameters of the first and second blind holes are smaller than the length or width of the metal block. This improves the heat dissipation performance of the circuit board while reducing the size of the metal conductors on the board surface, thereby reducing the spacing between circuits and achieving a high-density circuit distribution.

[0053] The above are merely embodiments of the present invention and do not limit the scope of patent protection of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A method of manufacturing a wiring board, characterized by, The manufacturing method includes: A plate is provided, in which a metal block is embedded, including: Provide a carrier; A first sub-dielectric layer, a first sub-metal layer, and a second sub-metal layer are sequentially stacked and pressed together on the carrier. A metal block for heat dissipation is formed on the surface of the second sub-metal layer away from the first sub-metal layer; A second sub-dielectric layer and a third sub-metal layer are stacked and pressed together on one side surface of the metal block formed by the second sub-metal layer; Separate the plates between the second sub-metal layer and the first sub-metal layer; Remove the third sub-metal layer and the second sub-metal layer from both sides of the second sub-dielectric layer; A first blind hole is made on the surface of the plate corresponding to the position of the metal block, so that the metal block is exposed through the first blind hole; A first metal conductor is formed within the first blind hole, the first metal conductor connecting the metal block and being exposed on one side of the plate; The second sub-dielectric layer has mounting holes for mounting components. A first core board and a second core board are respectively pressed onto opposite sides of the second sub-dielectric layer. The first core board includes a first dielectric layer and a first metal layer located on the side of the first dielectric layer away from the second sub-dielectric layer. The second core board includes a second dielectric layer and a second metal layer located on the side away from the second sub-dielectric layer. The first dielectric layer is used to fill the gap between the components and the second sub-dielectric layer at high temperatures, and the second dielectric layer is used to fill the gap between the pins of the components at high temperatures. A second blind hole and a third blind hole are made on the side of the plate opposite to the first blind hole; A second metal conductor is formed inside the second blind via, the second metal conductor is connected to the metal block and exposed on one side of the plate; the first blind via penetrates the first dielectric layer, the second blind via and the third blind via penetrate the second dielectric layer, the first metal conductor is connected to the first metal layer, and the second metal conductor is connected to the second metal layer; the third blind via is provided with a pin for connecting components and a third metal conductor of the second metal layer.

2. The method for manufacturing a circuit board according to claim 1, wherein The step of opening the first blind hole on the surface of the plate corresponding to the position of the metal block includes: The first blind hole is made on the surface of the plate corresponding to the position of the metal block by laser drilling. The diameter of the first blind hole is smaller than the length or width of the metal block.

3. The method of manufacturing a circuit board according to claim 1, wherein The formation of the first metallic conductor within the first blind hole includes: The first metal conductor is formed in the first blind hole by electroplating, and the first metal conductor is connected to the metal block and the circuit layer on the outer side of the board.

Images