High-fidelity waveform generator for qubit controller

Abstract

The qubit controller includes an in-phase path and a quadrature path. A first combiner is configured to combine the output of the in-phase path with the output of the quadrature path to create a single sideband. A splitter is provided, configured to divide the single sideband into N parts, providing a first part of the N parts to a qubit corresponding to the qubit controller, and providing each of the remaining N-1 parts to an adjacent qubit controller of a qubit cluster, the qubit cluster comprising qubits corresponding to the qubit controller. A second combiner is configured to combine the first part with N-1 feedback signals received from these adjacent qubit controllers of the qubit cluster.

Description

Technical Field

[0001] This disclosure relates generally to superconducting devices, and more specifically to scalable qubit architectures. Background Technology

[0002] Description of related technologies: Superconducting quantum computing is the realization of a quantum computer in superconducting electronic circuits. Quantum computing studies the application of quantum phenomena in information processing and communication. Various models of quantum computing exist, with the most popular models including the concepts of qubits and quantum gates. A qubit is a generalization of a bit having two possible states, but can exist in a quantum superposition of the two states. A quantum gate is a generalization of logic gates; however, it describes the transformation that one or more qubits will undergo after the gate is applied to them, given their initial states. Summary of the Invention

[0003] According to various embodiments, methods and apparatus for controlling qubits in a qubit cluster are provided. The qubit controller includes an in-phase path and a quadrature path. A first combiner is configured to combine the output of the in-phase path with the output of the quadrature path to create a single sideband. A splitter is configured to divide the single sideband into N portions; provide a first portion of the N portions to a qubit corresponding to the qubit controller; and provide each of the remaining N-1 portions to an adjacent qubit controller of the qubit cluster, the qubit cluster including qubits corresponding to the qubit controller. A second combiner is configured to combine the first portion with N-1 feedback signals received from the adjacent qubit controllers of the qubit cluster.

[0004] In one embodiment, the in-phase path includes: a first digital-to-analog converter (DAC) configured to receive an in-phase signal at a first frequency; and a first mixer configured to mix the output of the first DAC with a second in-phase frequency to create a third in-phase frequency at the output of the in-phase path.

[0005] In one embodiment, the quadrature phase path includes: a second digital-to-analog converter configured to receive a quadrature signal of a first frequency; and a second mixer configured to mix the output of the second digital-to-analog converter with a second quadrature frequency to generate a third quadrature frequency at the output of the quadrature path.

[0006] In one embodiment, the in-phase signal at a first frequency is shared among adjacent qubit controllers of the qubit cluster. The quadrature signal at the first frequency is shared among these adjacent qubit controllers of the qubit cluster. The in-phase signal at a second frequency is shared among the adjacent qubit controllers of the qubit cluster. Furthermore, the quadrature signal at the second frequency is shared among these adjacent qubit controllers of the qubit cluster.

[0007] In one embodiment, each of these adjacent qubit controllers is configured to control one qubit of the qubit cluster.

[0008] In one embodiment, the combined operation of the first part of the second combiner and the N-1 feedback signals is used to subtract the crosstalk contribution of the capacitive coupling of the qubit cluster.

[0009] In one embodiment, the cluster is based on a set of different center frequencies for the qubits in the cluster.

[0010] In one embodiment, a matching network is coupled to the output of the second combiner. The matching network can be configured to provide maximum power transfer to the corresponding qubit. The matching network can also be configured to filter out spurious signals introduced by at least one of the second in-phase frequency and the second quadrature frequency, which are located away from a center frequency corresponding to the qubit of the qubit controller.

[0011] In one embodiment, the splitter is a current-mode splitter. The first signal can be current.

[0012] In one embodiment, the number N is based on the number of qubits in the cluster.

[0013] In one embodiment, the qubit controller is configured to operate at low temperatures in a dilution refrigerator.

[0014] These and other features will become apparent from the following detailed description of illustrative embodiments thereof, which will be read in conjunction with the accompanying drawings. Attached Figure Description

[0015] The accompanying drawings are illustrative embodiments. They do not show all embodiments. Other embodiments may be used additionally or alternatively. Details that may be obvious or unnecessary may be omitted to save space or for more efficient illustration. Some embodiments may be practiced with additional components or steps and / or all components or steps not shown. When the same number appears in different drawings, it refers to the same or similar parts or steps.

[0016] Figure 1 An example architecture of a quantum computing system according to an illustrative embodiment is shown.

[0017] Figure 2 This is a block diagram of a quantum array system consistent with the illustrative embodiments.

[0018] Figure 3 This is a block diagram of a single channel quantum controller consistent with the illustrative embodiment.

[0019] Figure 4 This is a block diagram of a single channel of a quantum controller that receives feedback from an adjacent qubit controller, consistent with the illustrative embodiment.

[0020] Figure 5 This is a block diagram of a distributed current mode elimination system consistent with the illustrative embodiment.

[0021] Figure 6 Provided with Figure 4 A simplified block diagram of the double-sideband implementation of the quantum controller for the circuit-level components of the separator.

[0022] Figure 7 A simplified block diagram of a single-sideband implementation of a quantum controller is provided.

[0023] Figure 8 This is a block diagram illustrating an example frequency planning of qubits at the center frequency of a qubit array, consistent with the illustrative embodiment. Detailed Implementation

[0024] Overview

[0025] In the following detailed description, numerous specific details are illustrated by way of example to provide a thorough understanding of the relevant teachings. However, it should be clear that this teaching can be practiced without such details. In other cases, well-known methods, processes, components, and / or circuits have been described at a relatively high level without detailed description to avoid unnecessarily obscuring aspects of this teaching.

[0026] This disclosure generally relates to superconducting devices, and more specifically to low-noise, power-efficient, and scalable qubit architectures. The electromagnetic energy associated with a qubit can be stored in a so-called Josephson junction and in capacitive and inductive elements used to form the qubit. In one example, to read out the qubit state, a microwave signal is applied to a microwave readout cavity coupled to the qubit at that cavity frequency. For example, the qubit can be directly excited by an electrical waveform from a qubit controller having predetermined amplitude, phase, and frequency. The frequency of this excitation waveform can be the resonant frequency of the qubit, and the shape of the waveform provided by the qubit controller can be Gaussian or a set of its derivatives. Each qubit can also be excited by another qubit weakly coupled using a capacitive mechanism, sometimes referred to herein as crosstalk.

[0027] The transmitted (or reflected) microwave signal passes through multiple thermal isolation stages and low-noise amplifiers to block or reduce noise and improve the signal-to-noise ratio. Most of the process can be carried out in a cold environment (e.g., in a low-temperature room), while the microwave signal of the qubit is ultimately measured at room temperature. The amplitude and / or phase of the returned / output microwave signal carry information about the qubit's state, such as whether the qubit has phase-shifted to the ground or excited state. The microwave signal carrying quantum information about the qubit's state is typically very weak (e.g., on the order of a few microwave photons). To measure this weak signal with room-temperature electronics (i.e., outside of a refrigerated environment), low-noise quantum limiting amplifiers (QLAs) (such as Josephson amplifiers and traveling-wave parametric amplifiers (TWPAs)) can be used as preamplifiers (i.e., the first amplification stage) at the output of the quantum system to amplify the quantum signal while adding a minimum amount of noise prescribed by quantum mechanics to improve the signal-to-noise ratio of the output chain. In addition to Josephson amplifiers, Josephson microwave components that use Josephson amplifiers or Josephson mixers (such as Josephson circulators, Josephson isolators, and Josephson mixers) can be used in scalable quantum processors.

[0028] The ability to include more qubits is significant for the potential of realizing quantum computers. In some cases, the computing environment is cooled to cryogenic temperatures for the quantum processor to operate. Typically, performance improves as the temperature decreases, for example, by reducing the remaining thermally excited qubit group and reducing the thermal broadening of the transition frequencies of these qubits. Therefore, the lower the temperature, the better the performance of the quantum processor.

[0029] The applicant has recognized that improvements to increase the computational power and reliability of quantum computers can be made along two main dimensions. First, there is the qubit count itself. The more qubits in a quantum processor, the more states can be manipulated and stored in principle. Second, there is the low error rate, which involves precisely manipulating qubit states and performing sequential operations that provide consistent results rather than just unreliable data. Therefore, to improve the fault tolerance of quantum computers, a large number of physical qubits should be used to store logical qubits. Each of these qubits can be controlled by a corresponding qubit controller. In this way, the local information is delocalized, making the quantum computer less susceptible to local errors and the performance of measurements in the eigenbase of the qubits, similar to parity checking in classical computers, thus advancing to more fault-tolerant qubits. The architecture described in this paper reduces crosstalk introduced from adjacent qubits in the qubit array.

[0030] Example Architecture

[0031] Figure 1An example architecture 100 of a quantum computing system conforming to an illustrative embodiment is shown. Architecture 100 includes a qubit array 112 comprising a plurality of qubits 114. The qubit array 112 is located in a cooling unit 110, which may be a dilution cooler. The cooling unit may also house a control circuit block 113, which is sometimes referred to herein as a second set of control electronics. For example, the control circuit block 113 may be configured to provide various functions, such as performing write and / or read operations on one or more qubits in the qubit array 112. The control circuit block 113 is sometimes referred to herein as a quantum controller.

[0032] In one embodiment, the cooling unit 110 may have multiple chambers or regions, each with a different controlled temperature. For example, the control circuit module 113 may be at a controlled temperature of 1K to 4K, while the qubit array 112 may be at a controlled temperature of 240mK or lower. A dilution refrigerator is a cryogenic device that provides sustained cooling down to temperatures as low as 2mK. A large portion of the physical volume of the architecture 100 is attributed to the large size of the cooling unit 110. Optimal performance of these qubits can be obtained at the lowest possible temperature. However, due to thermodynamic efficiency, it is not possible to easily reach the coldest temperature from room temperature in one step. At this point, the applicant has determined that operating auxiliary electronics at 240mK is energy inefficient and therefore, instead of being placed in a third controlled temperature environment (T3), it is placed in a second controlled temperature environment (T2). The cooling materials / reagents used in each of these temperature ranges (e.g., liquid nitrogen at 77K, liquid helium at 4K and lower) may also be different.

[0033] To achieve near-absolute zero operating temperatures, the refrigeration unit 110 can use liquid helium as a coolant. For example, the "dry" refrigeration unit can operate in two closed gaseous cycles: one using He-4, which lowers the refrigerator to 3K ("pulse tube" cycle); and another using a He-3 / He-4 mixture, which lowers the refrigerator to 10mK, or the lowest temperature ("dilution" cycle). The only liquid in the system is inside the refrigerator, where the He-3 / He-4 mixture condenses.

[0034] A measurement and control unit 130 (sometimes referred to herein as the first set of control electronics) is located outside the refrigeration unit 110. For example, the measurement and control unit 130 can operate at room temperature. This measurement and control unit 130 is able to communicate with the quantum processor through an opening 116 (sometimes referred to as the partition of the dilution cooler 110), which also forms a hermetically sealed barrier separating the ambient atmospheric pressure of the operating cryostat from the vacuum pressure. In one embodiment, the qubit controller discussed herein is located in control circuit block 113 and operates at a second control temperature T2. In other embodiments, control circuit block 113 and qubit array 112 operate at the same cryogenic temperature.

[0035] Now for reference Figure 2 This is a block diagram of a quantum array system consistent with the illustrative embodiment. System 200 includes multiple qubit clusters 202(A) to 202(D). Advantageous clustering will be discussed in more detail later. The system includes a local channel low-power phase-locked loop (PLL), such as 216, for each write / read channel controller 210 (sometimes referred to herein as a qubit controller). The entire system 200 has a common reference clock. There are digital control blocks, such as 220, that can be shared between clusters. Each group of local channel low-power PLLs receives signals from the reference clock via its corresponding buffer. The quantum array system 200 uses a common clock system, and each channel can use a unique frequency control element. In this way, the quantum array system 200 can provide (i) a common clock as the reference clock for all PLLs, where each channel includes a PLL; and (ii) all channels use a common PLL and each channel includes a unique frequency shifting element (e.g., a divider and / or a multiplier).

[0036] like Figure 2 As shown, architecture 200 provides an arrangement of multiple channels for a qubit cluster. Each write / read controller (e.g., 210) provides a band-limited single-sideband pulse for a single qubit. Each WR / RD channel controller (i.e., qubit controller) connects to its corresponding qubit interface and provides a write pulse and reads the state information of the corresponding qubit in the cluster. Signal processing is performed using transistor-level circuitry. In one example, this transistor-level circuitry is located in CMOS. Compared to architecture 200, existing methods utilize the direct digitization of signals. For example, a digital-to-analog converter is responsible for providing a frequency shift in addition to the specific waveform used for communication with each qubit.

[0037] For example, a digital-to-analog converter (DAC) can provide a 100MHz signal, which is positioned at 450MHz off-center. Therefore, the maximum bandwidth of the signal is 450 + 0.5 * 100 = 500MHz. According to the Nyquist sampling theorem, the clock frequency should be at least 1000MHz (i.e., twice the signal bandwidth). If this offset is not present, the bandwidth will only be 100MHz, and a 200MHz clock should be sufficient. Thus, for the same bandwidth (i.e., the information content of the signal), the frequency offset leads to higher power consumption. This involves higher power DACs and higher sampling frequencies to provide the desired resolution of the DAC (e.g., 12-14 bits). Typically, a higher resolution DAC means many channels communicating between the cryogenic chamber and the control logic outside the cryogenic chamber (e.g., room temperature). Alternatively, a single channel with significant fan-out for all qubits could exist. Neither of these is optimal for the power, area, and scalability of the quantum system.

[0038] The room-temperature and cryogenic electronics in the cryogenic chamber use very few wires. For example, since the DAC is implemented with low power consumption in one aspect, it can reside in the cryogenic environment T2 and requires very few interconnects / cables between the first temperature region T1 and the cryogenic chamber. In one embodiment, all components of the WR / RD controller are integrated into the control circuit block 113 within the cryogenic environment 110, thereby eliminating a large number of wires between the cryogenic environment and the first set of control electronics at room temperature.

[0039] In one embodiment, each qubit of a qubit array can be measured to determine what frequency can be used for its excitation (e.g., 5.27 GHz). This determination can be used to logically cluster these qubits, such as... Figure 2 This is illustrated in clusters 202(A) to 202(D) and will be explained in more detail later. In other cases, the center frequency of the qubits is more easily controlled during manufacturing, allowing for physical grouping of the qubits as described herein. Figure 2 In this example, each different pattern of qubits in a qubit cluster represents a different center frequency of the corresponding qubit.

[0040] For example, once the center frequency of each qubit in a qubit array is determined, the array is divided into different clusters, each containing the most diverse set of qubit center frequencies. This allows each qubit to be provided with a signal that has better fidelity and less interference. For instance, a 20-qubit array could include four qubits with a center frequency of 4 GHz, four with a center frequency of 5.5 GHz, four with a center frequency of 6 GHz, four with a center frequency of 7 GHz, and four with a center frequency of 7.5 GHz. The 20-qubit array can be divided into five clusters, each containing qubits with center frequencies of 4 GHz, 5.5 GHz, 6 GHz, 7 GHz, and 7.5 GHz. This substantially reduces interference between these qubits. In different embodiments, the clusters discussed herein can be (i) logical clusters (based on the determination of the center frequency of each qubit in the array, which are located at different positions on the chip) or (ii) physical clusters, wherein the qubits are precisely configured to have predetermined center frequencies and are placed based on their center frequencies, as discussed in more detail later. The latter approach has become increasingly prominent with improvements in qubit fabrication technology. Logical grouping can be performed via superconducting strips and / or cables.

[0041] Example diagram

[0042] Figure 3 This is a single-channel block diagram of a quantum controller 300 consistent with the illustrative embodiment. The quantum controller 300 includes two mutually similar paths: (i) an in-phase path (I) and (ii) a quadrature path (Q). The in-phase path (I) includes a first digital processing block 302A configured to provide an envelope and center frequency offset for waveform generation of the qubits. A first digital-to-analog converter (DAC) 304A is configured to receive an in-phase signal at a first frequency (F1), sometimes referred to herein as the sampling frequency. For example, the sampling frequency could be 1 GHz, 2 GHz, etc. Although in Figure 3 A 10-bit signal is illustrated by way of example, but it should be understood that any number of bits can be used. The first mixer 306A is configured to mix the output of the first DAC 304B with the second in-phase frequency (F2) to produce a third in-phase frequency at the output of the in-phase path 308A.

[0043] Similarly, the quadrature path (Q) includes a second digital processing module 302B. A second digital-to-analog converter (DAC) 304B is present, configured to receive a quadrature signal at a first frequency (F1), sometimes referred to herein as the sampling frequency. A second mixer 306B is present, configured to mix the output of the second DAC 304B with a second quadrature frequency (F2) to generate a third quadrature frequency at the output of the quadrature path 308B. In one embodiment, the first in-phase frequency and the first quadrature frequency (F1), as well as the second in-phase frequency and the second quadrature frequency (F2), all originate from a common PLL.

[0044] The first combiner 310 is configured to combine the output of the in-phase path 308A with the output of the quadrature path to create a single sideband at its output. The splitter 312 receives the output of the first combiner 310 and is configured to provide a predetermined number of signals N based on the received output, where the number N is based on the number of qubit controllers for the predetermined qubit cluster, discussed in more detail in subsequent figures. In one embodiment, the splitter 312 is a current-mode splitter. The splitter 312 splits the signal (e.g., current) received at the output of the first combiner 310 into N portions. These N portions are distributed to each of the N qubit controllers associated with the qubit cluster. For example, the largest portion, the first portion, may be provided to the corresponding qubit of that qubit controller via the second combiner 330, while the remaining N-1 portions are each assigned to the other qubit controllers of the qubit cluster. The second combiner 330 is configured to combine a first portion of the N sections of the separator with a feedback signal used to subtract spurious signals (e.g., crosstalk) introduced by other adjacent qubit controllers of the qubit array. The operation of the second combiner 330 will be discussed in more detail later.

[0045] In one embodiment, there is a matching network 340 configured to provide maximum power transfer to the corresponding qubit and filter out any spurious signals that may have been introduced by the second in-phase frequency LO-I (F2) and / or the second quadrature frequency LO-Q (F2).

[0046] Now for reference Figure 4 , Figure 4 This is a block diagram of a single channel of a quantum controller 400 that receives feedback from an adjacent qubit controller, consistent with the illustrative embodiment. Figure 4 Many components in Figure 3 The components are similar, so for the sake of brevity, they will not be repeated here.

[0047] Consider, by way of example and not limitation, a cluster of N = 5 qubits 432, 434, 436, 438, and 452 in a qubit array, each qubit controlled by its corresponding qubit controller. In one embodiment, there is one qubit controller 400 for each corresponding qubit. For example, qubit 452 is controlled by controller 400, while qubits 432, 434, 436, and 438 each have their own corresponding qubit controller, which may be similar to qubit controller 400. A splitter 312 splits the signal (e.g., current) received at the output of the first combiner 310 into N portions. These N portions are allocated to each of the N qubit controllers associated with the cluster of qubits 432, 434, 436, 438, and 452. For example, the total current allocated by the splitter 312 may be X. A first portion is dedicated to its corresponding qubit 452 (e.g., 95% of X). The remaining N-1 portions (represented by different patterned arrows emanating from the splitter) are distributed to the other adjacent qubit controllers 432, 434, 436, and 438 of the qubit cluster. In different embodiments, each adjacent qubit controller in the qubit cluster may receive an equal portion of the current from the splitter 312, while the corresponding qubit 452 of qubit controller 400 receives the larger portion. The distribution of signal amplitude is given by the capacitive coupling terms between the qubits and is obtained during the qubit calibration phase. Thus, the subject qubit 452 is assigned a first portion (e.g., 95%) of the split current, while each of the remaining qubit controllers (N-1) in the array of (N) qubit controllers receives an equal portion of the remaining amount. In one embodiment, each of the remaining qubit controllers (N-1) receives a different portion of the N portions provided by the splitter 312. For example, each qubit may have a corresponding readout controller (not shown) that operates to read the output signal of its corresponding qubit. The readout controller can identify the frequency components in the output signal of a qubit, thereby determining the amplitude and frequency components of the spurious signal of the corresponding qubit. The stronger the spurious signal at a specific frequency, the larger the portion of the N parts allocated to that qubit. In this way, accurate cancellation can be performed by the second combiner 330.

[0048] For example, the main qubit 452 is configured to operate at 5.2 GHz. However, other qubits operate at, for example, qubit 432 at 4.5 GHz, qubit 434 at 5.7 GHz, qubit 436 at 6.2 GHz, and qubit 438 at 7 GHz. The main qubit 452 receives a first portion of the signal (e.g., 95%) (e.g., 0.95 mA of a 1 mA current), and the remaining qubits 432 to 438 each receive an equal portion of the remaining current. For example, if N is 5, the remaining qubit controllers receive (e.g., 0.05 mA / (5-1) = 0.05 mA / 4).

[0049] A second combiner 330 is configured to combine a first portion of the N portions provided by the splitter 312 with feedback signals received from adjacent qubit controllers 432, 434, 436, and 438 of the qubit cluster. The second combiner 330 is operable to subtract these feedback signals from the first portion, thereby removing spurious signals (e.g., crosstalk) introduced by these feedback signals from the adjacent qubit controllers 432, 434, 436, and 438 of the qubit cluster. By receiving feedback signals from each qubit controller 432, 434, 436, and 438 of the qubit cluster and subtracting the introduced crosstalk from the main portion, a higher quality signal is obtained that does not have frequency components outside the center frequency of the qubit under test. This "cleaned" output is ultimately provided to the qubit under test 452. This is done by way of example for simplicity. Figure 4 Feedback to the second combiner 330 from adjacent qubits 432, 434, 436, and 438 is shown. It should be noted that the crosstalk mechanism is achieved through a capacitive coupling network of N coupled qubits. The power of quantum computing depends on this coupling to realize a cross-resonant gate. However, unwanted signal coupling is eliminated by the second combiner 330.

[0050] In one implementation, this "purified" output is provided to the matching network 340, previously in Figure 3 This is discussed in the context of the controller's operation. Although in Figure 4 The example shows an arrangement of N=5, and it will be understood that the number N can be varied based on the size of the qubit cluster (the number of qubits). Compared to known methods that use dedicated filters at the output of the first combiner to remove spurious signals introduced by the second in-phase frequency and the second quadrature frequency, this approach avoids the use of dedicated filters in the in-phase path (I), the quadrature path (Q), and between these two paths and qubit 452, as in... Figure 4As described, this saves chip area and reduces power consumption. In other words, the function of filtering to remove these spurious tones (e.g., crosstalk signals) is primarily provided by the combination of splitter 312 and second combiner 330.

[0051] Figure 5 This is a block diagram of a distributed current mode cancellation system 500 consistent with the illustrative embodiment. System 600 includes multiple qubit controllers 502(1) to 502(N). Each qubit controller can be similar to... Figure 4 The qubit controller 400 is described, and for the sake of brevity, its components will not be repeated here. In one embodiment, there is one qubit controller for each qubit.

[0052] exist Figure 5 In this example, each channel (e.g., quantum controllers 502(1) to 502(N)) can be targeted with a unique qubit frequency. A local oscillator 310 is present, which can be a phase-locked loop (PLL) or a delay phase-locked loop (DLL) configured to provide a first in-phase frequency and a first quadrature frequency (F1) and a second in-phase frequency and a second quadrature frequency (F2), as previously described. Figure 4 This is described in the context of [the previous sentence]. Therefore, in one embodiment, the F1 and F2 signals are shared for each of the qubit controllers 502(1) to 502(N), where N is the number of qubits in a qubit cluster. In different embodiments, the center frequencies of the corresponding qubits can be provided in different ways. In one example, each qubit channel includes a dedicated phase-locked loop (PLL) to synthesize different frequencies from a common reference frequency provided to all qubits. This reference frequency is a low-frequency reference (e.g., approximately 100 MHz), which is multiplied by the local PLL to obtain the qubit center frequency. In another example, each qubit channel receives a common high-frequency clock (i.e., no PLL is required), and each channel uses [the following information is missing from the original text]. Figure 4 The digital processors 302-A and 302-B provide a unique frequency shift.

[0053] To prevent stray signals from one qubit controller (e.g., 502(1)) from affecting another qubit controller (e.g., 502(2) to 502(N)), current-mode crosstalk cancellation is performed from one qubit controller to another based on static interference calculation. For example, ε i This represents the signal coupling from qubit N to qubit M in the cluster ((ε i =S N / S M When N and M are not equal, εi typically takes a smaller value, and due to energy conservation, provides the following amplitude distribution:

[0054] ε1+ε2+ε3+…+ε N =1 (Formula 1)

[0055] Where (ε2+ε3+…+ε N ) / ε1<<1.

[0056] Each qubit experiences x-talk from neighboring qubits at different frequencies, which is canceled out by current-mode filtering as provided by Equation 2 below:

[0057] in:

[0058] S qNC (t) is the combined signal of these N qubits in the time domain, and

[0059] S qN (t) is the time-domain signal of the Nth qubit in the cluster, and

[0060] Sqn(t) is the time-domain signal of the nth qubit in the cluster, and

[0061] εn is the coupling coefficient between the nth qubit and the Nth qubit.

[0062] All n qubits are located near the Nth qubit in this cluster. The signal separation term can be reconfigured after the calibration phase. For example, for a qubit cluster {ε2,…ε...} N-1 One set of values ​​can be taken, while for another cluster, those values ​​can be completely different. These coefficients are obtained due to the coupling between these qubits and are acquired during the qubit calibration process.

[0063] pass Figure 4 The above description of the single-channel quantum controller and Figure 5 A block diagram of a distributed current-mode cancellation system, providing a more detailed explanation of current-mode cancellation, could be helpful. In this regard, Figure 6 Provided with Figure 4 A simplified block diagram of a double-sideband implementation of the quantum controller for the circuit-level components of the splitter. The quantum controller 600 includes in-phase paths (i) and quadrature paths (Q), which are similar to each other. There exists an in-phase signal i configured to receive a sampling frequency. DC The first digital-to-analog converter (DAC) 604A and configured to receive quadrature signals i DCThe second DAC 604B. Each of the first and second mixers 606A and 606B is used to mix the output of its corresponding DAC with a second frequency (F2) to generate a third in-phase frequency, which is added at combiner 610. In some embodiments, each DAC 604A and 604B includes DC offset cancellation circuitry to provide better matching between the two DACs 604A and 604B and / or accommodate any mismatch between mixers 606A and 606B.

[0064] exist Figure 6 In this example, splitter 612 separates the signal (e.g., current) received at the output of combiner 610 into N parts. These N parts are distributed to each of the N qubit controllers associated with the qubit cluster. The first part is provided to the corresponding qubit via matching network 650. Figure 6 In this context, the term "topic qubit" refers to the qubit in question. The remaining N-1 parts are distributed among the other qubit controllers in the qubit cluster. Figure 6 In this context, adjacent qubits and alternating adjacent qubits are referred to as adjacent qubits and alternating adjacent qubits. Figure 6 The architecture shown in the diagram uses a feedforward current-mode weighted vector summation to share current between the DAC 604A / B and the mixer 606A / B, facilitating a low-power qubit controller array and improving the linearity of the output signal by removing signal components outside the center frequency of the subject qubit. It should be noted that the more active stages in the architecture, the more distortion they may introduce into the output signal. By sharing current between the DAC and the mixer, this architecture eliminates the filtering components, reduces distortion, and consumes less power.

[0065] Figure 7 A simplified block diagram 700 of a single-sideband implementation of a quantum controller is provided. In this arrangement, the currents are first splittered into N parts by splitters 712A and 712B, depending on the strength of the coupling coefficients between the qubits in the cluster. For example, the total current from the in-phase current processing element 604A is divided into N parts by splitter 712A, such as S... 1I S 2I S 3I S 4I and S 5I Where N = 5. Similarly, the total current from the quadrature phase current processing element 604B is divided into N parts by the shunt 712B, such as S 1Q S 2Q S 3Q S 4Q and S 5Q The up-converted single-sideband signal is given by the following formula:

[0066] Y k=S kI *cos(ω LO t)± S kQ *sin(ω LO t) (Formula 3)

[0067] Depending on the specific qubit frequency, either the upper or lower sideband is used. Another method for generating sidebands includes the following formula:

[0068] Y j =S jI *sin(ω LO t)± S jQ *cos(ω LO t) (Formula 4)

[0069] Depending on the specific qubit frequency, either the upper sideband or the lower sideband is used.

[0070] Despite Figure 6 and 7 PFETs are shown and / or discussed in the examples, but these transistors are provided by way of example only and not as a limitation. It will be understood that other types of insulated-gate field-effect transistors (IGFETs), including NFETs, with complementary logic can also be used based on the concepts disclosed herein. For example, any FET from columns 11I-V of the periodic table (including carbon nanotube FETs) can also be used to implement the structures described herein. In some embodiments, bipolar transistors (e.g., PNP or NPN), BiCMOS, and / or FinFETs can be used instead of MOS transistors.

[0071] Example planar diagram of a qubit cluster

[0072] In one embodiment, a qubit array comprises multiple clusters, each cluster being arranged to provide maximum spacing between resonant frequencies to minimize crosstalk between adjacent clusters. In this regard, reference... Figure 8 This figure is a block diagram of an example frequency planning of multiple qubits based on the center frequency of a qubit array, consistent with the illustrative embodiment. This equally spaced, hexagonal arrangement with a common centroid provides an equal amount of physical separation between each qubit and its neighboring qubits. Each box in arrangement 800 represents a qubit. Each box pattern represents a unique center frequency of the qubit. A predetermined physical distance is maintained to minimize crosstalk between these different qubits. The distance between each qubit with a similar center frequency is maximized. In this way, deterministic crosstalk between one qubit and another is reduced.

[0073] In one embodiment, when the manufacturing process is more controlled and the center frequency can be configured, the center frequency can be set by the manufacturing process itself. In other cases, where the exact center frequency of the qubit cannot be predetermined by the manufacturing process, the grouping discussed here is logical (i.e., not physical) grouping. For example, the determination of the center frequency is performed by providing a waveform of a certain amplitude at a certain frequency and enabling the readout circuitry. The architecture for tuning the center frequency of a qubit includes a flux-coupled arrangement in which an additional magnetic field is superimposed on the qubit under consideration.

[0074] Therefore, the determined center frequencies of the qubits are used to group these qubits. More precisely, the center frequency of each qubit in the qubit array is determined, and the qubit array is logically divided into different groups, where each group includes a set of the most diverse qubit center frequencies.

[0075] The pattern of each box representing a qubit represents a different center frequency. In embodiments where the manufacturing process receives more control and the center frequency can be precisely achieved, these qubits can be spatially arranged to minimize interference between adjacent and alternating adjacent qubits. This physical arrangement improves computational fidelity. In this way, each qubit can be given a signal with better fidelity and less interference. Thus, the qubit chip spatially implements qubits to minimize crosstalk between qubits and provide signal fidelity. These arrangements can follow a uniform spatial arrangement of these qubit resonators. Each qubit is spaced equidistant from its neighboring qubits. For example, if qubit Qn is surrounded by multiple qubits QA, QB, QC, QD, and QE, the interference terms between each pair {Qn, Qx} remain the same, x = A, B, C, D, E. Therefore, when qubit Qn is active, it is sufficient to send only one cancellation term (e.g., a copy of the main signal). Thus, if the desired signal is Yqn, the cancellation term is given as α*Yqn. This signal (signal = α*Yqn) is sent to each of Qx and added to the corresponding Qx signal to eliminate the x-talk effect caused by spatial interference of Qn.

[0076] Given that it is used for Figure 8 The circular arrangement profile for static reciprocal cancellation provides deterministic signal coupling, which can be easily eliminated in the current domain, since x-talk is a static component. Another advantage of this arrangement involves the fact that only one term is sufficient to eliminate crosstalk across the entire array (because the spatial distance between any two box patterns is constant throughout the qubit array). Such an arrangement facilitates the crosstalk cancellation term, which can be implemented in the current mode to maintain linearity.

[0077] in conclusion

[0078] Various embodiments of this teaching have been described for illustrative purposes, but are not intended to be exhaustive or limiting. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements to technologies found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0079] While the content considered to be the best state and / or other instances has been described above, it should be understood that various modifications may be made therein, and the subject matter disclosed herein can be implemented in different forms and instances, and the teachings can be applied to many applications, of which only some have been described herein. The appended claims are intended to claim protection for any and all applications, modifications, and variations falling within the true scope of the teachings herein.

[0080] The components, steps, features, purposes, benefits, and advantages discussed herein are illustrative only. They, and the discussions associated with them, are not intended to limit the scope of protection. While various advantages have been discussed herein, it should be understood that not all embodiments are necessarily intended to include all advantages. Unless otherwise stated, all measurements, values, ratings, locations, amplitudes, sizes, and other specifications set forth in this specification (including in the following claims) are approximate and imprecise. They are intended to have a reasonable range of functionality associated with them and consistent with functionality customary in the art to which they pertain.

[0081] Many other embodiments are also contemplated. These include embodiments with fewer, additional, and / or different components, steps, features, purposes, benefits, and advantages. These also include embodiments in which components and / or steps are arranged and / or ordered differently.

[0082] The calling flows, flowcharts, and block diagrams in this document illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to different embodiments of this disclosure. Each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the diagram. For example, depending on the functions involved, two consecutively shown blocks may actually execute substantially simultaneously, or these blocks may sometimes execute in reverse order. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0083] Although the foregoing has been described in conjunction with exemplary embodiments, it should be understood that the term "exemplary" means only as an example and not as best or most desirable. Nothing else stated or shown outside the foregoing is intended or should be construed as causing any part, step, feature, object, benefit, advantage, or equivalent to be offered to the public, whether or not it is stated in the claims.

[0084] It should be understood that the terms and expressions used herein have their general meanings as assigned to their respective corresponding queries and fields of study, unless otherwise specified herein. Relational terms such as "first" and "second" may be used merely to distinguish one entity or action from another, without necessarily requiring or implying any actual such relationship or order between these entities or actions. The terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but may also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element beginning with "an" or "a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes that element.

[0085] An abstract of this disclosure is provided to allow the reader to quickly determine the nature of this technical disclosure. It is submitted under the understanding that it is not intended to interpret or limit the scope or meaning of the claims. Furthermore, as can be seen from the above detailed description, various features are combined in various embodiments for the purpose of simplification. The method of this disclosure should not be construed as reflecting an intention to have more features than expressly recited in each claim of the claimed embodiments. Rather, as reflected in the following claims, the inventive subject matter lies in fewer than all features of a single disclosed embodiment. Therefore, the following claims are hereby incorporated into the detailed description, wherein each claim is independently claimed as a separate subject matter.

Claims

1. A quantum bit controller, comprising: In-phase path; Orthogonal paths; A first combiner is configured to combine the output of the in-phase path with the output of the quadrature path to create a single sideband; The splitter is configured as follows: Divide the single sideband into N parts; The first portion of the N portions is provided to the qubit corresponding to the qubit controller; and Each of the remaining N-1 portions is provided to an adjacent qubit controller of a qubit cluster, the qubit cluster comprising qubits corresponding to that qubit controller, where N equals the number of qubit controllers in the qubit cluster; and The second combiner is configured to combine the first part with N-1 feedback signals received from the adjacent qubit controller of the qubit cluster.

2. The quantum bit controller according to claim 1, wherein the in-phase path comprises: The first digital-to-analog converter (DAC) is configured to receive an in-phase signal at a first in-phase frequency; as well as A first mixer is configured to mix the output of the first digital-to-analog converter (DAC) with a second in-phase frequency to create a third in-phase frequency at the output of the in-phase path.

3. The quantum bit controller according to claim 2, wherein the orthogonal path comprises: The second digital-to-analog converter (DAC) is configured to receive quadrature signals of the first quadrature frequency; as well as The second mixer is configured to mix the output of the second digital-to-analog converter (DAC) with a second quadrature frequency to create a third quadrature frequency at the output of the quadrature path.

4. The quantum bit controller according to claim 3, wherein: The in-phase signal at the first in-phase frequency is shared among the adjacent qubit controllers in the qubit cluster; The orthogonal signals at the first orthogonal frequency are shared among the adjacent qubit controllers in this qubit cluster; The in-phase signal at the second in-phase frequency is shared among adjacent qubit controllers in this qubit cluster; and The orthogonal signals at the second orthogonal frequency are shared among the adjacent qubit controllers in the qubit cluster.

5. The quantum bit controller according to any one of claims 1 to 4, wherein, Each of the adjacent qubit controllers is configured to control the qubits of the qubit cluster.

6. The qubit controller according to any one of claims 1 to 4, wherein the combination of the first portion of the second combiner and the N-1 feedback signals is operable to subtract the crosstalk contribution of the capacitive coupling of the qubit cluster.

7. The qubit controller according to any one of claims 1 to 4, wherein the cluster is a different set of qubit center frequencies based on the cluster.

8. The qubit controller according to claim 3 or 4, further comprising a matching network coupled to the output of the second combiner.

9. The quantum bit controller according to claim 8, wherein: The matching network is configured to provide maximum power transfer to the corresponding qubit; as well as The matching network is configured to filter out spurious signals introduced by at least one of the second in-phase frequency and the second quadrature frequency, which are far from the center frequency of the qubit corresponding to the qubit controller.

10. The quantum bit controller according to any one of claims 1 to 4, wherein the splitter is a current-mode splitter.

11. The quantum bit controller of claim 10, wherein the single sideband is an electric current.

12. The qubit controller according to any one of claims 1 to 4, wherein N is based on the number of qubits in the cluster.

13. The qubit controller according to any one of claims 1 to 4, wherein the qubit controller is configured to operate at low temperature in a dilution refrigerator.

14. A method for controlling qubits with a controller having in-phase paths and quadrature paths, the method comprising: The first combiner combines the output of the in-phase path with the output of the quadrature path to create a single sideband. The single sideband is divided into N parts by a splitter; The splitter provides the first of the N parts to the qubit corresponding to the qubit controller. The splitter supplies each of the remaining N-1 portions to the adjacent qubit controller of the qubit cluster, which includes qubits corresponding to that qubit controller, where N equals the number of qubit controllers in the qubit cluster; and The first part is combined with N-1 feedback signals received from the adjacent qubit controller of the qubit cluster by the second combiner.

15. The method of claim 14, further comprising: In the in-phase path: The in-phase signal is received by the first digital-to-analog converter (DAC) at the first in-phase frequency; as well as The first mixer mixes the output of the first digital-to-analog converter (DAC) with a second in-phase frequency to create a third in-phase frequency at the output of the in-phase path; and In the orthogonal path: The quadrature signal is received at the first quadrature frequency via a second digital-to-analog converter; as well as The output of the second digital-to-analog converter is mixed with a second quadrature frequency by a second mixer to generate a third quadrature frequency at the output of the quadrature path.

16. The method of claim 15, wherein: The in-phase signal at the first in-phase frequency is shared among the adjacent qubit controllers in the qubit cluster; The orthogonal signals at the first orthogonal frequency are shared among the adjacent qubit controllers in this qubit cluster; The in-phase signal at the second in-phase frequency is shared among adjacent qubit controllers in this qubit cluster; and The orthogonal signals at the second orthogonal frequency are shared among the adjacent qubit controllers in the qubit cluster.

17. The method according to any one of claims 14 to 16, wherein, Each of the adjacent qubit controllers is configured to control the qubits of the qubit cluster.

18. The method according to any one of claims 14 to 16, wherein the combination of the first portion of the second combiner and the N-1 feedback signals is operable to subtract the crosstalk contribution of the capacitive coupling of the qubit cluster.

19. The method according to claim 15 or 16, further comprising: Maximum power is transferred to the corresponding qubit through a matching network; as well as The matching network filters out spurious signals introduced by at least one of the second in-phase frequency and the second quadrature frequency, which are far from the center frequency of the qubit corresponding to the qubit controller.

20. The method according to any one of claims 14 to 16, wherein the splitter is a current-mode splitter.

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