FinFET with lateral charge balance at the drain drift region

Abstract

A semiconductor device (100) includes an extended drain finFET (102). A drain drift region (128) of the finFET (102) extends between a drain contact region (132) and a body (124) of the finFET (102). The drain drift region (128) includes an enhanced portion (136) of the drain drift region (128) between the drain contact region (132) and the body (124). The drain drift region (128) also includes a first charge balance region and a second charge balance region laterally adjacent to the enhanced portion (136) of the drain drift region (128) and located on opposite sides of the enhanced portion. The enhanced portion (136) of the drain drift region (128) and the drain contact region (132) have a first conductivity type; the body (124), the first charge balance region, and the second charge balance region have a second, opposite conductivity type. The drain drift region (128) is wider than the body (124).

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices. More particularly, but not exclusively, the present invention relates to fin field effect transistors (finFETs) in semiconductor devices. Background Art

[0002] A fin field-effect transistor (finFET) is a type of field-effect transistor in which the body is located within a fin of semiconductor material. The gate wraps around the body on at least three sides of the fin. FinFETs are typically used in "low-voltage" circuits (such as logic circuits), where the operating potential applied to the drain is less than the breakdown potential of the gate dielectric layer between the gate and the body. Creating a finFET that can operate at a drain potential above the breakdown potential of the gate dielectric has been challenging. Summary of the Invention

[0003] The present invention describes a semiconductor device including an extended-drain finFET (hereinafter referred to as a finFET). The finFET includes a drain drift region between a drain contact region and a body of the finFET. The drain drift region includes an enhanced portion of the drain drift region between the drain contact region and the body. The finFET further includes a first charge balance region and a second charge balance region laterally adjacent to and located on opposite sides of the enhanced portion of the drain drift region. The enhanced portion of the drain drift region and the drain contact region have a first conductivity type. The body, the first charge balance region, and the second charge balance region have a second, opposite conductivity type. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figures 1A to 1G are perspective and cross-sectional views of a semiconductor device including an extended-drain finFET depicted at various stages of an example formation method.

[0005] Figures 2A to 2G are perspective and cross-sectional views of a semiconductor device including an extended-drain finFET depicted at various stages of another example formation method. DETAILED DESCRIPTION

[0006] The present invention is described with reference to the accompanying drawings. The figures are not drawn to scale and are provided solely for the purpose of illustrating the present invention. Several aspects of the present invention are described below with reference to example applications used for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of the present invention. The present invention is not limited by the illustrated ordering of the actions or events, as some actions may occur in different orders and / or simultaneously with other actions or events. Furthermore, not all illustrated actions or events are required to implement the methods of the present invention.

[0007] A semiconductor device includes a finFET having a fin of semiconductor material on a substrate of the semiconductor device. The FinFET includes a drain contact region having a first conductivity type in the fin and a body having a second conductivity type opposite to the first conductivity type in the fin. The FinFET further includes a drain drift region having the first conductivity type in the fin between the drain contact region and the body. The drain drift region includes an enhanced portion of the drain drift region having the first conductivity type between the drain contact region and the body. The enhanced portion of the drain drift region has a higher net average first conductivity type dopant concentration than the remainder of the drain drift region, the net average first conductivity type dopant concentration being the average first conductivity type dopant concentration in the enhanced portion of the drain drift region minus the average second conductivity type dopant concentration. The terms "first conductivity type dopant" and "second conductivity type dopant" should be understood to mean a dopant that provides the first conductivity type and a dopant that provides the second conductivity type, respectively, in the semiconductor material. For example, for a case where the first conductivity type is n-type and the second conductivity type is p-type, phosphorus, arsenic, and antimony are first conductivity type dopants because they provide n-type conductivity in the semiconductor material, and boron, gallium, and indium are second conductivity type dopants because they provide p-type conductivity in the semiconductor material. The FinFET also includes a first charge balance region and a second charge balance region. The first charge balance region is laterally adjacent to and abuts the enhanced portion of the drain drift region between the body and the drain contact region. The second charge balance region is laterally adjacent to and abuts the enhanced portion of the drain drift region between the body and the drain contact region opposite the first charge balance region. In the examples disclosed herein, the terms "lateral" and "laterally" refer to directions parallel to the top surface of the fin. The first charge balance region and the second charge balance region each have the second conductivity type. The body has a body width, which is the maximum lateral dimension of the fin perpendicular to the direction of current flow through the body during operation of the finFET. The drift region has a drain width that is the maximum lateral dimension of the fin across the drain drift region in a direction perpendicular to current flow during operation of the finFET. The drain width is greater than the body width. The FinFET may include one or more fins arranged in parallel, each having a drain contact region, a body and drain drift region, a reinforced portion of the drain drift region, and first and second charge balancing regions. The reinforced portion of the drain drift region can advantageously concentrate current flow between the first and second charge balancing regions during operation of the finFET, thereby providing a lower resistance for the finFET. The first and second charge balancing regions can advantageously enable a higher operating potential to be applied to the drain contact region compared to a similar finFET without charge balancing regions.

[0008] It should be noted that terms such as top, over, above, below, and under may be used in the present invention and should not be interpreted as limiting the position or orientation of structures or elements, but rather are used to provide spatial relationships between structures or elements.

[0009] Figures 1A to 1G 1 is a perspective view and a cross-sectional view of a semiconductor device 100 including an extended drain finFET 102 (hereinafter finFET 102) depicted at various stages of an example formation method. Figure 1A By way of example, semiconductor device 100 may be implemented as a discrete semiconductor device, an integrated circuit, a microelectronic sensor, a microelectromechanical system (MEMS) device, an electro-optical device, or a micro-optical mechanical system (MOMS) device. Semiconductor device 100 is formed on a substrate 104. For example, substrate 104 may be implemented as a semiconductor wafer, such as a silicon wafer or a silicon-on-insulator (SOI) wafer. Alternatively, substrate 104 may be implemented as a dielectric substrate, such as a sapphire wafer. Substrate 104 may have regions for additional semiconductor devices (not shown) similar to semiconductor device 100. In this example, semiconductor material 106 is disposed on substrate 104. For example, semiconductor material 106 may primarily include single crystal silicon and a dopant, or may include another semiconductor material, such as silicon and germanium, or silicon and carbon. In versions of this example in which substrate 104 is implemented as a semiconductor wafer, semiconductor material 106 may be continuous with substrate 104.

[0010] A fin mask 108 is formed over semiconductor material 106 to cover areas for first fin 110 and second fin 112 of finFET 102. Fin mask 108 may include photoresist and antireflective material formed by a photolithography process. Fin mask 108 may also include a hard mask material, such as silicon dioxide, patterned by a reactive ion etch (RIE) process.

[0011] The semiconductor material 106 is removed at locations exposed by the fin mask 108, leaving the semiconductor material 106 beneath the fin mask 108 to form a first fin 110 and a second fin 112. The semiconductor material 106 can be removed from the substrate 104 by an RIE process using halogen radicals (e.g., fluorine radicals). The first fin 110 and the second fin 112 have a top surface 114 to which the semiconductor material 106 extends.

[0012] After forming the first fin 110 and the second fin 112, the fin mask 108 is removed. The photoresist in the fin mask 108 can be removed by a plasma process using oxygen radicals (e.g., an ashing process) followed by a wet cleaning process using an aqueous solution of ammonium hydroxide and hydrogen peroxide. Alternatively, the photoresist in the fin mask 108 can be removed by a wet etching process using an aqueous mixture of sulfuric acid and hydrogen peroxide followed by a wet cleaning process using an aqueous solution of ammonium hydroxide and hydrogen peroxide. The hard mask material in the fin mask 108 can be removed by an RIE process or by a buffered aqueous solution of dilute hydrofluoric acid.

[0013] refer to Figure 1B , a recessed oxide 116 may be formed on the substrate 104 around the first fin 110 and the second fin 112. The recessed oxide 116 comprises a dielectric material, such as silicon dioxide. The recessed oxide 116 may be formed by forming a dielectric material over the substrate and removing the dielectric material from over the first fin 110 and the second fin 112, and then recessing the dielectric material below the top surface 114 to expose the first fin 110 and the second fin 112. The first fin 110 extends above the substrate 104 to a fin height 118, which, by way of example, may be 300 nanometers to 800 nanometers.

[0014] A first conductivity type dopant (in this example, an n-type dopant, such as phosphorus) is introduced into the first fin 110 to form a first source 120 and into the second fin 112 to form a second source 122. A second conductivity type dopant (in this example, a p-type dopant, such as boron) is introduced into the first fin 110 to form a first body 124 and into the second fin 112 to form a second body 126 in the second fin 112. A first conductivity type dopant (in this example, such as phosphorus) is introduced into the first fin 110 to form a first drain drift region 128 and into the second fin 112 to form a second drain drift region 130. The first drain drift region 128 and the second drain drift region 130 may have an average concentration of the first conductivity type dopant (by way of example, from 1×10 16 cm -3 to 4×10 16 cm -3 ) to enable finFET 102 to operate at a desired drain potential. First conductivity type dopants (such as phosphorus and arsenic in this example) are introduced into first fin 110 to form first drain contact region 132 and into second fin 112 to form second drain contact region 134. First drain contact region 132 and second drain contact region 134 may have greater than 1×10 19 cm -3to provide an average concentration of the first drain drift region 128 and the second drain drift region 130 and to the subsequently formed enhanced portions 136 and 138 of the drain drift regions 128 and 130 (shown in FIG. Figure 1E In this example, the first drain contact region 132 and the second drain contact region 134 may be continuous, such as Figure 1B As depicted in , this can advantageously provide lower resistance connections to the first and second drain drift regions 128 and 130 and to subsequently formed enhanced portions 136 and 138 of the drain drift regions 128 and 130, compared to a similar finFET with a segmented drain contact region.

[0015] Drain length 140, which is the lateral dimension between first body 124 and first drain contact region 132 along top surface 114 of first fin 110 in a direction parallel to the direction of current flow during operation of finFET 102, can be selected to enable finFET 102 to operate at a desired drain potential. By way of example, drain length 140 can be 200 nanometers to 1 micron. For a specific example, drain length 140 having a value of 800 nanometers can enable finFET 102 to operate at a drain potential of 20 volts.

[0016] First body 124 has a body width 142, which is the maximum lateral dimension of first body 124 perpendicular to the direction of current flow during operation of finFET 102. The direction of body width 142 is perpendicular to the direction of drain length 140. Furthermore, first drain drift region 128 has a drain width 144, which is the maximum lateral dimension of first drain drift region 128 perpendicular to the direction of current flow during operation of finFET 102. The direction of drain width 144 is perpendicular to the direction of drain length 140. Drain width 144 is greater than body width 142. By way of example, body width 142 may be 100 nanometers to 300 nanometers. By way of example, drain width 144 may be 300 nanometers to 600 nanometers. By way of example, drain width 144 may be 200 nanometers to 300 nanometers greater than body width 142.

[0017] refer to Figure 1CA charge balancing mask 146 is formed over the semiconductor device 100. The charge balancing mask 146 exposes the first fin 110 in the area for the first charge balancing region 148 and the area for the second charge balancing region 150, and exposes the second fin 112 in the area for the third charge balancing region 152 and the area for the fourth charge balancing region 154. The area for the first charge balancing region 148 and the area for the second charge balancing region 150 are located on opposite sides of the first drain drift region 128. Similarly, the area for the third charge balancing region 152 and the area for the fourth charge balancing region 154 are located on opposite sides of the second drain drift region 130. The charge balancing mask 146 may include a photoresist and an anti-reflective material (e.g., a bottom anti-reflective coating (BARC)) and may be formed by a photolithography process.

[0018] A second conductivity type dopant 156 (such as boron in this example) is implanted into the first and second fins 110 and 112 where exposed by the charge balance mask 146, i.e., the regions for the charge balance regions 148, 150, 152, and 154. 11 cm -2 to 1×10 13 cm -2 The second conductivity type dopant 156 is implanted with a total dose of 100 Å. The second conductivity type dopant 156 may be implanted with more than one implant energy to vertically distribute the second conductivity type dopant 156 in the first fin 110 and the second fin 112 .

[0019] Charge balance mask 146 is removed after implanting second conductivity type dopant 156. The photoresist and anti-reflective material in charge balance mask 146 may be removed by a plasma process using oxygen radicals, such as an ashing process.

[0020] refer to Figure 1D , a drift region mask 158 is formed above the semiconductor device 100. The drift region mask 158 is used for Figure 1B The first fin 110 is exposed in the region of the first enhanced portion 136 in the first drain drift region 128, and in the region of the first enhanced portion 136 in the first drain drift region 128. Figure 1B The second fin 112 is exposed in the area of ​​the second enhanced portion 138 in the second drain drift region 130. The area of ​​the first enhanced portion 136 for the first drain drift region 128 is located between the area for the first charge balance region 148 and the area for the second charge balance region 150. Similarly, the area of ​​the second enhanced portion 138 for the second drain drift region 130 is located between the area for the third charge balance region 152 and the area for the fourth charge balance region 154. The drift region mask 158 may have the same Figure 1CThe charge balancing mask 146 has a similar composition and can be formed by a similar process.

[0021] A first conductivity type dopant 160 (such as phosphorus in this example) is implanted into the first fin 110 and the second fin 112 where exposed by the drift region mask 158, i.e., the areas for the enhanced portions 136 and 138 of the drain drift regions 128 and 130. Figure 1C First conductivity type dopant 160 is implanted at a total dose of 65% to 150% of the total dose of second conductivity type dopant 156 disclosed to achieve a desired charge balance during operation of finFET 102. First conductivity type dopant 160 may be implanted at more than one implant energy to vertically distribute first conductivity type dopant 160 in first fin 110 and second fin 112.

[0022] The drift region mask 158 is removed after implanting the first conductivity type dopant 160. The drift region mask 158 may be removed by a process similar to the process used to remove the charge balance mask 146.

[0023] In an alternative version of this example, the implanted regions of the first enhanced portion 136 and the second enhanced portion 138 for the first drain drift region 128 and the second drain drift region 130, respectively, may extend to Figure 1B In another alternative version, the implanted regions of the first enhanced portion 136 and the second enhanced portion 138 for the first drain drift region 128 and the second drain drift region 130 may extend to Figure 1B In another alternative version, the first drain contact region 132 and the second drain contact region 134 may be formed. Figure 1C The first conductivity type dopant 160 is implanted before the second conductivity type dopant 156 is implanted.

[0024] refer to Figure 1E , by making Figure 1D The annealing process 162 for activating the first conductivity type dopant 160 heats the substrate 104 to form a first enhanced portion 136 in the first drain drift region 128 and a second enhanced portion 138 of the second drain drift region 130 in the second drain drift region 130. The annealing process 162 also activates the first conductivity type dopant 160. Figure 1C The second conductivity type dopant 156 is activated to form a first charge balance region 148 and a second charge balance region 150 in the first fin 110 and a third charge balance region 152 and a fourth charge balance region 154 in the second fin 112. The enhanced portions 136 and 138 of the drain drift regions 128 and 130 may have a 1×10 16 cm-3 to 4×10 16 cm -3 The net average first conductivity type dopant concentration is .

[0025] Charge balance regions 148, 150, 152, and 154 may have a net average second conductivity type dopant concentration that is 65% to 150% of the net average first conductivity type dopant concentration in enhanced portions 136 and 138 of drain drift regions 128 and 130, where the net average second conductivity type dopant concentration is the average second conductivity type dopant concentration in charge balance regions 148, 150, 152, and 154 minus the average first conductivity type dopant concentration. By way of example, annealing process 162 may be implemented as a rapid thermal anneal, a spike anneal, or a flash anneal. Rapid thermal annealing may heat substrate 104 to 1000° C. to 1150° C. in 5 to 60 seconds and may be implemented using an incandescent lamp in a rapid thermal processor. Spike annealing may heat substrate 104 to 1100° C. to 1250° C. in 100 milliseconds to 5 seconds and may be implemented using an arc flash lamp. Flash annealing can heat the substrate 104 to 1200° C. to 1350° C. in 50 μs to 1 ms and can be performed by a flash lamp or a scanning laser.

[0026] As disclosed in this example, forming the enhanced portions 136 and 138 of the drain drift regions 128 and 130 by implanting the first conductivity type dopant 160 without overlapping with the implantation of the second conductivity type dopant 156 can provide a consistent average dopant concentration in the enhanced portions 136 and 138 of the drain drift regions 128 and 130, thereby advantageously providing consistent performance of the finFET 102. Similarly, as disclosed in this example, forming the charge balance regions 148, 150, 152, and 154 by implanting the second conductivity type dopant 156 without overlapping with the implantation of the first conductivity type dopant 160 can provide a consistent average dopant concentration in the charge balance regions 148, 150, 152, and 154, thereby advantageously providing even more consistent performance of the finFET 102.

[0027] The first charge balance region 148 is adjacent to the first enhanced portion 136 of the first drain drift region 128 between the first body 124 and the first drain contact region 132, and the second charge balance region 150 is adjacent to the first enhanced portion 136 of the first drain drift region 128 between the first body 124 and the first drain contact region 132 on a side of the first enhanced portion 136 of the first drain drift region 128 opposite the first charge balance region 148. Similarly, the third charge balance region 152 is adjacent to the second enhanced portion 138 of the second drain drift region 130 between the second body 126 and the second drain contact region 134, and the fourth charge balance region 154 is adjacent to the second enhanced portion 138 of the second drain drift region 130 between the second body 126 and the second drain contact region 134 on a side of the second enhanced portion 138 of the second drain drift region 130 opposite the third charge balance region 152. In this example, the second charge balance region 150 may be continuous with the third charge balance region 152 .

[0028] Having the first charge balancing region 148 and the second charge balancing region 150 adjacent to and on opposite sides of the first enhanced portion 136 of the first drain drift region 128 and having the third charge balancing region 152 and the fourth charge balancing region 154 in a similar relationship relative to the second enhanced portion 138 of the second drain drift region 130 advantageously enables a higher operating potential to be applied to the first drain contact region 132, compared to a similar finFET without charge balancing regions.

[0029] Figure 1F and Figure 1G It is a depiction of other stages of formation along the lines shown in Figure 1E 1 is a cross-sectional view of the semiconductor device 100 along the cutting line. Figure 1F , forming a field plate dielectric layer 164 over the substrate 104, the field plate dielectric layer extending from close to the first body 124 and from close to Figure 1E The second body 126 (in Figure 1F The first drain contact region 132 and the second drain contact region 134 are at least partially overlapped with the first enhanced portion 136 of the first drain drift region 128 and are connected to the first drain contact region 132 and the second drain contact region 134. Figure 1E The second enhanced portion 138 of the second drain drift region 130 (at Figure 1F The field plate dielectric layer 164 may also overlap with the Figure 1E The first charge balance region 148 (at Figure 1F was dissected) and Figure 1E The second charge balance region 150, the third charge balance region 152 and the fourth charge balance region 154 (in Figure 1F 126 ). Field plate dielectric layer 164 may include silicon dioxide or a silicon dioxide-based dielectric material and may be formed by a chemical vapor deposition (CVD) process or a plasma-enhanced chemical vapor deposition (PECVD) process (by way of example). The thickness of field plate dielectric layer 164 may depend on the desired drain potential of finFET 102. By way of example, the thickness of field plate dielectric layer 164 may be 30 nanometers for a desired drain potential of 5 volts and 120 nanometers for a desired drain potential of 20 volts. Field plate dielectric layer 164 may be patterned by a wet etch process to provide a tapered profile proximate to first and second bodies 124, 126.

[0030] On the first body 124 and Figure 1E The second body 126 (in Figure 1F A gate dielectric layer 166 is formed on the first and second fins 110, 112 (masked in the figure), and on the top surfaces 114 of the first and second fins 110, 112. The gate dielectric layer 166 extends to lateral surfaces of the first and second bodies 124, 126, which extend from the top surfaces 114 to the recessed oxide 116. The gate dielectric layer 166 may include silicon dioxide, silicon dioxide nitride, hafnium oxide, zirconium oxide, tantalum oxide, or other dielectric materials suitable for the gate dielectric of a finFET. The gate dielectric layer 166 may be formed by a thermal oxidation process, a CVD process, a nitridation process, or any combination thereof. By way of example, the gate dielectric layer 166 may have a thickness of 2 to 12 nanometers.

[0031] A field plate 168 is formed over the field plate dielectric layer 164, and a gate 170 is formed over the gate dielectric layer 166. In this example, the field plate 168 can be continuous with the gate 170. The gate 170 extends over the top surface 114 of the first fin 110 and the second fin 112, overlapping the first body 124 and the second body 126, and over the lateral surfaces of the first body 124 and the second body 126. The field plate 168 and the gate 170 can comprise polycrystalline silicon (commonly referred to as polysilicon) and can include a metal silicide layer on the polysilicon. Alternatively, the field plate 168 and the gate 170 can comprise a metal gate material, such as titanium, titanium nitride, tantalum, or tantalum nitride. Field plate 168 and gate 170 may be formed by forming a conductive layer of polysilicon or gate metal over field plate dielectric layer 164 and gate dielectric layer 166 , forming a combined field plate / gate mask over the conductive layer, and removing the conductive layer where exposed by the combined field plate / gate mask.

[0032] The field plate 168 can advantageously reduce the electric field in the first enhanced portion 136 of the first drain drift region 128 and the second enhanced portion 138 of the second drain drift region 130 during operation of the finFET 102. As disclosed in this example, forming the field plate 168 and the gate 170 simultaneously can advantageously reduce the fabrication complexity and cost of the semiconductor device 100.

[0033] refer to Figure 1G , on the first drain contact region 132 and Figure 1F The second drain contact region 134 (at Figure 1G Drain terminal 172 is formed on finFET 102 (shielded in FIG. 1 ). In this example, drain terminal 172 is continuous. Source terminal 174 is formed on first source 120 and second source 122. Drain terminal 172 and source terminal 174 are conductive and can be formed simultaneously. A pre-metal dielectric (PMD) layer (not shown) can be formed over finFET 102 before forming drain terminal 172 and source terminal 174. Drain terminal 172 and source terminal 174 can be formed by forming contact holes through the PMD layer and forming one or more layers of conductive material (e.g., titanium, titanium nitride, and tungsten) on the PMD layer that extend into the contact holes and make electrical connections to first drain contact region 132, second drain contact region 134, first source 120, and second source 122. The conductive material layer is then removed from over the PMD layer, leaving the conductive material layer in the contact holes to provide drain terminal 172 and source terminal 174. Drain terminal 172 and source terminal 174 provide nodes for electrically connecting finFET 102 to other components in semiconductor device 100 , such as active components or input / output terminals.

[0034] Figures 2A to 2G 2 is a perspective view and a cross-sectional view of a semiconductor device 200 including an extended drain finFET 202 (hereinafter finFET 202) depicted at various stages of another example formation method. Figure 2A , the semiconductor device 200 may be implemented as a reference Figure 1A The semiconductor device 100 of FIG. 1 may be any of the examples disclosed herein. In this example, the formation of the semiconductor device 200 begins by obtaining a substrate 204. For example, the substrate 204 may be implemented as a silicon wafer or an SOI wafer. The substrate 204 may have regions for additional semiconductor devices (not shown) similar to the semiconductor device 200.

[0035] A recessed oxide 216 is formed over substrate 204. Recessed oxide 216 may include one or more layers of silicon dioxide or silicon dioxide with a low weight percent hydrogen content and may be formed by thermal oxidation of silicon or by a low-pressure chemical vapor deposition (LPCVD) process. Recessed oxide 216 may be formed by forming one or more silicon dioxide layers and simultaneously patterning the one or more layers.

[0036] A fin mask 208 is formed over the recessed oxide 216. The fin mask 208 may include one or more epitaxial mask materials such as silicon dioxide, silicon nitride, or boron nitride doped with silicon at 1 atomic % to 30 atomic % silicon. x The first fin 210 and the second fin 212 may be formed by forming one or more epitaxial mask material layers over the one or more silicon dioxide layers of the recessed oxide 216, forming a hard mask over the one or more silicon nitride or silicon-doped boron nitride layers to expose the areas for the first fin 210 and the second fin 212, and then etching the one or more silicon nitride or silicon-doped boron nitride layers of the fin mask 208 and the one or more silicon dioxide layers of the recessed oxide 216 using an RIE process using fluorine radicals to simultaneously form the fin mask 208 and the recessed oxide 216. Including silicon-doped boron nitride in the fin mask 208 can provide etch selectivity to underlying materials such as silicon and silicon dioxide. The fin mask 208 exposes areas for the first fin 210 and the second fin 212 of the finFET 202.

[0037] A first fin 210 and a second fin 212 are simultaneously formed from semiconductor material 206 via an epitaxial process on substrate 204 in locations exposed by fin mask 208 and recessed oxide 216. In this example, the semiconductor material 206 of first fin 210 and second fin 212 may have a different composition than substrate 204. For example, substrate 204 may comprise primarily single-crystalline silicon, substantially free of germanium or carbon. In the version of this example where finFET 202 is a p-channel finFET 202, the semiconductor material 206 of first fin 210 and second fin 212 may comprise silicon-germanium to provide higher hole mobility compared to silicon. In the version of this example where finFET 202 is an n-channel finFET 202, the semiconductor material 206 of first fin 210 and second fin 212 may comprise silicon-carbon to provide higher electron mobility compared to silicon. This example will describe finFET 202 as a p-channel finFET 202. A corresponding n-channel finFET 202 may be formed by appropriately varying the conductivity type of the dopants used to form finFET 202 .

[0038] The semiconductor material 206 extends to the top surface 214 of the first fin 210 and the second fin 212. The first fin 210 and the second fin 212 may have a reference Figure 1B The first fin 110 and the second fin 112 have dimensions disclosed. In an alternative version of this example, the epitaxial process can be continued until the semiconductor material 206 extends above the top surface of the fin mask 208, and the semiconductor material 206 above the top surface of the fin mask 208 can be removed by an etch-back process or a chemical mechanical polishing (CMP) process.

[0039] After forming the first fin 210 and the second fin 212, the fin mask 208 is removed, leaving the recessed oxide 216 in place. The silicon nitride and silicon-doped boron nitride in the fin mask 208 can be removed by a plasma etch process using fluorine radicals.

[0040] refer to Figure 2B, a first conductivity type dopant (in this example, a p-type dopant, such as boron and optionally gallium or indium) is introduced into the substrate 204 to form a first source 220 in the first fin 210 and a second source 222 in the second fin 212. A second conductivity type dopant (in this example, an n-type dopant, such as phosphorus and optionally arsenic or antimony) is introduced into the substrate 204 to form a first body 224 in the first fin 210 and a second body 226 in the second fin 212. A first conductivity type dopant (in this example, such as boron) is introduced into the substrate 204 to form a first drain drift region 228 in the first fin 210 and a second drain drift region 230 in the second fin 212. The first drain drift region 228 and the second drain drift region 230 may have a first conductivity type dopant concentration ranging from 1×10 16 cm -3 to 4×10 16 cm -3 The average concentration of Figure 1B A first conductivity type dopant (in this example, such as boron and optionally gallium or indium) is introduced into the first drain drift region 228 to form a first drain contact region 232 in the first fin 210 and into the second drain drift region 230 to form a second drain contact region 234 in the second fin 212. The first drain contact region 232 and the second drain contact region 234 may have a first conductivity type dopant concentration greater than 1×10 19 cm -3 The average concentration of Figure 1B In this example, the first drain contact region 232 and the second drain contact region 234 are segmented, which can advantageously reduce current congestion in the finFET 202 during operation of the semiconductor device 200 .

[0041] refer to Figure 2C , a drift region mask 258 is formed over the substrate 204. The drift region mask 258 extends across the first fin 210 for Figure 2B The first enhanced portion 236 of the first drain drift region 228 (shown in FIG. Figure 2E and extending across the second fin 212 for Figure 2B The second enhanced portion 238 of the second drain drift region 230 (shown in FIG. Figure 2E The drift region mask 258 may have a shape similar to Figure 1DThe drift region mask 158 may be formed by a process similar to that used to form the drift region mask 158. Forming the drift region mask 258 to continuously expose the substrate 204 across the first fin 210 and the second fin 212 may advantageously provide greater process latitude for the process used to form the drift region mask 258 compared to a mask having discrete exposed regions. The regions exposed by the drift region mask 258 may be formed from Figure 2B The first body 224 and the second body 226 extend to Figure 2B The first drain contact region 232 and the second drain contact region 234 are as follows: Figure 2C Alternatively, the region exposed by the drift region mask 258 may be recessed from the first and second bodies 224 and 226 , or may be recessed from the first and second drain contact regions 232 and 234 .

[0042] A first conductivity type dopant 260 (such as boron in this example) is implanted into the first fin 210 and the second fin 212 where exposed by the drift region mask 258. 11 cm -2 to 3×10 12 cm -2 The first conductivity type dopant 260 is implanted with a total dose of 100 Å. The first conductivity type dopant 260 may be implanted at more than one implant energy to vertically distribute the first conductivity type dopant 260 in the first fin 210 and the second fin 212 .

[0043] The drift region mask 258 is removed after implanting the first conductivity type dopant 260. Figure 1D Removal of Drift Region Mask 158 The disclosed process removes the drift region mask 258 .

[0044] refer to Figure 2D , a charge balancing mask 246 is formed over the substrate 204. The charge balancing mask 246 is used in the first charge balancing region 248 (shown in FIG. Figure 2E and for the second charge balance region 250 (shown in Figure 2E ) and in the second fin 212 for the third charge balance region 252 (shown in Figure 2E and for the fourth charge balance region 254 (shown in Figure 2E The area for the first charge balance region 248 and the area for the second charge balance region 250 are located at Figure 2E Similarly, the area for the third charge balance region 252 and the area for the fourth charge balance region 254 are located on opposite sides of the first drain drift region 228. Figure 2EOn the opposite side of the second drain drift region 230. In this example, the charge balancing mask 246 can expose the area for the second charge balancing region 250 and the area for the third charge balancing region 252 in a single overlapping exposure zone, compared to a mask with discrete exposure areas, which can advantageously provide greater process latitude for the process used to form the charge balancing mask 246. The charge balancing mask 246 can have a similar Figure 2C The drift region mask 258 is composed of and can be formed by a process similar to the process used to form the drift region mask 258.

[0045] A second conductivity type dopant 256 (such as phosphorus in this example) is implanted into the first fin 210 and the second fin 212 where exposed by the charge balancing mask 246, i.e., the areas for the charge balancing regions 248, 250, 252, and 254. Figure 2C The second conductivity type dopant 256 is implanted at a total dose of 165% to 250% of the total dose of the first conductivity type dopant 260 to achieve counter-doping with the first conductivity type dopant 260 to provide a net average dopant density in the charge balance regions 248, 250, 252, and 254 that is 65% to 150% of the net average dopant density in the first enhanced portion 236 of the first drain drift region 228 and the second enhanced portion 238 of the second drain drift region 230. The second conductivity type dopant 256 may be implanted at more than one implantation energy to vertically distribute the second conductivity type dopant 256 in the first fin 210 and the second fin 212.

[0046] The charge balancing mask 246 is removed after implanting the second conductivity type dopant 256. Figure 2C Removal of the drift region mask 258 The disclosed process removes the charge balancing mask 246 .

[0047] In an alternative version of this example, you can Figure 2C The second conductivity type dopant 256 is implanted before the first conductivity type dopant 260 is implanted.

[0048] refer to Figure 2E , by making Figure 2C The first conductivity type dopant 260 is activated and Figure 2DThe substrate 204 is heated by an annealing process 262 for activating the second conductivity type dopant 256 in the first drain drift region 228. In this example, the activated first conductivity type dopant 260 forms a first enhanced portion 236 of the first drain drift region 228 in the first drain drift region 228 and a second enhanced portion 238 of the second drain drift region 230 in the second drain drift region 230, and extends into the first charge balance region 248 and the second charge balance region 250 and into the third charge balance region 252 and the fourth charge balance region 254. The activated second conductivity type dopant 256 and the activated first conductivity type dopant 260 achieve counter-doping to form the first charge balance region 248 and the second charge balance region 250 in the first fin 210 and the third charge balance region 252 and the fourth charge balance region 254 in the second fin 212. By way of example, the annealing process 262 can be implemented as a rapid thermal anneal, a spike anneal, or a flash anneal.

[0049] The first charge balance region 248 is adjacent to and abuts the first enhanced portion 236 of the first drain drift region 228 between the first body 224 and the first drain contact region 232, and the second charge balance region 250 is adjacent to and abuts the first enhanced portion 236 of the first drain drift region 228 between the first body 224 and the first drain contact region 232 on a side of the first enhanced portion 236 of the first drain drift region 228 opposite the first charge balance region 248. Similarly, the third charge balance region 252 is adjacent to and abuts the second enhanced portion 238 of the second drain drift region 230 between the second body 226 and the second drain contact region 234, and the fourth charge balance region 254 is adjacent to and abuts the second enhanced portion 238 of the second drain drift region 230 between the second body 226 and the second drain contact region 234 on a side of the second enhanced portion 238 of the second drain drift region 230 opposite the third charge balance region 252. Having the first charge balancing region 248 and the second charge balancing region 250 adjacent to and on opposite sides of the first enhanced portion 236 of the first drain drift region 228 and having the third charge balancing region 252 and the fourth charge balancing region 254 in a similar relationship relative to the second enhanced portion 238 of the second drain drift region 230 advantageously enables a higher operating potential to be applied to the first drain contact region 232, compared to a similar finFET without charge balancing regions.

[0050] Figure 2F and Figure 2G It is a depiction of other stages of formation along the lines shown in Figure 2E sectional view of the semiconductor device 200 along the cutting line. Figure 2FA field plate dielectric layer 264 is formed over the substrate 204. The field plate dielectric layer extends from near the first body 224 toward the first drain contact region 232 and from near the second body 226 toward the second drain contact region 234, at least partially overlapping the first enhanced portion 236 of the first drain drift region 228, and Figure 2E The second enhanced portion 238 of the second drain drift region 230 (at Figure 2F The field plate dielectric layer 264 may also overlap with the Figure 2E The first charge balance region 248 (at Figure 2F was dissected) and Figure 2E The second charge balance region 250, the third charge balance region 252 and the fourth charge balance region 254 (in Figure 2F The field plate dielectric layer 264 may have a thickness similar to Figure 1F The field plate dielectric layer 164 has the same properties as that of the field plate dielectric layer 164 and can be formed by a similar process.

[0051] A field plate 268 is formed over the field plate dielectric layer 264. Field plate 268 may include polysilicon and a metal silicide layer over the polysilicon, or may include other conductive materials, such as aluminum, copper, titanium, titanium nitride, tantalum, or tantalum nitride. Field plate 268 may be formed by forming a field plate material layer over the field plate dielectric layer 264, forming a field plate mask over the field plate material layer, and removing the field plate material layer at locations exposed by the field plate mask.

[0052] refer to Figure 2G , a gate dielectric layer 266 is formed on the first body 224 and the second body 226. The gate dielectric layer 266 extends onto the top surface 214 of the first fin 210 and the second fin 212, above the first body 224 and the second body 226, and onto two lateral surfaces of each of the first body 224 and the second body 226, the lateral surfaces extending from the top surface 214 to the recessed oxide 216. The gate dielectric layer 266 may include a reference Figure 1F The gate dielectric layer 166 may be made of any of the materials disclosed herein and may be formed by any of the processes disclosed with reference to the gate dielectric layer. By way of example, the gate dielectric layer 266 may have a thickness of 2 to 12 nanometers.

[0053] A gate 270 is formed over the gate dielectric layer 266. The gate 270 extends across the top surface 214, over the first body 224 and the second body 226, and over the lateral surfaces of the first body 224 and the second body 226. In this example, the field plate 268 can be separated from the gate 270. The gate 270 can include a reference Figure 1F The gate 170 may be made of any of the materials disclosed herein and may be formed by any of the processes disclosed with reference to the gate.

[0054] In this example, the field plate 268 can be biased independently of the gate 270 to advantageously reduce the first enhanced portion 236 of the first drain drift region 228 and the Figure 2E The second enhanced portion 238 of the second drain drift region 230 (at Figure 2G Separating field plate 268 from gate 270 may enable finFET 202 to operate at a higher potential than a comparable finFET with a continuous gate and field plate.

[0055] Various features of the examples disclosed herein may be combined in other embodiments of example semiconductor devices. For example, in finFET 102, drain contact regions 132 and 134 may be segmented. In finFET 202, drain contact regions 232 and 234 may be continuous. In finFET 102, gate 170 and field plate 168 may be separate. In finFET 202, gate 270 and field plate 268 may be continuous. In finFET 102, fins 110 and 112 may be formed by an epitaxial process. In finFET 202, fins 210 and 212 may be formed by an etching process. In finFET 102, charge balancing regions 148, 150, 152, and 154 may be counter-doped. In finFET 202, charge balancing regions 248, 250, 252, and 254 may be implanted with dopants of one conductivity type. In finFET 102 and finFET 202, enhanced portions 136 and 138 of drain drift regions 128 and 130 and enhanced portions 236 and 238 of drain drift regions 228 and 230 may be counter-doped. FinFET 102 may be a p-channel finFET. FinFET 202 may be an n-channel finFET.

[0056] While various embodiments of the present invention have been described above, it should be understood that these embodiments are presented by way of example only and not limitation. Numerous changes may be made to the disclosed embodiments in light of the disclosure herein without departing from the spirit or scope of the present invention. Therefore, the breadth and scope of the present invention should not be limited by any of the embodiments described above. Rather, the scope of the present invention should be defined in accordance with the appended claims and their equivalents.

Claims

1. A semiconductor device comprising: substrate; and A fin field effect transistor on the substrate, the fin field effect transistor comprising: a fin of semiconductor material on the substrate; a source electrode in the fin, the source electrode having a first conductivity type; a body in the fin adjacent to the source, the body having a second conductivity type opposite to the first conductivity type; a drain drift region in the fin, the drain drift region abutting the body opposite the source, the drain drift region having the first conductivity type, wherein the drain drift region is wider than the body, the drain drift region including an enhanced portion of the drain drift region, the enhanced portion of the drain drift region having a higher net average first conductivity type dopant concentration than a remaining portion of the drain drift region; a first charge balance region in the fin laterally adjacent to and abutting the enhanced portion of the drain drift region, the first charge balance region having the second conductivity type; a second charge balance region in the fin, laterally adjacent to and abutting the enhanced portion of the drain drift region opposite the first charge balance region, the second charge balance region having the second conductivity type; a drain contact region in the fin, adjacent to the drain drift region opposite the body, the drain contact region having the first conductivity type; a gate dielectric layer on the body above the top surface of the fin, the gate dielectric layer extending over both lateral surfaces of the body; and A gate is over the gate dielectric layer, the gate extending over the top surface of the fin and over the two lateral surfaces of the body.

2. The semiconductor device according to claim 1, wherein the enhanced portion of the drain drift region has a 1×10 16 cm -3 to 4×10 16 cm -3 The net average first conductivity type dopant concentration is .

3. A semiconductor device according to claim 1, wherein the first charge balance region and the second charge balance region each have a net average second conductivity type dopant concentration that is 65% to 150% of the net average first conductivity type dopant concentration in the enhanced portion of the drain drift region. 4 . The semiconductor device of claim 1 , wherein the enhanced portion of the drain drift region has a length between the body and the drain contact region of 200 nanometers to 1 micron. The semiconductor device of claim 1 , wherein the body is 100 nm to 300 nm wide. 6 . The semiconductor device of claim 1 , wherein the enhanced portion of the drain drift region is 200 nm to 400 nm wider than the body. The semiconductor device according to claim 1 , wherein the fin extends 300 nm to 800 nm above the substrate. 8 . The semiconductor device of claim 1 , wherein the FinFET further comprises a field plate at least partially overlapping the enhanced portion of the drain drift region. The semiconductor device according to claim 8 , wherein the field plate is continuous with the gate.

10. The semiconductor device according to claim 1, wherein: The fin is a first fin; The source is a first source; The subject is a first subject; The drain drift region is a first drain drift region; the enhanced portion of the first drain drift region is a first enhanced portion of the first drain drift region; The drain contact region is a first drain contact region; and The FinFET further comprises: a second fin of said semiconductor material on said substrate; a second source in the second fin, the second source having the first conductivity type; a second body in the second fin, adjacent to the second source, the second body having the second conductivity type; and a second drain drift region in the second fin, the second drain drift region abutting the second body opposite the second source, the second drain drift region having the first conductivity type, wherein the second drain drift region is wider than the second body, the second drain drift region including a second enhanced portion of the second drain drift region, the second enhanced portion of the second drain drift region having a higher net average first conductivity type dopant concentration than a remaining portion of the second drain drift region; a third charge balance region in the fin, laterally adjacent to and abutting the second enhanced portion of the second drain drift region, the third charge balance region having the second conductivity type; a fourth charge balance region in the fin, laterally adjacent to and abutting the second enhanced portion of the second drain drift region opposite the third charge balance region, the fourth charge balance region having the second conductivity type; as well as a second drain contact region in the second fin adjacent to the second enhanced portion of the second drain drift region opposite the second body, the second drain contact region having the first conductivity type; wherein the gate dielectric layer extends onto the second body, above the top surface of the second fin and extends on both lateral surfaces of the second body; and The gate extends over the top surface of the second fin, over the second body, and over the two lateral surfaces of the second body. The semiconductor device according to claim 10 , wherein the second drain contact region is continuous with the first drain contact region.

12. A method of forming a semiconductor device, comprising: providing a substrate; forming a fin of semiconductor material on the substrate; forming a source electrode in the fin, the source electrode having a first conductivity type; forming a body in the fin, the body adjacent to the source, the body having a second conductivity type opposite to the first conductivity type; forming a drain drift region in the fin, the drain drift region having the first conductivity type, the drain drift region being wider than the body; forming a drain contact region in the drain drift region, the drain contact region having the first conductivity type; forming an enhanced portion of the drain drift region in the drain drift region between the body and the drain contact region, the enhanced portion of the drain drift region having the first conductivity type, the enhanced portion of the drain drift region having a higher net average first conductivity type dopant concentration than a remaining portion of the drain drift region; forming a first charge balance region in the fin, the first charge balance region being adjacent to the enhanced portion of the drain drift region between the body and the drain contact region, the first charge balance region having the second conductivity type; forming a second charge balance region in the fin, the second charge balance region being adjacent to the enhanced portion of the drain drift region opposite the first charge balance region between the body and the drain contact region, the second charge balance region having the second conductivity type; forming a gate dielectric layer on the body above the top surface of the fin, the gate dielectric layer extending over both lateral surfaces of the body; and A gate is formed over the gate dielectric layer, the gate extending over the top surface of the fin, over the body, and over the two lateral surfaces of the body.

13. The method of claim 12, wherein forming the enhanced portion of the drain drift region comprises forming a 5×10 11 cm -2 to 3×10 12 cm -2 The first conductivity type dopant is implanted into the drain drift region with a total dose of .

14. The method of claim 12, wherein forming the first charge balance region and the second charge balance region includes implanting a second conductivity type dopant into the fin at a total dose of 65% to 150% of a total dose of the first conductivity type dopant implanted in the drain drift region to form the enhanced portion of the drain drift region. 15 . The method of claim 12 , wherein the enhanced portion of the drain drift region is formed to have a length of 200 nanometers to 1 micron between the body and the drain contact region.

16. The method of claim 12, wherein the body is formed to be 100 nm to 300 nm wide. 17 . The method of claim 12 , wherein the enhanced portion of the drain drift region is formed to be 200 nm to 400 nm wider than the body.

18. The method of claim 12, wherein the fin is formed to extend 300 nanometers to 800 nanometers above the substrate.

19. The method of claim 12, wherein: The fin is a first fin; The source is a first source; The subject is a first subject; The drain drift region is a first drain drift region; The drain contact region is a first drain contact region; and the enhanced portion of the first drain drift region is a first enhanced portion of the first drain drift region; and The method further comprises: forming a second fin of the semiconductor material on the substrate; forming a second source electrode in the second fin, the second source electrode having the first conductivity type; forming a second body in the second fin, the second body being adjacent to the second source, the second body having the second conductivity type; forming a second drain drift region in the second fin, the second drain drift region adjoining the second body opposite the second source, the second drain drift region having the first conductivity type, wherein the second drain drift region is wider than the second body; forming a second drain contact region in the second drain drift region, the second drain contact region having the first conductivity type; forming a second enhanced portion of the second drain drift region in the second drain drift region, the second enhanced portion of the second drain drift region adjoining the second body opposite the second source, the second enhanced portion of the second drain drift region having the first conductivity type, the second enhanced portion of the second drain drift region having a higher net average first conductivity type dopant concentration than a remaining portion of the second drain drift region; forming a third charge balance region in the second fin, the third charge balance region being adjacent to the second enhanced portion of the second drain drift region between the second body and the second drain contact region, the third charge balance region having the second conductivity type; forming a fourth charge balance region in the second fin, the fourth charge balance region being adjacent to the second enhanced portion of the second drain drift region opposite to the third charge balance region and between the second body and the second drain contact region, the fourth charge balance region having the second conductivity type; forming the gate dielectric layer to extend onto the second body, above the top surface of the second fin, and on both lateral surfaces of the second body; and The gate is formed to extend over the top surface of the second fin and over the two lateral surfaces of the second body.

20. The method of claim 19, wherein the second drain contact region is formed to be continuous with the first drain contact region.

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