Display substrate and display device

Abstract

A display substrate and a display device. The display substrate includes a first display area and a first region at least partially surrounding the first display area; the first display area includes a plurality of first light-emitting elements, the first region includes a plurality of first pixel circuits and at least one first capacitance compensation structure, and the display substrate includes a plurality of transparent traces extending from the first region to the first display area; at least one first pixel circuit is electrically connected to at least one light-emitting element through at least one pair of transparent traces, and is configured to control a driving current that flows through the at least one first pixel circuit, the at least one transparent trace, and the at least one first light-emitting element and drives the at least one first light-emitting element to emit light; the at least one first capacitance compensation structure is coupled to the at least one transparent trace, and is configured to compensate for parasitic capacitance caused by the at least one transparent trace coupled to the at least one first capacitance compensation structure.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate and a display device. Background Art

[0002] With the development of display electronic products such as mobile phones, the increase in the screen-to-body ratio of display screens has become a product trend, and the functional components that are essential for mobile phones, such as front cameras, have become a major factor restricting the increase in the screen-to-body ratio. In response to this problem, the industry has proposed a solution called "under-screen camera" that combines the camera and the display substrate into a display device. In such a solution, the display device includes a display substrate and a camera located under the display substrate. The area of ​​the display device with the under-screen camera can emit light and display like other areas, and at the same time have a camera function. Summary of the invention

[0003] At least some embodiments of the present disclosure provide a display substrate, which includes a first display area and a first area at least partially surrounding the first display area. The first display area includes a plurality of first light-emitting elements, the first area includes a plurality of first pixel circuits and at least one first capacitance compensation structure, and the display substrate includes a plurality of transparent wires extending from the first area to the first display area; at least one first pixel circuit among the plurality of first pixel circuits is electrically connected to at least one first light-emitting element among the plurality of first light-emitting elements through at least one transparent wire among the plurality of transparent wires, and is configured to control a driving current flowing through the at least one first pixel circuit, the at least one transparent wire and the at least one first light-emitting element and driving the at least one first light-emitting element to emit light; the at least one first capacitance compensation structure is coupled to at least one transparent wire among the plurality of transparent wires, and is configured to compensate for the parasitic capacitance caused by the at least one transparent wire.

[0004] For example, in the display substrate provided in some embodiments of the present disclosure, the compensation capacitance provided by the at least one first capacitance compensation structure and the parasitic capacitance caused by the at least one transparent trace coupled to the at least one first capacitance compensation structure are connected in parallel.

[0005] For example, in the display substrate provided in some embodiments of the present disclosure, the sum of the parasitic capacitance value of the at least one transparent wiring coupled to the at least one first capacitance compensation structure and the compensation capacitance value of the at least one first capacitance compensation structure is approximately equal to the target capacitance value.

[0006] For example, in the display substrate provided in some embodiments of the present disclosure, the target capacitance value is greater than or equal to the maximum value of the parasitic capacitance values ​​of the plurality of transparent traces.

[0007] For example, in the display substrate provided in some embodiments of the present disclosure, there is at least one transparent wiring among the multiple transparent wirings, the parasitic capacitance value of the transparent wiring is approximately equal to the target capacitance value, and the transparent wiring is not coupled to the at least one first capacitance compensation structure.

[0008] For example, in the display substrate provided in some embodiments of the present disclosure, the plurality of transparent routing lines are divided into a plurality of transparent routing groups, each of the plurality of transparent routing groups includes at least one transparent routing line; the average value of the parasitic capacitance value of the at least one transparent routing line in each transparent routing group is used as the average parasitic capacitance value of each transparent routing group; and the target capacitance value is greater than or equal to the maximum value of the average parasitic capacitance values ​​of the plurality of transparent routing groups.

[0009] For example, in the display substrate provided in some embodiments of the present disclosure, there is at least one transparent routing group among the multiple transparent routing groups, the average parasitic capacitance value of the transparent routing group is approximately equal to the target capacitance value, and the at least one transparent routing in the transparent routing group is not coupled to the at least one first capacitance compensation structure.

[0010] For example, in the display substrate provided in some embodiments of the present disclosure, the first region includes a peripheral region, and the peripheral region is located between the first display area and at least one side edge of the display substrate; the multiple first pixel circuits and the multiple first capacitor compensation structures are all located in the peripheral region.

[0011] For example, in the display substrate provided in some embodiments of the present disclosure, the first area includes a second display area, the second display area at least partially surrounds the first display area, the second display area includes a second pixel unit, the second pixel unit includes a second light-emitting element and a second pixel circuit, the second pixel circuit is electrically connected to the second light-emitting element and is configured to control a driving current flowing through the second pixel circuit and the second light-emitting element and driving the second light-emitting element to emit light; the multiple first pixel circuits and the multiple first capacitor compensation structures are all located in the second display area.

[0012] For example, in the display substrate provided in some embodiments of the present disclosure, the first area includes a second display area and a peripheral area, the second display area at least partially surrounds the first display area, and the peripheral area is located between the first display area and at least one side edge of the display substrate; the second display area includes a second pixel unit, the second pixel unit includes a second light-emitting element and a second pixel circuit, the second pixel circuit is electrically connected to the second light-emitting element, and is configured to control a driving current flowing through the second pixel circuit and the second light-emitting element and driving the second light-emitting element to emit light; a portion of the multiple first pixel circuits and a portion of the multiple first capacitor compensation structures are located in the peripheral area, and another portion of the multiple first pixel circuits and another portion of the multiple first capacitor compensation structures are located in the second display area.

[0013] For example, in the display substrate provided in some embodiments of the present disclosure, the second display area also includes a second capacitor compensation structure, which is coupled to the second pixel circuit and the second light-emitting element and is configured to provide compensation capacitance to the second pixel circuit; the compensation capacitance value of the second capacitor compensation structure is approximately equal to the target capacitance value.

[0014] For example, in the display substrate provided in some embodiments of the present disclosure, within the plane where the display substrate is located, the at least one first capacitance compensation structure is located on a side of the first pixel circuit corresponding to the at least one first capacitance compensation structure away from the first display area.

[0015] For example, in some embodiments of the present disclosure, the display substrate includes a base substrate and a pixel circuit layer, a transparent wiring layer and a light-emitting element layer sequentially arranged on the base substrate; the pixel circuit layer includes a gate layer and a source-drain layer; each of the multiple first light-emitting elements is located in the light-emitting element layer; each of the multiple first pixel circuits includes a thin film transistor, the thin film transistor includes a gate, a source and a drain, the gate is located in the gate layer, and at least one of the source and the drain is located in the source-drain layer; each of the multiple transparent wirings is located in the transparent wiring layer; the at least one first capacitor compensation structure includes a first capacitor electrode and a second capacitor electrode, and one of the first capacitor electrode and the second capacitor electrode is located in the gate layer, the source-drain layer or the transparent wiring layer.

[0016] For example, in the display substrate provided in some embodiments of the present disclosure, the source or drain is electrically connected to one of the first capacitor electrode and the second capacitor electrode, and the source or drain is also electrically connected to the first light-emitting element through the transparent wiring.

[0017] For example, in the display substrate provided in some embodiments of the present disclosure, the pixel circuit layer further includes a capacitor plate layer, and the other of the first capacitor electrode and the second capacitor electrode is located on the capacitor plate layer.

[0018] For example, in the display substrate provided in some embodiments of the present disclosure, the at least one first capacitor compensation structure includes a plurality of capacitor compensation structures, and another of the first capacitor electrode and the second capacitor electrode of the plurality of capacitor compensation structures is an integrated structure.

[0019] For example, in the display substrate provided in some embodiments of the present disclosure, the display substrate includes a first panel surface and a second panel surface, the first panel surface is used for display when the display substrate is working; the first display area is a transparent display area, which is configured to transmit light incident from one side of the first panel surface to one side of the second panel surface.

[0020] At least some embodiments of the present disclosure further provide a display device, comprising the display substrate provided by any embodiment of the present disclosure.

[0021] For example, some embodiments of the present disclosure provide a display device that further includes a sensor. The display substrate includes a first panel and a second panel, the first panel being used for display during operation; the first display area is a transparent display area, configured to transmit light incident from one side of the first panel to one side of the second panel; the sensor is disposed on one side of the second panel of the display substrate, the orthographic projection of the sensor on the display substrate at least partially overlaps with the first display area, and the sensor is configured to receive light incident from one side of the first panel.

[0022] For example, in the display device provided in some embodiments of the present disclosure, the sensor includes at least one of an image sensor, an infrared sensor, and a distance sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0024] Figure 1A is a schematic plan view of a display substrate;

[0025] Figure 1B is a schematic cross-sectional view of a partial structure of a display device;

[0026] Figure 1C for Figure 1A A partial enlarged schematic diagram of a display substrate shown;

[0027] Figure 2A is a schematic diagram of an equivalent circuit in which a transparent wiring is coupled to a first light-emitting element;

[0028] Figure 2B For flow through Figure 2A A schematic diagram showing a change in the driving current of the first light emitting element shown;

[0029] Figure 3A A schematic plan view of a display substrate provided for some embodiments of the present disclosure;

[0030] Figure 3B A partially enlarged schematic diagram of a display substrate provided in some embodiments of the present disclosure;

[0031] Figure 3C A partially enlarged schematic diagram of another display substrate provided for some embodiments of the present disclosure;

[0032] Figure 4 A schematic diagram of an equivalent circuit of a transparent wiring coupled to a first capacitance compensation structure and a first light-emitting element provided in some embodiments of the present disclosure;

[0033] Figure 5A A schematic plan view of coupling of a pixel group, a transparent wiring group, a pixel circuit group and a compensation structure group provided in some embodiments of the present disclosure;

[0034] Figure 5B A plan view schematically showing another coupling of a pixel group, a transparent wiring group, a pixel circuit group and a compensation structure group provided in some embodiments of the present disclosure;

[0035] Fig. 6A A schematic diagram of a circuit structure of a pixel driving circuit provided in some embodiments of the present disclosure;

[0036] Figure 6B A signal timing diagram of a driving method of a pixel driving circuit provided in some embodiments of the present disclosure;

[0037] Fig. 7A A local area layout of the overall structure of a display substrate provided in some embodiments of the present disclosure;

[0038] Figure 7B for Fig. 6A A schematic cross-sectional view of a display substrate along line MN is shown;

[0039] Figure 7C for Fig. 7AA schematic plan view of a first conductive layer in a display substrate shown;

[0040] Fig.7D for Fig. 7A A schematic plan view of a second conductive layer in a display substrate shown;

[0041] Fig. 7E for Fig. 7A A schematic plan view of a stack of a first conductive layer and a second conductive layer in a display substrate shown;

[0042] Figure 7F for Fig. 7A A schematic plan view of a third conductive layer in the display substrate shown;

[0043] Figure 7G for Fig. 7A A schematic plan view of a stack of a first conductive layer, a second conductive layer and a third conductive layer in a display substrate shown;

[0044] Figure 7H for Fig. 7A A schematic plan view of a fourth conductive layer in the display substrate shown;

[0045] Fig.7I for Fig. 7A A schematic plan view of a stack of a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer in a display substrate shown;

[0046] Figure 8 A schematic plan view of a display device provided in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0048] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0049] In the design of the "under-screen camera", part of the display area used to install sensors (such as image sensors, infrared sensors, distance sensors) and other components can be designed as a transparent display area. The transparent display area can facilitate the installation of sensors and other components while realizing the display function. In this way, these sensors can perform functions such as imaging, infrared sensing, distance sensing, etc. through the transparent display area without basically affecting the display function of the transparent display area, thereby helping to realize an electronic device with a full screen.

[0050] Figure 1A is a schematic plan view of a display substrate. Figure 1A As shown, the display substrate 100 includes a display area and a peripheral area 40 surrounding the display area, and the display area includes a transparent display area 10, a transition display area 20, and a main display area 30. For example, the transparent display area 10 allows light to be transmitted from one side of the display substrate 100 to the other side of the display substrate 100.

[0051] Figure 1B is a schematic cross-sectional view of a partial structure of a display device. Figure 1B As shown, the display device 100 includes Figure 1A The display substrate 110 and the sensor 120 are shown. The display substrate 110 has a first panel F1 and a second panel F2, wherein the first panel is used for display (i.e. facing the user) during operation of the display substrate 110. The sensor 120 is arranged on one side of the second panel F2 (i.e. the side of the display substrate 110 away from the user, i.e. the non-display side of the display substrate 110), and the orthographic projection of the sensor 120 on the display substrate at least partially overlaps with the transparent display area 10. The sensor 120 is configured to receive light incident from one side of the first panel F1 (i.e. the display side of the display substrate 110).

[0052] Figure 1C for Figure 1A The partially enlarged schematic diagram of the display substrate shown in FIG. Figure 1C As shown, the main display area 30 is the main display area (or called the conventional display area); compared with the transparent display area 10 and the transition display area 20, the main display area 30 may have a higher resolution (PPI, Pixel Per Inch), that is, pixels for display are arranged with a higher density in the main display area 30 (a pixel may include multiple sub-pixels). For example, in the main display area 30, each sub-pixel (as shown in the box P in the main display area 30) includes a light-emitting element and a pixel circuit for driving the light-emitting element.

[0053] For example, Figure 1C As shown, pixels for display with relatively low density (one pixel may include multiple sub-pixels) are arranged in the transparent display area 10 and / or the transition display area 20. For example, the transparent display area 10 and the transition display area 20 have the same resolution.

[0054] For example, compared with the main display area 30, pixels for display (one pixel may include multiple sub-pixels) are arranged with equal density in the transparent display area 10 and / or the transition display area 20, and the area of ​​the pixel driving circuit in the transparent display area 10 and / or the transition display area 20 is smaller than the area of ​​the pixel driving circuit in the main display area 30.

[0055] The transparent display area 10 can allow light incident from the display side of the display substrate 110 to pass through the display substrate 110 and reach the non-display side of the display substrate 110, so as to facilitate normal operation of components such as the sensor 120 located on the non-display side of the display substrate 110. Of course, the transparent display area 10 can also allow light emitted from the non-display side 120 of the display substrate 110 to pass through the display substrate 110 and reach the display side of the display substrate 110. However, since the pixel circuit of the sub-pixel is usually not light-transmissive, in order to improve the light transmittance of the transparent display area 10, the light-emitting element of the sub-pixel of the transparent display area 10 can be physically separated from the pixel circuit driving the light-emitting element.

[0056] For example, Figure 1CAs shown, the sub-pixels in the transparent display area 10 (as shown in the box A in the transparent display area 10) only retain the light-emitting elements, and the pixel circuits of the sub-pixels in the transparent display area 10 can be set in the transition display area 20, as shown in the box D in the transition display area 20, thus occupying part of the space of the transition display area 20; and part or all of the remaining space of the transition display area 20 is used to set the sub-pixels of the transition display area 20 (as shown in the box P in the transition display area 20), and the sub-pixels in the transition display area include light-emitting elements and pixel circuits driving the light-emitting elements. For example, Figure 1C As shown, there may be an idle area in the transition display area 20 (as shown by the box V in the transition display area 20), and in the idle area, usually no light-emitting element and no pixel circuit are set.

[0057] For example, Figure 1C As shown, the light emitting elements of the sub-pixels in the transparent display area 10 are connected via wiring L (such as Figure 1C ) is electrically connected to the corresponding pixel circuit in the transition display area 20. In order to improve the light transmittance of the transparent display area 1, the above-mentioned wiring L is usually a transparent wiring, or at least the portion of the wiring L located in the transparent display area 10 is transparent (in this case, even if the rest of the wiring L is not transparent, the wiring L can be considered as a transparent wiring in the present disclosure). For example, the transparent wiring can be made of transparent conductive materials, such as transparent metal oxides, such as indium tin oxide (ITO), indium gallium zinc oxide (IGZO), etc., so as to have good light transmittance. It should be noted that in the present disclosure, "transparency" and "light transmittance" only require a certain light transmittance, such as a light transmittance greater than 0, and do not require a light transmittance of 100%. For example, generally, if the light transmittance of any structure or region is greater than a certain value (for example, 40%, 45%, 50%, etc.), the structure or region can be considered "transparent" or "light transmittance".

[0058] It should be noted that in Figure 1C In the example, the box P may represent a sub-pixel, the box A may represent a light-emitting element, the box D may represent a pixel circuit, and the line L may represent a transparent line connecting a light-emitting element A and a pixel circuit D; or Figure 1C In the figure, box P can represent a pixel (i.e., a sub-pixel group, including multiple sub-pixels), box A can represent a group of light-emitting elements (including multiple light-emitting elements in a pixel), box D can represent a group of pixel circuits (including multiple pixel circuits corresponding to multiple light-emitting elements in a pixel), and line L can represent a group of transparent lines (including multiple transparent lines) connecting a group of light-emitting elements A and a group of pixel circuits D.

[0059] Figure 2Ais a schematic diagram of an equivalent circuit in which a transparent wiring L is coupled to a first light emitting element LE. Figure 1C and Figure 2A As shown, one end of the transparent wiring L is connected to the pixel circuit ( Figure 2A The other end of the transparent wiring L is coupled to the light emitting element EL (for example, coupled to the anode of the light emitting element EL). Figure 1C and Figure 2A , there is a coupling effect between the transparent wiring L and the components, wiring and other electrical structures arranged near it, so there is usually a parasitic capacitance C_L on the transparent wiring L. For different transparent wirings L (it can be generally assumed that different transparent wirings L have the same width and the same thickness), their lengths are not the same, and the pixel areas they cross are also different (various components, wiring and other electrical structures are usually present in the pixel area), so the parasitic capacitance C_L of different transparent wirings L is also different. Generally speaking, the longer the length of the transparent wiring L is and the more pixel areas it crosses, the larger its parasitic capacitance C_L is.

[0060] Figure 2B For flow through Figure 2A Schematic diagram of the change of the driving current of the first light emitting element LE shown in FIG. Figure 2A and Figure 2B When the first pixel circuit provides a driving current, first, a portion of the driving current is used to charge the parasitic capacitor C_L of the transparent wiring L, and the remaining portion of the driving current flows through the first light-emitting element LE (reference Figure 2A ), until the voltage of the parasitic capacitor C_L reaches electrical equilibrium (i.e., the voltage no longer changes), the driving current will act entirely on the first light-emitting element LE. Therefore, the driving current actually flowing through the first light-emitting element LE will experience a process from small to large until it stabilizes (refer to Figure 2B As shown in the I1 curve or the I2 curve in FIG, the larger the parasitic capacitance C_L is, the longer the time required for the driving current actually flowing through the first light-emitting element LE to reach a stable state is.

[0061] Considering two first light-emitting elements LE1 and LE2, the parasitic capacitances of the corresponding transparent wiring L are C_L1 and C_L2 (it is not prevented to assume C_L1 and C_L2), and ignoring the difference between the two first light-emitting elements LE1 and LE2 and the difference between the corresponding first pixel circuits, when displaying the same gray scale (that is, the magnitude of the driving current provided by the first pixel circuit corresponding to the two first light-emitting elements LE1 and LE2 is basically the same), the changes of the driving current actually flowing through the two first light-emitting elements LE1 and LE2 are respectively as follows: Figure 2BAs shown in the I1 curve and the I2 curve in FIG, the first light-emitting element LE1 does not emit light according to the stable value of the driving current (i.e., the driving current provided by the first pixel circuit) in a relatively short period of time, while the first light-emitting element LE2 does not emit light according to the stable value of the driving current in a relatively long period of time. Therefore, relative to the expected luminous brightness corresponding to the displayed grayscale, the luminous brightness of the two first light-emitting elements LE1 and LE2 is reduced; moreover, the reduction in the luminous brightness of the first light-emitting element LE2 is greater than the reduction in the luminous brightness of the first light-emitting element LE1, that is, the brightness of the two first light-emitting elements LE1 and LE2 is uneven, and this phenomenon is more obvious at low grayscales.

[0062] At least some embodiments of the present disclosure provide a display substrate, which includes a first display area and a first area at least partially surrounding the first display area; the first display area includes a plurality of first light-emitting elements, the first area includes a plurality of first pixel circuits and at least one first capacitor compensation structure, and the display substrate includes a plurality of transparent wirings extending from the first area to the first display area; at least one first pixel circuit among the plurality of first pixel circuits is electrically connected to at least one light-emitting element among the plurality of first light-emitting elements through at least one transparent wiring among the plurality of transparent wirings, and is configured to control a driving current flowing through the at least one first pixel circuit, the at least one transparent wiring and the at least one first light-emitting element and driving the at least one first light-emitting element to emit light; the at least one first capacitor compensation structure is coupled to at least one transparent wiring among the plurality of transparent wirings, and is configured to compensate for parasitic capacitance caused by the at least one transparent wiring coupled to the at least one first capacitor compensation structure.

[0063] Some embodiments of the present disclosure also provide a display device corresponding to the above-mentioned display substrate.

[0064] The display substrate provided in the embodiment of the present disclosure can compensate the parasitic capacitance of the transparent wiring through the first capacitance compensation structure, so that the light emitting brightness of different first light-emitting elements has better uniformity, so as to alleviate or solve the problem of uneven brightness in the first display area (especially the problem of uneven brightness when the first display area displays low grayscale), thereby improving the display effect of the first display area.

[0065] Several embodiments of the present disclosure are described in detail below in conjunction with the accompanying drawings. It should be noted that in order to keep the description of the embodiments of the present disclosure clear and concise, the detailed description of known functions and known components (elements) may be omitted. When any part (element) of the embodiments of the present disclosure appears in more than one accompanying drawing, the part (element) is represented by the same or similar reference numeral in each of the accompanying drawings.

[0066] Figure 3AA schematic plan view of a display substrate provided in some embodiments of the present disclosure, Figure 3B A partially enlarged schematic diagram of a display substrate provided in some embodiments of the present disclosure, Figure 3C A partially enlarged schematic diagram of another display substrate provided for some embodiments of the present disclosure.

[0067] For example, Figure 3A As shown, the display substrate 210 includes a first display area Rb and a first region Ra at least partially surrounding the first display area Rb. Figure 1A As shown, similar to Figure 1A The display substrate 110 shown, the display substrate 210 may also include a display area (refer to the display area of ​​the display substrate 110) and a peripheral area 40 surrounding the display area (refer to the peripheral area 40 of the display substrate 110), and the display area may include a first display area 10 (refer to the transparent display area 10 of the display substrate 110), a second display area 20 (refer to the transition display area 20 of the display substrate 110) and a third display area 30 (refer to the transition display area 10 of the display substrate 110); in this case, the first display area Rb is the first display area 10, and the first area Ra includes the second display area 20, the third display area 30 and the peripheral area 40.

[0068] For example, in some embodiments, in combination Figure 1A as well as Figures 3A-3C As shown, the first display area Rb (i.e., the first display area 10) includes a plurality of first light-emitting elements A, the first area Ra includes a plurality of first pixel circuits D and at least one first capacitor compensation structure C, and the display substrate 210 includes a plurality of transparent wires L extending from the first area Ra to the first display area Rb; each first pixel circuit D is electrically connected to a corresponding first light-emitting element A through a corresponding transparent wire L, and each first pixel circuit D is configured to control a driving current that flows through the first pixel circuit D, the corresponding transparent wire L, and the corresponding first light-emitting element A and drives the corresponding first light-emitting element A to emit light; the at least one first capacitor compensation structure C is coupled to at least one transparent wire among the plurality of transparent wires L, and is configured to compensate for the parasitic capacitance caused by the at least one transparent wire.

[0069] Figure 4 A schematic diagram of an equivalent circuit of a transparent wiring L coupled to a first capacitance compensation structure C and a first light-emitting element EL (ie, first light-emitting element A) provided in some embodiments of the present disclosure. Figure 3B , Figure 3C and Figure 4 As shown, the transparent trace L (such as Figure 3B and Figure 3C One end of the line segment or the broken line segment connecting the first pixel circuit D and the first light emitting element A is connected to the first pixel circuit D ( Figure 4 The transparent wiring L is coupled to the first compensation capacitor structure C, and the other end of the transparent wiring L is coupled to the light emitting element EL (for example, coupled to the anode of the light emitting element EL). Figure 4 As shown, the compensation capacitor C provided by the first capacitor compensation structure C is connected in parallel with the parasitic capacitor C_L caused by the transparent wiring L, so that the compensation capacitor C of the first capacitor compensation structure C can be used to compensate for the parasitic capacitor C_L caused by the transparent wiring L. For example, in some embodiments, the sum of the parasitic capacitance value C_L of the transparent wiring L and the compensation capacitance value of the first capacitor compensation structure C can be substantially equal to the same target capacitance value; thus, referring to the aforementioned Figure 2B It can be seen from the relevant description that in this way, the change curve of the driving current flowing through each first light-emitting element LE can be adjusted to be basically consistent. In other words, by setting the first capacitor compensation structure C, the luminance of the first light-emitting elements LE in the first display area 10 when displaying the same gray scale can be basically consistent, thereby alleviating or solving the problem of uneven brightness in the first display area and improving the display effect of the first display area.

[0070] It should be noted that, in the present disclosure, "a is approximately equal to b" means that the value of a fluctuates within x% of the value of b; for example, the value range of x can be 3 to 10, and the embodiments of the present disclosure include but are not limited to this. For example, x can be equal to 3, 5, 7, 10, etc., and the embodiments of the present disclosure include but are not limited to this.

[0071] For example, in some embodiments, the target capacitance value may be greater than or equal to the maximum value of the parasitic capacitance value C_L of each transparent wiring L. For example, in some embodiments, the target capacitance value may be equal to the maximum value of the parasitic capacitance value C_L of each transparent wiring L. In this case, the transparent wiring L having a parasitic capacitance value substantially equal to the target capacitance value does not need to be compensated, that is, the transparent wiring L having a parasitic capacitance value substantially equal to the target capacitance value may not be coupled to the first capacitance compensation structure C; thus, the number of first capacitance compensation structures C arranged may be reduced, saving space on the display substrate.

[0072] For example, in some embodiments, in combination Figure 3A and Figure 3B As shown, the first region Ra may include a peripheral region 40, and the peripheral region 40 is located at the first display area 10 and at least one side edge of the display substrate (eg Figure 3B For example, Figure 3B As shown, the first pixel circuits D and the first capacitance compensation structures C in the display substrate 210 may all be located in the peripheral area 40, and each first capacitance compensation structure C is coupled to the corresponding first pixel circuit D. For example, Figure 3BAs shown, the first capacitor compensation structure C, the first pixel circuit D and the transparent wiring L corresponding to each other are coupled to the same node (such as Figure 3B As shown in the figure, the endpoint of the line segment connecting the first capacitance compensation structure C and the first pixel circuit D is located in the box D, and the endpoint coincides with one endpoint of the transparent wiring L).

[0073] For example, in some embodiments, Figure 3B In the display substrate shown in FIG. 1 , the first region Ra may further include a second display area 20 and a third display area 30. Figure 3B As shown, the second display area includes a second pixel unit P, and the second pixel unit P may include a second light emitting element ( Figure 3B ) and a second pixel circuit ( Figure 3B For example, the second pixel circuit is electrically connected to the second light-emitting element (the connection path does not include the transparent wiring L), and is configured to control the driving current flowing through the second pixel circuit and the second light-emitting element and driving the second light-emitting element to emit light. Similarly, the third display area 30 also includes a second pixel unit P. For example, Figure 3B As shown, there may also be an idle area (such as Figure 3B In the idle area, no light emitting element or pixel circuit is usually set. For example, the resolution of the second display area 20 can be generally greater than or equal to the resolution of the first display area 10, and the resolution of the third display area 30 can be generally greater than or equal to the resolution of the second display area 20 / the first display area 10. The embodiments of the present disclosure include but are not limited to this.

[0074] For example, in some embodiments, Figure 3B In the display substrate shown, at least a portion of the transparent wiring L may extend through the second display area 20 .

[0075] It should be understood that Figure 1C Compared to the display substrate shown in Figure 3B In the display substrate shown in FIG. 1 , the first pixel circuit D does not need to be provided in the second display area 20. Therefore, the second pixel units P in the second display area 20 may have the same dense arrangement structure as the second pixel units P in the third display area 30. That is, in some embodiments, Figure 3B A second pixel unit is arranged in an idle area V in the second display area 20 of the display substrate shown, so that the second display area 20 has the same pixel unit arrangement structure as the third display area 30 , that is, the resolution of the second display area 20 is the same as that of the third display area 30 .

[0076] For example, in some embodiments, in combination Figure 3A and Figure 3CAs shown, the first area Ra may include a second display area 20, and the second display area 20 at least partially surrounds the first display area 10. Figure 3C As shown, the second display area 20 includes a second pixel unit P, and the second pixel unit P may include a second light emitting element ( Figure 3C ) and a second pixel circuit ( Figure 3C For example, the second pixel circuit is electrically connected to the second light-emitting element (the connection path does not include a transparent wiring), and is configured to control a driving current that flows through the second pixel circuit and the second light-emitting element and drives the second light-emitting element to emit light. Figure 3C As shown, the first pixel circuits D and the first capacitance compensation structures C in the display substrate 210 may all be located in the second display area 40, and each first capacitance compensation structure C is coupled to the corresponding first pixel circuit D. For example, Figure 3C As shown, the first capacitor compensation structure C, the first pixel circuit D and the transparent wiring L corresponding to each other are coupled to the same node (such as Figure 3C As shown in FIG. 1 , the endpoint of the line segment connecting the first capacitance compensation structure C and the first pixel circuit D is located in the box D, and the endpoint coincides with an endpoint of the transparent wiring L. For example, Figure 3C As shown, there may also be an idle area (such as Figure 3C As shown in the box V in the second display area 20, in the idle area, usually no light-emitting element and no pixel circuit are set.

[0077] For example, in some embodiments, in combination Figures 3A-3C As shown, a portion of the first pixel circuit D and a portion of the first capacitor compensation structure C may be located in the peripheral area 40, while another portion of the first pixel circuit D and another portion of the first capacitor compensation structure C may be located in the second display area 20. In this case, the layout and other details of the first pixel circuit D and the first capacitor compensation structure C located in the peripheral area 40 may refer to Figure 3B For the description of the embodiment shown in FIG. 1 , the layout and other details of the first pixel circuit D and the first capacitor compensation structure C in the second display area 20 can be referred to. Figure 3C The relevant descriptions of the embodiments shown are not repeated here. Thus, on the one hand, the problem of large parasitic capacitance of some transparent wirings caused by too many first pixel circuits D and first capacitor compensation structures C in the peripheral area 40 can be avoided, and on the other hand, the problem of the peripheral area 40 occupying too large a display substrate area and causing a reduction in the display area can be avoided.

[0078] For example, in some embodiments, in order to simplify the design and layout of the first capacitance compensation structure C, the transparent routing L can be grouped and compensated. For example, a plurality of transparent routings can be divided into a plurality of transparent routing groups, each transparent routing group including at least one transparent routing. For example, in the case where the transparent routing group includes a plurality of transparent routings, the parasitic capacitance values ​​of the plurality of transparent routings are roughly equal. For example, the average value of the parasitic capacitance value of the at least one transparent routing in each transparent routing group can be used as the average parasitic capacitance value of each transparent routing group. For example, in the case where the transparent routing group includes a transparent routing, the parasitic capacitance value of the transparent routing (regarded as the average value of the parasitic capacitance value) is used as the average parasitic capacitance value of the transparent routing group; in the case where the transparent routing group includes a plurality of transparent routings, the average value of the parasitic capacitance values ​​of the plurality of transparent routings is used as the average parasitic capacitance value of the transparent routing group. For example, the target capacitance value is greater than or equal to the maximum value of the average parasitic capacitance value of each transparent routing group.

[0079] For example, in some embodiments, the first light-emitting element corresponding to the transparent routing in each transparent routing group can be used as a pixel group, the pixel circuit corresponding to the transparent routing in each transparent routing group can be used as a pixel circuit group, and the first capacitance compensation structure corresponding to the transparent routing in each transparent routing group can be used as a compensation structure group. For example, in some embodiments, the target capacitance value is equal to the maximum value of the average parasitic capacitance value of the transparent routing group. In this case, the transparent routing in the transparent routing group whose average parasitic capacitance value is approximately equal to the target capacitance value does not need to be compensated, that is, the transparent routing group whose average parasitic capacitance value is approximately equal to the target capacitance value does not need to be provided with a corresponding compensation structure group. That is, the transparent routing whose parasitic capacitance value is approximately equal to the target capacitance value may not be coupled to the first capacitance compensation structure C. Thereby, the number of compensation structure groups arranged can be reduced, that is, the number of first capacitance compensation structures C arranged can be reduced, thereby saving space on the display substrate.

[0080] It should be understood that, corresponding to the above-mentioned group compensation scheme, Figure 3B and Figure 3C The boxes A, D, and C in FIG. 1 are respectively regarded as a pixel group (including the first light-emitting element), a pixel circuit group, and a compensation structure group. Similarly, Figure 3B and Figure 3C The box P in the figure is regarded as a pixel group (including the second light-emitting element and the second pixel circuit).

[0081] Figure 5A A planar schematic diagram of the coupling of a pixel group, a transparent wiring group, a pixel circuit group and a compensation structure group provided for some embodiments of the present disclosure. Figure 5AThe pixel circuit group D and the compensation structure group C are shown in the case where they are located in the peripheral area 40. Schematically, Figure 5A The figure shows a situation where the pixel group A includes three first light emitting elements, the transparent wiring group L includes three transparent wirings, the pixel circuit group includes three first pixel circuits, and the compensation structure group C includes three first capacitor compensation structures. Figure 5A As shown, the first light emitting element in each pixel group A is electrically connected to the first pixel circuit in the corresponding pixel circuit group through the transparent wiring of the corresponding transparent wiring group L, and the first pixel circuit in the pixel circuit group is also coupled to the first capacitor compensation structure in the corresponding compensation structure group. Figure 5A As shown, the transparent wiring and the first capacitance compensation structure are coupled to the same node (such as Figure 5A ).

[0082] Figure 5B A plan view schematically showing another coupling of pixel groups, transparent wiring groups, pixel circuit groups and compensation structure groups provided for some embodiments of the present disclosure. Figure 5B The pixel circuit group D and the compensation structure group C are shown in the second display area 20. Schematically, Figure 5B The figure shows a situation where the pixel group A includes three first light emitting elements, the transparent wiring group L includes three transparent wirings, the pixel circuit group includes three first pixel circuits, and the compensation structure group C includes three first capacitor compensation structures. Figure 5B As shown, the first light emitting element in each pixel group A is electrically connected to the first pixel circuit in the corresponding pixel circuit group through the transparent wiring of the corresponding transparent wiring group L, and the first pixel circuit in the pixel circuit group is also coupled to the first capacitor compensation structure in the corresponding compensation structure group. Figure 5B As shown, the transparent wiring and the first capacitance compensation structure are coupled to the same node (such as Figure 5B ).

[0083] It should be noted that in practical applications, Figure 3B and Figure 3C As shown, the first light emitting element, the first pixel circuit, the first capacitor compensation structure, and the second pixel unit are usually arranged in an array in the display area where they are located. In addition, Figure 3B and Figure 3C The layout of the transparent wiring L in the figure is schematic, and the embodiments of the present disclosure are not limited thereto. In practical applications, on the basis of convenient manufacturing, the transparent wiring can be reasonably laid out according to actual needs to minimize the difference in the parasitic capacitance values ​​of each transparent wiring, thereby reducing the compensation capacitance value of the first capacitance compensation structure, and further reducing the space occupied by the first capacitance compensation structure.

[0084] It should also be noted that the embodiments of the present disclosure do not limit the specific structures of the first light-emitting element, the first pixel circuit, the first capacitor compensation structure, and the second pixel unit. For example, in order to simplify the design and facilitate manufacturing, the specific structure of the first light-emitting element can be the same as the specific structure of the second light-emitting element in the second pixel unit, and the specific structure of the first pixel circuit can be the same as the specific structure of the second pixel circuit in the second pixel unit. The embodiments of the present disclosure include but are not limited to this.

[0085] For example, in order to achieve the same PPI of the second display area 20 and the first display area 10, the projection area of ​​the first light-emitting element on the substrate is smaller than the projection area of ​​the second light-emitting element in the second pixel unit on the substrate, and the projection area of ​​the first pixel circuit on the substrate is smaller than the projection area of ​​the second pixel circuit in the second pixel unit on the substrate. The embodiments of the present disclosure include but are not limited to this. For example, in some embodiments, as Figure 3B , Figure 3C , Figure 5A and Figure 5B As shown, in the plane where the display substrate is located, the first capacitance compensation structure can be arranged on a side of the corresponding first pixel circuit away from the first display area 10, so as to facilitate the layout of the transparent wiring.

[0086] For example, in some embodiments, in order to make the brightness of the second display area 20 and the first display area 10 uniform, the second pixel unit P in the second display area 20 may be capacitively compensated. For example, the second display area 20 may further include a second capacitive compensation structure, which is coupled to the second pixel circuit and the second light-emitting element in the second pixel unit P and is configured to provide a compensation capacitance to the second pixel circuit. For example, the compensation capacitance value of the second capacitive compensation structure is substantially equal to the target capacitance value, so that, referring to the aforementioned Figure 2B From the relevant description, it can be seen that in this way, the variation curve of the driving current flowing through the second light-emitting element can be adjusted to be basically consistent with the variation curve of the driving current flowing through the first light-emitting element, thereby making the brightness of the second display area 20 and the first display area 10 uniform, thereby improving the overall display effect of the first display area 10 and the second display area 20.

[0087] It should be noted that, in practical applications, the parasitic flashlight value of the transparent wiring and the compensation capacitance value of the first capacitance compensation structure may be determined by simulation and / or experimental measurement and other technical means.

[0088] For example, in some embodiments, the first pixel circuit and the second pixel circuit may adopt common pixel driving circuits such as 2T1C, 4T1C, 4T2C, 7T1C, etc., but are not limited thereto. The present disclosure does not limit the specific structures of the first pixel circuit and the second pixel circuit. For example, Fig. 6A A 7T1C pixel driving circuit is shown. Fig. 6A As shown, the 7T1C pixel driving circuit includes first to seventh transistors T1-T7 and a storage capacitor Cst.

[0089] For example, Fig. 6A As shown, the gate of the first transistor T1 is connected to the first reset signal terminal (or the first reset signal line) to receive the first reset signal Reset1, the first electrode of the first transistor T1 is connected to the first reset voltage terminal (or the first reset voltage line) to receive the first reset voltage Vinit1, and the second electrode of the first transistor T1 is connected to the first node N1; the gate of the second transistor T2 is connected to the scan signal terminal (or the scan signal line) to receive the scan signal Gate, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the third node N3; the gate of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T2 is connected to the third node N3, and the second electrode of the second transistor T3 is connected to the second node N3; the gate of the fourth transistor T4 is connected to the scan signal terminal (or the scan signal line) to receive the scan signal Gate, the first electrode of the fourth transistor T4 is connected to the second node N2, and the second electrode of the fourth transistor T4 is connected to the data signal terminal (or the data signal line) to receive the data signal Vdata; the fifth transistor T The gate of the fifth transistor T5 is connected to the light emitting control signal terminal (or the light emitting control signal line) to receive the light emitting control signal EM, the first electrode of the fifth transistor T5 is connected to the second node N2, and the second electrode of the fifth transistor T5 is connected to the first power supply terminal (or the first power supply line) to receive the first power supply voltage VDD (for example, a high voltage); the gate of the sixth transistor T6 is connected to the light emitting control signal terminal (or the light emitting control signal line) to receive the light emitting control signal EM, the first electrode of the sixth transistor T6 is connected to the fourth node N4, and the second electrode of the sixth transistor T6 is connected to the third node N3; the gate of the seventh transistor T7 is connected to the second reset signal terminal (or the second reset signal line) to receive the second reset signal Reset2, the first electrode of the seventh transistor T7 is connected to the second reset voltage terminal (or the second reset voltage line) to receive the second reset voltage Vinit2, and the second electrode of the seventh transistor T7 is connected to the fourth node N4; the first end of the storage capacitor Cst is coupled to the first node N1, and the second end of the storage capacitor Cst is coupled to the first power supply terminal (or the first power supply line) to receive the first power supply voltage VDD.

[0090] For example, for the first pixel circuit, the anode of the first light emitting element EL is electrically connected to the fourth node N4 through the transparent wiring, the cathode of the first light emitting element EL is connected to the second power supply terminal (or the second power supply line) to receive the second power supply voltage VSS (for example, a low voltage), and the first capacitor compensation structure ( Fig. 6A(not shown) is coupled to the fourth node N4. For example, for the second pixel circuit, the anode of the second light emitting element EL is directly coupled to the fourth node N4, and the cathode of the second light emitting element EL is connected to the second power supply terminal (or the second power supply line) to receive the second power supply voltage VSS (for example, a low voltage). For example, for the second pixel circuit in the second display area 20, in the case of setting the second capacitor compensation structure, the second capacitor compensation structure ( Fig. 6A ) is coupled to the fourth node N4.

[0091] It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics. The source and drain of the transistors used here may be symmetrical in structure, so the source and drain may have no difference in structure. Fig. 6A In the illustrated embodiment, in order to distinguish the two electrodes of the transistor except the gate, one of the electrodes is directly described as the first electrode and the other as the second electrode.

[0092] In addition, transistors can be divided into N-type and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages); when the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages). For example, in Fig. 6A In the pixel driving circuit shown, the first to seventh transistors T1-T7 are all P-type transistors, such as low temperature polysilicon thin film transistors. However, the disclosed embodiment does not limit the type of transistors. When the type of transistors changes, the connection relationship in the circuit and the polarity of the signal can be adjusted accordingly.

[0093] The following combination Figure 6B The signal timing diagram shown is Fig. 6A The working principle of the pixel driving circuit shown in FIG. Figure 6B As shown, the display process of each frame of image includes three stages, namely initialization stage 1, data writing and compensation stage 2, and light emitting stage 3.

[0094] In the initialization phase 1, a first reset control signal Reset1 is input to turn on the first transistor T1, and a first reset voltage Vinit1 is applied to the gate of the first transistor T1, so as to reset the first node N1.

[0095] In the data writing and compensation phase 2, the scan signal Gate and the data signal Vdata are input, the second transistor T2 and the fourth transistor T4 are turned on, the data signal data is written into the second node N2 via the fourth transistor T4, and the first node N1 is charged via the third transistor T3 and the second transistor T2, until the potential of the first node N1 changes to Vdata+Vth, and the third transistor T3 is turned off, where Vth is the threshold voltage of the third transistor T3. The potential of the first node N1 is stored in the storage capacitor Cst and maintained, that is, the voltage information with the data signal Vdata and the threshold voltage Vth is stored in the storage capacitor Cst, so as to provide grayscale display data and compensate the threshold voltage of the third transistor T3 itself in the subsequent light-emitting phase.

[0096] In the data writing and compensation phase 2, the second reset control signal Reset2 may be input to turn on the seventh transistor T7, and the second reset voltage Vinit2 may be applied to the fourth node N4, thereby resetting the fourth node N4. For example, the fourth node N4 may also be reset in the initialization phase 1, for example, the first reset control signal Reset1 and the second reset control signal Reset2 may be the same. The embodiments of the present disclosure are not limited to this.

[0097] In the light emitting stage 3, the light emitting control signal EM is input to turn on the fifth transistor T5, the sixth transistor T6 and the third transistor T3, and the sixth transistor T6 applies the driving current to the light emitting element EL to make it emit light. The value of the driving current Id provided by the pixel driving circuit can be obtained according to the following formula:

[0098] Id=K(VGS-Vth) 2 =K[(Vdata+Vth-VDD)-Vth] 2 =K(Vdata-VDD) 2 ,

[0099] Where K is a constant.

[0100] In the above formula, Vth represents the threshold voltage of the first transistor T1, VGS represents the voltage between the gate and the source (here, the first electrode) of the third transistor T3, and K is a constant value related to the third transistor T3 itself. It can be seen from the above calculation formula of Id that the driving current Id provided by the pixel driving circuit is no longer related to the threshold voltage Vth of the third transistor T3, thereby achieving compensation for the pixel driving circuit, solving the problem of threshold voltage drift caused by the process and long-term operation of the driving transistor (the third transistor T3 in the embodiment of the present disclosure), eliminating its influence on the driving current Id, and thus improving the display effect of the display device using it.

[0101] Fig. 7A A local area layout of the overall structure of a display substrate is provided in some embodiments of the present disclosure. Fig. 7A The layout of the first pixel circuit D and the first capacitance compensation structure is exemplarily shown. Figure 7B for Fig. 7A The cross-sectional view of the display substrate along the MN line is shown in FIG. Figure 7B As shown, the display substrate includes a base substrate SUB and a pixel circuit layer LX1, a transparent wiring layer LX2 and a light emitting element layer LX3 which are sequentially arranged on the base substrate SUB.

[0102] For example, Figure 7B As shown, the pixel circuit layer LX1 includes an active layer AL, a gate layer Gate1 and a source-drain layer SD (for example, including a first source-drain layer SD1 and a second source-drain layer SD2). For example, the active layer AL may include a semiconductor material, and the gate layer Gate1, the first source-drain layer SD1 and the second source-drain layer SD2 may include a metal material or an alloy material. For example, the first pixel circuit includes a thin film transistor, which includes a gate, a source and a drain, the gate is located in the gate layer Gate1, and at least one of the source and the drain is located in the source-drain layer SD. It should be noted that Figure 7B Only one thin film transistor in the first pixel circuit is schematically shown in FIG. Fig. 6A The sixth transistor in the 7T1C pixel driving circuit shown, embodiments of the present disclosure include but are not limited to this.

[0103] For example, Figure 7B As shown, the transparent wiring layer LX2 includes a first transparent wiring layer ITO1, a second transparent wiring layer ITO2, and a third transparent wiring layer ITO3. For example, each transparent wiring is located in the transparent wiring layer LX2. For example, each transparent wiring includes a portion located in the first transparent wiring layer ITO1, the second transparent wiring layer ITO2, and the third transparent wiring layer ITO3, and the embodiments of the present disclosure include but are not limited to this. For example, the first transparent wiring layer ITO1, the second transparent wiring layer ITO2, and the third transparent wiring layer ITO3 may include a transparent conductive material, such as a transparent metal oxide, such as indium tin oxide (ITO), indium gallium zinc oxide (IGZO), etc., to have good light transmittance.

[0104] For example, Figure 7B As shown, the light emitting element layer LX3 includes an anode layer Anode, a light emitting layer ELL and a cathode layer Cathode. For example, the first light emitting element includes an anode located in the anode layer Anode, a light emitting material located in the light emitting layer ELL and a cathode located in the cathode layer Cathode. For example, Figure 7BThe display substrate shown can be an organic light emitting diode (OLED) display substrate or a quantum dot light emitting diode (QLED) display substrate, etc. The embodiments of the present disclosure do not limit the specific type of the display substrate. For example, in the case where the display substrate is an organic light emitting diode display substrate, the light emitting layer ELL may include small molecule organic materials or polymer molecule organic materials, which may be fluorescent luminescent materials or phosphorescent luminescent materials, and may emit red light, green light, blue light, or white light, etc.; and, according to actual needs, the light emitting layer ELL may further include one or more functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer. For example, in the case where the display substrate is a quantum dot light emitting diode (QLED) display substrate, the light emitting layer ELL may include quantum dot materials, such as silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots, and indium arsenide quantum dots. For example, as Figure 7B As shown, the source or drain of the thin film transistor is electrically connected to the first light-emitting element (for example, to the anode of the first light-emitting element) through a transparent wiring.

[0105] For example, the first capacitor compensation structure includes a first capacitor electrode and a second capacitor electrode. For example, the compensation capacitance value of the first capacitor compensation structure is generally proportional to the overlap area of ​​the first capacitor electrode and the second capacitor electrode, and inversely proportional to the distance between the first capacitor electrode and the second capacitor electrode (the distance in the direction perpendicular to the display substrate). For example, Figure 7B As shown, the pixel circuit layer LX1 may further include a capacitor plate layer Gate2. Figure 7B As shown, one of the first capacitor electrode and the second capacitor electrode is located at the gate layer Gate1, and the other of the first capacitor electrode and the second capacitor electrode is located at the capacitor plate layer Gate2. Figure 7B As shown, the source or drain of the thin film transistor is electrically connected to one of the first capacitor electrode and the second capacitor electrode. For example, the other of the first capacitor electrode and the second capacitor electrode can be electrically connected to a DC signal, such as the first power line VDD or the second power line VSS. For example, in some embodiments, the other of the first capacitor electrode and the second capacitor electrode of the plurality of capacitor compensation structures can be an integrated structure, thereby simplifying the process during the manufacturing process.

[0106] It should be noted that Figure 7BThe arrangement of the first capacitor compensation structure shown is schematic, and the embodiments of the present disclosure are not limited thereto. For example, in some embodiments, one of the first capacitor electrode and the second capacitor electrode can be located in a certain layer among the gate layer Gate1, the source-drain layer SD, the transparent wiring layer LX2, and the capacitor plate layer Gate2, and the other of the first capacitor electrode and the second capacitor electrode can be located in any layer of the above layers except the certain layer, as long as the first capacitor compensation structure thus formed can meet the requirements of capacitor compensation. Of course, in the case where the first capacitor electrode and the second capacitor electrode are respectively located in two layers among the gate layer Gate1, the source-drain layer SD, and the transparent wiring layer LX2, the capacitor plate layer Gate2 can be omitted in the display substrate.

[0107] It should be noted that multiple elements, components, structures and / or parts located in the same layer or arranged in the same layer can usually be made of the same material and can be formed by the same composition process. Specifically, the same film-forming process can be used to form a film layer for forming a specific pattern, and then the same mask can be used to pattern the film layer through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous.

[0108] By arranging a capacitor electrode in the first capacitor compensation structure on the same layer as a layer of the display substrate, the process can be simplified and the cost can be saved. Of course, in some embodiments, a conductive layer can be specially arranged on the display substrate to form a capacitor electrode in the first capacitor compensation structure.

[0109] For example, Figure 7B As shown, as needed, the display substrate may also include a first gate insulating layer GI1, a second gate insulating layer GI2, an interlayer dielectric layer ILD, a passivation layer PVX (for example, it may also serve as a planarization layer PLN1), planarization layers PLN2-PLN5, and a pixel defining layer PDL and other functional layers. For example, these functional layers may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene or phenolic resin. It should be noted that the embodiments of the present disclosure do not specifically limit the materials of the aforementioned various functional layers.

[0110] For example, in some embodiments, the configuration of the second pixel circuit can refer to the configuration of the first pixel circuit, and the configuration of the second light-emitting element can refer to the configuration of the first light-emitting element, and the embodiments of the present disclosure are not limited to this. For example, in some embodiments, when the display substrate includes a second capacitor compensation structure, the configuration of the second capacitor compensation structure can refer to the configuration of the first capacitor compensation structure, and the embodiments of the present disclosure are not limited to this.

[0111] It should be understood that Figure 7B The structure of each layer of the display substrate shown is schematic. Figure 7B The display substrate shown can reduce some of the shown functional layers as needed, as long as it does not affect the display function of the display substrate and the capacitance compensation function of the first capacitance compensation structure; of course, some functional layers (for example, buffer layers, encapsulation layers, etc.) not shown can also be added as needed. The embodiments of the present disclosure are not limited to this.

[0112] Figure 7C for Fig. 7A Schematic diagram of a plan view of the first conductive layer (ie, the aforementioned gate layer Gate1) in the display substrate shown in FIG. Figure 7C As shown, the capacitor plate M1 of the first capacitor compensation structure, the gate of the thin film transistor, a capacitor plate Cst1 of the storage capacitor Cst, the gate line W1 (including the reset signal line, the scan signal line, the light-emitting control signal line), etc. can all be located in the first conductive layer; it should be noted that the present disclosure includes but is not limited to this. For example, Figure 7C As shown, the capacitor plates M1 of each first capacitor compensation structure are separately arranged.

[0113] Fig.7D for Fig. 7A Schematic diagram of the second conductive layer (i.e., the aforementioned capacitor plate layer Gate2) in the display substrate shown in FIG. Fig.7D As shown, the capacitor plate M2 of the first capacitor compensation structure, another capacitor plate Cst2 of the aforementioned storage capacitor Cst, the reset voltage line W2, etc. can all be located in the second conductive layer; it should be noted that the present disclosure includes but is not limited to this. Fig.7D As shown, the capacitor plates M2 of each first capacitor compensation structure can be integrally arranged, and the embodiments of the present disclosure include but are not limited to this.

[0114] Fig. 7E for Fig. 7A Schematic diagram of a plan view of a first conductive layer and a second conductive layer stacked in a display substrate shown in FIG. Fig. 7EAs shown, the capacitor plate Cst1 and the capacitor plate Cst2 overlap to form a storage capacitor Cst; the capacitor plate M1 and the capacitor plate M2 overlap to form a capacitor structure. If the capacitor plate M1 is coupled to the source or drain of the sixth transistor T6, the capacitor structure can be used as a first capacitor compensation structure. For example, in some embodiments, Fig. 7E As shown, a shielding portion S2 may also be provided in the second conductive layer, and the shielding portion is used to shield certain thin film transistors (for example, Fig. 6A For example, in some embodiments, a first power line may be provided in the second conductive layer; for example, the first power line may be coupled to the capacitor plate M2 of the first capacitor compensation structure.

[0115] Figure 7F for Fig. 7A Schematic diagram of the third conductive layer (ie, the first source-drain electrode layer SD1) in the display substrate shown in FIG. Figure 7F As shown, the capacitor plate M3, the first power line W31, the data signal line W32, etc. of the first capacitor compensation structure can all be located in the third conductive layer; it should be noted that the present disclosure includes but is not limited to this. Figure 7F As shown, the capacitor plates M3 of each first capacitor compensation structure are separately arranged.

[0116] Figure 7G for Fig. 7A FIG. 1 is a schematic plan view of a stack of a first conductive layer, a second conductive layer, and a third conductive layer in a display substrate. Figure 7G As shown, the capacitor plate M3 and the capacitor plate M2 overlap to form a capacitor structure; in this case, the first capacitor compensation structure can be a complex capacitor structure including three capacitor plates (i.e., capacitor plates M1-M3) arranged in different layers, and at least one of the capacitor plates M1 and M3 can be coupled to the source or drain of the sixth transistor T6. It should be understood that for the first capacitor compensation structure, an additional capacitor plate is provided on the basis of the two capacitor plates, which increases the way to adjust the compensation capacitance value of the first capacitor compensation structure.

[0117] Figure 7H for Fig. 7A Schematic diagram of a fourth conductive layer (ie, the aforementioned second source-drain electrode layer SD2) in the display substrate shown in FIG. Figure 7H As shown, the capacitor plate M4 of the first capacitor compensation structure, the wiring W4 (used to connect the first pixel circuit and the first capacitor compensation structure), etc. can all be located in the fourth conductive layer; it should be noted that the present disclosure includes but is not limited to this. Figure 7HAs shown, the capacitor plates M4 of each first capacitor compensation structure can be integrally arranged, and the embodiments of the present disclosure include but are not limited to this. For example, one end of the wiring W4 can be coupled to the source or drain of the sixth transistor T6, and the other end of the wiring W4 can be coupled to at least one of the capacitor plates M1 and the capacitor plates M3.

[0118] Fig.7I for Fig. 7A Schematic diagram of a plan view of a stack of a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer in a display substrate shown in FIG. Figure 7G As shown, the first pixel circuit and the first capacitor compensation structure are electrically connected via a wiring W4. In this case, the first capacitor compensation structure may be a complex capacitor structure including four capacitor plates (i.e., capacitor plates M1-M4) disposed on different layers, and at least one of the capacitor plates M1 and M3 may be coupled to the source or drain of the sixth transistor T6. It should be understood that, for the first capacitor compensation structure, two additional capacitor plates are provided on the basis of the two capacitor plates, further increasing the way to adjust the compensation capacitance value of the first capacitor compensation structure.

[0119] It should be understood that in Figure 7C-Figure 7I In the illustrated embodiment, each first capacitor compensation structure may include X capacitor plates C0 (one capacitor plate C0 of the first capacitor compensation structure is arranged in each conductive layer) arranged in any X conductive layers of the above-mentioned four conductive layers (i.e., the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer), wherein X=2, 3, 4, the capacitor plate C0 electrically connected to the first pixel circuit is discrete in the conductive layer where it is located, and the capacitor plate C0 not electrically connected to the first pixel circuit can be discrete in the conductive layer where it is located, or can be integrally arranged with the remaining capacitor plates C0 in the same conductive layer.

[0120] It should also be understood that in the aforementioned embodiments, the capacitor plates of the first capacitor compensation structure are all in the shape of long strips, and the present disclosure includes but is not limited to this. For example, according to actual needs, the capacitor plates of the first capacitor compensation structure can also be in the shape of a wave, a broken line, etc. Similarly, in the case where the display substrate includes a second capacitor compensation structure, the capacitor plates of the second capacitor compensation structure can also be in the shape of a long strip, a wave, a broken line, etc.

[0121] For example, refer to Figure 1B As shown, similar to Figure 1B The display substrate shown in the embodiment of the present disclosure may also include a first panel surface F1 and a second panel surface F2. The first panel surface F1 is used for display during operation of the display substrate. The first display area is a transparent display area, which is configured to transmit light incident from one side of the first panel surface F1 to the second side of the second panel surface F2.

[0122] It should be noted that the embodiments of the present disclosure do not limit the shapes of the first display area, the first region, the second display area, the third display area, the peripheral region, etc. For example, the first display area may be circular (eg Figure 3A As shown), rectangle, hexagon, irregular figures and other arbitrary shapes.

[0123] The display substrate provided in the embodiment of the present disclosure can compensate the parasitic capacitance of the transparent wiring through the first capacitance compensation structure, so that the light emitting brightness of different first light-emitting elements has better uniformity, so as to alleviate or solve the problem of uneven brightness in the first display area (especially the problem of uneven brightness when the first display area displays low grayscale), thereby improving the display effect of the first display area.

[0124] Some embodiments of the present disclosure further provide a display device, which includes a display substrate provided by any embodiment of the present disclosure. Figure 8 A schematic plan view of a display device provided in some embodiments of the present disclosure. Figure 8 As shown, the display device 300 may include Figure 3A The display substrate and sensor S are shown.

[0125] For example, refer to Figure 1B As shown, similar to Figure 1B In the display device 100 shown in FIG. 1 , in the display device 300 , the sensor S (refer to the sensor 120 in the display device 100 ) may be disposed on the second panel F2 side of the display substrate (refer to the display substrate 110 in the display device 100 ). Figure 1B and Figure 8 As shown, the orthographic projection of the sensor S on the display substrate at least partially overlaps with the first display area Rb, and the sensor S is configured to receive light incident from one side of the first panel F1.

[0126] For example, the sensor S is overlapped with the first display area Rb in the normal direction of the display substrate (i.e., the direction perpendicular to the first panel surface F1 or the second panel surface F2 of the display substrate), and the sensor S can receive and process the optical signal passing through the first display area Rb, which can be visible light, infrared light, etc. For example, the first display area Rb allows the light incident from the side of the first panel surface F1 to be at least partially transmitted to the side of the second panel surface F2. For example, only the light-emitting element (i.e., the first light-emitting element) is provided in the first display area Rb, and the pixel circuit (i.e., the first pixel circuit) is not provided. In this case, the light transmittance of the first display area Rb can be improved.

[0127] For example, in some embodiments, when a direct-down arrangement is adopted, the orthographic projection of the sensor S on the display substrate is located within the first display area Rb. For example, in other embodiments, when other light-guiding elements (such as a light guide plate, a light guide tube, etc.) are used to allow light to be incident on the sensor S from, for example, a direction parallel to the display substrate (i.e., a direction parallel to the first panel surface F1 or the second panel surface F2 of the display substrate), the orthographic projection of the sensor S on the display substrate partially overlaps with the first display area Rb. At this time, since the light can propagate laterally to the sensor S, it is not necessary for the sensor S to be completely located directly below the first display area Rb.

[0128] For example, the sensor S may be an image sensor, which may be used to collect images of the external environment facing the light-collecting surface of the sensor S, such as a CMOS image sensor or a CCD image sensor. The sensor S may also be an infrared sensor, a distance sensor, and the like. For example, in a case where the display device 300 is a mobile terminal such as a mobile phone or a notebook, the sensor S may be implemented as a camera of a mobile terminal such as a mobile phone or a notebook, and may also include optical devices such as lenses, reflectors, or optical waveguides as needed to modulate the optical path. For example, the sensor S may include photosensitive pixels arranged in an array. For example, each photosensitive pixel may include a photosensitive detector (e.g., a photodiode, a phototransistor) and a switching transistor (e.g., a thin film transistor). For example, a photodiode may convert a light signal irradiated thereon into an electrical signal, and a switching transistor may be electrically connected to the photodiode to control whether the photodiode is in a state of collecting light signals and the time of collecting light signals.

[0129] The display device 300 may be any electronic device with a display function, such as a smart phone, a laptop, a tablet computer, a television, etc. For example, when the display device 300 is a smart phone or a tablet computer, the smart phone or the tablet computer may have a full-screen design; Figure 3B and Figure 3C The display substrate shown in the figure can bend the peripheral area 40 that cannot display to the side or back of the display device, thereby realizing a full-screen design; of course, for Figure 3C The display substrate shown may also be a display substrate that does not include the peripheral area 40, thereby realizing a full panel design. In addition, the smart phone or tablet computer may also perform image capture, distance perception, light intensity perception, and other operations through an under-screen sensor (such as a camera, an infrared sensor, etc.).

[0130] It should be noted that, for the sake of clarity and simplicity, the entire structure of the display device 300 is not shown. To achieve the necessary functions of the display device, those skilled in the art may set other structures not shown according to specific application scenarios, and the embodiments of the present disclosure do not limit this.

[0131] The technical effects of the display device provided by the embodiments of the present disclosure can be referred to the corresponding description of the display driving device in the above embodiments, which will not be repeated here.

[0132] There are a few points to note about this disclosure:

[0133] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0134] (2) In the absence of conflict, features in the same embodiment or in different embodiments of the present disclosure may be combined with each other.

[0135] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display substrate, comprising a first display area and a first region at least partially surrounding the first display area; wherein: The first display area includes a plurality of first light emitting elements, The first area includes a plurality of first pixel circuits and at least one first capacitance compensation structure, The display substrate includes a plurality of transparent wirings extending from the first area to the first display area, At least one first pixel circuit among the plurality of first pixel circuits is electrically connected to at least one first light-emitting element among the plurality of first light-emitting elements through at least one transparent wiring among the plurality of transparent wirings, and is configured to control a driving current that flows through the at least one first pixel circuit, the at least one transparent wiring, and the at least one first light-emitting element and drives the at least one first light-emitting element to emit light, The at least one first capacitance compensation structure is coupled to at least one transparent trace of the plurality of transparent traces and is configured to compensate for parasitic capacitance caused by the at least one transparent trace coupled to the at least one first capacitance compensation structure; The sum of the parasitic capacitance value of the transparent wiring and the compensation capacitance value of the first capacitance compensation structure is substantially equal to the same target capacitance value. The multiple transparent routing lines are divided into multiple transparent routing groups, each of the multiple transparent routing groups includes multiple transparent routing lines; the average value of the parasitic capacitance values ​​of the multiple transparent routing lines in each transparent routing group is used as the average parasitic capacitance value of each transparent routing group; the target capacitance value is greater than or equal to the maximum value of the average parasitic capacitance values ​​of the multiple transparent routing groups.

2. The display substrate according to claim 1, wherein: The compensation capacitance provided by the at least one first capacitance compensation structure and the parasitic capacitance caused by the at least one transparent trace coupled to the at least one first capacitance compensation structure are connected in parallel.

3. The display substrate according to claim 1, wherein: There is at least one transparent line among the plurality of transparent lines, a parasitic capacitance value of the transparent line is substantially equal to the target capacitance value, and the transparent line is not coupled to the at least one first capacitance compensation structure.

4. The display substrate according to claim 1, wherein: There is at least one transparent routing group among the plurality of transparent routing groups, the average parasitic capacitance value of the transparent routing group is substantially equal to the target capacitance value, and the at least one transparent routing line in the transparent routing group is not coupled to the at least one first capacitance compensation structure.

5. The display substrate according to any one of claims 1 to 3, wherein: The first region includes a peripheral region, and the peripheral region is located between the first display area and at least one side edge of the display substrate; The plurality of first pixel circuits and the plurality of first capacitance compensation structures are both located in the peripheral area.

6. The display substrate according to any one of claims 1 to 3, wherein: The first region includes a second display area, the second display area at least partially surrounds the first display area, and the second display area includes a second pixel unit. The second pixel unit includes a second light emitting element and a second pixel circuit. The second pixel circuit is electrically connected to the second light emitting element and is configured to control a driving current that flows through the second pixel circuit and the second light emitting element and drives the second light emitting element to emit light; The plurality of first pixel circuits and the plurality of first capacitance compensation structures are all located in the second display area.

7. The display substrate according to any one of claims 1 to 3, wherein: The first region includes a second display area and a peripheral area, the second display area at least partially surrounds the first display area, and the peripheral area is located between the first display area and at least one side edge of the display substrate; The second display area includes a second pixel unit, the second pixel unit includes a second light-emitting element and a second pixel circuit, the second pixel circuit is electrically connected to the second light-emitting element, and is configured to control a driving current flowing through the second pixel circuit and the second light-emitting element and driving the second light-emitting element to emit light; A portion of the multiple first pixel circuits and a portion of the multiple first capacitor compensation structures are located in the peripheral area, and another portion of the multiple first pixel circuits and another portion of the multiple first capacitor compensation structures are located in the second display area.

8. The display substrate according to claim 6, wherein: The second display area further includes a second capacitance compensation structure, The second capacitance compensation structure is coupled to the second pixel circuit and the second light emitting element, and is configured to provide a compensation capacitance to the second pixel circuit. The compensation capacitance value of the second capacitance compensation structure is substantially equal to the target capacitance value.

9. The display substrate according to claim 5, wherein: In the plane where the display substrate is located, the at least one first capacitance compensation structure is located on a side of a first pixel circuit corresponding to the at least one first capacitance compensation structure that is away from the first display area.

10. The display substrate according to any one of claims 1 to 3, wherein: The display substrate comprises a base substrate and a pixel circuit layer, a transparent wiring layer and a light emitting element layer sequentially arranged on the base substrate; The pixel circuit layer includes a gate layer and a source-drain layer; Each of the plurality of first light-emitting elements is located in the light-emitting element layer; Each of the plurality of first pixel circuits comprises a thin film transistor, wherein the thin film transistor comprises a gate, a source and a drain, wherein the gate is located at the gate layer, and at least one of the source and the drain is located at the source-drain layer; Each of the plurality of transparent routing lines is located in the transparent routing layer; The at least one first capacitor compensation structure includes a first capacitor electrode and a second capacitor electrode, and one of the first capacitor electrode and the second capacitor electrode is located in the gate layer, the source-drain electrode layer or the transparent wiring layer.

11. The display substrate according to claim 10, wherein: The source or drain is electrically connected to one of the first capacitor electrode and the second capacitor electrode, and the source or drain is also electrically connected to the first light-emitting element through the transparent wiring.

12. The display substrate according to claim 11, wherein: The pixel circuit layer further includes a capacitor plate layer, and the other of the first capacitor electrode and the second capacitor electrode is located on the capacitor plate layer.

13. The display substrate according to claim 12, wherein: The at least one first capacitance compensation structure includes a plurality of capacitance compensation structures, and another one of the first capacitance electrode and the second capacitance electrode of the plurality of capacitance compensation structures is an integrated structure.

14. The display substrate according to any one of claims 1 to 3, wherein: The display substrate comprises a first panel surface and a second panel surface, wherein the first panel surface is used for displaying during operation of the display substrate. The first display area is a transparent display area configured to transmit light incident from one side of the first panel surface to one side of the second panel surface.

15. A display device comprising the display substrate according to any one of claims 1-14.

16. The display device according to claim 15, further comprising a sensor, wherein: The display substrate comprises a first panel surface and a second panel surface, wherein the first panel surface is used for display during operation. The first display area is a transparent display area configured to transmit light incident from one side of the first panel surface to one side of the second panel surface. The sensor is disposed on one side of the second panel surface of the display substrate, the orthographic projection of the sensor on the display substrate at least partially overlaps with the first display area, and the sensor is configured to receive light incident from one side of the first panel surface.

17. The display device according to claim 16, wherein: The sensor includes at least one of an image sensor, an infrared sensor, and a distance sensor.

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