Semiconductor equipment

Abstract

To provide a semiconductor device with a configuration that can sufficiently reduce parasitic capacitance between wirings. This will be one of the issues to address. [Solution] A stack of a first layer in which part or all of a metal thin film is oxidized and an oxide semiconductor layer is formed. In the thin-film transistor with a bottom gate structure used, the oxide semiconductor overlaps with the gate electrode layer. An oxide insulating layer is formed on a part of the body layer to serve as a channel protective layer, and when the insulating layer is formed... An oxide insulating layer is formed to cover the peripheral edges (including the sides) of the stacked oxide semiconductor layers.

Description

[Technical Field]

[0001] This invention relates to a semiconductor device using an oxide semiconductor and a method for manufacturing the same.

[0002] In this specification, a semiconductor device refers to a device that can function by utilizing semiconductor properties. This refers to all types of semiconductor devices, including electro-optical devices such as display devices, semiconductor circuits, and electronic equipment. be. [Background technology]

[0003] In recent years, semiconductor thin films (thickness of several to several hundred nm) formed on substrates having an insulating surface have been used The technology for constructing thin-film transistors (TFTs) is attracting attention. Thin-film transistors are I It is widely applied in electronic devices such as carbon and electro-optical devices, and especially in switches for image display devices. Development as a luminaire element is being expedited. Metal oxides exist in diverse forms and are used in a variety of applications. Indium oxide is a well-known material and is required in liquid crystal displays, etc. It is used as a transparent electrode material.

[0004] Some metal oxides exhibit semiconductor properties. For example, there are tungsten oxide, tin oxide, indium oxide, zinc oxide, and so on. Thin-film transistors using metal oxides exhibiting semiconductor properties as channel formation regions are already known. (Patent Documents 1 and 2) [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2007-123861 [Patent Document 2] Japanese Patent Publication No. 2007-96055 [Overview of the project] [Problems that the invention aims to solve]

[0006] When fabricating multiple thin-film transistors on an insulating surface, for example, gate wiring and source wiring There is a point where they intersect. At the point of intersection, there is a gate wire and a wire with a different potential from the gate wire. An insulating layer is provided between the source wires, and this insulating layer acts as a dielectric, forming capacitance. Capacitance, also known as parasitic capacitance between wires, can cause distortion of the signal waveform. Large raw capacity may slow down signal transmission.

[0007] Furthermore, an increase in parasitic capacitance can lead to crosstalk, where electrical signals leak between wiring connections, and also to increased power consumption. This leads to an increase in power.

[0008] Furthermore, in an active-matrix display device, the signal wiring that supplies the video signal is particularly important. If a large parasitic capacitance is formed between the wiring or electrodes, the display quality may deteriorate. There is.

[0009] Furthermore, when miniaturizing circuits, the spacing between wires becomes narrower, increasing the parasitic capacitance between wires. There is a risk of it happening.

[0010] One aspect of the present invention provides a semiconductor device having a configuration that can sufficiently reduce parasitic capacitance between wirings. One of the tasks is to do the following.

[0011] Furthermore, when a drive circuit is formed on an insulating surface, the operation of the thin-film transistor used in the drive circuit A faster speed is preferable.

[0012] For example, shortening the channel length (L) of a thin film transistor or widening the channel width W increases the operating speed. However, shortening the channel length has a problem that switching characteristics, for example, the on / off ratio becomes small. Also, widening the channel width W has a problem of increasing the capacitance load of the thin film transistor itself. Even when the channel length is short, it is also an issue to provide a semiconductor device including a thin film transistor having stable electrical characteristics. Also, when forming a plurality of different circuits on an insulating surface, for example, when forming a pixel portion and a driving circuit on the same substrate, the thin film transistor used for the pixel portion is required to have excellent switching characteristics, for example, a large on / off ratio, and the thin film transistor used for the driving circuit is required to have a high operating speed. Particularly, the higher the definition of the display device, the shorter the writing time of the display image, so it is preferable that the thin film transistor used for the driving circuit has a high operating speed. One of the problems is to provide a method for manufacturing a semiconductor device that forms a plurality of types of thin film transistor structures on the same substrate to constitute a plurality of types of circuits.

[0013] After forming a metal thin film on an insulating surface, an oxide semiconductor layer thicker than the metal thin film is laminated, and then a part or all of the metal thin film is oxidized by performing an oxidation treatment such as a heat treatment. The lamination of the first layer in which a part or all of the metal thin film is oxidized and the oxide semiconductor layer is used as the semiconductor layer of the thin film transistor.

[0014]

[0015]

[0016]

[0017] ​​​​​​​​​​​​​​ Specifically, when fabricating multiple types of thin-film transistors on the same substrate, at least one A first layer in which part or all of a metal thin film is oxidized as the semiconductor layer of the thin-film transistor. This method uses stacking of oxide semiconductor layers.

[0018] Furthermore, a stacking of a first layer in which part or all of a metal thin film is oxidized and an oxide semiconductor layer is used. In a thin-film transistor with a bottom gate structure, the oxide semiconductor layer overlaps with the gate electrode layer. A partial oxide insulating layer is formed on top of the channel protective layer, and during the formation of this oxide insulating layer... An oxide insulating layer is formed to cover the peripheral edges (including the sides) of the stacked oxide semiconductor layers.

[0019] The oxide insulating layer covering the peripheral edge (including the sides) of the stacked oxide semiconductor layers is a gate electrode layer, The distance from the wiring layers (such as source wiring layers and capacitive wiring layers) formed above or around it is increased. The aim is to reduce the parasitic capacity of the plant.

[0020] Furthermore, the oxide insulating layer covers the edges of the first layer, which has oxidized part or all of the metal thin film. This can reduce leakage current.

[0021] The oxide insulating layer covering the periphery of the stacked oxide semiconductor layers is formed in the same process as the channel protection layer. Therefore, the parasitic capacity can be reduced without increasing the number of processes.

[0022] Furthermore, the oxide insulating layer covering the peripheral edges (including the sides) of the stacked oxide semiconductor layers provides parasitic capacitance. This can reduce the signal waveform distortion and suppress it.

[0023] Furthermore, in order to reduce parasitic capacitance, an oxide insulating layer with a low dielectric constant is used as the insulating layer sandwiched between the wiring. It is preferable to use edge material.

[0024] By providing an oxide insulating layer that covers the peripheral edge (including the sides) of the oxide semiconductor layer, parasitic container By minimizing the amount, high-speed operation of thin-film transistors can be achieved. Also, the operating speed Using fast thin-film transistors improves the integration density of circuits.

[0025] One aspect of the present invention disclosed herein relates to a first thin-film transistor and a second thin-film transistor The first thin-film transistor has a first gate electrode via a first gate insulating layer. The layer has a stack of a first oxide semiconductor layer and a second oxide semiconductor layer that overlap the layer, and a second thin film trace The inverter has a third oxide semiconductor layer that overlaps with the second gate electrode layer via a second gate insulating layer. Having a body layer, the lamination of the first oxide semiconductor layer and the second oxide semiconductor layer covers the periphery and sides. A second oxide semiconductor layer is electrically connected to the oxide insulating layer, which is in contact with the oxide insulating layer. This is a semiconductor device having a drain electrode layer and a drain electrode layer.

[0026] As for the metal thin film, materials that exhibit semiconductor properties upon oxidation treatment, such as indium, zinc, tin, and monoxide, are used. It is preferable to use ribdenum or tungsten. The oxidized metal thin film is the first This results in a first oxide semiconductor layer, and a stacked structure is obtained with a second oxide semiconductor layer provided on top of it. Furthermore, the first oxide semiconductor layer has a lower electrical resistivity compared to the second oxide semiconductor layer. Let's assume that (i.e., high conductivity). Also, the first oxide semiconductor layer is between the gate electrode and the gate electrode. It is placed on the side with the closest separation distance and is in contact with at least the gate insulating film. This stacking is used for thin-film tracing. By fabricating a converter, thin films with excellent electrical properties (such as field-effect mobility) can be produced. A transistor can be realized.

[0027] The above configuration solves at least one of the above problems.

[0028] Furthermore, in order to realize the above structure, one aspect of the present invention involves forming a gate electrode layer, A gate insulating layer is formed on the layer, a metal thin film is formed on the gate insulating layer, and an oxide is formed on the metal thin film. After forming a semiconductor layer and dehydrating or dehydrogenating the oxide semiconductor layer, it is not exposed to the atmosphere. Furthermore, it prevents the re-importation of water and hydrogen into the oxide semiconductor layer, and is in contact with a portion of the oxide semiconductor layer, An oxide insulating layer is formed to cover the periphery and sides of the oxide semiconductor layer, and the metal thin film is oxidized. A source electrode layer and a drain electrode layer are formed on a material insulating layer, and an oxide insulating layer, source electrode layer, Method for fabricating a semiconductor device in which a drain electrode layer and a protective insulating layer in contact with an oxide semiconductor layer are formed. It is the law.

[0029] Metal thin films are formed using methods such as sputtering, vacuum deposition, or coating. The thickness of the thin film shall be greater than 0 nm and less than or equal to 10 nm, preferably 3 nm or more. A stack of thin metal films may be used, and the total film thickness shall be 10 nm or less. Oxidizing at least a portion of the film means that it functions as a thin-film transistor and has switching characteristics. It oxidizes to the extent that it shows the following: That is, the source electrode with and without a gate voltage applied A state in which the current flowing between the source electrode and the drain electrode hardly changes, or between the source electrode and the drain The metal thin film is oxidized so that the electrodes do not become conductive. Also, the source electrode and The oxidized edges and sides of the metal thin film prevent the drain electrode from becoming conductive. An oxide insulating layer is provided to cover it.

[0030] Furthermore, the final obtained first oxide semiconductor layer (i.e., an oxide semiconductor obtained by oxidizing a metal thin film) The average total film thickness of the main layer and the second oxide semiconductor layer shall be between 3 nm and 30 nm.

[0031] Furthermore, the second oxide semiconductor layer preferably contains at least one of the same elements as the metal thin film. If the second oxide semiconductor layer contains at least one of the same elements as the metal thin film, then the same E The second oxide semiconductor layer and the metal thin film are etched using the same etching process with etching solution or etching gas. Because it can be removed in this way, the number of steps can be reduced.

[0032] Furthermore, oxidation treatment is a heat treatment in either an oxygen-containing atmosphere or a nitrogen atmosphere (20 The temperature range is 0°C to 600°C. Even under a nitrogen atmosphere, the metal thin film can be heated. , oxygen in the oxide semiconductor layer (second oxide semiconductor layer) formed in contact with the metal thin film It combines with and oxidizes. In this case, the presence of the metal thin film draws oxygen from the second oxide semiconductor layer. It is also possible to remove the oxygen vacancies and form oxygen-deficient regions in the second oxide semiconductor layer. Heating in an open atmosphere is not the only way to preserve a thin metal film; heating in an oxygen-containing atmosphere can also preserve a thin metal film. As a result, oxygen is extracted from the second oxide semiconductor layer, creating an oxygen vacancy in the second oxide semiconductor layer. It is also possible to form regions. By forming oxygen vacancy regions in the second oxide semiconductor layer... This can improve the field-effect mobility. Also, depending on the material of the metal thin film, In some cases, the interface with the oxide semiconductor layer formed on top may become unclear due to the heat treatment. However, the oxide semiconductor layer on the gate insulating layer side, that is, the lower part of the oxide semiconductor layer, and the oxide semiconductor layer It exhibits different electrical characteristics in the upper and lower layers.

[0033] The second oxide semiconductor layer is, for example, InMO3(ZnO) m (m>0) A thin film is formed, and a thin-film transistor is fabricated using this thin film as an oxide semiconductor layer. Note that M is one metallic element or multiple gold elements selected from Ga, Fe, Ni, Mn, and Co. This indicates the group element. For example, M can be Ga, or Ga and Ni or Ga and F Other metal elements besides Ga, such as e, may be present. Also, the above oxide semiconductor may contain odor In addition to the metallic elements included as M, impurity elements include Fe, Ni, and other transition metal elements. Some contain an element or an oxide of the transition metal. In this specification, InM O3(ZnO) m Among oxide semiconductor layers with a structure represented by (m>0), where M is Ga Oxide semiconductors containing this structure are called In-Ga-Zn-O based oxide semiconductors, and their thin films are In -Also called a Ga-Zn-O non-single crystal film.

[0034] In addition to the above, other metal oxides that can be applied to oxide semiconductor layers include In-Sn-Zn-O In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn -Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In- O-based, Sn-O-based, and Zn-O-based metal oxides can be applied. Silicon oxide may be included in the oxide semiconductor layer made of the material.

[0035] Heat treatment is performed under an inert gas atmosphere of nitrogen or a noble gas (argon, helium, etc.). In this case, the oxide semiconductor layer becomes oxygen-deficient due to the heat treatment, resulting in lower resistance, i.e., N-type ( N - (e.g., chemical treatment), and then the formation of an oxide insulating film in contact with the oxide semiconductor layer, or after formation, By heat treatment, the oxide semiconductor layer is subjected to an oxygen-rich state, thereby increasing its resistance, i.e., I It can also be said that they are being molded. Furthermore, solid-phase oxidation is performed to create an oxygen-rich state in the oxide semiconductor layer. It can also be said that this results in thin-film transistors with good electrical characteristics and high reliability. This makes it possible to manufacture and provide semiconductor devices.

[0036] Dehydration or dehydrogenation is performed using nitrogen or an inert gas such as a noble gas (argon, helium, etc.). Under ambient conditions, heating at temperatures above 400°C, below the substrate's strain point, preferably between 420°C and 570°C. Heat treatment is performed to reduce impurities such as moisture contained in the oxide semiconductor layer.

[0037] The oxide semiconductor layer that has undergone dehydration or dehydrogenation is the oxide semiconductor layer after dehydration or dehydrogenation. Even when measuring TDS up to 450°C for the body layer, two peaks for water are still visible, at least 300°C. The heat treatment conditions should be such that the single peak appearing around °C is not detectable. Therefore, dehydration Alternatively, for thin-film transistors using an oxide semiconductor layer that has undergone dehydrogenation, the TDS is 45 Even when measurements are taken down to 0°C, the water peak that typically appears around 300°C is not detected.

[0038] Then, the temperature is lowered from the heating temperature T used for dehydration or dehydrogenation of the oxide semiconductor layer. When doing so, by using the same furnace that performed the dehydration or dehydrogenation and not exposing it to the atmosphere, water or It is important to prevent hydrogen from being reintroduced. Dehydration or dehydrogenation is performed to remove the oxide semiconductor. The body layer is made less resistant, i.e., N-type (N - After performing (etc.), the oxide semiconductor is made into a type I by increasing its resistance. When a thin-film transistor is fabricated using a conductive layer, the threshold voltage value of the thin-film transistor can be increased. This allows for the realization of a so-called normally-off switching element. Thin film transistor The channel is formed with a positive threshold voltage as close as possible to 0V as the gate voltage of the transistor. This is desirable for semiconductor devices (display devices). Furthermore, the threshold voltage value of the thin-film transistor... If the gate voltage is negative, current will flow between the source and drain electrodes even if the gate voltage is 0V. In this case, it tends to become what is known as normally-on. In active-matrix display devices, The electrical characteristics of the thin-film transistors that make up the circuit are important, and these electrical characteristics affect the performance of the display device. It affects performance. In particular, the threshold voltage (Vth) is an important electrical characteristic of thin-film transistors. This is important. Even if the field effect mobility is high, the threshold voltage value is high, or the threshold voltage value is high. If it is an INAS, it is difficult to control as a circuit. The threshold voltage value is high, In the case of thin-film transistors with a large absolute value of voltage, when the driving voltage is low, the TFT and It may not be able to perform its switching function and could become a load. In the case of thin-film transistors, a channel is formed only when a positive voltage is applied to the gate voltage. Therefore, a transistor that allows drain current to flow is desirable. If the drive voltage is not high enough, the channel Transistors in which a channel is not formed, or in which a channel is formed even under negative voltage conditions and drain current The transistors used for current flow are unsuitable as thin-film transistors for use in circuits.

[0039] Furthermore, the gas atmosphere used to lower the temperature from heating temperature T is different from the gas atmosphere used to raise the temperature to heating temperature T. The atmosphere may be switched to a gaseous atmosphere. For example, in the same furnace where dehydration or dehydrogenation has been performed, the atmosphere may be switched to air. Without contact, high-purity oxygen gas or N2O gas, or ultra-dry air (with a dew point) is passed through the furnace. Cooling is performed by filling the container with water at -40°C or below, preferably -60°C or below.

[0040] After reducing the moisture content in the membrane by heat treatment that involves dehydration or dehydrogenation, the moisture content is reduced. Slow cooling (or cooling) in an atmosphere where there is no dew (dew point of -40°C or lower, preferably -60°C or lower). Using the oxide semiconductor film, the electrical characteristics of thin-film transistors are improved, and mass production is also possible. To realize thin-film transistors that possess both low performance and high efficiency.

[0041] In this specification, under an inert gas atmosphere of nitrogen or a noble gas (argon, helium, etc.) The heat treatment is referred to as a heat treatment for dehydration or dehydrogenation. In this specification, this heat treatment Dehydrogenation is not simply defined as the process of removing H2 through scientific means, but rather as H For convenience, this process, including the removal of OH groups, will be referred to as dehydration or dehydrogenation.

[0042] Heat treatment is performed under an inert gas atmosphere of nitrogen or a noble gas (argon, helium, etc.). In this case, the oxide semiconductor layer becomes oxygen-deficient due to the heat treatment, resulting in lower resistance, i.e., N-type ( N - To cause (such as) transformation.

[0043] Furthermore, there is a high-resistance drain region (HRD(High)) which is oxygen-deficient and overlaps with the drain electrode layer. A resistance drain region (also called a resistance drain region) is formed. High-resistance source region (HRS) is an oxygen-deficient type that overlaps with the layer. A region (also called the e Source) is formed.

[0044] Specifically, the carrier concentration in the high-resistance drain region is 1 × 10⁻⁶. 18 / cm 3 Within the above range and is at least higher than the carrier concentration in the channel formation region (less than 1×10 18 / cm 3 ). The carrier concentration in this specification refers to the value of the carrier concentration obtained from Hall effect measurement at room temperature. Then, by making at least a part of the stack of dehydrated or dehydrogenated oxide semiconductor layers in an oxygen-excessive state, the resistance is further increased, that is, it is made into a type-I state to form a channel formation region. In addition,

[0045] as a treatment for making the stack of dehydrated or dehydrogenated oxide semiconductor layers in an oxygen-excessive state, there are film formation of an oxide insulating film in contact with the stack of dehydrated or dehydrogenated oxide semiconductor layers by sputtering method, or heat treatment after the formation of the oxide insulating film, or heat treatment in an atmosphere containing oxygen, or treatment of cooling in an oxygen atmosphere after heating in an inert gas atmosphere, cooling with ultra-dry air (dew point is -40°C or lower, preferably -60°C or lower), etc.

[0046] Also, in order to make at least a part (the part overlapping with the gate electrode layer) of the stack of dehydrated or dehydrogenated oxide semiconductor layers into a channel formation region, by selectively making it in an oxygen-excessive state, the resistance can be increased, that is, it can be made into a type-I state.

[0047] As a result, it becomes possible to fabricate and provide a semiconductor device having a thin film transistor with good electrical characteristics and high reliability.

[0048] In addition, by forming a high-resistance drain region in the oxide semiconductor layer overlapping with the drain electrode layer, it is possible to improve the reliability when forming a drive circuit. Specifically, by forming a high resistance drain region, from the drain electrode layer to the high-resistance drain region, the channel It is possible to create a structure in which the conductivity can be changed in stages across the formation region. Therefore, when operating by connecting to wiring that supplies a high power potential VDD to the drain electrode layer, Even when a high electric field is applied between the drain electrode layer and the drain electrode layer, the high-resistance drain region buffs This configuration prevents the application of a localized high electric field, thereby improving the transistor's breakdown voltage. It is possible.

[0049] Furthermore, in the oxide semiconductor layer superimposed on the drain electrode layer (and source electrode layer), high resistance By forming a rain region (and a high-resistance source region), the drive circuit is formed. This can reduce leakage current in the channel formation region. Specifically, high-resistance drain By forming a region, the transistor's recurrent flow between the drain electrode layer and the source electrode layer is reduced. The current path includes the drain electrode layer, the high-resistance drain region on the drain electrode layer side, and the channel. The order is flannel formation region, high-resistance source region on the source electrode layer side, and then the source electrode layer. In the channel formation region, flow occurs from the high-resistance drain region on the drain electrode layer side to the channel region. The leakage current is reduced by the gate insulating layer and channel formation region, which have high resistance when the transistor is off. It can be concentrated near the interface, and the back channel portion (the channel away from the gate electrode layer) This can reduce leakage current in a portion of the surface of the channel formation region.

[0050] Furthermore, there is a high-resistance source region that overlaps the source electrode layer and a high-resistance drain region that overlaps the drain electrode layer. The region depends on the width of the gate electrode layer, but it overlaps with a part of the gate electrode layer and the gate insulating layer. This allows for a more effective reduction of the electric field strength near the edges of the drain electrode layer.

[0051] In addition, as a display device having a drive circuit, besides liquid crystal display devices, there are also light-emitting devices using light-emitting elements. Examples include display devices and electronic paper displays that use electrophoretic display elements. .

[0052] In a light-emitting display device using a light-emitting element, the pixel section has multiple thin-film transistors, In the basic structure, the gate electrode of one thin-film transistor and the source wiring of another transistor, It has a location for connecting the drain wiring. It also has a light-emitting display device using a light-emitting element. In the drive circuit, the gate electrode of the thin-film transistor and the source of the thin-film transistor It has a point for connecting wiring or drain wiring.

[0053] Furthermore, by fabricating the matrix circuit and drive circuit on the same substrate, the manufacturing cost of semiconductor devices is reduced. This reduces the amount of drive circuits, which include circuits that prioritize high-speed operation, such as logic circuits. Such circuits utilize a thin layer structure that stacks a first oxide semiconductor layer and a second oxide semiconductor layer. It is constructed using film transistors, and a single layer of a third oxide semiconductor layer is used for the other circuits. This allows for a thin, different structure between circuits that prioritize high-speed operation, such as logic circuits, and other circuits. A film transistor can be arranged.

[0054] Furthermore, thin-film transistors are susceptible to damage from static electricity, so the gate wire or source wire may be damaged. For each line, a protection circuit for protecting the thin-film transistors in the pixel area is provided on the same substrate. Preferably, the protection circuit is constructed using a nonlinear element with an oxide semiconductor layer. It's nice.

[0055] The ordinal numbers "1st" and "2nd" are used for convenience only and do not represent the order of processes or stacking. This does not indicate that the invention is uniquely named. This does not indicate anything. [Effects of the Invention]

[0056] A semiconductor device is provided that uses stacked oxide semiconductor layers and incorporates thin-film transistors with excellent electrical properties. This is achievable. The periphery and sides of the stacked oxide semiconductor layers are covered with an oxide insulating layer, reducing leakage current. This can reduce the amount of oxide semiconductor material. Furthermore, the peripheral and side edges of the laminated oxide semiconductor layer are made of oxide insulating material. It is formed in the same process as the oxide insulating layer, which functions as a channel protection layer.

[0057] Furthermore, a thin-film transistor having stacked oxide semiconductor layers on the same substrate, and a single-layer oxide semiconductor Thin-film transistors having a conductive layer can be fabricated to construct multiple types of circuits. [Brief explanation of the drawing]

[0058] [Figure 1] These are a plan view and a cross-sectional view showing one aspect of the present invention. [Figure 2] This is a cross-sectional view showing one aspect of the present invention. [Figure 3] This is a cross-sectional view showing one aspect of the present invention. [Figure 4] These are a plan view and a cross-sectional view showing one aspect of the present invention. [Figure 5] These are a plan view and a cross-sectional view showing one aspect of the present invention. [Figure 6] This is a cross-sectional view showing one aspect of the present invention. [Figure 7] These are a plan view and a cross-sectional view showing one aspect of the present invention. [Figure 8] This is a cross-sectional view showing one aspect of the present invention. [Figure 9] A diagram illustrating a semiconductor device. [Figure 10] A diagram illustrating a semiconductor device. [Figure 11]A diagram illustrating a semiconductor device. [Figure 12] A diagram illustrating the pixel equivalent circuit of a semiconductor device. [Figure 13] A diagram illustrating a semiconductor device. [Figure 14] A diagram illustrating the block diagram of a semiconductor device. [Figure 15] A diagram illustrating the configuration of the signal line drive circuit and a timing chart illustrating its operation. [Figure 16] A circuit diagram showing the configuration of a shift register. [Figure 17] A diagram illustrating the configuration of a shift register and a timing chart illustrating its operation. [Figure 18] A diagram illustrating a semiconductor device. [Figure 19] A diagram illustrating a semiconductor device. [Figure 20] An external view showing an example of an e-book. [Figure 21] External view showing examples of television equipment and digital photo frames. [Figure 22] An external view showing an example of a gaming machine. [Figure 23] An external view showing an example of a portable computer and mobile phone. [Figure 24] A diagram illustrating a semiconductor device. [Figure 25] A diagram illustrating a semiconductor device. [Figure 26] A diagram illustrating a semiconductor device. [Figure 27] A diagram illustrating a semiconductor device. [Figure 28] A diagram illustrating a semiconductor device. [Figure 29] A diagram illustrating a semiconductor device. [Figure 30] A diagram illustrating a semiconductor device. [Figure 31] A diagram illustrating a semiconductor device. [Figure 32] A diagram illustrating a semiconductor device. [Figure 33] A diagram illustrating a semiconductor device. [Figure 34] A diagram illustrating a semiconductor device. [Figure 35] A diagram illustrating a semiconductor device. [Figure 36] A diagram illustrating a semiconductor device. [Modes for carrying out the invention]

[0059] The embodiments will be described in detail with reference to the drawings. However, the following description is not limited to the present invention. The form and details can be changed in various ways without departing from the gist and scope thereof, as is the case for those skilled in the art. Therefore, it is easy to understand. Accordingly, the description of the embodiment shown below should be interpreted as being limited to the following. It is not the case that... The same reference numeral is used consistently across different drawings for parts that are repeated, and explanations of their repetition are omitted.

[0060] (Embodiment 1) In this embodiment, one form of a semiconductor device and a method for manufacturing a semiconductor device is shown in Figures 1, 2, and 3. This will be explained using Figure 4.

[0061] Figure 1(A) is a plan view of the channel-protected thin-film transistor 448 placed in the pixel. Therefore, Figure 1(B) is a cross-sectional view along line D1-D2 in Figure 1(A) and line D5 in Figure 1(A) —This is a cross-sectional view at D6. Also, Figure 1(C) shows the line D3-D4 in Figure 1(A). This is a cross-sectional view. Note that Figure 2(E) is identical to Figure 1(B).

[0062] The thin-film transistor 448 placed in the pixel is channel-protected (also known as channel-stopped) (u) is a thin-film transistor, and a gate electrode layer 421 is placed on a substrate 400 having an insulating surface. a. A stacked oxide semiconductor layer 442 including a gate insulating layer 402 and a channel formation region 423, The oxide insulating layer 426a, which functions as a channel protective layer, the source electrode layer 425a, and the drain It includes an in electrode layer 425b. It also covers the thin-film transistor 448 and an oxide insulating layer 426 a, a protective insulating layer 403 in contact with the source electrode layer 425a and the drain electrode layer 425b, and A flattening insulating layer 404 is laminated and provided. On the flattening insulating layer 404, drain electricity A pixel electrode layer 427 is provided in contact with the polar layer 425b, and a thin-film transistor 448 and an electric field are connected. They are connected by energy.

[0063] Furthermore, the stacked oxide semiconductor layer 442 is formed by stacking a metal thin film and an oxide semiconductor layer, and then the metal Because it is obtained by oxidizing a thin film, depending on the material of the metal thin film and oxide semiconductor layer, a clear Since there are no boundaries, in this specification, the boundaries of the layers are indicated by dotted lines.

[0064] The thin-film transistor 448 for the pixel has a high-resistance source region 424a and a high-resistance drain region 4 The source has a stacked oxide semiconductor layer 442 including 24b and a channel-forming region 423. A high-resistance source region 424a is formed in contact with the lower surface of the electrode layer 425a. A high-resistance drain region 424b is formed in contact with the lower surface of the in electrode layer 425b. Transistor 448 maintains high resistance in its drain region or high resistance in its source region even when a high electric field is applied. This configuration uses a buffer zone to prevent the application of a localized high electric field, thereby improving the transistor's breakdown voltage. That's how it is.

[0065] The channel formation region of the thin-film transistor 448 placed in the pixel is a stacked oxide semiconductor layer. Of the 442, the oxide insulating layer 426a, which is the channel protective layer, is in contact with the gate electrode layer 4 This region overlaps with 21a. The thin-film transistor 448 is connected by the oxide insulating layer 426a. To protect, etching is performed to form the source electrode layer 425a and the drain electrode layer 425b. This prevents the oxide semiconductor layer 442 from being etched during the process.

[0066] Furthermore, the thin-film transistor 448 has a high aperture ratio as a light-transmitting thin-film transistor. To realize a display device, the source electrode layer 425a and the drain electrode layer 425b are light-transmitting. A conductive film having the following properties is used.

[0067] Furthermore, the gate electrode layer 421a of the thin-film transistor 448 also uses a transparent conductive film. .

[0068] Furthermore, pixels on which thin-film transistors 448 are located have a pixel electrode layer 427, or other The electrode layer (such as a capacitive electrode layer) and the wiring layer (such as a capacitive wiring layer) have light transmission to visible light. A conductive film is used to realize a display device with a high aperture ratio. Of course, the gate insulating layer 402, It is preferable to use a film that is transparent to visible light for the oxide insulating layer 426a.

[0069] Furthermore, it is preferable that the metal thin film be oxidized to become a film that is transparent to visible light, Because thin films are less than 10 nm thick, they are transparent to visible light, depending on the material.

[0070] In this specification, a film that is transparent to visible light is defined as a film with a visible light transmittance of 75 to 100. This refers to a film with a thickness of %; if the film is conductive, it is also called a transparent conductive film. Also, gate electrode layer, source electrode layer, drain electrode layer, pixel electrode layer, or other electrodes As a metal oxide applied to the layer and other wiring layers, a conductive film that is semi-transparent to visible light is used. It is acceptable. Semi-transparent to visible light means that the transmittance of visible light is between 50% and 75%. .

[0071] Furthermore, at the wiring intersection where the gate wiring and source wiring intersect, in order to reduce parasitic capacitance, Between the gate electrode layer 421b and the source electrode layer 425a are the gate insulating layer 402 and the oxide insulating layer 426b is provided. Note that the oxide insulating layer in the region overlapping with the channel formation region 423. 426a and the oxide insulating layer 426b in the region that does not overlap with the channel formation region 423 are different. Although indicated by the symbol, these layers are formed from the same material and using the same process.

[0072] Hereafter, using Figures 2(A) to 2(E), thin-film transistor 448 and wiring are connected on the same substrate. The process for manufacturing the difference part will be explained. In addition, the thin-film transistors of the drive circuit, not just the pixel part, will be explained. They may be formed by molding, or they can be fabricated on the same substrate using the same process.

[0073] First, a translucent conductive film is formed on a substrate 400 having an insulating surface, and then the first film The gate electrode layers 421a and 421b are formed by a trisography process. The gate electrode layers 421a and 421b are made of the same translucent material as the first photolithography material. The capacitive wiring layer is formed by the roughing process. In addition, the drive circuit is formed not only for the pixel portion but also for the drive circuit. Additionally, if capacitance is required in the drive circuit, a capacitance wiring layer is also formed in the drive circuit. The resist mask may be formed by an inkjet method. Since this method eliminates the need for a photomask, manufacturing costs can be reduced.

[0074] In addition to glass substrates, the substrate 400 also includes ceramic substrates, quartz substrates, and sapphire substrates. A substrate made of an insulator such as the above may be used. Alternatively, crystallized glass can also be used. ru.

[0075] Furthermore, an insulating film that serves as the base layer is provided between the substrate 400 and the gate electrode layers 421a and 421b. This is also good. The undercoat has the function of preventing the diffusion of impurity elements from the substrate 400, and silicon nitride By using one or more films selected from films, silicon oxide films, silicon nitride films, or silicon oxide-nitride films It can be formed by a laminated structure.

[0076] The materials of the gate electrode layers 421a and 421b are conductive materials that are transparent to visible light, e.g. For example, In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al -Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, The application of Al-Zn-O, In-O, Sn-O, and Zn-O metal oxides is possible. The film thickness can be appropriately selected within the range of 50 nm to 300 nm. Guard electrode layer 421 The metal oxide film deposition methods used in a and 421b include sputtering and vacuum deposition (electron beam vapor deposition). Methods such as coating, arc discharge ion plating, and spraying are used. When using the tactic, a target containing 2% to 10% by weight of SiO2 is used. A film is made, and a transparent conductive film is made containing SiOx (X>0) which inhibits crystallization, and the subsequent This process suppresses crystallization during the heat treatment for dehydration or dehydrogenation. It is preferable.

[0077] Next, a gate insulating layer 402 is formed on the gate electrode layers 421a and 421b.

[0078] The gate insulating layer 402 is formed by a silicon oxide layer using plasma CVD or sputtering. , a silicon nitride layer, a silicon oxide nitride layer, a silicon oxide nitride layer, or an aluminum oxide layer as a single layer or It can be formed by stacking. For example, SiH4, oxygen, and nitrogen can be used as the film-forming gas. Then, a silicon oxide nitride layer can be formed by plasma CVD. The thickness shall be between 100 nm and 500 nm, and in the case of lamination, for example, the film thickness shall be 50 nm or more. A first gate insulating layer with a thickness of 00 nm or less, and a layer with a film thickness of 5 nm or more and 300 nm on the first gate insulating layer. The second gate insulating layer is laminated with a length of m or less.

[0079] In this embodiment, a silicon nitride layer with a thickness of 200 nm or less is created by plasma CVD. This is referred to as the insulating layer 402.

[0080] Next, indium, zinc, tin, molybdenum, or tungsten are added to the gate insulating layer 402. Thin metal films such as tungsten are formed. Furthermore, these alloy thin films, or their laminated films, are used. It is also possible to shape the metal thin film using sputtering, vacuum deposition, or coating methods. To achieve this, an indium film is made using a vapor deposition method to a thickness greater than 0 nm, preferably 10 nm or less. Alternatively, it is formed with a thickness of 3 nm to 5 nm. Furthermore, the metal thin film is subjected to subsequent heat treatment. The oxide then forms in contact with the metal thin film, resulting in an oxide with lower electrical resistivity than the oxide semiconductor layer. The material used is a metal thin film. Also, depending on the material and deposition conditions of the metal thin film, the surface of the gate insulating layer 402 may vary. A state in which a part of the gate insulating layer 402 is exposed, rather than a film covering the surface, for example, when metal clusters They may also exist dispersed in a cluster-like manner. However, if it becomes an oxide semiconductor through subsequent oxidation treatment, then the electric field transfer of a thin-film transistor... The degree can be improved. Also, when metals are dispersed in a cluster shape, the metal and Furthermore, in addition to the materials mentioned above, aluminum, copper, and other materials can be used, and on top of that... By depositing an indium metal thin film, the electrical characteristics of thin-film transistors are being improved. That's good too.

[0081] Next, an oxide semiconductor film with a thickness of 2 nm to 200 nm is formed on a metal thin film. Even if heat treatment for dehydration or dehydrogenation is performed after the formation of the oxide semiconductor film, the oxide semiconductor film To achieve an amorphous state, it is preferable to make the film thickness thin, to 50 nm or less. Oxide semiconductor By thinning the film thickness of the body film, when the oxide semiconductor layer is heated after formation, crystallization occurs. It can prevent people from putting things away.

[0082] Oxide semiconductor films include In-Ga-Zn-O non-single crystal films, In-Sn-Zn-O films, and In -Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al- Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, S nO-based and Zn-O-based oxide semiconductor films are used. In this embodiment, In-Ga-Zn -O-based oxide semiconductor targets are used to deposit films by sputtering. The film is prepared under a noble gas (typically argon) atmosphere, an oxygen atmosphere, or a noble gas (typically It can be formed by sputtering under an argon and oxygen atmosphere. When using the putter method, a target containing 2% to 10% by weight of SiO2 is used. The film is formed to include SiOx (X>0), which inhibits crystallization, in the subsequent process. To suppress crystallization during the heat treatment for dehydration or dehydrogenation. It is preferable.

[0083] The oxide semiconductor is preferably an oxide semiconductor containing In, more preferably In, and It is an oxide semiconductor containing Ga. To make the oxide semiconductor layer type I (intrinsic), dehydration is performed. Performing a chemical or dehydrogenation process is effective.

[0084] Here, an oxide semiconductor target containing In, Ga, and Zn (In2O3:Ga2O 3:ZnO=1:1:1[mol ratio], In:Ga:Zn=1:1:0.5[at ratio]) Using this method, the distance between the substrate and the target is 100 mm, the pressure is 0.2 Pa, and the current is DC. Power supply 0.5kW, argon and oxygen (argon:oxygen = 30 sccm:20 sccm) The film is deposited in an atmosphere with a raw flow rate ratio of 40%. Note that if a pulsed DC power supply is used, This is preferable because it reduces distortion and results in a uniform film thickness distribution. In-Ga-Zn-O non-single crystal The film thickness shall be 5 nm to 200 nm. In this embodiment, as the oxide semiconductor film, I Using an n-Ga-Zn-O oxide semiconductor target, a 20 nm film thickness was produced by sputtering. An in-Ga-Zn-O non-single crystal film is deposited.

[0085] Sputtering methods include RF sputtering, which uses a high-frequency power supply for sputtering, and DC sputtering. There is also the pulsed DC sputtering method, which applies a pulsed bias. RF sputtering The method is mainly used when depositing insulating films, while the DC sputtering method is mainly used when depositing metal films. It is used for this purpose.

[0086] There are also multi-point sputtering systems that can set up multiple targets made of different materials. The apparatus can deposit multiple layers of different material films in the same chamber, or multiple types of materials in the same chamber. It is also possible to deposit films by simultaneously discharging electrical currents from similar materials.

[0087] Furthermore, a sputtering apparatus that uses the magnetron sputtering method, which has a magnetic mechanism inside the chamber. Alternatively, ECR sputtering uses plasma generated with microwaves instead of glow discharge. There are sputtering machines that use this method.

[0088] Furthermore, as a film deposition method using the sputtering method, the target material and sputtering gas components are deposited during film deposition. Reactive sputtering is a method that uses chemical reactions to form thin films of these compounds, and during film formation... There is also a bias sputtering method that applies voltage to the circuit board.

[0089] Next, the stacking of the metal thin film and the oxide semiconductor film is performed in an island-like manner by a second photolithography process. The metal layer 428 and island-shaped oxide semiconductor layer 429 are processed. A resist mask for forming a shaped oxide semiconductor layer 429 is formed by an inkjet method. It is also acceptable. If the resist mask is formed by the inkjet method, a photomask is not used. Therefore, manufacturing costs can be reduced.

[0090] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature for the heat treatment in step 1 shall be 400°C or higher but below the strain point of the substrate, preferably 425°C or higher. Furthermore, if the temperature is 425°C or higher, the heat treatment time can be 1 hour or less, but if it is below 425°C... The heat treatment time shall be longer than one hour. Here, one of the heat treatment devices is A substrate is placed in an electric furnace, and the oxide semiconductor layer is subjected to heat treatment under a nitrogen atmosphere. After that, without exposure to the atmosphere, it prevents the re-importation of water and hydrogen into the oxide semiconductor layer, and the oxide semiconductor... A conductive layer 442 is obtained. In this embodiment, the oxide semiconductor layer is dehydrated or dehydrogenated. Using the same furnace, from the heating temperature T, the temperature is raised to a level sufficient to prevent water from entering again. Specifically, heating Slow cooling is performed under a nitrogen atmosphere until the temperature drops by more than 100°C below temperature T. Instead, dehydration or dehydrogenation occurs under a noble gas atmosphere such as helium, neon, or argon. To do so.

[0091] In the first heat treatment, nitrogen or a noble gas such as helium, neon, or argon is used. It is preferable that it does not contain water, hydrogen, etc. Alternatively, nitrogen introduced into the heat treatment device, Alternatively, the purity of noble gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably 7N (99.99999%) or higher (i.e., impurity concentration of 1 ppm or less, preferably It is preferable to keep the concentration at 0.1 ppm or less.

[0092] Furthermore, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, crystallization may occur, and microcrystalline formation may occur. It may also form a crystalline film or a polycrystalline film.

[0093] Furthermore, the first heat treatment of the oxide semiconductor layer is performed on the oxide before it is processed into an island-shaped oxide semiconductor layer. This can also be done on semiconductor films. In that case, after the first heat treatment, the substrate is removed from the heating device. The material is removed and the photolithography process is performed.

[0094] Alternatively, this first heat treatment may oxidize the metal layer 428 to form an oxide semiconductor layer. Furthermore, the first heating treatment is not limited to oxidizing the metal layer 428, but also includes the first heating In addition to the treatment, an oxidation treatment may be performed to oxidize the metal layer 428, for example, later An oxidation treatment may be performed after the deposition of the oxide insulating film formed by the sputtering method.

[0095] Next, an oxide insulating film 44 is applied to the gate insulating layer 402 and the oxide semiconductor layer by sputtering. Form 6 (see Figure 2(A)).

[0096] Next, a resist mask is formed by a third photolithography process, and then selectively etched. After performing the process, oxide insulating layers 426a and 426b are formed, and then the resist mask is removed. At this stage, a region is formed in the stacked oxide semiconductor layer that is in contact with the oxide insulating layer. Within the region, the gate electrode layer and the gate insulating layer overlap via the oxide insulating layer 426a. The overlapping region becomes the channel formation region. Furthermore, it covers the periphery and sides of the stacked oxide semiconductor layers. A region overlapping with the oxide insulating layer 426b is also formed.

[0097] The oxide insulating film shall have a thickness of at least 1 nm, and oxide insulating film shall be manufactured by sputtering or other methods. The membrane can be formed using appropriate methods to prevent the introduction of impurities such as water and hydrogen. In this configuration, a silicon oxide film with a thickness of 300 nm is used as the oxide insulating film by sputtering. The film is then formed. The substrate temperature during film formation should be between room temperature and 300°C, and in this embodiment... The temperature is assumed to be at room temperature. For silicon oxide film deposition by sputtering, a noble gas (typically Argonaut) is used. Under an atmosphere of (n), under an oxygen atmosphere, or under an atmosphere of a noble gas (typically argon) and oxygen It can be done in a place. Also, silicon oxide target or silicon target as the target. A set can be used. For example, a silicon target can be used under an oxygen and nitrogen atmosphere. A silicon oxide film can be formed by sputtering. This results in a low-resistance oxide semiconductor. The oxide insulating film formed in contact with the body layer contains water, hydrogen ions, and OH - Contains impurities such as First, an inorganic insulating film is used to block these from entering from the outside, typically as an oxidation Using a silicon film, silicon nitride / oxide film, aluminum oxide film, or aluminum oxide / nitride film, etc. ru.

[0098] Next, a second heat treatment (preferably) is performed under an inert gas atmosphere (for example, under a nitrogen gas atmosphere). The temperature should be between 200°C and 400°C, for example, between 250°C and 350°C (see Figure 2(B)). Illuminate. ) For example, a second heating treatment is performed at 250°C for 1 hour under a nitrogen atmosphere. Second heating When the process is performed, the edge of the oxide semiconductor layer 442 that overlaps with the oxide insulating layer 426b and the oxide insulating layer A portion of the oxide semiconductor layer 442 overlapping with the edge layer 426a is heated in contact with the oxide insulating layer. Furthermore, when the second heat treatment is performed, the oxide semiconductor layer that does not overlap with the oxide insulating layer is formed. A portion of 442 is exposed and heated. The stacked oxide semiconductor layer 442 is exposed. When heat treatment is performed under nitrogen or an inert gas atmosphere, the stacked oxide semiconductor layer 4 The high-resistance (Type I) region exposed at 42 can be made to have low resistance. Furthermore, the oxide insulating layer 426a is located in the channel formation region of the stacked oxide semiconductor layer 442. It is provided in contact with the region and functions as a channel protection layer.

[0099] Next, the gate insulating layer 402, oxide insulating layers 426a, 426b, and the laminated oxide semiconductor After forming a translucent conductive film on the body layer 442, the fourth photolithography step is performed. A resist mask is formed, and selective etching is performed on the source electrode layer 425a, and A drain electrode layer 425b is formed (see Figure 2(C)). Method for forming a transparent conductive film. The methods include sputtering, vacuum deposition (such as electron beam deposition), and arc discharge ion plate. The coating method or spray method is used. The conductive film material is transparent to visible light. Conductive materials such as In-Sn-Zn-O systems, In-Al-Zn-O systems, Sn-Ga-Z nO system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn -Zn-O, Al-Zn-O, In-O, Sn-O, and Zn-O metal oxides It can be applied, and the film thickness can be appropriately selected within the range of 50 nm to 300 nm. When using the sputtering method, a target containing 2% to 10% by weight of SiO2 is used. The film is then formed, and the transparent conductive film contains SiOx (X>0) which inhibits crystallization. It is preferable to suppress crystallization during the subsequent heat treatment process.

[0100] Note that a resist mask is used to form the source electrode layer 425a and the drain electrode layer 425b. The resist mask may be formed by an inkjet method. Because it does not use a photomask, manufacturing costs can be reduced.

[0101] Next, oxide insulating layers 426a, 426b, source electrode layer 425a, drain electrode layer 42 A protective insulating layer 403 is formed on 5b. In this embodiment, nitriding is performed using the RF sputtering method. A silicon film is formed. RF sputtering is a method for forming the protective insulating layer 403 because it offers good mass production capabilities. This is preferable. The protective insulating layer 403 is protected from moisture, hydrogen ions, and OH - Contains impurities such as First, an inorganic insulating film is used to block these from entering from the outside, and then a silicon nitride film, nitrogen Aluminum oxide film, silicon nitride film, aluminum oxide nitride, etc. are used. Of course, protective insulation The margin layer 403 is a light-transmitting insulating film.

[0102] Next, a planar insulating layer 404 is formed on the protective insulating layer 403. For example, polyimide, acrylic resin, benzocyclobutene resin, polyamide, epoxy Heat-resistant organic materials such as resins can be used. In addition to the above organic materials, Low dielectric constant materials (low-k materials), siloxane resins, PSG (phosphorus glass), BPSG (Limboron glass) and the like can be used. Furthermore, insulating films formed from these materials can be used. A planar insulating layer 404 may be formed by stacking multiple layers.

[0103] Siloxane-based resins are formed using siloxane-based materials as the starting material for Si-OS. This corresponds to a resin containing i-bonds. Siloxane resins use organic groups (e.g., alkyl groups) as substituents. You may also use aryl groups or fluoro groups. Furthermore, organic groups may have fluoro groups. You can.

[0104] The method for forming the planar insulating layer 404 is not particularly limited and can be done by sputtering, SO2, or other methods depending on the material. G method, spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen coating) It can use methods such as screen printing and offset printing, and also a doctor's knife and a roll cord. It can be formed using a coater, curtain coater, knife coater, etc.

[0105] Next, a fifth photolithography step is performed to form a resist mask and a planar insulating layer 4 04, and etching of the protective insulating layer 403 leads to the contacts reaching the drain electrode layer 425b A duct hole 441 is formed, and the resist mask is removed (see Figure 2(D)). Figure 2(D) As shown in the image, an oxide insulating layer 426b is provided below the contact hole, Compared to cases where an oxide insulating layer is not provided below the contact hole, the planar insulating layer that is removed is The film thickness of the margin layer can be reduced, and the etching time can be shortened. Also, the contact hole The depth of the contact hole 441 is compared to the case where an oxide insulating layer is not provided below the hole. This allows for a shallower depth, and in the region overlapping with the contact hole 441, it can be formed in a later process. This allows for good coverage of the conductive film having light-transmitting properties. Etching also forms contact holes that reach the gate electrode layer 421b. A resist mask for forming contact holes that reach the drain electrode layer 425b It may also be formed by the inkjet method. If the resist mask is formed by the inkjet method, Because no tomask is used, manufacturing costs can be reduced.

[0106] Next, a light-transmitting conductive film is formed. The material for the light-transmitting conductive film is an oxide Indium (In2O3) and indium oxide tin oxide alloy (In2O3-SnO2, IT Translucent conductive materials (abbreviated as O) are formed using sputtering or vacuum deposition methods. Other materials for the film include Al-Zn-O non-single crystal films containing nitrogen, i.e., Al-Zn- ON-based non-single crystal films, Zn-ON-based non-single crystal films, Sn-Zn-ON-based non-single crystal films You may also use [this]. Note that the zinc composition ratio (atomic %) of the Al-Zn-ON non-single crystal film is: It should be 47 atomic percent or less, and greater than the composition ratio of aluminum in a non-single crystal film (atomic percent). The composition ratio (atomic %) of aluminum in a crystalline film is equal to the composition ratio (atomic %) of nitrogen in a non-single-crystal film. Larger. Etching of such materials is carried out with hydrochloric acid-based solutions. However, especially Etching ITO tends to leave residue, so oxidation is used to improve etching processability. Indium zinc oxide alloy (In2O3-ZnO) may also be used.

[0107] The composition ratio of the light-transmitting conductive film is expressed in atomic percent, and the electron beam microanalyzer... (EPMA:Electron Probe X-ray MicroAnalyzer The evaluation shall be conducted by analysis using ).

[0108] Next, a sixth photolithography step is performed to form a resist mask, and etching is performed. The unnecessary parts are removed to form the pixel electrode layer 427, and the resist mask is removed (Figure 2( See E). ).

[0109] Through the above process, using six masks, thin-film transistors 448 and a junction are placed on the same substrate. A wiring intersection with reduced raw capacitance can be fabricated. Pixel thin-film transistor 44 8 is a high-resistance source region 424a, a high-resistance drain region 424b, and a channel formation region. This is a channel-protected thin-film transistor containing a stacked oxide semiconductor layer 442 including 423. Therefore, the thin-film transistor 448 maintains a high resistance drain region 424 even when a high electric field is applied. b or the high-resistance source region 424a acts as a buffer, preventing the application of a localized high electric field. The inverter has been redesigned to improve its pressure resistance.

[0110] Furthermore, the gate insulating layer 402 is used as a dielectric, and the retained capacitance formed by the capacitive wiring layer and the capacitive electrode is also It can be formed on the same substrate. Thin-film transistors 448 and retaining capacitances are provided for each individual pixel. The pixels are arranged in a matrix to form an active-matrix display device. It can be used as one of the substrates for manufacturing. In this specification, for convenience, such a substrate is referred to as a capacitive matrix substrate.

[0111] Also, thin film transistors of the driving circuit can be provided on the same substrate. By forming the driving circuit and the pixel portion on the same substrate, the connection wiring for the external signal input to the driving circuit can be shortened, and miniaturization and cost reduction of the semiconductor device are possible.

[0112] Also, the oxide semiconductor layer 442 of the stack of the thin film transistor 448 for pixels shown in FIG. 1(B) has a first region 424c and a second region 424d overlapping the oxide insulating layer 426b at the peripheral portion and is. The first region 424c and the second region 4 24d, which are the peripheral portions of the stacked oxide semiconductor layer 442, are in the same oxygen-excessive state as the channel formation region 423, and when wiring with different potentials or stacked oxide semiconductor layers are arranged nearby, reduction of leakage current and reduction of parasitic capacitance can be achieved [[ID=2(4]]realized.

[0113] Also, by providing the oxide insulating layer 426b, even if the metal thin film is not oxidized it covers the side surface of the metal thin film and has a structure that prevents short-circuiting between the source electrode layer and the drain electrode layer and.

[0114] Especially in the driving circuit, for high integration, it is preferable to arrange the intervals between a plurality of wirings and a plurality of oxide semiconductor layers narrowly, and by overlapping with the oxide insulating layer 426b, the first region 424c and the second region 424d are provided, and it is effective to reduce leakage current and parasitic capacitance. Also, when arranging a plurality of thin film transistors in series or in parallel, the oxide semiconductor layers of the plurality of thin film transistors are made into one island, and element isolation for each is performed by oxide insulation layer. This is performed by overlapping with the layer 426b, and a region overlapping with the oxide insulating layer 426b is defined as an element isolation region. By doing so, a plurality of thin film transistors can be arranged in a narrow area, and thus high integration of the drive circuit can be achieved.

[0115] (Embodiment 2) In this embodiment, an example of manufacturing an active matrix type liquid crystal display device by forming a pixel portion and a drive circuit on the same substrate using the thin film transistor shown in Embodiment 1 is shown.

[0116] An example of the cross-sectional structure of the active matrix substrate is shown in FIG. 3(A).

[0117] In Embodiment 1, the thin film transistor and the wiring intersection portion in the pixel portion were illustrated. In this embodiment, in addition to the thin film transistor and the wiring intersection portion, the thin film transistor in the drive circuit, the holding capacitance, and the terminal portions of the gate wiring, source wiring will also be illustrated and described. The terminal portions of the capacitance, gate wiring, and source wiring can be formed by the same process as the manufacturing process shown in Embodiment 1. Also, in the portion that becomes the display region of the pixel portion, the gate wiring, source wiring, and capacitance wiring layer are all formed of a conductive film having translucency, realizing a high aperture ratio.

[0118] In FIG. 3(A), the thin film transistor 220 electrically connected to the pixel electrode layer 227 is a channel protection type thin film transistor provided in the pixel portion. In this embodiment, the same structure as the thin film transistor 448 of Embodiment 1 is used. Also, the width in the channel length direction of the gate electrode layer of the thin film transistor 220 is narrower than the width in the channel length direction of the oxide semiconductor layer of the thin film transistor 220.

[0119] A material having the same light-transmitting properties as the gate electrode layer of the thin-film transistor 220, and formed using the same process. The capacitive wiring layer 230 is connected to the capacitive electrode 231 via the gate insulating layer 202 which acts as a dielectric. They overlap and form a retaining capacitance. The capacitive electrode 231 is a saw of the thin-film transistor 220. The material is the same as the light-transmitting material as the drain electrode layer or the drain electrode layer, and is formed using the same process. Therefore, in addition to the light-transmitting properties of the thin-film transistor 220, each of its holding capacities Because it also has light-transmitting properties, the aperture ratio can be improved.

[0120] The fact that the holding capacity is light-transmitting is important for improving the aperture ratio, especially for 10-inch lenses. In the following small LCD display panel, increasing the number of gate wires, etc., improves the display image quality. To achieve higher resolution, even when pixel dimensions are reduced, a high aperture ratio can be achieved. By using a light-transmitting film for the components of the thin-film transistor 220 and the retaining capacitor, To achieve a wide viewing angle, a high aperture ratio is achieved even when one pixel is divided into multiple subpixels. This is possible. In other words, even when arranging a high-density group of thin-film transistors, it is possible to achieve a large aperture ratio. This allows for sufficient display area to be secured. For example, 2- When there are four subpixels and a retaining capacitance, the thin-film transistor is translucent. In addition, since each of the holding capacities is also light-transmitting, the aperture ratio can be improved. ru.

[0121] Furthermore, the retaining capacitance is provided below the pixel electrode layer 227, and the capacitance electrode 231 is located below the pixel electrode layer 2 It is electrically connected to 27.

[0122] In this embodiment, a storage capacitor is formed using the capacitive electrode 231 and the capacitive wiring layer 230. Although an example has been shown, the structure for forming the storage capacitor is not particularly limited. For example, without providing a capacitive wiring layer, the pixel electrode layer may be overlapped with the gate wiring of adjacent pixels through the planarization insulating layer, the protective insulating layer, and the gate insulating layer to form a storage capacitor.

[0123] Also, in FIG. 3(A), since the storage capacitor forms a large capacitance, only the gate insulating layer 202 is provided between the capacitive wiring and the capacitive electrode, and in the wiring intersection part, in order to reduce the parasitic capacitance, a gate insulating layer 202 and an oxide insulating layer 266b are provided between the gate electrode layer 421b and the wiring formed above it. In the storage capacitor, when only the gate insulating layer 202 is provided between the capacitive wiring and the capacitive electrode, etching conditions for selectively leaving only the gate insulating layer 202 or the material of the gate insulating layer are selected during the etching for removing the oxide insulating layer 266b. In this embodiment, since the oxide insulating layer 266b is a silicon oxide film obtained by sputtering and the gate insulating layer 202 is a silicon nitride film obtained by plasma CVD, selective removal is possible. Note that when the oxide insulating layer 266b and the gate insulating layer 202 are made of materials removed under the same etching conditions, even if a part of the gate insulating layer is thinned by etching, it is preferable that at least the gate insulating layer remains and has a film thickness capable of forming a capacitance. In order to increase the storage capacitor, it is preferable to reduce the film thickness of the gate insulating layer. Therefore, a configuration may be adopted in which the gate insulating layer on the capacitive wiring is thinned during the selective etching of the oxide insulating layer 266b.

[0124] ​​​​​Furthermore, the thin-film transistor 260 is a channel-protected thin-film transistor provided in the drive circuit. It is a standard transistor, and compared to the thin-film transistor 220, the channel length L is shortened to increase the operating speed. This is the result. The channel length of the channel-protected thin-film transistor provided in the drive circuit. L is preferably 0.1 μm or more and 2 μm or less. The width of the electrode layer 261 in the channel length direction is the channel of the oxide semiconductor layer of the thin-film transistor 260. Wider than the width in the length direction of the gate electrode layer 261, the end face of the gate insulating layer 202 and the oxide The source electrode layer 265a or the drain electrode layer 265b overlaps via the material insulating layer 266b. .

[0125] Furthermore, the thin-film transistor 260 is formed by removing the metal thin film and then depositing an oxide semiconductor film, and then acid Compared to the thin-film transistor 220, the thickness of the oxide semiconductor layer is thinner by using only a single layer of oxide semiconductor layer. Thus, the operating speed has been increased. The oxide semiconductor layer of the thin-film transistor 260 When a single layer is used, the metal thin film is selectively etched, so the acid of the thin-film transistor 260 Compared to stacking multiple ion semiconductor layers, the number of photomasks increases by one.

[0126] The thin-film transistor 260 has a gate electrode layer 261 and a gate electrode layer on a substrate 200 having an insulating surface. The insulating layer 202, at least the channel forming region 263, the high-resistance source region 264a, and An oxide semiconductor layer having a high-resistance drain region 264b, a source electrode layer 265a, and It includes a rain electrode layer 265b. Also, an oxide insulating layer 26 in contact with the channel forming region 263. 6a is provided.

[0127] Furthermore, the gate electrode layer of the thin-film transistor 260 in the drive circuit is located above the oxide semiconductor layer. The structure may also be one in which the conductive layer 267 is electrically connected. In that case, the thin film tracer A connector for electrically connecting the drain electrode layer of the inverter 220 and the pixel electrode layer 227. Using the same photomask as Tact Hole, planar insulating layer 204, protective insulating layer 203, oxidation The physical insulating layer 266b and the gate insulating layer 202 are selectively etched to form contact holes. This allows the conductive layer 267 and the thin-film transistor 26 of the drive circuit to connect through this contact hole. The gate electrode layer 261 of component 0 is electrically connected to it.

[0128] The protective insulating layer 203 uses an inorganic insulating film, consisting of a silicon nitride film, an aluminum nitride film, and a silicon nitride oxide film. A film such as an aluminum oxide nitride is used. In this embodiment, a silicon nitride film is used.

[0129] Furthermore, in the thin-film transistor 260, the width of the gate electrode layer 261 is greater than the width of the oxide semiconductor layer. It has a broad structure. Also, the oxide insulating layer 266b overlaps with the peripheral edge of the oxide semiconductor layer. It is also overlapping with the gate electrode layer 261. The oxide insulating layer 266b is made of Dre The gap between the in electrode layer 265b and the gate electrode layer 261 is widened, and the drain electrode layer 265b and gate electrode layer 261 are widened. It also plays a role in reducing the parasitic capacitance formed between the electrode layer 261 and the acid The first region 264c and the second region 264d of the oxide semiconductor layer overlapping with the oxide insulating layer 266b are, This region is in the same oxygen-rich state as channel formation region 263, which reduces leakage current and parasitic capacitance. It also serves a function of reducing it.

[0130] Furthermore, the size of the LCD display panel has exceeded 10 inches, reaching 60 inches, and even 120 inches. In that case, the wiring resistance of the light-transmitting wiring may become a problem, so part of the wiring It is preferable to reduce wiring resistance by using metal wiring. For example, as shown in Figure 3(A), - The electrode layer 265a and the drain electrode layer 265b are connected to a metal wiring (metal electrode) such as Ti. do.

[0131] In that case, a metal electrode such as Ti comes into contact with the dehydrated or dehydrogenated oxide semiconductor layer. A source electrode layer and drain electrode layer are formed, and a high-resistance source region overlaps the source electrode layer. A high-resistance drain region is formed that overlaps with the drain electrode layer, and a high-resistance source region and a high-resistance drain region are formed. The region between the drain region and the channel formation region is the channel formation region.

[0132] Furthermore, in order to reduce wiring resistance, as shown in Figure 3(A), the source electrode layer 265a and the drain Auxiliary electrode layers 268a and 268b using a metal electrode with lower resistance are placed on the in electrode layer 265b. Forms. In this case as well, since metal wiring (metal electrodes) is formed, it is even more efficient than in Embodiment 1. The number of photomasks increases by one.

[0133] Source electrode layer 265a, drain electrode layer 265b, auxiliary electrode layers 268a, 268b, thin film The source electrode layer and drain electrode layer of transistor 220 are made of a translucent conductive film and gold A thin conductive film is formed by laminating the film and selectively etching it using a photolithography process. The metal conductive film on the source electrode layer and drain electrode layer of the film transistor 220 is removed.

[0134] Furthermore, during etching of the metal conductive film, the source electrode layer and the etched metal of the thin-film transistor 220 The materials and etching conditions are adjusted appropriately to ensure that the in-electrode layer is not removed.

[0135] For example, an alkaline etchant is used to selectively etch a metal conductive film. The material for the metal conductive film is selected from Al, Cr, Cu, Ta, Ti, Mo, and W. The element, or an alloy containing the above-mentioned elements, or an alloy film combining the above-mentioned elements, etc. These are some examples. Furthermore, the metal conductive film may be a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, or a titanium film laminated on top of an aluminum film. It has a two-layer structure, a Ti film, and an aluminum film stacked on top of the Ti film, and further on Examples include a three-layer structure in which a Ti film is deposited on Al. Tungsten (W), Molybdenum (Mo), Chromium (Cr), Neodymium (N) d) Films and alloy films comprising one or more elements selected from scandium (Sc). Alternatively, a nitride film may be used.

[0136] In this embodiment, a Ti film is used as the metallic conductive film, and the source electrode layer and drain electrode layer In-Sn-O based oxides are used, and ammonia peroxide is used as the etchant. A. Use a mixture of water and hydrogen peroxide.

[0137] A drain electrode layer provided between the oxide semiconductor layer and the auxiliary electrode layer 268b made of a metal material. 265b is a low-resistance drain region (LRN (Low Resistance N-type)). conductivity) area, LRD (Low Resistance Drai) It also functions as an n) region. Oxide semiconductor layer, low-resistance drain region, metal electrode By configuring the auxiliary electrode layer 268 in this way, the breakdown voltage of the transistor can be further improved. This is possible. Specifically, the carrier concentration in the low-resistance drain region is lower than that in the high-resistance drain region. Larger than the region (HRD region), for example, 1 × 10⁻⁶20 / cm 3 The above 1 x 10 21 / cm 3 It is preferable that the range be within the following:

[0138] Furthermore, gate wiring, source wiring, and capacitive wiring layers are provided in multiple layers depending on the pixel density. Furthermore, at the terminal section, there is a first terminal electrode at the same potential as the gate wiring, and a source wiring. Multiple terminal electrodes, such as a second terminal electrode at the same potential as the capacitive wiring layer and a third terminal electrode at the same potential as the capacitive wiring layer, are arranged in a row. They are arranged. The number of each terminal electrode can be any number you like. The contractor should make the decision as appropriate.

[0139] In the terminal section, the first terminal electrode, which is at the same potential as the gate wiring, has the same light transmission as the pixel electrode layer 227. It can be formed from a material having properties. The first terminal electrode reaches the gate wiring. It is electrically connected to the gate wiring via a contact hole. The wire electrically connects the drain electrode layer of the thin-film transistor 220 and the pixel electrode layer 227. Using the same photomask as the contact holes for continuation, a planar insulating layer 204, protective insulating The marginal layer 203 is selectively etched to form it.

[0140] Furthermore, the second terminal electrode 255 is at the same potential as the source wiring 254 and auxiliary wiring 269 of the terminal section. This can be formed from a material having the same light-transmitting properties as the pixel electrode layer 227. Pole 255 is electrically connected to the source wiring through a contact hole that reaches source wiring 254. The source wiring 254 is connected to the source electrode layer 265a of the thin-film transistor 260. They are made of the same material, formed by the same process, and have the same potential. On the other hand, the auxiliary wiring 269 is the same as the source wiring 25 This is a metal wiring using a metal material with lower resistance than 4, and is an auxiliary electrode layer for the thin-film transistor 260. 268a and 268b were formed using the same materials and process, and have the same potential.

[0141] Furthermore, the third terminal electrode, which is at the same potential as the capacitive wiring layer 230, has the same light transmission properties as the pixel electrode layer 227. It can be formed from a material having the following properties. Also, contact holes reaching the capacitive wiring layer 230 The capacitive electrode 231 has contact holes for electrically connecting with the pixel electrode layer 227. The same photomask can be formed using the same process.

[0142] Furthermore, when manufacturing an active matrix type liquid crystal display device, the active matrix A liquid crystal layer is provided between the substrate and the opposing substrate on which the opposing electrodes are provided, and an active matrix is ​​formed. The substrate and the opposing substrate are fixed together. Furthermore, the opposing electrode provided on the opposing substrate is electrically connected. A common electrode is provided on the active matrix substrate, and a fourth terminal is electrically connected to the common electrode. An electrode is provided at the terminal. This fourth terminal electrode is connected to a common electrode at a fixed potential, for example, GND, 0 This is a terminal for setting V, etc. The fourth terminal electrode has the same light transmittance as the pixel electrode layer 227. It can be formed from a material having the following properties.

[0143] Also, gate electrode layer, source electrode layer, drain electrode layer, pixel electrode layer, or other electrodes Using the same material for the layers and other wiring layers allows for the use of common sputtering targets and common manufacturing equipment. It can be used, and the material cost and the etchant used during etching (or This reduces the cost required for etching gas, and as a result, reduces manufacturing costs. It is possible.

[0144] Furthermore, in the structure shown in Figure 3(A), a photosensitive resin material is used as the planar insulating layer 204. In this case, the step of forming a resist mask can be omitted.

[0145] Furthermore, Figure 3(B) shows a cross-sectional structure that differs in part from that of Figure 3(A). Figure 3(B) is a reference to Figure 3( A) The absence of the planar insulating layer 204 at the terminal and the structure of the thin-film transistor in the drive circuit Since they are the same except for the differences, the same symbols are used for the same parts, and the detailed explanation of the same parts is... (Details omitted.) Figure 3(B) shows a thin-film transistor 270 using metal wiring. Furthermore, the terminal electrodes are formed using the same materials and processes as the metal wiring.

[0146] Furthermore, in the structure shown in Figure 3(B), a photosensitive resin material is used as the planar insulating layer 204. Therefore, the process of forming a resist mask is omitted. Therefore, a configuration can be made in which the planar insulating layer 204 does not exist at the terminal portion. The absence of a planar insulating layer makes it easier to achieve a good connection with the FPC.

[0147] The thin-film transistor 270 has a gate electrode layer 271 and a gate electrode layer on a substrate 200 having an insulating surface. The insulating layer 202, at least the channel forming region 273, the high-resistance source region 274a, and An oxide semiconductor layer having a high-resistance drain region 274b, a source electrode layer 275a, and It includes a rain electrode layer 275b. Also, an oxide insulating layer 27 in contact with the channel forming region 273. 6a is provided.

[0148] Furthermore, the first region 274c and the second region 27 of the oxide semiconductor layer overlap with the oxide insulating layer 276b. 4d is in the same oxygen-rich state as channel formation region 273, which reduces leakage current and... It also serves the function of reducing raw capacitance. Furthermore, the oxide semiconductor layer in contact with the protective insulating layer 203... The third region 274e is provided between the channel formation region 273 and the high-resistance source region 274a. Furthermore, the fourth region 274f of the oxide semiconductor layer in contact with the protective insulating layer 203 is channel It is provided between the drain formation region 273 and the high-resistance drain region 274b. Protective insulating layer 203 and The third region 274e and the fourth region 274f of the contacting oxide semiconductor layer are designed to reduce the off-current. It is possible.

[0149] Furthermore, channel-protected thin-film transistors shorten the channel length L of the channel formation region. Therefore, the width of the oxide insulating layer is narrowed, and the source electrode layer and drain are placed on the narrow oxide insulating layer. If an electrode layer is provided, there is a risk of short-circuiting on the oxide insulating layer. Therefore, a narrow oxide insulating layer The source electrode layer 275a and the drain electrode layer 275b are provided, separated from the edge layer 276a. It has that configuration.

[0150] Furthermore, during the etching of the metal conductive film, the oxide semiconductor layer of the thin-film transistor 270 is also removed. To prevent this from happening, adjust the materials and etching conditions accordingly.

[0151] In this embodiment, a Ti film is used as the metal conductive film, and the oxide semiconductor layer is In-Ga- Using Zn-O-based oxides, the etchant is aqueous ammonia peroxide (ammonia, water, peroxide). Use a mixture of hydrogen oxide and water.

[0152] Furthermore, the gate electrode layer of the thin-film transistor 270 in the drive circuit is located above the oxide semiconductor layer. The structure may also be one in which the conductive layer 277 is electrically connected.

[0153] Furthermore, the second terminal electrode 257, which is at the same potential as the source wiring 256 of the terminal section, is connected to the pixel electrode layer 227. It can be formed from a material having the same light-transmitting properties. The source wiring is metal wiring, and it is a thin film. The source electrode layer 275a of transistor 270 is formed using the same material and process, and at the same potential. be.

[0154] Furthermore, thin-film transistors are susceptible to damage from static electricity, etc., so the pixel area or driving circuit It is preferable to provide the protection circuit on the same substrate. The protection circuit uses an oxide semiconductor layer. It is preferable to use nonlinear elements in the configuration. For example, the protection circuit consists of a pixel section and a scan line input It is arranged between the terminal and the signal line input terminal. In this embodiment, multiple protection circuits are arranged. When a surge voltage is applied to the scan line, signal line, and capacitive bus line due to static electricity, the pixel It is designed to prevent damage to transistors and other components. Therefore, the protection circuit is designed to protect against surge currents. When pressure is applied, the system is configured to allow charge to escape to the common wiring or to the common wiring. The protection circuit is composed of nonlinear elements arranged in parallel with respect to the scan lines. Elements and nonlinear elements include two-terminal elements such as diodes or three-terminal elements such as transistors. It is composed of elements. For example, it is formed using the same process as the thin-film transistor 220 of the pixel portion. It is also possible to connect the gate terminal and drain terminal in the same way as a diode, for example. It can be given these characteristics.

[0155] Furthermore, the process of forming the planar insulating layer 204 is omitted, resulting in a structure without the planar insulating layer 204. This is also possible. In this case, the conductive layer 267, conductive layer 277, pixel electrode layer 227, and second terminal electrode 255 and 257 are provided in contact with the protective insulating layer 203.

[0156] This embodiment can be freely combined with Embodiment 1.

[0157] (Embodiment 3) Furthermore, in this embodiment, one of the configurations of the terminal portion provided on the same substrate as the thin-film transistor An example is shown. Note that in Embodiment 2, an example of the terminal portion of the source wiring is shown, but in this embodiment... Next, we will illustrate the terminal section of the source wiring and the terminal section of the gate wiring, which have a different configuration from that of Embodiment 2. In Figure 4, the same reference numerals are used for the same parts as in Figure 3(A) or Figure 3(B). explain.

[0158] Figures 4(A1) and 4(A2) show the top view and cross-sectional view of the gate wiring terminal section, respectively. Figure 4(A1) corresponds to a cross-sectional view along the line C1-C2 in Figure 4(A2). In (A1), the conductive layer 225 formed on the protective insulating layer 203 is used as an input terminal. These are terminal electrodes for connection. Also, in Figure 4(A1), the terminal portion is a gate electrode. A first terminal 221 formed from the same material as layer 421b, and a source wiring formed from the same material A connecting electrode layer 223, and an auxiliary electrode formed of a metal electrode material with lower resistance than the connecting electrode layer 223. The pole layer 228 overlaps with the gate insulating layer 202, and is electrically connected by the conductive layer 225. Furthermore, if the connecting electrode layer 223 has the configuration shown in Figure 3(B), a metal wiring material is used. It is possible.

[0159] Furthermore, Figures 4(B1) and 4(B2) are different from the source wiring terminal section shown in Figure 3(B). The top view and cross-sectional view of the source wiring terminal section are shown, respectively. Also, Figure 4(B1) This corresponds to the cross-sectional view along the line C3-C4 in Figure 4(B2). In Figure 4(B1), protection The conductive layer 225 formed on the insulating layer 203 is a terminal electrode for connection that functions as an input terminal. Furthermore, in Figure 4(B1), the terminal section is formed from the same material as the gate wiring. The electrode layer 226 provides gate insulation below the second terminal 222, which is electrically connected to the source wiring. They overlap via layer 202. The electrode layer 226 is not electrically connected to the second terminal 222. The electrode layer 226 is at a different potential from the second terminal 222, for example, floating, GND, 0V. By setting it to such a value, you can create capacitance for noise suppression or capacitance for static electricity suppression. This can be done. In addition, a metal electrode material with lower resistance than the second terminal 222 is provided on the second terminal 222. An auxiliary electrode layer 229 formed of material is laminated, and a contact is formed on the protective insulating layer 203. It is electrically connected to the conductive layer 225 via a hole. Also, the second terminal 222 is shown in Figure 3. Metal wiring materials can be used when the configuration shown in (B) is adopted.

[0160] Multiple gate lines, source lines, and capacitive lines are provided depending on the pixel density. Furthermore, at the terminal section, there is a first terminal at the same potential as the gate wiring, and a second terminal at the same potential as the source wiring. Multiple terminals, such as terminal 2 and a third terminal at the same potential as the capacitance wiring, are arranged in a row. The number of terminals can be any number desired, and the implementer may decide this as appropriate.

[0161] This embodiment can be freely combined with Embodiment 1 or Embodiment 2.

[0162] (Embodiment 4) Here, in a liquid crystal display device in which a liquid crystal layer is sealed between a first substrate and a second substrate, the second A common connection portion for electrically connecting to a counter electrode provided on the substrate is formed on the first substrate. An example is shown. Note that a thin-film transistor is formed on the first substrate as a switching element. The manufacturing process for the common connection section is made common with the manufacturing process for the switching elements of the pixel section. This allows for the formation process without complicating it.

[0163] The common connection section is positioned to overlap with the sealing material used to bond the first substrate and the second substrate. Then, an electrical connection is made with the counter electrode via conductive particles contained in the sealing material. A common connection part is provided in the area that does not overlap with the sealing material (except for the pixel area), and the common connection part A paste containing conductive particles is provided separately from the sealing material so as to overlap with the opposing electrode, and electrical A connection is established.

[0164] Figure 5(A) shows a cross-section of a semiconductor device in which a thin-film transistor and a common connection part are fabricated on the same substrate. This is a diagram showing the structure.

[0165] In Figure 5(A), the thin-film transistor 220 electrically connected to the pixel electrode layer 227 is This is a channel-protected thin-film transistor provided in the pixel section, and in this embodiment, It uses the same structure as the thin-film transistor 448 of form 1.

[0166] Furthermore, Figure 5(B) shows an example of a top view of a common connection, and the dashed line C5-C6 in the figure is This corresponds to the cross-section of the common connection part in Figure 5(A). Note that in Figure 5(B) it is the same as in Figure 5(A). The same symbols will be used to explain the part.

[0167] The common potential line 205 is provided on the gate insulating layer 202 and is the saw of the thin-film transistor 220. The same material and process are used to manufacture the drain electrode layer and the common potential line 2. On top of 05 is an auxiliary wiring 21 made of metal wiring manufactured using the same material and process as the auxiliary electrode layer. A zero is formed.

[0168] Furthermore, the common potential line 205 is covered with a protective insulating layer 203, and the protective insulating layer 203 is at the common potential It has multiple openings in a position that overlaps with line 205. These openings are located in thin-film transistor 2 The 20 drain electrode layers and the pixel electrode layer 227 are made using the same process as the contact holes. To be manufactured.

[0169] Note that, since the area size is significantly different here, the contact hole in the pixel area and the common We will use the terms "opening" and "connection part" to distinguish them. Also, in Figure 5(A), the pixel part and common connection The continuation section is not illustrated at the same scale; for example, the length of the dashed line C5-C6 in the common connection section is 500. While the width is approximately μm, the width of a thin-film transistor is less than 50 μm, and in reality it is 10 Although the area size is more than twice as large, for clarity, Figure 5(A) shows the pixel section and the common connection section. The figures are illustrated with varying scales.

[0170] Furthermore, the common electrode layer 206 is provided on the protective insulating layer 203, and the pixel electrode layer 227 of the pixel portion It is made using the same materials and processes.

[0171] In this way, the manufacturing process for the common connection section is made common with the manufacturing process for the switching elements of the pixel section. conduct.

[0172] Then, a first substrate having a pixel section and a common connection section, and a second substrate having a counter electrode Secure it using a sealant.

[0173] When incorporating conductive particles into the sealing material, a pair of bases should be placed so that the sealing material and the common connection part overlap. The panels are aligned. For example, in a small LCD panel, the diagonal of the pixel area is aligned. Two common connection points are placed overlapping with the sealing material. Furthermore, in large LCD panels, Four or more common connection points are arranged overlapping with the sealing material.

[0174] Furthermore, the common electrode layer 206 is an electrode that comes into contact with the conductive particles contained in the sealing material, and the second An electrical connection is made with the opposing electrode on the substrate.

[0175] When using the liquid crystal injection method, after fixing the pair of substrates with a sealing material, the liquid crystal is injected between the pair of substrates. Inject. Also, when using the liquid crystal drop method, apply a sealant to the second or first substrate. After drawing the image and dropping the liquid crystal, the pair of substrates are bonded together under reduced pressure.

[0176] In this embodiment, an example of a common connection part that electrically connects to the counter electrode is shown, but in particular It is not limited to connections to other wiring or to connections to external terminals. It is possible.

[0177] Furthermore, Figure 5(C) shows a cross-sectional structure that differs in part from that of Figure 5(A). Figure 5(C) is a reference to Figure 5( A) and the laminated oxide semiconductor layer overlapping the common electrode layer 206 and the oxide insulating layer covering the edges exist. Since the configuration is the same except for the point of presence and the use of metal wiring as a common potential line, the same location The same symbols are used for the same locations, and detailed explanations of the same locations are omitted.

[0178] The stacked oxide semiconductor layer 207 is provided on the gate insulating layer 202, and the thin-film transistor 2 It is fabricated using the same materials and processes as the 20 stacked oxide semiconductor layers. An oxide insulating layer 208 is formed to cover layer 207. Then, a metal A common potential line 209 is formed from wiring. This common potential line 209, which is made of metal wiring, As shown in Figure 3(B) of Embodiment 2, the source electrode layer of the thin-film transistor of the drive circuit Alternatively, it can be formed using the same process as the drain electrode layer.

[0179] Furthermore, the common electrode layer 206 is covered with a protective insulating layer 203, and the protective insulating layer 203 is at a common potential. It has multiple openings in a position that overlaps with line 209. These openings are located in thin-film transistor 2 The 20 drain electrode layers and the pixel electrode layer 227 are made using the same process as the contact holes. To be manufactured.

[0180] Furthermore, the common potential line 209 is provided on the protective insulating layer 203, and the pixel electrode layer 227 of the pixel portion It is made using the same materials and processes.

[0181] In this way, the manufacturing process for the common connection section is made common with the manufacturing process for the switching elements of the pixel section. Alternatively, the common potential line may be made of metal wiring to reduce wiring resistance.

[0182] This embodiment can be freely combined with any one of embodiments 1 to 3.

[0183] (Embodiment 5) In Embodiment 1 or Embodiment 2, an example was shown in which the gate insulating layer was a single layer, but in this embodiment... Now, let's look at an example of lamination. Note that in Figure 6, the same location as in Figure 3(A) or Figure 3(B) The same symbols are used to explain this.

[0184] In Figure 6(A), the thin-film transistor 280 is a channel-protected thin film provided in the pixel. This is a film transistor with two gate insulating layers and is an example of two oxide semiconductor layers. Furthermore, the thin-film transistor 260 is a channel-protected thin-film transistor provided in the drive circuit. This is a sta, with two gate insulating layers and an example of a single oxide semiconductor layer. (See Figure 3) The thin-film transistor 260 shown in (A) and the thin-film transistor 260 shown in Figure 6(A) are identical. Therefore, we will omit the explanation here.

[0185] In this embodiment, a first gate insulating layer 282a with a film thickness of 50 nm to 200 nm is provided, A gate insulating layer consisting of a second gate insulating layer 282b with a film thickness of 50 nm to 300 nm and The first gate insulating layer 282a is a silicon nitride film or oxidized nitride film with a thickness of 100 nm. A silicon film is used. In addition, the second gate insulating layer 282b is a silicon oxide film with a thickness of 100 nm. A film is used.

[0186] Furthermore, the thin-film transistor 280 has a gate electrode layer 281 on a substrate having an insulating surface, Gate insulating layer 282a, second gate insulating layer 282b, at least channel forming region A layered acid having 283, a high-resistance source region 284a, and a high-resistance drain region 284b It includes a synthetic semiconductor layer, a source electrode layer 285a, and a drain electrode layer 285b. A laminated oxide insulating layer 286a is provided in contact with the flannel-forming region 283. The first region 284c and the second region 284d of the stacked oxide semiconductor layer overlapping with layer 286b are This region is in the same oxygen-rich state as channel formation region 283, which reduces leakage current and parasitic capacity. It also performs a function of reducing. Furthermore, the pixel electrode layer 227 has electrical connections with the drain electrode layer 285b. Connected.

[0187] Furthermore, the retaining capacitance is provided below the pixel electrode layer 227, and the capacitance electrode 231 is located below the pixel electrode layer 2 It is electrically connected to 27.

[0188] In this embodiment, a capacitive electrode 231 and a capacitive wiring layer 230 are used to form a retained capacitance. .

[0189] Furthermore, in Figure 6(A), the retained capacitance forms a large capacitance, and the capacitance wiring and capacitance electrode are used. Only a gate insulating layer is used in between.

[0190] In this embodiment, a silicon oxide film obtained by sputtering is used as the oxide insulating layer 286b. When removing the laminated oxide insulating layer that overlaps with the capacitive wiring layer 230, the second silicon oxide film This is an example where the gate insulating layer is also etched and thinned to form a third gate insulating layer 282c. The first gate insulating layer 282a is a silicon nitride film or a silicon oxide nitride film, and etch It functions as an etching stopper, preventing etching damage to the gate electrode layer and substrate.

[0191] By using a thin third gate insulating layer 282c, the retention capacity can be increased. can.

[0192] Furthermore, Figure 6(B) shows a cross-sectional structure that differs in some respects from Figure 6(A). In Figure 6(B), Thin-film transistor 290 is a channel-protected thin-film transistor provided in the pixel. The gate insulating layer has two layers, and this is an example of two oxide semiconductor layers. Also, thin film transistor The TA245 is a channel-protected thin-film transistor provided in the drive circuit, and has a gate isolation function. This is an example of a single-layer oxide semiconductor layer with two marginal layers. Note that the thin film trace shown in Figure 6(B) is also shown. In the thin-film transistor 260 shown in Figure 6(A), the transistor 245 has an auxiliary electrode layer 26 Since the structure is identical except for the absence of 8a and 268b, we will omit the explanation here. Like the thin-film transistor 245, the drive circuit also uses a light-transmitting sole without an auxiliary electrode layer. The structure may consist only of a drain electrode layer and a drain electrode layer.

[0193] In the thin-film transistor 290 shown in Figure 6(B), the first film has a film thickness of 50 nm to 200 nm. The gate insulating layer 292a and the second gate insulating layer 292b with a thickness of 1 nm to 50 nm The gate insulating layer is made of a laminated material. The first gate insulating layer 292a is made of an acid with a film thickness of 100 nm. A silicon dioxide film is used. In addition, the second gate insulating layer 292b is a silicon nitride film with a thickness of 10 nm. A film of silicon nitride or a silicon oxide film is used.

[0194] The thin-film transistor 290 has a gate electrode layer 291 on a substrate 200 having an insulating surface, Gate insulating layer 292a, second gate insulating layer 292b, at least channel forming region A layered acid having 293, a high-resistance source region 294a, and a high-resistance drain region 294b It includes a synthetic semiconductor layer, a source electrode layer 295a, and a drain electrode layer 295b. An oxide insulating layer 296a is provided in contact with the flannel-forming region 293.

[0195] Furthermore, the first region 294c and the second region of the stacked oxide semiconductor layer overlap with the oxide insulating layer 296b. Region 294d is in the same oxygen-rich state as channel formation region 293, resulting in a reduction of leakage current. Furthermore, it also serves the function of reducing parasitic capacitance. In addition, the acid in the laminate that is in contact with the protective insulating layer 203 The third region 294e of the ionized semiconductor layer consists of a channel formation region 293 and a high-resistance source region 294 It is provided between a. Also, the fourth region of the laminated oxide semiconductor layer in contact with the protective insulating layer 203. 294f is provided between the channel formation region 293 and the high-resistance drain region 294b. Third region 294e and fourth region 29 of the laminated oxide semiconductor layer in contact with the protective insulating layer 203 4f can reduce the off-current.

[0196] Furthermore, the third region 294e and the fourth region 294f of the oxide semiconductor layer are silicon nitride film or nitrogen It also comes into contact with the second gate insulating layer 292b, which is a silicon oxide film. The protective insulating layer 203 is moisture Or, hydrogen ions, oxygen ions, OH - It does not contain impurities such as these, and these do not enter from the outside. Using an inorganic insulating film that blocks this process, silicon nitride film, aluminum nitride film, oxidized nitride Silicon films, aluminum oxide nitride, etc., are used.

[0197] Furthermore, in this embodiment, the silicon oxide film obtained by sputtering is used as the oxide insulating layer 296b. When removing the oxide insulating layer that overlaps with the capacitance wiring layer 230, a silicon nitride film or an acid nitride film is used. The oxide insulating layer is etched using the second gate insulating layer, which is a silicon dioxide film, as an etching stopper. This is an example of ing.

[0198] Furthermore, channel-protected thin-film transistors shorten the channel length L of the channel formation region. Therefore, the width of the oxide insulating layer is narrowed, and the source electrode layer and drain are placed on the narrow oxide insulating layer. If an electrode layer is provided, there is a risk of short-circuiting on the oxide insulating layer. Therefore, a narrow oxide insulating layer The source electrode layer 295a and the drain electrode layer 295b are provided, separated from the edge layer 296a at the end. It has that configuration.

[0199] This embodiment can be freely combined with any one of embodiments 1 to 4.

[0200] (Embodiment 6) In this embodiment, Figure 7 shows an example where part of the thin-film transistor fabrication process differs from that of Embodiment 1. This is shown in Figure 8. Figures 7 and 8 are the same as Figures 1 and 2, except that the process differs slightly. Therefore, the same symbols are used for the same sections, and detailed explanations of the same sections are omitted.

[0201] First, according to Embodiment 1, a gate electrode layer, a gate insulating layer, and a metal thin film and an acid are placed on the substrate. A semiconductor film is formed. Then, according to Embodiment 1, an island-shaped metal layer 428, island-shaped An oxide semiconductor layer 429 is formed.

[0202] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature for the heat treatment in step 1 shall be 400°C or higher but below the strain point of the substrate, preferably 425°C or higher. Furthermore, if the temperature is 425°C or higher, the heat treatment time can be 1 hour or less, but if it is below 425°C... The heat treatment time shall be longer than one hour. Here, one of the heat treatment devices is A substrate is placed in an electric furnace, and the oxide semiconductor layer is subjected to heat treatment under a nitrogen atmosphere. After that, without exposure to the atmosphere, it prevents the re-importation of water and hydrogen into the oxide semiconductor layer, and the oxide semiconductor... A conductive layer 422 is obtained. Then, high-purity oxygen gas, high-purity N2O gas, or ultra-high-purity gas is introduced into the same furnace. Cooling is performed by introducing dry air (with a dew point of -40°C or lower, preferably -60°C or lower). It is preferable that the gas or N2O gas does not contain water, hydrogen, etc. Alternatively, heat treatment may be used. The purity of the oxygen gas or N2O gas introduced into the device should be 6N (99.9999%) or higher. More than 7N (99.99999%) (i.e., impurities in oxygen gas or N2O gas) It is preferable to set the concentration to 1 ppm or less, preferably 0.1 ppm or less.

[0203] Furthermore, after the first heat treatment in which dehydration or dehydrogenation is performed, the temperature is preferably between 200°C and 400°C. Alternatively, heating treatment at a temperature between 200°C and 300°C under an oxygen or N2O gas atmosphere. It is permissible to act rationally.

[0204] Furthermore, the first heat treatment of the oxide semiconductor layer is performed on the oxide before it is processed into an island-shaped oxide semiconductor layer. This can also be done on semiconductor films. In that case, after the first heat treatment, the substrate is removed from the heating device. The material is removed and the photolithography process is performed.

[0205] By going through the above process, the entire oxide semiconductor film is made into an oxygen-rich state, To counteract, that is, to convert to type I.

[0206] Alternatively, this first heat treatment may oxidize the metal layer 428 to form an oxide semiconductor layer. Furthermore, the first heating treatment is not limited to oxidizing the metal layer 428, but also includes the first heating In addition to the treatment, an oxidation treatment may be performed to oxidize the metal layer 428, for example, later An oxidation treatment may be performed after the deposition of the oxide insulating film formed by the sputtering method.

[0207] Next, an oxide insulating film is formed on the gate insulating layer 402 and the oxide semiconductor layer by sputtering. To accomplish (see Figure 8(A)).

[0208] Next, a resist mask is formed by a third photolithography process, and then selectively etched. After performing the process, oxide insulating layers 426a and 426b are formed, and then the resist mask is removed. (See Figure 8(B)).

[0209] Next, the gate insulating layer 402, oxide insulating layers 426a, 426b, and the laminated oxide semiconductor After forming a translucent conductive film on the body layer 422, the fourth photolithography step is performed. A resist mask is formed, and selective etching is performed on the source electrode layer 425a, and The drain electrode layer 425b is formed (see Figure 8(C)).

[0210] Next, in order to reduce variations in the electrical characteristics of thin-film transistors, under an inert gas atmosphere or perform heat treatment under a nitrogen gas atmosphere (preferably 150°C or higher and less than 350°C). Alternatively, a heat treatment may be performed at 250°C for 1 hour under a nitrogen atmosphere.

[0211] Next, oxide insulating layers 426a, 426b, source electrode layer 425a, drain electrode layer 42 A protective insulating layer 403 is formed on 5b.

[0212] Next, a planar insulating layer 404 is formed on the protective insulating layer 403.

[0213] Next, a fifth photolithography step is performed to form a resist mask and a planar insulating layer 4 04, and etching of the protective insulating layer 403 leads to the contacts that reach the drain electrode layer 425b. This creates a duct hole 441 and removes the resist mask (see Figure 8(D)).

[0214] Next, a light-transmitting conductive film is formed.

[0215] Next, a sixth photolithography step is performed to form a resist mask, and etching is performed. The unnecessary parts are removed to form the pixel electrode layer 427, and the resist mask is removed (Figure 8). See E). ).

[0216] Through the above process, using six masks, thin-film transistors 420 and a junction are placed on the same substrate. It is possible to create wiring intersections with reduced raw capacitance.

[0217] The thin-film transistor 420 for the pixel is located in a stacked oxide semiconductor layer 42 that includes a channel formation region. This is a channel-protected thin-film transistor that includes 2.

[0218] Furthermore, Figure 7(A) shows the planar view of the channel-protected thin-film transistor 420 arranged in the pixel. Figure 7(B) is a cross-sectional view of line D7-D8 in Figure 7(A) and line D This is a cross-sectional view at 11-D12. Also, Figure 7(C) is a cross-sectional view of line D9-D10 in Figure 7(A). This is a cross-sectional view. Note that Figure 8(E) is identical to Figure 7(B).

[0219] This embodiment can be freely combined with any one of Embodiments 1 to 5.

[0220] (Embodiment 7) In this embodiment, an example of the configuration of the holding capacity that differs from that of Embodiment 2 is shown in Figure 9(A) and This is shown in Figure 9(B). Figure 9(A) is the same as Figure 3(A) except that the configuration of the holding capacity is different. Therefore, the same symbols are used for the same locations, and detailed explanations of the same locations are omitted. (See Figure 9) (A) shows the cross-sectional structure of the thin-film transistor 220 and retaining capacitance in the pixel area.

[0221] Figure 9(A) shows the dielectric material as a protective insulating layer 203 and a planar insulating layer 204, and the pixel electrode layer 2 This is an example in which a retained capacitance is formed by 27 and the capacitive wiring layer 250 that overlaps with the pixel electrode layer 227. The capacitive wiring layer 250 has the same light transmittance as the source electrode layer of the thin-film transistor 220 in the pixel section. Because the materials and the same process are used to form the source wiring layer of the thin-film transistor 220 They are laid out so that they do not overlap.

[0222] The retention capacity shown in Figure 9(A) is due to the fact that the pair of electrodes and dielectric material are translucent, and the total retention capacity is It is translucent as a body.

[0223] Furthermore, Figure 9(B) is an example of a different storage capacity configuration from Figure 9(A). Since it is the same as 3(A) except for the difference in the configuration of the holding capacity, the same symbols are used for the same parts. I will omit a detailed explanation of the same section.

[0224] Figure 9(B) shows a dielectric material as the gate insulating layer 202, with a capacitive wiring layer 230 and the same capacitive wiring layer 2 In an example where a retained capacitance is formed by stacking an oxide semiconductor layer 251 that overlaps with 30 and a capacitive electrode 231, Yes. Also, the capacitive electrode 231 is stacked in contact with the oxide semiconductor layer 251, and the holding capacity It functions as one of the electrodes of the quantity. The oxide semiconductor layer 251 is a thin-film transistor 22 The oxide semiconductor layer 0 is formed using a different process. The oxide semiconductor layer 251 is formed by removing the metal thin film. After that, an oxide semiconductor layer is formed on a single layer. In addition, the capacitive wiring layer 230 is a thin film transistor Because it is made of the same translucent material as the gate electrode layer of ZISTA 220 and formed using the same process, it is thin. It is laid out so as not to overlap with the gate wiring layer of film transistor 220. Electrode 231 is electrically connected to the pixel electrode layer 227.

[0225] The retention capacity shown in Figure 9(B) is also due to the fact that the pair of electrodes and dielectric material are translucent, and the total retention capacity It is translucent as a body.

[0226] The holding capacities shown in Figures 9(A) and 9(B) are translucent and the number of gate wires To increase the resolution of the displayed image by increasing the number of pixels, even if the pixel dimensions are reduced, sufficient capacity is required. It can be obtained, and a high aperture ratio can be achieved.

[0227] This embodiment can be freely combined with other embodiments.

[0228] (Embodiment 8) In this embodiment, at least a part of the drive circuit and a thin film to be placed in the pixel area are placed on the same substrate. An example of how to fabricate a lunger is described below.

[0229] The thin-film transistors placed in the pixel area are formed according to Embodiments 1, 2, 5, and 6. Furthermore, the thin-film transistors shown in embodiments 1, 2, 5, and 6 are n-channel type TFTs. Of the driving circuits, a portion of the driving circuit that can be constructed with an n-channel TFT is used in the pixel section. It is formed on the same substrate as the thin-film transistor.

[0230] An example of a block diagram of an active-matrix display device is shown in Figure 14(A). On the substrate 5300 are a pixel section 5301, a first scan line drive circuit 5302, and a second scan line drive circuit. It has a motion circuit 5303 and a signal line drive circuit 5304. The pixel section 5301 has multiple signal lines The signal line drive circuit 5304 extends and is arranged, and multiple scan lines are connected to the first scan line drive circuit 5302, and the second scan line drive circuit 5303 are arranged as extensions. In the intersection region of the signal line, pixels, each having a display element, are arranged in a matrix. Furthermore, the substrate 5300 of the display device is FPC (Flexible Printed Circuit Board). The timing control circuit 5305 (controller, control I) is connected via a connection part such as rcuit. (Also known as C) It is connected.

[0231] Figure 14(A) shows the first scan line drive circuit 5302, the second scan line drive circuit 5303, and The line drive circuit 5304 is formed on the same substrate 5300 as the pixel section 5301. Furthermore, since the number of external components such as drive circuits is reduced, costs can be lowered. Furthermore, when a drive circuit is provided outside the circuit board 5300, extending the wiring at the connection point can cause problems. This can reduce the number of connections, leading to improved reliability or yield.

[0232] The timing control circuit 5305 is, for example, related to the first scan line drive circuit 5302. Then, the start signal for the first scan line drive circuit (GSP1), the clock signal for the scan line drive circuit. (GCK1) is supplied. The timing control circuit 5305 also supplies the second scan line drive circuit For example, for 5303, the start signal (GSP2) for the second scan line drive circuit (start) It supplies the clock signal (GCK2) for the scan line drive circuit (also called a pulse). The drive circuit 5304 receives a start signal (SSP) for the signal line drive circuit and a crossover signal for the signal line drive circuit. SCK signal, video signal data (DATA) (also simply called video signal), A clock signal (LAT) shall be supplied. Each clock signal shall consist of multiple signals with different periods. It can be a clock signal, or it can be supplied along with an inverted clock signal (CKB). It may also be a first scan line drive circuit 5302 and a second scan line drive circuit 53 It is possible to omit either 03 or 03.

[0233] In Figure 14(B), a circuit with a low drive frequency (for example, the first scan line drive circuit 5302, the second The scan line driving circuit 5303 is formed on the same substrate 5300 as the pixel section 5301, and the signal line driving This shows a configuration in which the dynamic circuit 5304 is formed on a separate substrate from the pixel section 5301. Due to its configuration, it exhibits a lower field-effect mobility compared to transistors using single-crystal semiconductors. A drive circuit can be formed on the substrate 5300 using film transistors. Therefore, it is possible to increase the size of the display device, reduce costs, or improve yield. ru.

[0234] Furthermore, the thin-film transistors shown in embodiments 1, 2, 5, and 6 are n-channel type TFTs. Figures 15(A) and 15(B) show the configuration of a signal line driving circuit composed of n-channel TFTs. Let's explain the operation by showing an example.

[0235] The signal line driving circuit includes a shift register 5601 and a switching circuit 5602. Switching circuit 5602 is a switching circuit 5602_1~5602_N (where N is natural). It has multiple circuits, each of which is called a number. Switching circuits 5602_1 to 5602_N are, , multiple transistors called thin-film transistors 5603_1~5603_k (where k is a natural number) It has a thin-film transistor 5603_1~5603_k, which is an N-channel type TFT. Let me explain an example.

[0236] The connection relationships of the signal line drive circuit will be explained using the switching circuit 5602_1 as an example. The first terminals of thin-film transistors 5603_1 to 5603_k are connected to wiring 5604_1, respectively. Connected to ~5604_k. Second terminal of thin-film transistor 5603_1~5603_k These are connected to signal lines S1~Sk, respectively. Thin-film transistors 5603_1~5603_ The gate of k is connected to wiring 5605_1.

[0237] The shift register 5601 sequentially supplies high levels (high signals) to the wiring 5605_1 to 5605_N. It outputs a signal at a high power supply potential level, also known as the switching circuit 5602_1~56 It has the function of selecting 02_k in order.

[0238] Switching circuit 5602_1 consists of wiring 5604_1~5604_k and signal lines S1~Sk A function to control the conductivity state (conduction between the first terminal and the second terminal), i.e., wiring 5604_ It has a function to control whether or not to supply potentials between 1 and 5604k to signal lines S1 and Sk. Thus, the switching circuit 5602_1 functions as a selector. The film transistors 5603_1 to 5603_k are connected to wiring 5604_1 to 5604_k, respectively. A function to control the continuity state between this and the signal lines S1~Sk, i.e., wiring 5604_1~5604_k It has the function of supplying the potential to the signal lines S1~Sk. Thus, thin-film transistor 56 Each of the 03_1 to 5603_k functions as a switch.

[0239] Note that wiring 5604_1 to 5604_k each contain video signal data (DATA). The input is video signal data (DATA), which is image information or analog corresponding to the image signal. It is often a G signal.

[0240] Next, regarding the operation of the signal line drive circuit in Figure 15(A), see the timing chart in Figure 15(B). Refer to the explanation. Figure 15(B) shows signals Sout_1 to Sout_N, and signals An example of Vdata_1 to Vdata_k is shown. Signals Sout_1 to Sout_N are each The following is an example of the output signals of the shift register 5601, with signals Vdata_1 to Vdata _k represents an example of a signal input to wiring 5604_1~5604_k. One operating period of the signal line drive circuit corresponds to one gate selection period in the display device. The selection period is divided into, for example, periods T1 to TN. Periods T1 to TN are each , a period for writing video signal data (DATA) to pixels belonging to the selected row be.

[0241] Note that the signal waveform distortions, etc., of each configuration shown in the drawings, etc. of this embodiment are for clarity. The figures may be exaggerated for aesthetic reasons. Therefore, they are not necessarily limited to that scale. It should be noted that...

[0242] During periods T1 to TN, the shift register 5601 receives a high-level signal via wiring 560 Outputs are sent sequentially from 5_1 to 5605_N. For example, during period T1, shift register 5 601 outputs a high-level signal to wiring 5605_1. Then the thin-film transistor... Since 5603_1~5603_k will be turned on, the wiring 5604_1~5604_k and signal Lines S1 to Sk become conductive. At this time, wiring 5604_1 to 5604_k are Data(S1) to Data(Sk) are entered. Each of these belongs to the selected row via thin-film transistors 5603_1 to 5603_k. Of the pixels, the data is written to the pixels in columns 1 through k. In this way, during the period T1 to TN... Then, the video signal data (DATA) is sequentially placed in k columns for each pixel belonging to the selected row. It will be written.

[0243] As described above, video signal data (DATA) is written to pixels in multiple columns. This allows for a reduction in the number of video signal data (DATA) or the number of wires. Therefore, the number of connections to external circuits can be reduced. Also, video signal data (DAT) A) By writing to the pixels in multiple columns at a time, the writing time can be increased. This prevents insufficient writing of video signal data (DATA).

[0244] Note that the shift register 5601 and the switching circuit 5602 are as follows: It is possible to use circuits composed of thin-film transistors as shown in 2, 5, and 6. In addition, the polarity of all transistors in the shift register 5601 is set to N-channel type or P It can be configured using only one of the channel-type polarities.

[0245] A form of shift register used in part of a scan line drive circuit and / or signal line drive circuit. This will be explained using Figures 16 and 17.

[0246] Next, the configuration of the scan line drive circuit will be explained. The scan line drive circuit has a shift register. It also may have level shifters or buffers in some cases. In the operating circuit, the shift register receives the clock signal (CLK) and the start pulse signal (S When P) is input, a selection signal is generated. The generated selection signal is buffered It is buffered and amplified in the scan line and supplied to the corresponding scan line. The scan line contains pixels for one line. The gate electrodes of the transistors are connected. And the transistors for one line of pixels Since they all need to be turned ON at once, the buffer must be capable of handling a large current. This is used.

[0247] The shift register consists of the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N( N is a natural number greater than or equal to 3 (see Figure 16(A)). The shift rate shown in Figure 16(A) The first pulse output circuit 10_1 to the Nth pulse output circuit 10_N of the ZISTA are: The first clock signal CK1 is transmitted from wiring 11, and the second clock signal CK2 is transmitted from the second wiring 12. The third clock signal CK3 is transmitted from the third wire 13, and the fourth clock signal is transmitted from the fourth wire 14. CK4 is supplied. Also, in the first pulse output circuit 10_1, from the fifth wiring 15 The start pulse SP1 (the first start pulse) is input. Also, the nth pulse from the second stage onward In the pulse output circuit 10_n (where n is a natural number between 2 and N), the pulse output cycle of the preceding stage A signal from the road (referred to as the preceding signal OUT(n-1)) is input. Also, the first pulse output Circuit 10_1 receives a signal from the third pulse output circuit 10_3, which is two stages later. Similarly, in the nth pulse output circuit 10_n from the second stage onward, the (n+2)th pulse of the second stage onward The signal from output circuit 10_(n+2) (referred to as the subsequent signal OUT(n+2)) is input. Therefore, the pulse output circuit of each stage outputs to the pulse output circuit of the subsequent and / or two stages prior. The first output signal OUT(1)(SR) to OUT(N)(SR) is input, and another time... A second output signal, OUT(1) to OUT(N), which is electrically input to the circuit, is output. As shown in Figure 16(A), the last two stages of the shift register have a subsequent signal O Since UT(n+2) is not input, one example is to separately input a second start pulse SP2. The configuration should involve inputting a third start pulse SP3 to each device.

[0248] The clock signal (CK) alternates between high and low levels (L signal, low power supply potential) at regular intervals. This is a signal that repeats the same values ​​(also called the level). Here, the first clock signal (CK1) to the second... The four clock signals (CK4) are sequentially delayed by 1 / 4 period (i.e., 90 to each other). °The phase is shifted). In this embodiment, the first clock signal (CK1) to the fourth clock signal The clock signal (CK4) is used to control the drive of the pulse output circuit, etc. The signal may be GCK or SCK depending on the input drive circuit, but here it is C I will explain using the term K.

[0249] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11~ It is electrically connected to one of the fourth wires 14. For example, in Figure 16(A), The first pulse output circuit 10_1 has a first input terminal 21 that is electrically connected to the first wiring 11. The second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is It is electrically connected to the third wiring 13. Also, the second pulse output circuit 10_2 is Input terminal 21 is electrically connected to the second wiring 12, and input terminal 22 is connected to the third wiring The third input terminal 23 is electrically connected to the fourth wiring 14, and the third input terminal 23 is electrically connected to the fourth wiring 14. Yes, they are.

[0250] Each of the first pulse output circuits 10_1 to the Nth pulse output circuits 10_N has a first input terminal Child 21, second input terminal 22, third input terminal 23, fourth input terminal 24, fifth input terminal Assume that it has a child 25, a first output terminal 26, and a second output terminal 27 (see Figure 16(B)). (See). In the first pulse output circuit 10_1, the first clock signal is connected to the first input terminal 21. When signal CK1 is input, the second clock signal CK2 is input to the second input terminal 22, and the third The third clock signal CK3 is input to input terminal 23, and the start signal is input to the fourth input terminal 24. A pulse is input, and the subsequent signal OUT(3) is input to the 5th input terminal 25, and the 1st output The first output signal OUT(1)(SR) is output from terminal 26, and the second output terminal 27 This indicates that the second output signal, OUT(1), is being output.

[0251] The first pulse output circuit 10_1 to the Nth pulse output circuit 10_N are 3-terminal thin film In addition to transistors (also known as TFT: Thin Film Transistors), there are 4 Thin-film transistors can be used at the terminals. If the sta has two gate electrodes separated by a semiconductor layer, the gate electrode below the semiconductor layer The lower gate electrode is also called the lower gate electrode, and the gate electrode above the semiconductor layer is also called the upper gate electrode.

[0252] When oxide semiconductors are used in the semiconductor layer including the channel formation region of a thin-film transistor, manufacturing Depending on the process, the threshold voltage may shift to the negative or positive side. Therefore, in thin-film transistors that use oxide semiconductors in the semiconductor layer including the channel formation region, A configuration that allows control of the threshold voltage is preferred. The four terminals shown in Figure 16(C) The threshold voltage of the thin-film transistor 28 controls the potential of the upper and / or lower gate electrodes. By controlling it, it can be controlled to the desired value.

[0253] Next, let's look at an example of a specific circuit configuration of the pulse output circuit shown in Figure 16(B). (D) will explain this.

[0254] The pulse output circuit shown in Figure 16(D) consists of the first transistor 31 to the thirteenth transistor It has a 43. Also, the first input terminal 21 to the fifth input terminal 25 described above, and In addition to the first output terminal 26 and the second output terminal 27, the first high power supply potential VDD is supplied to the power supply terminal 26. Power line 51, power line 52 to which a second high power potential VCC is supplied, and power line 52 to which a low power potential VSS is supplied. Signals are sent from the power line 53 to the first transistor 31 to the thirteenth transistor 43, and The power supply potential is supplied. Here, the relative magnitudes of the power supply potentials of each power line in Figure 16(D) are The first power supply potential VDD is set to be at or above the second power supply potential VCC, and the second power supply potential VCC The potential shall be greater than the third power supply potential VSS. Note that the first clock signal (CK1) ~ The fourth clock signal (CK4) is a signal that alternates between high and low levels at regular intervals. However, assume that VDD is at the H level and VSS is at the L level. Note that the power supply line 52 By lowering the source potential VCC to a lower value than the power potential VDD of the power line 51, the operation is affected. Without doing so, the potential applied to the gate electrode of the transistor can be kept low, This reduces the threshold shift of the transistor and suppresses degradation. Of the transistors 31 to 13, transistor 43, the first transistor 31 and the sixth transistor Transistors 36 to the 9th transistor 39 have a 4-terminal thin film transistor as shown in Figure 16(C). It is preferable to use transistor 28. First transistor 31, sixth transistor The operation of transistors 36 through 9 39 is such that one of the electrodes, which is either the source or the drain, is in contact. The potential of the connected nodes is required to be switched by the control signal of the gate electrode. It is a transistor, and it has a fast response to the control signal input to the gate electrode (on current rise). By making the rise steeper, the transistor can reduce malfunctions in the pulse output circuit. Therefore, the 4-terminal thin-film transistor 28 shown in Figure 16(C) is used. This allows for control of the threshold voltage, resulting in a pulse output circuit that further reduces malfunctions. It is possible.

[0255] In Figure 16(D), the first transistor 31 has its first terminal electrically connected to the power line 51. The second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode The (lower gate electrode and the upper gate electrode) are electrically connected to the fourth input terminal 24. The second transistor 32 has its first terminal electrically connected to the power line 53, and its second terminal The first terminal of the ninth transistor 39 is electrically connected, and the gate electrode is connected to the fourth transistor It is electrically connected to the gate electrode of transistor 34. The third transistor 33 is connected to the first terminal The first input terminal 21 is electrically connected, and the second terminal is electrically connected to the first output terminal 26. The fourth transistor 34 has its first terminal electrically connected to the power line 53. The second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 is The first terminal is electrically connected to the power line 53, and the second terminal is connected to the gate of the second transistor 32. The electrode and the gate electrode of the fourth transistor 34 are electrically connected, and the gate electrode is the fourth It is electrically connected to input terminal 24. The sixth transistor 36 has its first terminal connected to the power line. Electrically connected to 52, the second terminal is the gate electrode of the second transistor 32 and the fourth terminal Electrically connected to the gate electrode of the transistor 34, the gate electrode (the lower gate electrode and the upper The gate electrode of the transistor is electrically connected to the fifth input terminal 25. 37 has its first terminal electrically connected to the power line 52, and its second terminal connected to the eighth transistor 38. It is electrically connected to the second terminal, and the gate electrodes (lower gate electrode and upper gate electrode) The third input terminal 23 is electrically connected to the eighth transistor 38, the first terminal The gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34 are electrically charged. They are connected to the second input terminal, with the gate electrodes (lower gate electrode and upper gate electrode) connected to the second input terminal. It is electrically connected to 22. The ninth transistor 39 has its first terminal connected to the first transistor It is electrically connected to the second terminal of the sta 31 and the second terminal of the second transistor 32, and the second terminal The child is connected to the gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40. Electrically connected, the gate electrodes (lower gate electrode and upper gate electrode) are connected to power line 52 It is electrically connected to the first input terminal 2. The tenth transistor 40 has its first terminal connected to the first input terminal 2. It is electrically connected to terminal 1, and the second terminal is electrically connected to the second output terminal 27, and the gate electrode is electrically connected to terminal 1. This is electrically connected to the second terminal of the ninth transistor 39. The eleventh transistor 41 has its first terminal electrically connected to the power line 53, and its second terminal electrically connected to the second output terminal 27. Connected electrically, the gate electrode of the second transistor 32 and the fourth transistor It is electrically connected to the gate electrode of transistor 34. Transistor 42 is the 12th terminal The child is electrically connected to the power line 53, and the second terminal is electrically connected to the second output terminal 27. , the gate electrode is the gate electrode of the 7th transistor 37 (the lower gate electrode and the upper gate electrode It is electrically connected to the electrode. The 13th transistor 43 has its first terminal connected to the power line 5 It is electrically connected to 3, and the second terminal is electrically connected to the first output terminal 26, and the gate electrode is electrically connected to 3. The electrode of the seventh transistor 37 (the lower gate electrode and the upper gate electrode) is charged. They are connected by energy.

[0256] In Figure 16(D), the gate electrode of the third transistor 33 and the tenth transistor 4 The connection point between the gate electrode of transistor 0 and the second terminal of transistor 9 39 is defined as node A. Also, the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, and The second terminal of transistor 35 (number 5), the second terminal of transistor 36 (number 6), and the eighth transistor The connection point between the first terminal of transistor 38 and the gate electrode of transistor 41 (number 11) is at node B. Let's assume that.

[0257] Figure 17(A) shows the pulse output circuit described in Figure 16(D) as the first pulse output circuit 10_ When applied to 1, the first input terminals 21 to the fifth input terminals 25 and the first output terminal 26 The signals input to or output to the second output terminal 27 are shown.

[0258] Specifically, the first clock signal CK1 is input to the first input terminal 21, and the second input terminal The second clock signal CK2 is input to child 22, and the third clock signal is input to the third input terminal 23. When signal CK3 is input, a start pulse is input to the fourth input terminal 24, and the fifth input terminal The subsequent signal OUT(3) is input to terminal 25, and the first output signal OUT is output from the first output terminal 26. (1)(SR) is output, and the second output signal OUT(1) is output from the second output terminal 27. It will be done.

[0259] A thin-film transistor is defined as a transistor with at least three components, including a gate, a drain, and a source. It is an element having terminals. Furthermore, a channel region is formed in the region superimposed on the gate in a semiconductor. It has a body and controls the gate potential, allowing the drain and saw through the channel region. The current flowing between the source and drain can be controlled. Here, the source and drain are thin film transistors. It depends on the structure and operating conditions of the converter, so which is the source and which is the drain. It is difficult to limit the extent of this. Therefore, the regions that function as source and drain are defined as They are sometimes not called drains or suctions. In that case, for example, each is called the first It may be referred to as terminal or second terminal.

[0260] Note that in Figures 16(C) and 17(A), the boot process is performed by setting node A to a floating state. A capacitive element may be provided separately to perform the strapping action. Also, the potential of node B may be maintained. Therefore, a capacitive element with one electrode electrically connected to node B may be provided separately.

[0261] Here, the timing of a shift register equipped with multiple pulse output circuits as shown in Figure 17(A) The chart is shown in Figure 17(B). Note that if the shift register is a scan line drive circuit... In total, period 61 in Figure 17(B) is the vertical retrace period, and period 62 corresponds to the gate selection period. do.

[0262] Furthermore, as shown in Figure 17(A), the ninth gate to which the second power supply potential VCC is applied By installing the Rangista 39, the following occurs before and after the bootstrap operation: It has advantages like these.

[0263] If there is no 9th transistor 39 to which the second power supply potential VCC is applied to the gate electrode, then When the potential of node A rises due to the trapping action, the second of the first transistor 31 The potential of the source terminal rises and becomes greater than the first power supply potential VDD. Then, the source of the first transistor 31 switches to the first terminal side, that is, to the power line 51 side. Therefore, in the first transistor 31, between the gate and source, and between the gate and drain Both are subjected to significant stress due to the application of a large bias voltage, and the transistor This can be a factor in degradation. Therefore, the 9th gate electrode is subjected to a second power supply potential VCC. By providing transistor 39, the power of node A is supplied by the bootstrap operation. Although the position rises, the potential of the second terminal of the first transistor 31 does not rise. This can be done. In other words, by providing the ninth transistor 39, the first transistor The value of the negative bias voltage applied between the gate and source of the zistor 31 can be reduced. Yes, it is possible. Therefore, by using the circuit configuration of this embodiment, the first transistor 31 The negative bias voltage applied between the gate and source can also be reduced, thus reducing stress. This makes it possible to suppress the degradation of the first transistor 31.

[0264] Furthermore, the location where the ninth transistor 39 is installed is the second of the first transistor 31. The terminal is connected to the gate of the third transistor 33 via the first and second terminals. Any configuration that is set up in this manner is acceptable. Note that the system in this embodiment has multiple pulse output circuits. In the case of a soft register, in a signal line drive circuit with more stages than a scan line drive circuit, the 9th transistor The ZISTA39 can be omitted, which has the advantage of reducing the number of transistors.

[0265] Furthermore, the semiconductor layers of the first transistor 31 to the thirteenth transistor 43 are made of oxide semiconductor material. By using a conductor, the off-current of the thin-film transistor is reduced, and the on-current and field effect are also reduced. This allows for increased mobility and reduced degradation, within the circuit. This can reduce malfunctions. Also, transistors using oxide semiconductors are amorphous. Compared to transistors using silicon, a high potential is applied to the gate electrode. The degree of transistor degradation is small. Therefore, the power line that supplies the second power supply potential VCC The same operation can be obtained by supplying the first power supply potential VDD, and the power supply is routed between circuits. Because the number of wires can be reduced, the circuit can be made smaller.

[0266] Note that the gate electrodes of the seventh transistor 37 (the lower gate electrode and the upper gate electrode) The clock signal supplied by the third input terminal 23, and the gateway of the eighth transistor 38. The electrodes (lower gate electrode and upper gate electrode) are supplied by the second input terminal 22. The clock signal is transmitted to the gate electrode of the 7th transistor 37 (the lower gate electrode and the upper The clock signal supplied by the second input terminal 22 to the gate electrode of the eighth transistor The gate electrodes of terminal 38 (lower gate electrode and upper gate electrode) are connected to the third input terminal 23. The same effect can be achieved by reversing the wiring so that the clock signal is supplied by [the specified component]. In addition, in the shift register shown in Figure 17(A), the seventh transistor 37 and From a state where the 8th transistor 38 is both ON, the 7th transistor 37 turns OFF, and the 8th Transistor 38 is ON, then transistor 37 (number 7) is OFF, and the 8th transistor By turning off the st38, the second input terminal 22 and the third input terminal 23 The decrease in potential at node B, caused by a decrease in the potential of the seventh transistor 37, is due to the decrease in the potential of node B. This is due to a decrease in the potential of the electrode and the decrease in the potential of the gate electrode of transistor 38. This will occur twice. On the other hand, in the shift register shown in Figure 17(A), the seventh trough With transistors 37 and 8 and 38 both turned ON, the 7th transistor 3 7 is ON, the 8th transistor 38 is OFF, and then the 7th transistor 37 is OFF. By turning off the eighth transistor 38, the second input terminal 22 and The decrease in the potential of node B caused by a decrease in the potential of the third input terminal 23 is controlled by the eighth trap This can be reduced to a single instance by lowering the potential of the gate electrode of the converter 38. Therefore, The gate electrodes (lower gate electrode and upper gate electrode) of the 7th transistor 37 are connected to the 3rd A clock signal is supplied from the input terminal, and the gate electrode of the 8th transistor 38 (below) A clock signal is supplied from the second input terminal to the gate electrode and the upper gate electrode. In relation to this, noise can be reduced by minimizing the potential fluctuations at node B. Therefore, it is suitable.

[0267] In this way, the period during which the potential of the first output terminal 26 and the second output terminal 27 is maintained at the L level In between, a configuration is set in which a high-level signal is periodically supplied to node B, and the pulse output This can suppress malfunctions in the force circuit.

[0268] (Embodiment 9) Thin-film transistors are fabricated, and these thin-film transistors are used in the pixel section and further in the driving circuit. It is possible to fabricate semiconductor devices (also called display devices) that have display functions. The transistor is integrated into the drive circuit, either partially or entirely, on the same substrate as the pixel section, and the system On-panel formation is possible.

[0269] A display device includes display elements. Display elements include liquid crystal elements (also called liquid crystal display elements) and light-emitting elements. A light-emitting element (also called a light-emitting display element) can be used. The light-emitting element is activated by current or voltage. This category includes elements whose brightness is controlled, specifically inorganic EL (Electrical LEDs). This includes Luminescence, organic EL, etc. Also, electronic inks, etc. Display media in which contrast changes due to the effect can also be applied.

[0270] Furthermore, the display device includes a panel in which the display elements are sealed, and a controller on the panel. It includes a module on which ICs and the like are mounted. Furthermore, it is a device for manufacturing the display device. With respect to an element substrate that corresponds to one form before the display element is completed in the process, the element substrate is The element substrate is specifically provided with means for supplying current to the display element in each of the multiple pixels. This may be a state where only the pixel electrodes of the display element are formed, or a conductive film that will serve as the pixel electrode may be formed. This may be the state after the film has been formed but before etching to form the pixel electrodes. All forms apply.

[0271] In this specification, the term "display device" refers to an image display device, a display device, or an optical display device. This refers to the power source (including lighting equipment). It also refers to connectors, such as FPC (Flexible Printed Circuit). (inted circuit) or TAB (Tape Automated Bon (ding) tape or TCP (Tape Carrier Package) Modules that have a printed circuit board attached to the end of the TAB tape or TCP. The display element or IC (integrated circuit board) is integrated using the COG (Chip On Glass) method. All modules in which the road is directly implemented are also included in the display device.

[0272] Figure 10 shows the external appearance and cross-section of a liquid crystal display panel, which is a form of semiconductor device. Let me explain. Figures 10(A1)(A2) show thin-film transistors 4010 and 4011, and liquid crystal. Element 4013 is placed between the first substrate 4001 and the second substrate 4006 in the sealing material 4005. Therefore, Figure 10(B) is a plan view of the sealed panel, and Figure 10(A1)(A2) is M - This corresponds to a cross-sectional view in N.

[0273] The pixel section 4002 and the scanning line driving circuit 4004 are surrounded on the first substrate 4001. A sealing material 4005 is provided in this manner. Also, the pixel section 4002 and the scan line drive rotation A second substrate 4006 is provided on the path 4004. Therefore, the pixel section 4002 and the scanning The line drive circuit 4004 consists of the first substrate 4001, the sealing material 4005, and the second substrate 4006. It is sealed together with the liquid crystal layer 4008. Also, the seal on the first substrate 4001 A single crystal is placed on a separately prepared substrate in a region different from the area enclosed by material 4005. A signal line driving circuit 4003, formed from a semiconductor film or a polycrystalline semiconductor film, is mounted.

[0274] Furthermore, the method of connecting the separately formed drive circuit is not particularly limited, and COG method, Wire bonding methods or TAB methods can be used. Figure 10(A1) This is an example of implementing the signal line drive circuit 4003 using the COG method, and Figure 10(A2) shows, This is an example of implementing the signal line drive circuit 4003 using the TAB method.

[0275] Furthermore, the pixel section 4002 and the scanning line driving circuit 4004 provided on the first substrate 4001 are, It has multiple thin-film transistors, and in Figure 10(B), the thin film included in the pixel section 4002 Transistor 4010 and thin-film transistor 4011 included in scan line drive circuit 4004 The following is an example. On thin-film transistors 4010 and 4011 are insulating layers 4041a and 40 41b, 4042a, 4042b, 4020, and 4021 are provided.

[0276] Thin-film transistors 4010 and 4011 are oxide semiconductors as shown in Embodiments 1, 2, 5, and 6. A highly reliable thin-film transistor including a body layer can be applied. Thin-film transistor for drive circuits. The transistor 4011 is the thin-film transistor 26 shown in Embodiments 1, 2, 5, and 6. For pixels 0, 245, 270, thin-film transistor 4010 is thin-film transistor 4 20, 448, 220, 280, and 290 can be used. In this embodiment, Thin-film transistors 4010 and 4011 are n-channel thin-film transistors.

[0277] On the insulating layer 4021, the oxide semiconductor layer of the thin-film transistor 4011 for the drive circuit A conductive layer 4040 is provided in a position that overlaps with the channel formation region. The conductive layer 4040 is acid By placing it in a position that overlaps with the channel formation region of the synthetic semiconductor layer, before and after BT testing... This can reduce the change in the threshold voltage of the thin-film transistor 4011. The conductive layer 4040 may have the same potential as the gate electrode layer of the thin-film transistor 4011. They can be different, and can also function as a second gate electrode layer. Also, the conductive layer The potential of 4040 may be GND, 0V, or floating.

[0278] Furthermore, the pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin-film transistor 4010. They are electrically connected. And the counter electrode layer 4031 of the liquid crystal element 4013 is on the second substrate 40 Formed on 06. Pixel electrode layer 4030, counter electrode layer 4031, and liquid crystal layer 4008 The overlapping portion corresponds to the liquid crystal element 4013. Note that the pixel electrode layer 4030 and the opposite The electrode layer 4031 is provided with insulating layers 4032 and 4033, which function as alignment films. The liquid crystal layer 4008 is sandwiched between insulating layers 4032 and 4033.

[0279] Furthermore, translucent substrates can be used as the first substrate 4001 and the second substrate 4006. Glass, ceramics, and plastics can be used. As for plastics... , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film or acrylic resin film Room can be used.

[0280] Furthermore, 4035 is a columnar spacer obtained by selectively etching an insulating film. This controls the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. It is provided for this purpose. A spherical spacer may also be used. Furthermore, the counter electrode layer 4031 is electrically connected to a common potential line provided on the same substrate as thin-film transistor 4010. They are connected. Using a common connection, conductive particles are placed between the pair of substrates, and opposing electric currents are connected. The polar layer 4031 and the common potential line can be electrically connected. Note that the conductive particles are sieve It is to be included in material 4005.

[0281] Alternatively, a liquid crystal exhibiting a blue phase without an alignment layer may be used. The blue phase is one of the liquid crystal phases. Yes, as the temperature of a cholesteric liquid crystal is increased, it transitions from the cholesteric phase to the isotropic phase. This is the phase that appears earlier. The blue phase appears in a relatively narrow temperature range, so improving the temperature range... To achieve this, a liquid crystal composition containing 5% or more by weight of a chiral agent is used in the liquid crystal layer 4008. The liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 1 msec. It is short, optically isotropic, and therefore requires no orientation processing, and has low dependence on viewing angle.

[0282] In addition to transmissive liquid crystal displays, this method can also be applied to semi-transmissive liquid crystal displays.

[0283] Furthermore, in liquid crystal display devices, a polarizing plate is provided on the outside (viewing side) of the substrate, and a colored layer and display element are provided on the inside. The example shows the electrode layers being arranged in the order of the child, but the polarizing plate may be placed on the inside of the substrate. Furthermore, the laminated structure of the polarizing plate and the colored layer is not limited to this embodiment, and the materials of the polarizing plate and the colored layer may also vary. The settings should be adjusted as appropriate depending on the manufacturing process conditions. In addition, a black matrix can be used in addition to the display area. A light-shielding film that functions in this way may be provided.

[0284] Thin-film transistor 4011 has an insulating layer 4041a that functions as a channel protection layer, and an oxide layer An insulating layer 4041b is formed that covers the peripheral edge (including the side surface) of the stacked semiconductor layers. Similarly, the thin-film transistor 4010 has an insulating layer 4042a that functions as a channel protection layer and An insulating layer 4042b is formed that covers the peripheral edge (including the side surface) of the stacked oxide semiconductor layer. Yes, they are.

[0285] Insulating layer 4041 is an oxide insulating layer that covers the peripheral (including the sides) of the stacked oxide semiconductor layers. b, 4042b is a gate electrode layer and a wiring layer (source wiring) formed above or around it. By increasing the distance from the wire layer and capacitive wiring layer, parasitic capacitance can be reduced. Layers 4041a, 4041b, 4042a, and 4042b are oxide insulating layers as shown in Embodiment 1. Layers 426a and 426b can be formed using the same materials and methods. To reduce surface irregularities, the structure is configured to cover the surface with an insulating layer 4021 that functions as a planarizing insulating film. Here, the insulating layers 4041a, 4041b, 4042a, and 4042b are used. A silicon oxide film is formed by sputtering using the application method 1.

[0286] Furthermore, insulating layer 4020 is formed on insulating layers 4041a, 4041b, 4042a, and 4042b. The insulating layer 4020 is made of the same material as the protective insulating layer 403 shown in Embodiment 1. It can be formed by the following method. Here, the insulating layer 4020 is nitrided by the RF sputtering method. It forms a silicon film.

[0287] Furthermore, an insulating layer 4021 is formed as a planarizing insulating film. It can be formed using the same materials and methods as the planarized insulating layer 404 shown in Embodiment 1, i.e., polyimide. Heat-resistant resins such as acrylic resins, benzocyclobutene resins, polyamides, and epoxy resins. Organic materials having properties can be used. In addition to the above organic materials, low dielectric constant materials (l (ow-k material), siloxane resin, PSG (phosphorus glass), BPSG (phosphorus boron glass) Materials such as (S) can be used. Furthermore, multiple insulating films formed from these materials can be stacked. This may result in the formation of an insulating layer 4021.

[0288] In this embodiment, multiple thin-film transistors in the pixel section are collectively surrounded by a nitride insulating film. Alternatively, a nitride insulating film can be used for the insulating layer 4020 and the gate insulating layer, as shown in Figure 10. The insulating layer 4020 surrounds at least the periphery of the pixel portion of the active matrix substrate. A configuration is provided in which the gate insulating layer and the outer layer are in contact. In this manufacturing process, the outer It can prevent moisture from entering. Also, semiconductor devices, such as display devices, Even after the construction is complete, it can prevent external moisture from entering for a long period of time, ensuring long-term reliability of the device. It can improve reliability.

[0289] Siloxane-based resins are formed using siloxane-based materials as the starting material for Si-OS. This corresponds to a resin containing i-bonds. Siloxane resins use organic groups (e.g., alkyl groups) as substituents. You may also use aryl groups or fluoro groups. Furthermore, organic groups may have fluoro groups. You can.

[0290] The method for forming the insulating layer 4021 is not particularly limited and can be sputtered or SOG depending on the material. Spin coating, dip coating, spray coating, droplet ejection (inkjet method, screen coating) Printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife A f-coater or the like can be used. The firing process of the insulating layer 4021 and the annealing of the semiconductor layer are performed. By combining these processes, it becomes possible to efficiently manufacture semiconductor devices.

[0291] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Titanium oxide-containing indium tin oxide, indium tin oxide (hereinafter referred to as ITO), Translucent conductive materials such as indium zinc oxide and indium tin oxide with added silicon dioxide. Materials can be used.

[0292] Furthermore, conductive polymers are used as the pixel electrode layer 4030 and the counter electrode layer 4031. It can be formed using a conductive composition containing (also known as). The resulting pixel electrodes have a sheet resistance of 10,000 Ω / □ or less and a light transmittance at a wavelength of 550 nm. It is preferable that the ratio is 70% or more. Also, the resistance of the conductive polymer contained in the conductive composition The ratio is preferably 0.1 Ω·cm or less.

[0293] As the conductive polymer, so-called π-electron conjugated conductive polymers can be used. For example For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene Examples include derivatives thereof, or copolymers of two or more of these.

[0294] Furthermore, a separately formed signal line drive circuit 4003 and a scan line drive circuit 4004 or pixel unit 4 The various signals and potentials supplied to 002 are provided by the FPC4018.

[0295] Is the connection terminal electrode 4015 made of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013? The terminal electrode 4016 is formed from the source electrode layer of the thin-film transistors 4010 and 4011. It is formed of the same conductive film as the drain electrode layer.

[0296] The connecting terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. They are electrically connected.

[0297] Furthermore, in Figure 10, a signal line drive circuit 4003 is formed separately and implemented on the first substrate 4001. The example shown illustrates this configuration, but it is not limited to this setup. A separate scan line drive circuit can be formed to implement it. Alternatively, you may install it, or separately form only a part of the signal line drive circuit or a part of the scan line drive circuit. It's okay to implement it.

[0298] Figure 19 shows a semiconductor device using a TFT substrate fabricated by the manufacturing method disclosed herein. This shows an example of how a liquid crystal display module is configured.

[0299] Figure 19 shows an example of a liquid crystal display module, where substrate 2600 and opposing substrate 2601 are sealed together. 2602 is used to fix the pixel portion 2603, which includes a TFT, etc., and the display element including the liquid crystal layer, between them. Child 2604 and colored layer 2605 are provided to form a display area. Colored layer 2605 is - This is necessary for display, and in the case of the RGB method, it corresponds to coloring for red, green, and blue. A layer is provided corresponding to each pixel. Polarizing light is present on the outside of substrate 2600 and opposing substrate 2601. A plate 2606, a polarizing plate 2607, and a diffuser plate 2613 are installed. The light source is a cold cathode tube 261. The circuit board 2612 consists of a 0 and a reflector 2611, and the flexible wiring board 260 9 connects to the wiring circuit section 2608 of the circuit board 2600, and controls the power supply circuit, etc. Which external circuits are incorporated? Also, is there a phase difference plate between the polarizing plate and the liquid crystal layer? They may be stacked.

[0300] The LCD display module has TN (Twisted Nematic) mode and IPS (I n-Plane-Switching) mode, FFS (Fringe Field Switching) (witching) mode, MVA (Multi-domain Vertical A) alignment) mode, PVA(Patterned Vertical Alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optical Compensated B) irefringence) mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq. You can use modes such as UID Crystal.

[0301] Through the above process, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device. ru.

[0302] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0303] (Embodiment 10) An example of electronic paper as a form of semiconductor device is shown.

[0304] Electronic paper is also called an electrophoretic display device (electrophoretic display), and is the same as paper. Advantages include readability, lower power consumption compared to other display devices, and the ability to create a thin and light form factor. It has a point.

[0305] Electrophoretic displays can take various forms, but one involves a first particle with a positive charge. A microcapsule containing a child and a second particle having a negative charge is placed in a solvent or solute. It is a dispersed substance, and by applying an electric field to the microcapsules, micro Move the particles inside the capsule in opposite directions and display only the color of the particles that have gathered on one side. It is such that the first or second particle contains dye and, in the absence of an electric field, It does not move. Also, the color of the first particle and the color of the second particle are different (colorless). (Includes)

[0306] Thus, in electrophoretic displays, substances with high dielectric constants move to regions with high electric fields. This is a display that utilizes the so-called dielectrophoretic effect.

[0307] When the above microcapsules are dispersed in a solvent, it is called an electronic ink. This electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. Color display is also possible by using color filters or particles containing pigments.

[0308] Furthermore, the microphone is placed on the active matrix substrate, appropriately sandwiched between the two electrodes. By arranging multiple microcapsules, an active-matrix type display device can be completed. By applying an electric field to the cell, a display can be created. For example, in Embodiments 1, 2, 5, and 6 An active matrix substrate obtained by thin-film transistors can be used.

[0309] Furthermore, the first and second particles in the microcapsules are made of conductive material, insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, electro A type of material selected from trochromic materials, magnetophoretic materials, or a composite material thereof Use it.

[0310] Figure 18 shows an active-matrix electronic paper as an example of a semiconductor device. The thin-film transistor 581 used in the device is the thin-film transistor shown in Embodiment 1. It can be fabricated in the same way as a transistor and is a highly reliable thin-film transistor containing an oxide semiconductor layer. The thin-film transistors shown in embodiments 2, 5, and 6 are also the thin-film transistors 581 of this embodiment. It can also be applied in this way.

[0311] Figure 18 shows an example of an electronic paper display using a twist ball display method. The Toball display method is an electrode layer that uses spherical particles painted in white and black as display elements. It is placed between the first electrode layer and the second electrode layer, and a potential difference is applied between the first electrode layer and the second electrode layer. This method of display is achieved by controlling the orientation of spherical particles by generating a phenomenon.

[0312] The thin-film transistor 581 formed on the substrate 580 is a thin-film transistor with a bottom gate structure. It is covered by an insulating film 583 that is in contact with the semiconductor layer. - An electrode layer or drain electrode layer is formed on the first electrode layer 587 and the insulating layer 585. They are in contact at an opening and are electrically connected. The first electrode layer 587 and the substrate 596 are formed on it. Between the second electrode layer 588 and the first electrode layer, there is a black region 590a and a white region 590b, and around it A spherical particle 589 is provided, which contains a cavity 594 filled with liquid. The area around the sub 589 is filled with a filler material 595 such as resin. The first electrode layer 587 is a pixel electrode The second electrode layer 588 corresponds to the common electrode, and the second electrode layer 588 corresponds to the common electrode. The second electrode layer 588 is a thin film It is electrically connected to a common potential line located on the same circuit board as the transistor 581. Common connection Using this part, conductive particles placed between the pair of substrates are used to connect to the second electrode layer 588 and the common electrode layer 588. It can be electrically connected to the current line.

[0313] Furthermore, instead of using twisted ball elements, electrophoretic elements can also be used. A transparent liquid containing positively charged white particles and negatively charged black particles, with a diameter of 1 Microcapsules of approximately 0 μm to 200 μm are used. Between the first electrode layer and the second electrode layer The microcapsules placed in between are subjected to an electric field by the first electrode layer and the second electrode layer. When this happens, the white and black particles move in opposite directions, resulting in either white or black being displayed. Yes, it is possible. An electrophoretic display element, commonly known as electronic paper, utilizes this principle. It is called that. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary It does not require a light, consumes little power, and the display can be seen even in dimly lit places. Furthermore, even if power is not supplied to the display unit, it retains the image that has been displayed. Because it is possible to transmit radio waves from a semiconductor device with a display function (simply a display device, or a display) Even when the semiconductor device (also known as a display device) is moved away, the displayed image is saved. It becomes possible to do so.

[0314] Through the above process, highly reliable electronic paper can be manufactured as a semiconductor device. .

[0315] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0316] (Embodiment 11) An example of a light-emitting display device is shown as a semiconductor device. The display elements of the display device are as follows: This is demonstrated using a light-emitting element that utilizes electroluminescence. Light-emitting devices that utilize luminescence depend on whether the light-emitting material is an organic compound or an inorganic compound. They are distinguished and generally referred to as organic EL elements and inorganic EL elements.

[0317] Organic EL elements emit electrons and holes from a pair of electrodes when a voltage is applied to the light-emitting element. Each of these is injected into a layer containing a luminescent organic compound, and an electric current flows through it. Then, these... The recombination of electrons and holes causes the luminescent organic compound to form an excited state. And when that excited state returns to the ground state, it emits light. From this mechanism, Such light-emitting devices are called current-excited light-emitting devices.

[0318] Inorganic electroluminescent (EL) elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements based on their element configuration. They are classified as such. Dispersive inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. The luminescence mechanism utilizes donor and acceptor levels, and the donor-acceptor level is the key to this process. This is a receptor recombination type light emission. Thin-film inorganic EL elements sandwich the light-emitting layer between dielectric layers. Furthermore, it has a structure where it is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. This is a localized light emission. Here, we will explain using an organic EL element as the light-emitting element. ru.

[0319] Figure 12 shows an example of a pixel configuration to which digital time-gradation driving can be applied as an example of a semiconductor device. This is a diagram.

[0320] This section describes the pixel configuration and operation to which digital time-based gradation driving can be applied. This uses an n-channel transistor with an oxide semiconductor layer as the channel formation region as one pixel. Here are two examples of its use.

[0321] Pixel 6400 consists of a switching transistor 6401, a driving transistor 6402, It has a light-emitting element 6404 and a capacitive element 6403. Switching transistor 64 01 has a gate connected to scan line 6406, and the first electrode (source electrode and drain electrode) The (side) is connected to signal line 6405, and the second electrode (the other of the source electrode and drain electrode) is driven It is connected to the gate of the drive transistor 6402. The drive transistor 6402 is The gate is connected to the power line 6407 via the capacitive element 6403, and the first electrode is connected to the power line 640 It is connected to 7, and the second electrode is connected to the first electrode (pixel electrode) of the light-emitting element 6404. The second electrode of the light-emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is identical It is electrically connected to a common potential line formed on the substrate. Note that the drive transistor 640 2 is a transistor for driving the light-emitting element 6404.

[0322] Furthermore, a low power supply potential is set for the second electrode (common electrode 6408) of the light-emitting element 6404. The low power supply potential is defined as the low power supply potential set on power line 6407 relative to the high power supply potential. The potential is the potential that satisfies the high power supply potential, and low power supply potentials include, for example, GND and 0V. It may be fixed. The potential difference between this high power supply potential and the low power supply potential is applied to the light-emitting element 6404. Then, in order to pass current through the light-emitting element 6404 and make the light-emitting element 6404 emit light, a high power supply potential is used. The potential difference between the low power supply potential and the light-emitting element 6404 is set to be greater than or equal to the forward threshold voltage of the light-emitting element 6404. Set the potential for each.

[0323] Note that the capacitive element 6403 is omitted by substituting the gate capacitance of the drive transistor 6402. This is also possible. Regarding the gate capacitance of the drive transistor 6402, the channel region A capacitance may be formed between the gate electrode and the gate electrode.

[0324] In the case of a voltage input / voltage drive method, the gate of the drive transistor 6402 is: The drive transistor 6402 is either fully on or completely off. The video signal is input. In other words, the driver transistor 6402 is operated in the linear region. The driver transistor 6402 operates in the linear region, therefore the voltage of the power line 6407 is higher than A high voltage is applied to the gate of the drive transistor 6402. The signal line 6405 is connected to... Apply a voltage equal to or greater than (power line voltage + Vth of the drive transistor 6402).

[0325] Furthermore, when using analog gradation drive instead of digital time gradation drive, the signal input is different. By doing so, the same pixel configuration as in Figure 12 can be used.

[0326] When performing analog grayscale driving, the gate of the driving transistor 6402 is connected to the light-emitting element 6404 Apply a voltage equal to or greater than the forward voltage of the drive transistor 6402 + Vth. (Light-emitting element 64) The forward voltage of 04 refers to the voltage required to achieve the desired brightness, and at least the forward voltage is Includes key voltage. Note that the drive transistor 6402 operates in the saturation region. By inputting an O signal, current can be supplied to the light-emitting element 6404. The drive transistor... To operate the 6402 in the saturation region, the potential of the power line 6407 is set to the drive transistor The gate potential of the TA6402 is set higher. By making the video signal analog, the light-emitting element... By supplying current to the 6404 according to the video signal, analog grayscale driving can be performed.

[0327] Note that the pixel configuration shown in Figure 12 is not limited to this. For example, if new pixels are added to the pixels shown in Figure 12... Switches, resistors, capacitives, transistors, or logic circuits may be added to it.

[0328] Next, the configuration of the light-emitting element will be explained using Figure 13. Here, the driving TFT is n Let's take the case of a type as an example to explain the cross-sectional structure of a pixel. Figure 13(A)(B)(C) The driving TFTs 7001 and 7011 are TFTs used to drive light-emitting elements in semiconductor devices. 7021 can be fabricated in the same manner as the thin-film transistor shown in Embodiment 1, and the oxide semiconductor layer is It is a highly reliable thin-film transistor. Also, the thin-film transistors shown in Embodiments 2, 5, and 6 The inverter can also be used as the drive TFT7001, 7011, and 7021.

[0329] A light-emitting element only needs to have at least one of its electrodes, either the anode or the cathode, transparent in order to extract light. Then, a thin-film transistor and a light-emitting element are formed on the substrate, and light is emitted from the side opposite to the substrate. This includes top-side emission, bottom-side emission which extracts light from the substrate side, and on the substrate side and the opposite side of the substrate. There is a light-emitting element with a double-sided emission structure that extracts light from the side surface, and the pixel configuration is which emission structure It can also be applied to optical elements.

[0330] The light-emitting element with an upper surface injection structure will be explained using Figure 13(A).

[0331] Figure 13(A) shows that the driving TFT 7001 is n-type, and the light emitted from the light-emitting element 7002 is Figure 13(A) shows a cross-sectional view of the pixel when the light passes through to the anode 7005 side. The cathode 7003 and the driver TFT 7001 of 02 are electrically connected, and on the cathode 7003 The light-emitting layer 7004 and the anode 7005 are stacked in order. The cathode 7003 is an insulating film 7006. and a conductive film formed on insulating film 7007, having a small work function and reflecting light. Various materials can be used. For example, Ca, Al, MgAg, AlLi, etc. are desirable. And even if the light-emitting layer 7004 is composed of a single layer, multiple layers are stacked. Either configuration is fine. If it consists of multiple layers, cathode 7003 The layers are stacked in the following order: electron injection layer, electron transport layer, light emission layer, hole transport layer, and hole injection layer. It is not necessary to provide all of these layers. The anode 7005 is a conductive material that is translucent and allows light to pass through. Formed using a material such as indium oxide containing tungsten oxide, tungsten oxide Indium zinc oxide containing tene, indium oxide containing titanium oxide, and titanium oxide containing Indium tin oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc Using a transparent conductive film such as indium tin oxide with added oxides and silicon dioxide That's good too.

[0332] Furthermore, between cathode 7003 and the cathode 7008 of the adjacent pixel, partitions cover each end. A 7009 partition wall is provided. The partition wall 7009 is made of polyimide, acrylic resin, polyamide, epoxy It is formed using an organic resin film such as a siloxane, an inorganic insulating film, or polysiloxane. Partition 70 09 is formed using a particularly photosensitive resin material, with the sides of the partition wall 7009 having a continuous curvature. It is preferable to form it so that it becomes an inclined surface. A photosensitive resin material is used as the partition wall 7009. When using this material, the step of forming a resist mask can be omitted.

[0333] The region between the cathode 7003 and the anode 7005, which sandwiches the light-emitting layer 7004, is the light-emitting element 7002. It corresponds to the pixel shown in Figure 13(A), where the light emitted from the light-emitting element 7002 is the arrow. As indicated by the mark, inject towards the anode 7005 side.

[0334] Next, the light-emitting element with a bottom-extrusion structure will be explained using Figure 13(B). Driving TFT7 When 011 is n-type and the light emitted from the light-emitting element 7012 is directed toward the cathode 7013 side, Figure 13(B) shows a cross-sectional view of a pixel. In Figure 13(B), the driving TFT7011 is electrically connected to the pixel. The cathode 7013 of the light-emitting element 7012 is deposited on a light-transmitting conductive film 7017. The light-emitting layer 7014 and the anode 7015 are stacked in order on the cathode 7013. If 015 is translucent, a shielding material to reflect or block light should be used to cover the anode. A film 7016 may be formed. The cathode 7013 is as in the case of Figure 13(A). Various materials can be used if the conductivity function is small. However, the film thickness is The film should transmit light to a certain extent (preferably around 5 nm to 30 nm). For example, a 20 nm film. A thick aluminum film can be used as the cathode 7013. And the light-emitting layer 7 014, as in Figure 13(A), consists of a single layer, but multiple layers are stacked on top of each other. Either configuration is acceptable. The anode 7015 does not need to transmit light, but as shown in the diagram... Similar to 13(A), it can be formed using a light-transmitting conductive material. The shielding film 7016 can be made of, for example, a light-reflecting metal, but is not limited to a metal film. It's not possible. For example, a resin with black pigment added can be used.

[0335] Furthermore, between the conductive film 7017 and the conductive film 7018 of the adjacent pixel, the respective edges are covered. A partition wall 7019 is provided. The partition wall 7019 is made of polyimide, acrylic resin, polyamide, etc. It is formed using an organic resin film such as a phenyl resin, an inorganic insulating film, or polysiloxane. 7019 uses a photosensitive resin material in particular, and the sides of the partition wall 7019 have a continuous curvature. It is preferable to form it so that it becomes an inclined surface. Photosensitive resin is used as the partition wall 7019. When using lipid materials, the step of forming a resist mask can be omitted.

[0336] The region between the cathode 7013 and anode 7015, sandwiching the light-emitting layer 7014, is the light-emitting element 7012. This corresponds to the pixel shown in Figure 13(B), where the light emitted from the light-emitting element 7012 is As indicated by the arrow, the material is injected towards the cathode 7013.

[0337] Next, a light-emitting element with a double-sided injection structure will be explained using Figure 13(C). Figure 13(C) Then, on the light-transmitting conductive film 7027 electrically connected to the driving TFT 7021, A cathode 7023 of the light-emitting element 7022 is formed, and a light-emitting layer 7024 is placed on the cathode 7023. The anodes 7025 are stacked in order. The cathode 7023 is the same as in Figure 13(A). Various materials can be used if the conductivity function is small. However, the film thickness is ...to the extent that it transmits light. For example, Al with a film thickness of 20 nm is used as cathode 7023. It can be used. The light-emitting layer 7024 is composed of a single layer, as in Figure 13(A). It is acceptable whether it is configured as a single layer or as multiple layers stacked on top of each other. Anode 70 25 is formed using a light-transmitting conductive material, similar to Figure 13(A). It is possible.

[0338] Furthermore, between the conductive film 7027 and the conductive film 7028 of the adjacent pixel, the respective edges are covered. A partition wall 7029 is provided. The partition wall 7029 is made of polyimide, acrylic resin, polyamide, etc. It is formed using an organic resin film such as a phenyl resin, an inorganic insulating film, or polysiloxane. 7029 uses a photosensitive resin material in particular, and the side surface of partition wall 7029 has a continuous curvature. It is preferable to form it so that it becomes an inclined surface. A photosensitive resin is used as the partition wall 7029. When using lipid materials, the step of forming a resist mask can be omitted.

[0339] The portion where the cathode 7023, the light-emitting layer 7024, and the anode 7025 overlap is the light-emitting element 70 This corresponds to 22. In the case of the pixel shown in Figure 13(C), the light emitted from the light-emitting element 7022 As indicated by the arrows, the material is injected into both the anode 7025 side and the cathode 7023 side.

[0340] Here, we have discussed organic EL elements as light-emitting elements, but inorganic EL elements can also be used as light-emitting elements. It is also possible to incorporate an L element.

[0341] Furthermore, a thin-film transistor (TFT for driving light-emitting elements) and a light-emitting element are used to control the driving of the light-emitting element. An example of an electrically connected TFT is shown, but a current control TFT is connected between the driving TFT and the light-emitting element. It is also acceptable to have a configuration where FT is connected.

[0342] The semiconductor device is not limited to the configuration shown in Figure 13, but is disclosed herein. Various modifications are possible based on the technical concept.

[0343] Next, the appearance of a light-emitting display panel (also called a light-emitting panel), which corresponds to a form of semiconductor device, and The cross-section will be explained using Figure 11. Figure 11 shows a thin film trace formed on the first substrate. The luminescent element and the luminescent element are sealed between the luminescent element and the second substrate with a sealing material, forming a flat panel. This is a diagram, and Figure 11(B) corresponds to the cross-sectional view of HI in Figure 11(A).

[0344] Pixel section 4502, signal line driving circuit 4503a, 450 provided on the first substrate 4501 3b, and the scan line drive circuits 4504a and 4504b are surrounded by a sealing material 4505 A pixel unit 4502, signal line driving circuits 4503a, 4503b, and A second substrate 4506 is provided on top of the scan line driving circuits 4504a and 4504b. The pixel section 4502, signal line driving circuits 4503a, 4503b, and scan line driving circuit 45 04a and 4504b consist of a first substrate 4501, a sealing material 4505, and a second substrate 4506. It is sealed together with the filler 4507. Highly dense protective film with minimal degassing (laminated film, UV-curing resin film) It is preferable to package (seal) the product with a cover material such as a linoleum.

[0345] Also provided on the first substrate 4501 are the pixel section 4502, the signal line driving circuit 4503a, 4 503b, and the scan line driving circuits 4504a and 4504b have multiple thin-film transistors. In Figure 11(B), the thin-film transistor 4510 included in the pixel section 4502 and the signal The thin-film transistor 4509 included in the wire drive circuit 4503a is shown as an example.

[0346] Thin-film transistors 4509 and 4510 are oxide semiconductors as shown in Embodiments 1, 2, 5, and 6. A highly reliable thin-film transistor including a body layer can be applied. Thin-film transistor for drive circuits. As the transistor 4509, the thin-film transistor 26 shown in Embodiments 1, 2, 5, and 6 For pixels 0, 245, 270, thin-film transistor 4510 is used. 20, 448, 220, 280, and 290 can be used. In this embodiment, Thin-film transistors 4509 and 4510 are n-channel thin-film transistors.

[0347] On the insulating layer 4544, the oxide semiconductor layer of the thin-film transistor 4509 for the drive circuit A conductive layer 4540 is provided in a position that overlaps with the channel formation region. The conductive layer 4540 is oxidized. By placing it in a position that overlaps with the channel formation region of the semiconductor layer, before and after BT testing This can reduce the change in the threshold voltage of the thin-film transistor 4509. The potential of the electrode layer 4540 may be the same as that of the gate electrode layer of the thin-film transistor 4509, or it may be different. It may also function as a second gate electrode layer. The potential of 540 may be GND, 0V, or floating.

[0348] Thin-film transistor 4509 has an insulating layer 4541a that functions as a channel protection layer, and an oxide layer. An insulating layer 4541b is formed that covers the peripheral edge (including the side surface) of the stacked semiconductor layers. Similarly, the thin-film transistor 4510 has an insulating layer 4542a that functions as a channel protection layer and An insulating layer 4542b is formed that covers the peripheral edge (including the side surface) of the stacked oxide semiconductor layer. Yes, they are.

[0349] Insulating layer 4541 is an oxide insulating layer that covers the peripheral (including the sides) of the stacked oxide semiconductor layers. b, 4542b is a gate electrode layer and a wiring layer (source wiring) formed above or around it. By increasing the distance from the wire layer and capacitive wiring layer, parasitic capacitance can be reduced. Layers 4541a, 4541b, 4542a, and 4542b are oxide insulating layers as shown in Embodiment 1. Layers 426a and 426b can be formed using the same materials and methods. To reduce surface irregularities, the structure is configured to cover the surface with an insulating layer 4543 that functions as a planarizing insulating film. Here, the insulating layers 4541a, 4541b, 4542a, and 4542b are used. A silicon oxide film is formed by sputtering using the application method 1.

[0350] Furthermore, insulating layer 4543 is formed on insulating layers 4541a, 4541b, 4542a, and 4542b. It is done. The insulating layer 4543 is made of the same material as the protective insulating layer 403 shown in Embodiment 1. It can be formed by the following method. Here, the insulating layer 4543 is nitrided by the RF sputtering method. It forms a silicon film.

[0351] Furthermore, an insulating layer 4544 is formed as a planar insulating film. It can be formed using the same materials and methods as the planarized insulating layer 404 shown in Embodiment 1. Here, Acrylic is used as the insulating layer 4544.

[0352] In this embodiment, multiple thin-film transistors in the pixel section are collectively surrounded by a nitride insulating film. Alternatively, a nitride insulating film can be used for the insulating layer 4543 and the gate insulating layer, as shown in Figure 11. Insulating layer 4543 surrounds at least the periphery of the pixel portion of the active matrix substrate. A configuration is provided in which the gate insulating layer and the outer layer are in contact. In this manufacturing process, the outer It can prevent moisture from entering. Also, semiconductor devices, such as display devices, Even after the construction is complete, it can prevent external moisture from entering for a long period of time, ensuring long-term reliability of the device. It can improve reliability.

[0353] Furthermore, 4511 corresponds to a light-emitting element, and the first electrode is a pixel electrode of the light-emitting element 4511. Layer 4517 is electrically connected to the source electrode layer or drain electrode layer of the thin-film transistor 4510. It is connected to the following. The configuration of the light-emitting element 4511 is a first electrode layer 4517 and an electroluminescent layer The structure is a stacked structure of 4512 and a second electrode layer 4513, but is not limited to the configuration shown. The configuration of the light-emitting element 4511 is changed as appropriate to match the direction of the light extracted from the element 4511. It is possible.

[0354] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or polysiloxane. Using a photosensitive material, an opening is formed on the first electrode layer 4517, and the side walls of the opening are connected It is preferable to form the inclined surface with a continuous curvature.

[0355] Even if the electroluminescent layer 4512 consists of a single layer, it is configured to be stacked with multiple layers. It's fine either way.

[0356] To prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light-emitting element 4511, the second electrode layer A protective film may be formed on 4513 and the partition wall 4520. The protective film may be a silicon nitride film. It can form silicon nitride oxide films, DLC films, and the like.

[0357] Also, signal line drive circuits 4503a, 4503b and scan line drive circuits 4504a, 4504b The various signals and potentials applied to the pixel section 4502 are FPC4518a, 4518 It is supplied by b.

[0358] The connection terminal electrode 4515 has the same conductive film as the first electrode layer 4517 of the light-emitting element 4511. Formed from, the terminal electrode 4516 has the same sole as that of the thin-film transistors 4509 and 4510. The drain electrode layer and the drain electrode layer are formed from the same conductive film.

[0359] The connecting terminal electrode 4515 is connected to the terminal of FPC4518a via the anisotropic conductive film 4519. They are electrically connected.

[0360] The second substrate 4506, located in the direction of light extraction from the light-emitting element 4511, must be translucent. It must be a glass plate, plastic plate, polyester film or A light-transmitting material, such as acrylic film, is used.

[0361] Furthermore, in addition to inert gases such as nitrogen and argon, UV-curable resin can also be used as the filler 4507. Oils or thermosetting resins can be used, such as PVC (polyvinyl chloride) and acrylics. Resins, polyimides, epoxy resins, silicone resins, PVB (polyvinyl butyral), and EVA (ethylene vinyl acetate) can be used. For example, nitrogen can be used as a filler. You can use it.

[0362] Furthermore, if necessary, a polarizing plate or circular polarizing plate (including elliptical polarizing plate) may be placed on the emission surface of the light-emitting element. You may also appropriately incorporate optical films such as phase difference plates (λ / 4 plate, λ / 2 plate) and color filters. Furthermore, an anti-reflective coating may be provided on the polarizing plate or circular polarizing plate. For example, by the surface irregularities An anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0363] The signal line drive circuits 4503a and 4503b, and the scan line drive circuits 4504a and 4504b are Drive turns formed by a single-crystal semiconductor film or polycrystalline semiconductor film on a separately prepared substrate It may be implemented in the circuit. Also, only the signal line drive circuit, or part of it, or the scan line drive circuit The road may be formed separately or partially, and the configuration is not limited to that shown in Figure 11.

[0364] Through the above process, a highly reliable light-emitting display device (display panel) is manufactured as a semiconductor device. It is possible.

[0365] This embodiment can be appropriately combined with the configurations described in Embodiments 1 to 4 and 6 to 8. It is possible to implement it.

[0366] (Embodiment 12) The semiconductor device disclosed herein can be used as electronic paper. PA can be used in electronic devices in any field that displays information. For example, using e-paper, e-books, posters, and trains This can be applied to in-vehicle advertisements for goods, displays on various cards such as credit cards, etc. An example of an electronic device is shown in Figure 20.

[0367] Figure 20 shows an example of the e-book 2700. For example, the e-book 2700 has a housing 2 It consists of two enclosures, 701 and enclosure 2703. Enclosure 2701 and enclosure 27 03 is integrated with the shaft portion 2711, and the shaft portion 2711 is used as the axis for opening and closing operations. This configuration makes it possible to perform actions similar to those of a paper book. .

[0368] The display unit 2705 is incorporated into the housing 2701, and the display unit 2707 is incorporated into the housing 2703. It is included. Display units 2705 and 2707 are configured to display a continuation screen. Alternatively, a configuration that displays different screens is also acceptable. For example, text is displayed on the right-hand display unit (display unit 2705 in Figure 20), and the left-hand display unit An image can be displayed on the display unit 2707 in Figure 20.

[0369] Furthermore, Figure 20 shows an example in which the housing 2701 is equipped with an operating unit, etc. For example, housing 2 Unit 701 is equipped with a power supply 2721, operation keys 2723, speaker 2725, and the like. The page can be turned using operation key 2723. Note that the key is located on the same side as the display unit of the casing. It may also be configured to include a board or pointing device. Furthermore, the back of the enclosure or On the side, there are external connection terminals (earphone jack, USB terminal, or AC adapter and USB A configuration that includes terminals that can connect to various cables such as cables, a recording medium insertion section, and so on. It may also be done this way. Furthermore, the eBook 2700 is configured to have the functionality of an electronic dictionary. That's fine.

[0370] Furthermore, the e-book 2700 may be configured to transmit and receive information wirelessly. By wireless means, The system will be configured to allow users to purchase and download desired book data from an e-book server. It is also possible.

[0371] (Embodiment 13) The semiconductor devices disclosed herein are applicable to a variety of electronic devices (including amusement machines). This is possible. As an electronic device, for example, a television set (television, or television Receivers (also called receivers), computer monitors, digital cameras, digital video cameras Digital photo frame, mobile phone (also called mobile phone or mobile phone device), portable Examples include game consoles, personal digital assistants, audio playback devices, and large game machines such as pachinko machines. ru.

[0372] Figure 21(A) shows an example of a television system. The television system 9600 is, The display unit 9603 is integrated into the housing 9601. The display unit 9603 displays video. It is possible to do so. In addition, here the stand 9605 supports the housing 9601. This shows the configuration.

[0373] The television unit 9600 is operated using the control switches on the housing 9601 and a separate remote control. This can be done using the control unit 9610. The remote control unit 9610 has control keys The 9609 allows you to control the channel and volume, and the information is displayed on the display unit 9603. The video can be controlled. Furthermore, the remote control unit 9610 can be controlled by the remote control unit. A display unit 9607 may be provided to display the information output from 9610.

[0374] The television system 9600 will consist of a receiver, modem, and other components. It can receive more general television broadcasts, and furthermore, it can connect via a modem, either wired or wirelessly. By connecting to the communication network, one-way (sender to receiver) or two-way communication is possible. It is also possible to communicate information (between a sender and a receiver, or between receivers, etc.).

[0375] Figure 21(B) shows an example of a digital photo frame. For example, a digital photo Frame 9700 has a display unit 9703 integrated into the housing 9701. Display unit 970 3 is capable of displaying various images, such as images taken with a digital camera. By displaying data, it can function just like a regular picture frame.

[0376] The Digital Photo Frame 9700 includes an operating unit and external connection terminals (USB terminal, USB port). A structure that includes terminals that can connect to various cables such as B cables, a recording medium insertion section, etc. These components may be incorporated on the same surface as the display unit, but may also be on the sides or back. It is desirable to include it as it improves the design. For example, the recording medium of a digital photo frame. A memory device containing image data captured by a digital camera is inserted into the body insertion site. The system can capture data and display the captured image data on the display unit 9703.

[0377] Furthermore, the 9700 digital photo frame may be configured to transmit and receive information wirelessly. It is also possible to configure the system to acquire and display desired image data wirelessly.

[0378] Figure 22(A) shows a portable gaming machine, which consists of two cabinets, cabinet 9881 and cabinet 9891. It is connected by a connecting part 9893 so that it can be opened and closed. The housing 9881 has a display unit The 9882 is incorporated, and the display unit 9883 is incorporated into the housing 9891. The portable gaming machine shown in 22(A) also includes a speaker section 9884 and a recording medium insertion section 988 6. LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, Chemical substances, sound, time, hardness, electric field, electric current, voltage, power, radiation, flow rate, humidity, gradient, vibration Equipped with a function to measure motion, odor, or infrared radiation, a microphone (9889), etc. Of course, the configuration of portable gaming machines is not limited to those described above, and at least in this specification. Any configuration that includes the semiconductor device disclosed herein, and other auxiliary equipment as appropriate, is acceptable. This can be done. The portable gaming machine shown in Figure 22(A) has the data recorded on the recording medium. Functions for reading programs or data and displaying them on the display unit, and wireless communication with other portable gaming machines. It has the function of sharing information by doing so. The functions are not limited to these, and it can have a variety of functions.

[0379] Figure 22(B) shows an example of a slot machine, which is a large-scale gaming machine. Slot machine 9 The 900 has a display unit 9903 integrated into the casing 9901. Also, slot machine 9 The 900 also includes other features such as a start lever, stop switch, coin slot, It is equipped with speakers, etc. Of course, the configuration of the slot machine 9900 is not limited to those mentioned above. Not specified, and any configuration comprising at least the semiconductor device disclosed herein is sufficient, and other The configuration can include ancillary equipment as appropriate.

[0380] Figure 23(A) is a perspective view showing an example of a portable computer.

[0381] The portable computer in Figure 23(A) is constructed by connecting the upper casing 9301 and the lower casing 9302. The hinge unit is in the closed position, and the upper housing 9301 has a display unit 9303, and the keyboard The lower housing 9302, which has code 9304, can be stacked on top of each other, making it easy to carry. This is convenient, and when the user is typing on the keyboard, the hinge unit can be opened. Therefore, input operations can be performed by looking at the display unit 9303.

[0382] In addition, the lower casing 9302 houses the keyboard 9304 and a pointing device for input operations. It has a chair 9306. Also, if the display unit 9303 is a touch input panel, one of the display units Input operations can also be performed by touching the part. In addition, the lower chassis 9302 contains the CPU and hardware. It has a processing unit such as a disk. Furthermore, the lower enclosure 9302 can be used with other devices, for example, U It has an external connection port 9305 into which a communication cable compliant with SB's communication standards is plugged in. Yes, they are.

[0383] The upper housing 9301 also contains a display unit 93 which can be slid and stored inside the upper housing 9301. It has 07, which enables a large display screen. It also has a retractable display unit 93 The user can adjust the orientation of the 07 screen. Additionally, the retractable display unit 9307 can be used for touch input. If it's a panel, input operations can also be performed by touching a part of the retractable display.

[0384] The display unit 9303 or the retractable display unit 9307 is a liquid crystal display panel, an organic light-emitting element, or This uses an image display device such as an inorganic light-emitting element or other light-emitting display panel.

[0385] Furthermore, the portable computer shown in Figure 23(A) is configured to include a receiver and other components, and can also function as a television. The broadcast can be received and the image displayed on the display unit or on the display unit. Also, the upper housing 93 With the hinge unit connecting 01 and the lower housing 9302 in the closed position, the display unit 930 Slide the 7 to expose the entire screen, adjust the screen angle, and the user can watch television broadcasts. It is also possible to open the hinge unit and display the display unit 9303. Furthermore, because it only activates the circuit that displays the television broadcast, it consumes minimal power and This is useful in portable computers with limited battery capacity. ru.

[0386] Furthermore, Figure 23(B) shows a portable device that can be worn on the user's wrist like a wristwatch. This is a perspective illustrating one example of the story.

[0387] This mobile phone includes a communication device having at least telephone functionality and a main unit having a battery, Band portion 9204 for attaching to the body on the arm, adjustment for fixing the band portion to the arm It consists of a node 9205, a display unit 9201, a speaker 9207, and a microphone 9208. Yes, they are.

[0388] The main unit also has an operation switch 9203, a power input switch, and a display switching switch. In addition to the start-up switch for imaging, for example, pressing a button will launch an internet-enabled program. Each function can be associated with a specific event, such as when it is activated.

[0389] Input operations on this mobile phone are performed by touching the display unit 9201 with a finger or input pen, or by operating it. This is done by operating switch 9203 or by voice input to microphone 9208. In 23(B), the display button 9202 displayed on the display unit 9201 is shown, and a finger Input can be performed by touching the screen.

[0390] Furthermore, the main unit is an imaging device that converts the image of the subject formed through the imaging lens into an electronic image signal. It has a camera section 9206 with a step. However, the camera section is not required.

[0391] Furthermore, the mobile phone shown in Figure 23(B) is configured to include a television broadcast receiver, etc. It can receive TV broadcasts and display the images on the display unit 9201, and furthermore, it can store memory and other data. With a configuration that includes a storage device, television broadcasts can be recorded into memory. Also, Figure 23( The mobile phone shown in B) may have a function that can collect location information such as GPS.

[0392] The display unit 9201 is a light-emitting display panel such as a liquid crystal display panel, an organic light-emitting element, or an inorganic light-emitting element. A video display device such as a NEL is used. The mobile phone shown in Figure 23(B) is small and lightweight. Therefore, the battery capacity is limited, and the display device used in the display unit 9201 is low power consumption. It is preferable to use a panel that can be driven by force.

[0393] Note that Figure 23(B) illustrates an electronic device that is worn on the "arm," but it is not particularly limited to this. In short, it just needs to be something that can be carried around.

[0394] (Embodiment 14) In this embodiment, as one form of a semiconductor device, the thin film shown in Embodiments 1, 2, 5, and 6 is used. An example of a display device having a transistor will be described with reference to Figures 24 to 35. This embodiment is An example of a liquid crystal display device using liquid crystal elements as display elements will be explained with reference to Figures 24 to 35. The TFTs 628 and 629 used in the liquid crystal display devices shown in Figures 24 to 35 are, in this embodiment Thin-film transistors shown in 1, 2, 5, and 6 can be applied, and embodiments 1, 2, and 5 This is a thin-film transistor with electrical characteristics and high reliability that can be manufactured in the same way using the process shown in 6. The FT628 has a channel protection layer 608, and the TFT629 has a channel protection layer 611. It is an inverse staggered thin-film transistor in which the semiconductor layer film is used as the channel formation region.

[0395] First, we will explain VA (Vertical Alignment) type liquid crystal display devices. A VA-type liquid crystal display device is a type of method that controls the arrangement of liquid crystal molecules in a liquid crystal display panel. Yes, there is. VA-type liquid crystal display devices have a liquid crystal component on the panel surface when no voltage is applied. This is a method in which the child faces vertically. In this embodiment, in particular, several pixels are used. It is designed to divide the image into regions (subpixels) and tilt the molecules in a different direction for each region. This is called multi-domainization or multi-domain design. In the following explanation, multi-domain This section describes a liquid crystal display device that takes design considerations into account.

[0396] Figures 25 and 26 show the pixel electrode and counter electrode, respectively. Figure 25 shows the pixel This is a plan view of the substrate side on which the electrodes are formed, and the cross-sectional structure corresponding to the cutting line EF shown in the figure is This is shown in Figure 24. Figure 26 is a plan view of the substrate side where the counter electrodes are formed. The explanation will be explained using these diagrams.

[0397] Figure 24 shows the TFT 628, the pixel electrode layer 624 connected to it, and the holding capacitance section 630. The formed substrate 600 and the opposing substrate 601 on which the opposing electrode layer 640 etc. are formed are superimposed. This indicates that the liquid crystal has been injected.

[0398] The opposing substrate 601 has a colored film 636, an opposing electrode layer 640, and protrusions 64 on the opposing electrode layer 640. 4 is formed. An alignment film 648 is formed on the pixel electrode layer 624, and similarly the counter electrode An orientation film 646 is also formed on layer 640 and protrusion 644. Substrate 600 and opposing substrate 6 A liquid crystal layer 650 is formed between 01.

[0399] On the substrate 600 are a TFT 628, a pixel electrode layer 624 connected to it, and a holding capacitance section 6 30 is formed. The pixel electrode layer 624 consists of a TFT 628, wiring 616, and a holding capacitance portion 6 Contacts that penetrate the insulating film 620 covering 30 and the insulating film 622 covering the insulating film 620, respectively The TFT628 is connected to the wiring 618 at the thorhole 623. The TFT628 is used in embodiments 1, 2, 5, and 6. The thin-film transistors shown can be used as appropriate. Also, the holding capacitance section 630 is TFT6 The first capacitive wiring 604 formed simultaneously with the 28 gate wirings 602, and the gate insulating film 606 It consists of a second capacitive wiring 617 formed simultaneously with wirings 616 and 618.

[0400] The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 overlap, forming the shape of the liquid crystal element. It has been done.

[0401] Figure 25 shows the planar structure on the substrate 600. The pixel electrode layer 624 is made of the material shown in Embodiment 1. It is formed using [a certain method]. A slit 625 is provided in the pixel electrode layer 624. The slit 625 is liquid This is for controlling the orientation of the crystals.

[0402] The TFT 629 shown in Figure 25, the pixel electrode 626 connected to it, and the holding capacitance unit 631 are Each can be formed in the same manner as the TFT628, pixel electrode layer624, and retention capacitance portion630. It works. Both TFT628 and TFT629 are connected to wiring 616. This LCD display panel The pixels of the image are composed of a pixel electrode layer 624 and a pixel electrode 626. The elementary electrode layer 624 and the pixel electrode 626 are subpixels.

[0403] Figure 26 shows the planar structure on the opposing substrate side. The opposing electrode layer 640 is formed on the light-shielding film 632. The counter electrode layer 640 is preferably formed using the same material as the pixel electrode layer 624. Furthermore, protrusions 644 that control the orientation of the liquid crystal are formed on the counter electrode layer 640. Figure 26 shows the pixel electrode layers 624 and 626 formed on the substrate 600, indicated by dashed lines. The opposing electrode layer 640 and the pixel electrode layer 624 and pixel electrode layer 626 are arranged to overlap. This shows the state of being.

[0404] The equivalent circuit of this pixel structure is shown in Figure 27. Both TFT628 and TFT629 have gate configurations. It is connected to wire 602 and wiring 616. In this case, the power of capacitive wiring 604 and capacitive wiring 605 By changing their positions, the operation of liquid crystal elements 651 and 652 can be made different. In other words, by individually controlling the potential of capacitive wiring 604 and capacitive wiring 605, liquid crystals can be formed. The field of view is widened by precisely controlling the orientation of the elements.

[0405] When a voltage is applied to the pixel electrode layer 624 with the slit 625, near the slit 625... This generates distortion of the electric field (oblique electric field). This slit 625 and the protrusion on the opposing substrate 601 side By arranging 644 and other elements in an alternating interlocking manner, a diagonal electric field is effectively generated, resulting in a liquid crystal. By controlling the orientation, the direction in which the liquid crystals align varies depending on the location. That is, The multi-domain architecture widens the viewing angle of the LCD display panel.

[0406] Next, a different type of VA liquid crystal display device will be described using Figures 28 to 31. ru.

[0407] Figures 28 and 29 show the pixel structure of a VA-type liquid crystal display panel. Figure 29 shows the substrate 600 This is a plan view, and Figure 28 shows the cross-sectional structure corresponding to the cutting line YZ shown in the figure.

[0408] This pixel structure has multiple pixel electrodes for each pixel, and a TFT is in contact with each pixel electrode. It continues. Each TFT is configured to be driven by a different gate signal. In a multi-domain designed pixel, the signals applied to each pixel electrode are independently It has a configuration that controls it.

[0409] The pixel electrode layer 624 has contact holes that penetrate the insulating film 620 and insulating film 622, respectively. In section 623, it is connected to the TFT 628 by wiring 618. Also, the pixel electrode layer 626 In the contact holes 627 that penetrate the insulating film 620 and insulating film 622, respectively... It is connected to the TFT629 with wiring 619. The gate wiring 602 of the TFT628 and TF The gate wiring 603 of T629 is isolated so that different gate signals can be applied. Meanwhile, wiring 616, which functions as a data line, is connected to TFT628 and TFT629. They are used in common. TFT628 and TFT629 are shown in Embodiments 1, 2, 5, and 6. Thin-film transistors can be used as appropriate. Note that gate wiring 602, gate wiring 60 A gate insulating film 606 is formed on 3 and the capacitive wiring 690.

[0410] The shapes of the pixel electrode layer 624 and the pixel electrode layer 626 are different, and they are separated by the slit 625. They are separated. The pixel electrode layer 626 surrounds the outside of the V-shaped pixel electrode layer 624. It is formed. The voltage applied to the pixel electrode layer 624 and the pixel electrode layer 626 is set to TFT628 The orientation of the liquid crystal is controlled by varying the TFT629. The equivalent circuit is shown in Figure 31. TFT628 is connected to gate wiring 602, and TFT629 is connected to gate It is connected to wiring 603. Also, both TFT628 and TFT629 are connected to wiring 616. It is connected to the gate wiring 602 and gate wiring 603, which provide different gate signals. Therefore, the operation of liquid crystal elements 651 and 652 can be made different. That is, TF By individually controlling the operation of T628 and TFT629, the liquid crystal element 651 and the liquid crystal element The viewing angle can be widened by precisely controlling the alignment of the 652 liquid crystals.

[0411] A colored film 636 and a counter electrode layer 640 are formed on the opposing substrate 601. A planarization film 637 is formed between 636 and the counter electrode layer 640 to prevent the alignment of the liquid crystal. Figure 30 shows the structure on the opposing substrate side. The opposing electrode layer 640 is common across different pixels. The electrode has a slit 641 formed on it. This slit 641 and the pixel electrode The polar layer 624 and the slit 625 on the pixel electrode layer 626 side are arranged to interlock alternately. This allows for the effective generation of oblique electric fields, thereby controlling the orientation of the liquid crystal. Furthermore, the orientation of the liquid crystal can be varied depending on the location, thereby widening the viewing angle. Figure 30 shows the pixel electrode layers 624 and 626 formed on the substrate 600, indicated by dashed lines. The opposing electrode layer 640 and the pixel electrode layer 624 and pixel electrode layer 626 are arranged to overlap. This shows the state of being.

[0412] An alignment film 648 is formed on the pixel electrode layer 624 and the pixel electrode layer 626, and similarly the counter electrode An alignment film 646 is also formed on layer 640. A liquid crystal is formed between substrate 600 and opposing substrate 601. Layer 650 is formed. Also, the pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 The overlapping of these forms the first liquid crystal element 651. Also, the pixel electrode layer 626 The liquid crystal layer 650 and the counter electrode layer 640 overlap, forming a second liquid crystal element 652. The pixel structure of the display panel, as described in Figures 28 to 31, has a first liquid crystal element in each pixel. It has a multi-domain structure with a child and a second liquid crystal element.

[0413] Next, we will describe a transverse electric field type liquid crystal display device. In the transverse electric field type, the liquid crystal molecules within the cell This method drives the liquid crystal by applying an electric field in the horizontal direction to express gradation. This allows the field of view to be expanded to approximately 180 degrees. The following explanation uses a transverse electric field method. The liquid crystal display device used will be described below.

[0414] Figure 32 shows the shape of the electrode layer 607, TFT 628, and the pixel electrode layer 624 connected to the TFT 628. This shows the completed substrate 600 and the opposing substrate 601 superimposed, with liquid crystal injected. A colored film 636, a planarization film 637, etc., are formed on the opposing substrate 601. No opposing electrodes are provided on the opposing substrate 601 side. Also, between substrate 600 and opposing substrate 601 A liquid crystal layer 650 is formed on top of this via alignment films 646 and 648.

[0415] On the substrate 600 are an electrode layer 607 and capacitive wiring 604 connected to the electrode layer 607, and T The FT628 is formed. The capacitive wiring 604 is formed simultaneously with the gate wiring 602 of the TFT628. This can be achieved. As for TFT628, the thin film shown in Embodiments 1, 2, 5, and 6 A transistor can be applied. The electrode layer 607 is the pixel electrode layer shown in Embodiment 1 and Similar materials can be used. Furthermore, the electrode layer 607 is divided into sections roughly the shape of a pixel. It is formed as follows. Furthermore, a gate insulating film 606 is formed on the electrode layer 607 and the capacitance wiring 604. It can be done.

[0416] The wiring 616 and wiring 618 of the TFT628 are formed on the gate insulating film 606. 6 is a data line in an LCD display panel that carries video signals and is a unidirectional wiring. At the same time, it connects to the source or drain area of ​​the TFT628, and the source and drain It becomes one electrode. Wiring 618 becomes the other electrode of the source and drain, and the pixel electrode layer This is the wiring that connects to 624.

[0417] An insulating film 620 is formed on wiring 616 and wiring 618. In addition, an insulating film is formed on the insulating film 620. Pixel electrical signals connected to wiring 618 via contact holes 623 formed in the edge film 620 A polar layer 624 is formed. The pixel electrode layer 624 is similar to the pixel electrode layer shown in Embodiment 1. Formed using materials.

[0418] In this way, the TFT 628 and the pixel electrode layer 624 connected to it are formed on the substrate 600. The retention capacity is formed between the electrode layer 607 and the pixel electrode layer 624.

[0419] Figure 33 is a plan view showing the configuration of the pixel electrode. The section corresponding to the cutting line OP shown in Figure 33 The surface structure is shown in Figure 32. A slit 625 is provided in the pixel electrode layer 624. The 625 is for controlling the orientation of the liquid crystal. In this case, the electric field is between the electrode layer 607 and It occurs between the pixel electrode layer 624. Gate insulation is present between electrode layer 607 and pixel electrode layer 624. A film 606 is formed, but the thickness of the gate insulating film 606 is 50-200 nm, 2 Since it is sufficiently thin compared to the thickness of the liquid crystal layer, which is approximately 10 μm, it is practically parallel to the substrate 600. An electric field is generated in the horizontal direction. This electric field controls the orientation of the liquid crystal. By using an electric field in a nearly parallel direction, the liquid crystal molecules are rotated horizontally. In this case, which Because it remains horizontal even in this state, the influence of contrast and other factors depending on the viewing angle is minimal, resulting in a wide viewing angle. This will result in... Also, since both electrode layer 607 and pixel electrode layer 624 are light-transmitting electrodes... This can improve the aperture ratio.

[0420] Next, we will show another example of a transverse electric field type liquid crystal display device.

[0421] Figures 34 and 35 show the pixel structure of an IPS-type liquid crystal display device. Figure 35 is a plan view. Yes, and the cross-sectional structure corresponding to the cutting line VW shown in the figure is shown in Figure 34. This will be explained by referring to these two figures.

[0422] Figure 34 shows a substrate 600 on which a TFT 628 and a pixel electrode layer 624 connected thereto are formed, This shows the state after the opposing substrate 601 has been placed on top and liquid crystal has been injected. A colored film 636, a planarization film 637, etc., are formed on the opposing substrate 601 side. No poles are provided. Between the substrate 600 and the opposing substrate 601, there is an alignment film 646 and an alignment film 6 A liquid crystal layer 650 is formed via 48.

[0423] A common potential line 609 and a TFT 628 are formed on the substrate 600. 9 can be formed simultaneously with the gate wiring 602 of the TFT628. Therefore, the thin-film transistors shown in Embodiments 1, 2, 5, and 6 can be applied.

[0424] The wiring 616 and wiring 618 of the TFT628 are formed on the gate insulating film 606. 6 is a data line in an LCD display panel that carries video signals and is a unidirectional wiring. At the same time, it connects to the source or drain area of ​​the TFT628, and the source and drain It becomes one electrode. Wiring 618 becomes the other electrode of the source and drain, and the pixel electrode layer This is the wiring that connects to 624.

[0425] An insulating film 620 is formed on wiring 616 and wiring 618. In addition, an insulating film is formed on the insulating film 620. Pixel electrical signals connected to wiring 618 via contact holes 623 formed in the edge film 620 A polar layer 624 is formed. The pixel electrode layer 624 is similar to the pixel electrode layer shown in Embodiment 1. It is formed using materials. As shown in Figure 35, the pixel electrode layer 624 is connected to a common potential line 6 The comb-shaped electrodes formed simultaneously with 09 are formed to generate a transverse electric field. Also, the pixel electrodes The comb-shaped portions of layer 624 interlock alternately with the comb-shaped electrodes formed simultaneously with the common potential line 609. It is formed in this way.

[0426] When an electric field is generated between the potential applied to the pixel electrode layer 624 and the potential of the common potential line 609, This electric field controls the orientation of the liquid crystal. The liquid crystal is formed using an electric field approximately parallel to the substrate. Rotate the molecules horizontally. In this case, since the liquid crystal molecules are horizontal in any state, the viewing angle... The impact on contrast and other factors is minimal, resulting in a wider viewing angle.

[0427] In this way, the TFT 628 and the pixel electrode layer 624 connected to it are formed on the substrate 600. The retention capacitance is achieved by providing a gate insulating film 606 between the common potential line 609 and the capacitive electrode 615. , thereby forming the capacitive electrode 615 and the pixel electrode layer 624 in contact hole 63 It is connected via 3.

[0428] Through the above steps, a liquid crystal display device can be manufactured as a display device. (Embodiment) This liquid crystal display device is a liquid crystal display device with a high aperture ratio.

[0429] (Embodiment 15) In this embodiment, the size of the liquid crystal display panel exceeds 10 inches, and is 60 inches, and furthermore... If the screen size is set to 120 inches, the wiring resistance of the translucent wiring may become a problem. This example shows how to reduce wiring resistance by using metal wiring for part of the gate wiring.

[0430] Note that Figure 36(A) uses the same reference numerals as Figure 3(A) for the same parts, and provides a detailed explanation of the same parts. The part is omitted. Note that this embodiment is suitable for the active matrix substrate shown in Embodiment 1. It can be used.

[0431] Figures 36(A) and 36(B) show an example where the gate electrode layer of the thin-film transistor in the drive circuit is made of metal wiring. In the drive circuit, the gate electrode layer is not limited to a translucent material. In order to form metal wiring, the number of photomasks is greater than in Embodiments 1 and 2. increase.

[0432] In Figure 36(A), the thin-film transistor 260 of the drive circuit is on the first metal wiring layer 242. The gate electrode layer is formed by laminating a second metal wiring layer 241 on top of the first metal wiring layer 2 Layer 42 can be formed using the same material and process as the first metal wiring layer 236. The second metal wiring layer 241 is formed using the same material and process as the second metal wiring layer 237. It is possible.

[0433] Similarly, in Figure 36(B), the thin-film transistor 270 of the drive circuit is the first metal wiring layer The gate electrode layer is formed by laminating a second metal wiring layer 243 on top of 244. The wiring layer 244 can be formed using the same material and process as the first metal wiring layer 236. Furthermore, the second metal wiring layer 243 is formed using the same material and process as the second metal wiring layer 237. It is possible.

[0434] Furthermore, when electrically connecting the first metal wiring layer 242 and the conductive layer 267, the first metal wiring It is preferable that the second metal wiring layer 241, which prevents oxidation of the wire layer 242, be a metal nitride film. i. Similarly, when electrically connecting the first metal wiring layer 244 and the conductive layer 277, the first The second metal wiring layer 243, which prevents oxidation of the metal wiring layer 244, is a metal nitride film. preferable.

[0435] First, a substrate 200 that can withstand a first heat treatment for dehydration or dehydrogenation A heat-resistant conductive material film (thickness between 100 nm and 500 nm) is formed.

[0436] In this embodiment, a tungsten film with a thickness of 370 nm and a tantalum nitride film with a thickness of 50 nm are used. Formed. Here, the conductive film is made of a laminate of a tantalum nitride film and a tungsten film, but there are no particular limitations. Not specified, an element selected from Ta, W, Ti, Mo, Al, Cu, or the above elements The alloy is a component of the above-mentioned elements, or an alloy film is a combination of the above-mentioned elements, or the above-mentioned elements are a component of the above-mentioned elements. It is formed from nitrides. The heat-resistant conductive material film is not limited to a single layer containing the above-mentioned elements, but rather two Multiple layers can be used.

[0437] A first photolithography process forms the metal wiring, and the first metal wiring layer 236 and the second The metal wiring layer 237, the first metal wiring layer 242 and the second metal wiring layer 241, the first metal wiring A wire layer 244 and a second metal wiring layer 243 are formed. Tungsten film and tantalum nitride film Etching is performed using ICP (Inductively Coupled Plasma). It is preferable to use a coupled plasma etching method. Using the ICP etching method, etching Conditions (amount of power applied to the coil-type electrode, amount of power applied to the electrode on the substrate side, substrate side By appropriately adjusting the electrode temperature, etc., the film can be etched into the desired tapered shape. This can be achieved by making the first metal wiring layer 236 and the second metal wiring layer 237 tapered. This reduces defects in the formation of a translucent conductive film that is in contact with the surface.

[0438] Next, after forming a light-transmitting conductive film, a second photolithography process is performed. A light-transmitting conductive wire is used to form the gate electrode layer of the thin-film transistor 220. The film used is a conductive material that is transparent to visible light as described in Embodiment 1.

[0439] Furthermore, depending on the material of the light-transmitting conductive film, for example, the gate wiring layer 238 may be the first gold If there is an interface in contact with the secondary wiring layer 236 or the second metal wiring layer 237, it will affect subsequent heat treatment, etc. Therefore, an oxide film may form, potentially increasing contact resistance, so the second metal wiring layer 237 It is preferable to use a metal nitride film to prevent oxidation of the first metal wiring layer 236.

[0440] Next, a gate insulating layer, an oxide semiconductor layer, and the like are formed using the same process as in Embodiment 1. The next step involves fabricating an active matrix substrate according to Embodiment 1.

[0441] In Figures 36(A) and 36(B), the gate wiring layer 238 overlaps with a portion of the second metal wiring layer 237. As shown, gate wiring covers the entirety of the first metal wiring layer 236 and the second metal wiring layer 237. They may be layers. That is, the first metal wiring layer 236 and the second metal wiring layer 237 are gates This can be called auxiliary wiring for reducing the resistance of wiring layer 238.

[0442] Furthermore, at the terminal section, the first terminal electrode, which is at the same potential as the gate wiring, is located on the protective insulating layer 203. It is formed and electrically connected to the second metal wiring layer 237. The wiring routed from the terminal is also metal. It is formed by wiring.

[0443] Furthermore, the gate wiring layer and capacitive wiring layer in areas not within the display area are designed to have low wiring resistance. Metal wiring, i.e., the first metal wiring layer 236 and the second metal wiring layer 237, as auxiliary wiring. It can also be used.

[0444] In this embodiment, metal wiring is partially used to reduce wiring resistance, and the size of the liquid crystal display panel is Even when exceeding 10 inches, reaching 60 inches, or even 120 inches, the displayed image This allows for higher resolution and a higher aperture ratio.

Claims

[Claim 1] It has a first transistor and a second transistor, The first transistor has a stack of a first oxide semiconductor layer and a second oxide semiconductor layer that overlap with a first gate electrode layer via a first gate insulating layer. The second transistor has a third oxide semiconductor layer that overlaps with the second gate electrode layer via a second gate insulating layer. The lamination of the first oxide semiconductor layer and the second oxide semiconductor layer is in contact with an oxide insulating layer covering the periphery and sides. A semiconductor device having a source electrode layer and a drain electrode layer electrically connected to a second oxide semiconductor layer on the oxide insulating layer.

Images