Display panel and display device

Abstract

A display panel and a display device are provided. The display panel includes: a substrate having a display area and a peripheral area, the peripheral area being located on at least one side of the display area; a pixel unit located on the substrate, including a pixel circuit and a light-emitting element, the pixel circuit being configured to drive the light-emitting element, the pixel circuit including a driving transistor and a data writing transistor, the driving transistor and the data writing transistor being connected; a data line connected to the data writing transistor and configured to provide a data signal to the pixel circuit; a compensation structure connected to the data line and located in the peripheral area, the compensation structure including at least one of a resistance compensation unit and a capacitance compensation unit.

Description

Technical Field

[0001] At least one embodiment of the present disclosure relates to a display panel and a display device. Background Art

[0002] With the continuous development of display technology, active-matrix organic light-emitting diode (AMOLED) display technology has been increasingly used in display devices such as mobile phones, tablet computers, digital cameras, etc. due to its advantages such as self-luminescence, wide viewing angle, high contrast, low power consumption, and high response speed.

[0003] The under-screen camera technology is a new technology proposed to increase the screen-to-body ratio of display devices. Summary of the invention

[0004] At least one embodiment of the present disclosure relates to a display panel and a display device.

[0005] At least one embodiment of the present disclosure provides a display panel, comprising: a substrate having a display area and a peripheral area, wherein the peripheral area is located on at least one side of the display area; a pixel unit, located on the substrate, comprising a pixel circuit and a light-emitting element, wherein the pixel circuit is configured to drive the light-emitting element, wherein the pixel circuit comprises a driving transistor and a data writing transistor, wherein the driving transistor and the data writing transistor are connected; a data line, connected to the data writing transistor and configured to provide a data signal to the pixel circuit; a compensation structure, connected to the data line and located in the peripheral area, wherein the compensation structure comprises at least one of a resistance compensation unit and a capacitance compensation unit.

[0006] For example, the capacitance compensation unit includes at least one compensation capacitor.

[0007] For example, the capacitance compensation unit includes a plurality of compensation capacitors, and the plurality of compensation capacitors are connected in parallel.

[0008] For example, the compensation capacitor includes a compensation portion connected to the data line, and at least one compensation plate that forms a compensation capacitor with the compensation portion.

[0009] For example, the compensation structure includes a resistance compensation unit, and the resistance compensation unit includes a first compensation part connected to the data line and a second compensation part connected to the first compensation part, the first compensation part and the second compensation part are located in different layers, and the orthographic projection of the first compensation part on the base substrate and the orthographic projection of the second compensation part on the base substrate at least partially overlap.

[0010] For example, the first compensation portion and the second compensation portion are connected through a via.

[0011] For example, the compensation structure includes a capacitor compensation unit, which includes a first compensation part, a first electrode, a second compensation part and a second electrode, the first compensation part is connected to the data line, the first compensation part overlaps with the first electrode to form a first compensation capacitor, the second compensation part overlaps with the first electrode to form a second compensation capacitor, the second compensation part overlaps with the second electrode to form a third compensation capacitor, and the first compensation capacitor, the second compensation capacitor, and the third compensation capacitor are connected in parallel.

[0012] For example, the first compensation part is located in the first conductive layer, the first electrode plate is located in the second conductive layer, the second compensation part is located in the third conductive layer, the second electrode plate is located in the fourth conductive layer, the first conductive layer is located on the first insulating layer, a second insulating layer is provided between the first conductive layer and the second conductive layer, a third insulating layer is provided between the second conductive layer and the third conductive layer, and a fourth insulating layer is provided between the third conductive layer and the fourth conductive layer.

[0013] For example, the first compensation part and the second compensation part constitute a resistance compensation unit.

[0014] For example, an orthographic projection of the first compensation portion on the base substrate at least partially overlaps with an orthographic projection of the second compensation portion on the base substrate.

[0015] For example, the width of the first compensation portion in a first direction is the same as the width of the second compensation portion in the first direction, and the first direction intersects with an extension direction of the first compensation portion and with an extension direction of the second compensation portion.

[0016] The first compensation part is connected to the second compensation part through a via hole penetrating the third insulating layer and the second insulating layer.

[0017] For example, the display panel further includes a first connection structure, and the data line is connected to the first compensation part through the first connection structure.

[0018] For example, the third conductive layer further includes a signal line, the signal line extends along the first direction, and an orthographic projection of the signal line on the base substrate partially overlaps with an orthographic projection of the first compensation portion on the base substrate.

[0019] For example, both the first electrode plate and the second electrode plate are connected to a constant voltage terminal, and the constant voltage terminal includes at least one of a first power supply terminal and a second power supply terminal.

[0020] For example, the display panel further includes a second connection structure, the data line is connected to the plurality of capacitance compensation units via the second connection structure, and the capacitances of the plurality of capacitance compensation units connected to the data line are connected in parallel.

[0021] For example, the first plates of different capacitance compensation units are an integrated structure, and the second plates of different capacitance compensation units are an integrated structure.

[0022] For example, multiple capacitor compensation units are arranged in a first direction, and on one side of the center line of the display panel, the size of the first electrode gradually changes in the second direction, and the size of the second electrode gradually changes in the second direction, the first direction intersects with the second direction, and the center line is parallel to the second direction.

[0023] For example, the display area includes a first display area and a second display area, the first display area is located at at least one side of the second display area, and the data line is not located in the second display area.

[0024] For example, the data line includes a first type of data line and a second type of data line, the compensation structure includes a first compensation structure and a second compensation structure, and the compensation amount of the first compensation structure connected to the first type of data line is greater than the compensation amount of the second compensation structure connected to the second type of data line.

[0025] For example, a plurality of first type data lines and a plurality of first compensation structures are provided, and the plurality of first compensation structures are arranged in sequence. Among the plurality of first compensation structures, the closer to the edge of the display panel, the smaller the compensation amount of the first compensation structure.

[0026] For example, a plurality of second-type data lines and a plurality of second compensation structures are provided, wherein the second-type data lines include a first part, a second part and a third part, wherein the first part and the second part are connected via the third part, an extension direction of the third part is different from an extension direction of the first part, and an extension direction of the third part is different from an extension direction of the second part, the third part is located in the display area, and an amount of compensation of the second compensation structure is inversely proportional to the length of the third part.

[0027] For example, the pixel unit includes a first pixel unit and a second pixel unit, the pixel circuit and the light-emitting element of the first pixel unit are both located in the first display area, the pixel circuit of the second pixel unit is located in the first display area, the light-emitting element of the second pixel unit is located in the second display area, the pixel circuit of the second pixel unit is connected to the light-emitting element of the second pixel unit through a conductive line, and the orthographic projection of the conductive line on the substrate partially overlaps with the orthographic projection of the pixel circuit of the first pixel unit on the substrate.

[0028] At least one embodiment of the present disclosure further provides a display device, comprising any one of the above-mentioned display panels.

[0029] For example, the display device further includes a photosensor, and the photosensor is located on one side of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0031] Figure 1 It is a structural schematic diagram of a display panel provided by an embodiment of the present disclosure.

[0032] Figure 2 is a schematic diagram of a pixel unit of a display panel provided in one embodiment of the present disclosure.

[0033] Figure 3 is a schematic diagram of a display panel provided by an embodiment of the present disclosure.

[0034] Figure 4 A schematic diagram of a first display area and a second display area in a display panel provided in an embodiment of the present disclosure.

[0035] FIG. 5A to FIG. 5E A partial plan view of a display panel provided according to an embodiment of the present disclosure.

[0036] Figure 6 A schematic diagram of a data line in a display panel.

[0037] Figure 7 A schematic diagram of a display panel display failure.

[0038] Figure 8 A schematic diagram of a data line in a display panel.

[0039] Fig. 9A A schematic diagram of a display panel provided according to an embodiment of the present disclosure.

[0040] Fig. 9B A schematic diagram of a display panel provided according to another embodiment of the present disclosure.

[0041] Fig. 9C A schematic diagram of a display panel provided according to another embodiment of the present disclosure.

[0042] Fig.9D for Fig. 9B or Fig. 9C A schematic diagram of a partial compensation structure in a display panel is shown.

[0043] Fig. 10A A schematic diagram of a display panel provided according to an embodiment of the present disclosure.

[0044] Fig. 10B A schematic diagram of a display panel provided according to another embodiment of the present disclosure.

[0045] Fig.11 A schematic diagram of the layout of a compensation unit provided in an embodiment of the present disclosure is shown.

[0046] Fig.12 for Fig.11 Sectional view along line A1-B1.

[0047] Fig.13A for Fig.11 A plan view of the first conductive layer in FIG.

[0048] Fig. 13B for Fig.11 A plan view of the second conductive layer in FIG.

[0049] Fig. 13C for Fig.11 A plan view of the third conductive layer in FIG.

[0050] Fig.13D for Fig.11 A plan view of the fourth conductive layer in FIG.

[0051] Fig.13E for Fig.11 Plan view of the vias in the .

[0052] Fig.13F for Fig.11 A plan view of a via hole penetrating at least one of the first insulating layer, the second insulating layer and the third insulating layer.

[0053] Figure 13G for Fig.11 A plan view of a via hole penetrating the fourth insulating layer and the fifth insulating layer.

[0054] FIG. 14A to FIG. 14G Schematic diagrams of compensation structures in some display panels provided for some embodiments of the present disclosure.

[0055] Fig.14H A schematic diagram of a display panel provided for an embodiment of the present disclosure.

[0056] Fig.14I A schematic diagram of a compensation structure in a display panel provided by an embodiment of the present disclosure.

[0057] Figure 14G for Fig.14I An enlarged schematic diagram of the compensation structure in FIG.

[0058] Fig.14J for Fig.14I An enlarged schematic diagram of the compensation structure in FIG.

[0059] Fig.15 A schematic diagram of a display panel provided according to an embodiment of the present disclosure.

[0060] Fig.16A is a schematic diagram of a pixel circuit provided by an embodiment of the present disclosure.

[0061] Fig. 16B It is a layout diagram of a pixel circuit provided by an embodiment of the present disclosure.

[0062] Fig. 16C for Fig. 16B A cross-sectional view along line AB.

[0063] Fig.16D It is a layout diagram of a pixel circuit provided by an embodiment of the present disclosure.

[0064] Fig.16E for Fig.16D A cross-sectional view along line CD.

[0065] Fig.16F It is a partial schematic diagram of a display panel provided by an embodiment of the present disclosure.

[0066] Figure 16G It is a partial schematic diagram of a display panel provided by an embodiment of the present disclosure.

[0067] Fig.16H It is a partial schematic diagram of a display panel provided by an embodiment of the present disclosure.

[0068] Fig.17 A layout diagram of a first pixel circuit or a second pixel circuit in a display panel provided in an embodiment of the present disclosure.

[0069] Fig.18A and Fig.18B A schematic diagram of a display device provided in accordance with an embodiment of the present disclosure.

[0070] Fig.19 for Fig.16A The working timing diagram of the pixel circuit shown. DETAILED DESCRIPTION

[0071] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0072] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, "include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0073] With the development of display technology, the existing notch screen or water drop screen design is gradually unable to meet the user's demand for a high screen-to-body ratio of display panels, and a series of display panels with a light-transmitting display area have emerged. In this type of display panel, hardware such as light sensors (such as cameras) can be set in the light-transmitting display area. Since there is no need to punch holes, a true full screen becomes possible while ensuring the practicality of the display panel.

[0074] In the related art, a display panel with an under-screen camera generally includes a first display area for normal display and a second display area for setting the camera. The second display area generally includes: a plurality of light-emitting elements and a plurality of pixel circuits, each pixel circuit is connected to a light-emitting element and is used to drive the light-emitting element to emit light, and the interconnected pixel circuits and light-emitting elements overlap in a direction perpendicular to the display panel.

[0075] Since a pixel circuit is also disposed in the second display area in the related art, the light transmittance of the second display area is poor, and accordingly, the display effect of the display panel is poor.

[0076] Figure 1 is a schematic diagram of the structure of a display panel provided by an embodiment of the present disclosure. Figure 1 As shown, the display panel may include: a substrate BS. The display panel includes a first display area R1 and a second display area R2, and the first display area R1 may be located on at least one side of the second display area R2. For example, in some embodiments, the first display area R1 surrounds the second display area R2. That is, the second display area R2 may be surrounded by the first display area R1. The second display area R2 may also be set at other positions, and the setting position of the second display area R2 may be determined as required. For example, the second display area R2 may be located at the top center of the substrate BS, or at the upper left corner or upper right corner of the substrate BS. For example, hardware such as a photosensitive sensor (such as a camera) is set in the second display area R2 of the display panel. For example, the second display area R2 is a light-transmitting display area, and the first display area R1 is a display area. For example, the first display area R1 is opaque and is only used for display.

[0077] Figure 2 FIG. 1 is a schematic diagram of a pixel unit of a display panel provided by an embodiment of the present disclosure. The display panel includes a pixel unit 100, and the pixel unit 100 is located on a substrate. Figure 2 As shown, the pixel unit 100 includes a pixel circuit 100a and a light emitting element 100b, and the pixel circuit 100a is configured to drive the light emitting element 100b. For example, the pixel circuit 100a is configured to provide a driving current to drive the light emitting element 100b to emit light. For example, the light emitting element 100b is an organic light emitting diode (OLED), and the light emitting element 100b emits red light, green light, blue light, or white light under the drive of its corresponding pixel circuit 100b. The color of the light emitted by the light emitting element 100b can be determined as required.

[0078] In order to improve the light transmittance of the second display area R2, only the light emitting element can be arranged in the second display area R2, and the pixel circuit driving the light emitting element of the second display area R2 can be arranged in the first display area R1. That is, the light transmittance of the second display area R2 can be improved by separately arranging the light emitting element and the pixel circuit.

[0079] Figure 3 is a schematic diagram of a display panel provided by an embodiment of the present disclosure. Figure 3 As shown, the display panel includes: a plurality of first pixel circuits 10, a plurality of second pixel circuits 20 and a plurality of first light-emitting elements 30 located in the first display area R1, and a plurality of second light-emitting elements 40 located in the second display area R2. For example, the plurality of second pixel circuits 20 may be distributed between the plurality of first pixel circuits 10 at intervals.

[0080] For example, Figure 3As shown, at least one first pixel circuit 10 among the plurality of first pixel circuits 10 may be connected to at least one first light-emitting element 30 among the plurality of first light-emitting elements 30, and the orthographic projection of at least one first pixel circuit 10 on the substrate BS may at least partially overlap with the orthographic projection of at least one first light-emitting element 30 on the substrate BS. The at least one first pixel circuit 10 may be used to provide a driving signal to the connected first light-emitting element 30 to drive the first light-emitting element 30 to emit light.

[0081] For example, Figure 3 As shown, at least one second pixel circuit 20 among the plurality of second pixel circuits 20 can be connected to at least one second light-emitting element 40 among the plurality of second light-emitting elements 40 through a conductive line L1, and the at least one second pixel circuit 20 can be used to provide a driving signal to the connected second light-emitting element 40 to drive the second light-emitting element 40 to emit light. Figure 3 As shown, since the second light emitting element 40 and the second pixel circuit 20 are located in different areas, the orthographic projection of at least one second pixel circuit 20 on the substrate BS does not overlap with the orthographic projection of at least one second light emitting element 40 on the substrate BS.

[0082] For example, in the embodiment of the present disclosure, the first display area R1 can be set as a non-light-transmitting display area, and the second display area R2 can be set as a light-transmitting display area. For example, the first display area R1 is not light-transmitting, and the second display area R2 is light-transmitting. In this way, the display panel provided by the embodiment of the present disclosure does not need to be processed by digging holes on the display panel, and the required hardware structures such as the photosensitive sensor can be directly set at the position corresponding to the second display area R2 on one side of the display panel, laying a solid foundation for the realization of a true full screen. In addition, since the second display area R2 only includes light-emitting elements but not pixel circuits, it is beneficial to improve the transmittance of the second display area R2, so that the display panel has a better display effect.

[0083] like Figure 3As shown, the pixel unit 100 includes a first pixel unit 101 and a second pixel unit 102, the pixel circuit 100a and the light-emitting element 100b of the first pixel unit 101 are both located in the first display area R1, the pixel circuit 100a of the second pixel unit 101 is located in the first display area R1, and the light-emitting element 100b of the second pixel unit 102 is located in the second display area R2. In the embodiment of the present disclosure, the pixel circuit 100a of the first pixel unit 101 is the first pixel circuit 10, the light-emitting element 100b of the first pixel unit 101 is the first light-emitting element 30, the pixel circuit 100a of the second pixel unit 101 is the second pixel circuit 20, and the light-emitting element 100b of the second pixel unit 102 is the second light-emitting element 40. For example, the first light-emitting element 30 can be referred to as an in-situ light-emitting element. For example, the first pixel circuit 10 can be referred to as an in-situ pixel circuit, and the second pixel circuit 20 can be referred to as a non-in-situ pixel circuit.

[0084] For example, Figure 3 As shown, the second light emitting element 40 and the second pixel circuit 20 connected to the second light emitting element 40 are located in the same row. That is, the light emitting signal of the second light emitting element 40 comes from the second pixel circuit in the same row. For example, the pixel circuits of the pixel units in the same row are connected to the same gate line.

[0085] like Figure 3 As shown, the pixel circuit (second pixel circuit 20) of the second pixel unit 102 is connected to the light-emitting element (second light-emitting element 40) of the second pixel unit 102 through the conductive line L1. For example, the conductive line L1 is made of a transparent conductive material. For example, the conductive line L1 is made of a conductive oxide material. For example, the conductive oxide material includes indium tin oxide (ITO), but is not limited thereto.

[0086] like Figure 3 As shown, one end of the conductive line L1 is connected to the second pixel circuit 20, and the other end of the conductive line L1 is connected to the second light emitting element 40. Figure 3 As shown, the conductive line L1 extends from the first display region R1 to the second display region R2.

[0087] like Figure 1 and Figure 3 As shown, in some embodiments, the display panel further includes an auxiliary area Ra, and the auxiliary area Ra may be provided with a second pixel circuit 20 connected to the second light emitting element in the second display area R2.

[0088] Figure 4 A schematic diagram of a first display area and a second display area in a display panel provided in an embodiment of the present disclosure. Figure 4 As shown, in the second display area R2, a light-transmitting area R0 is provided between adjacent second light-emitting elements 40. Figure 4As shown, a plurality of light-transmitting regions R0 are connected to each other to form a continuous light-transmitting region separated by a plurality of second light-emitting elements 40. The conductive line L1 is made of a transparent conductive material to increase the light transmittance of the light-transmitting region R0 as much as possible. Figure 4 As shown, the second display region R2 except for the area where the second light emitting element 40 is disposed may be a light-transmitting region.

[0089] FIG. 5A to FIG. 5E A partial plan view of a display panel provided by an embodiment of the present disclosure. FIG. 5A to FIG. 5E Give a description.

[0090] Figure 5A Schematic diagram of a first display area and a second display area of ​​a display panel provided in one embodiment of the present disclosure. Figure 5A As shown, the second display area R2 is a light-transmitting display area, and the first display area R1 is a display area.

[0091] Figure 5B A schematic diagram of a first light-emitting element in a first display area and a second light-emitting element in a second display area of ​​a display panel provided in an embodiment of the present disclosure. Figure 5B A first light emitting element 30 and a second light emitting element 40 are shown.

[0092] refer to Figure 5A , Figure 5B and Figure 3 In order to improve the display effect, the density of the second light emitting elements 40 may be equal to the density of the first light emitting elements 30. That is, the resolution of the second display area R2 is the same as the resolution of the first display area R1. Of course, in other embodiments, the density of the second light emitting elements 40 may be greater than or less than the density of the first light emitting elements 30. That is, the resolution of the second display area R2 may be greater than or less than the resolution of the first display area R1. For example, Figure 5B and Figure 4 As shown, the light emitting area of ​​the second light emitting element 40 is smaller than the light emitting area of ​​the first light emitting element 30 . Figure 4 The dotted lines show the light emitting area of ​​the second light emitting element 40 and the light emitting area of ​​the first light emitting element 30. For example, the light emitting area of ​​the light emitting element may correspond to the area of ​​the opening of the pixel definition layer.

[0093] Figure 5C A schematic diagram of a conductive line in a display panel provided by an embodiment of the present disclosure. Figure 5C A plurality of conductive lines L1 are shown.

[0094] Figure 5D A schematic diagram of a conductive line in a display panel provided by an embodiment of the present disclosure. Figure 5D The conductive line L1 is shown. Figure 5DAs shown, the conductive line L1 includes a first conductive line L11, a second conductive line L12, and a third conductive line L13. In a high PPI display panel, in order to avoid too dense conduction, multiple conductor pattern layers can be formed. An insulating layer is set between different conductor pattern layers. For example, the first conductive line L11 is located in the first conductor pattern layer, the second conductive line L12 is located in the second conductor pattern layer, and the third conductive line L13 is located in the third conductor pattern layer. Of course, in other embodiments, multiple conductive lines of other forms can also be set. For example, a conductive line L1 is formed by conductive parts located in different conductor pattern layers. For example, conductive parts located in different conductor pattern layers can be connected by vias that penetrate the insulating layer.

[0095] Figure 5E The first light emitting element 30, the second light emitting element 40, the first pixel circuit 10, the second pixel circuit 20, the connecting element CE0, and the conductive line L1 are shown. Each pixel circuit is connected to the light emitting element through the connecting element CE0. That is, each pixel unit has a connecting element CE0. That is, the first pixel circuit 10 is connected to the first light emitting element 30 through the connecting element CE0, and the second pixel circuit 20 is connected to the second light emitting element 40 through the connecting element CE0. For example, one end of the conductive line L1 is connected to the second pixel circuit 20 through the connecting element CE0, and the other end of the conductive line L1 is connected to the second light emitting element 40.

[0096] like Figure 5E As shown, a conductive line L1 passes through the area where the pixel circuit of the pixel unit is located to respectively connect the second pixel circuit 20 and the second light-emitting element 40 on both sides of the pixel unit. For example, the area where the pixel circuit of the pixel unit is located overlaps with multiple conductive lines L1 passing through the area, so that the pixel circuit and the conductive lines overlapping the pixel circuit are coupled to form parasitic capacitance, resulting in brightness differences and display defects such as stripes (Mura). The area in the first display area R1 where the second pixel circuit 20 connected to the second light-emitting element 40 is set can be called an auxiliary area Ra (such as Figure 1 and Figure 3 As shown in FIG. 1 , the auxiliary area Ra can also be called a transition area. Due to the coupling between the conductive line and the pixel circuit, the auxiliary area (transition area) is prone to dimming, and the dim pixel unit is the pixel unit (first pixel unit) in the first display area R1, not the second light-emitting element 40 in the second display area R2. For example, the dimming of the auxiliary area is more obvious in the case of high grayscale than in the case of low grayscale. Figure 5E Taking the example that a first pixel circuit 10 overlaps with at most two conductive lines L1, in other embodiments, a first pixel circuit 10 may also overlap with more conductive lines L1. Figure 5CAs shown, in some embodiments, one first pixel circuit 10 may overlap with 10-15 conductive lines L1. The number of conductive lines L1 overlapped with one first pixel circuit 10 may be determined according to needs.

[0097] In some embodiments, the size of the first pixel circuit 10 can be compressed in the first direction X to obtain an area for arranging the second pixel circuit 20. Figure 5E As shown, in the auxiliary area, a column of second pixel circuits 20 is provided for every set column of first pixel circuits 10. For example, the number of columns of first pixel circuits 10 between two adjacent columns of second pixel circuits 20 can be determined as required.

[0098] Figure 6 A schematic diagram of a data line in a display panel. Figure 7 A schematic diagram of a display panel display failure. Figure 8 A schematic diagram of a data line in a display panel. Fig. 9A A schematic diagram of a display panel provided according to an embodiment of the present disclosure. Fig. 9B A schematic diagram of a display panel provided according to another embodiment of the present disclosure. Fig. 9C A schematic diagram of a display panel provided according to another embodiment of the present disclosure. Fig. 10A A schematic diagram of a display panel provided according to an embodiment of the present disclosure. Fig. 10B A schematic diagram of a display panel provided according to another embodiment of the present disclosure. Figures 8 to 10B The center line a0 of the display panel is shown. For example, the center line a0 extends along the second direction Y. For example, the center line a0 is parallel to the second direction Y. For example, the display panel is symmetrically arranged with respect to the center line a0. Figures 8 to 9C Taking the second display area R2 located on one side of the first display area R1 as an example, FIG. 10A to FIG. 10B Take the example that the first display area R1 surrounds the second display area R2.

[0099] like Figure 6 As shown, the second display area R2 is a light-transmitting display area. Figure 3 and Figure 6 , the second pixel circuit 20 is separated from the second light emitting element 40, and the second pixel circuit 20 is disposed in the first display area R1, then the second pixel unit 102 (see Figure 3 ) is formed in segments. Figure 6 As shown, the data line DTn includes a first portion DT01, a second portion DT02 and a third portion DT03. Figure 6As shown, the first part DT01 and the second part DT02 both extend along the second direction Y, the third part DT03 extends along the first direction X, and the first part DT01 and the second part DT02 are connected through the third part DT03. The extension direction of the third part DT03 is different from the extension direction of the first part DT01, and the extension direction of the third part DT03 is different from the extension direction of the second part DT02, and the third part DT03 is located in the display area R0. The third part DT03 is located in the first display area R1. Because the data line DTn includes a longitudinal portion and a transverse portion, the length of the data line DTn is longer than the first pixel unit 101 (see Figure 3 ) has a larger length of the data line DTm, so the load of the data line DTn is larger than that of the data line DTm. Figure 7 As shown, the display panel has a poor display with dark vertical stripes when displaying. Figure 7 A dark vertical stripe MR is shown. In an embodiment of the present disclosure, the data line may be divided into a data line DTm and a data line DTn, the data line DTm may be referred to as a first type of data line DTm, and the data line DTn may be referred to as a second type of data line DTn. For example, the first type of data line DTm extends along the second direction Y, and the second type of data line DTn includes a portion extending along the first direction X and also includes a portion extending along the second direction Y. For example, in an embodiment of the present disclosure, the first direction X is a row direction of a pixel unit, and the second direction Y is a column direction of a pixel unit, but is not limited thereto.

[0100] For example, in some embodiments, no metal wire is provided in the second display area R2, but the present invention is not limited thereto. For example, in other embodiments, metal wire may also be provided in the second display area R2. The structure in the second display area R2 may be provided as required.

[0101] like Figure 8 As shown, the display panel includes a display area R0 and a peripheral area R3, and the display area R0 includes a first display area R1 and a second display area R2. In other words, the base substrate BS has a display area R0 and a peripheral area R3, and the peripheral area R3 is located on at least one side of the display area R0. The peripheral area R3 is a non-display area.

[0102] For example, refer to Figure 2 and Figure 3 The pixel unit 100 is located on the substrate BS and includes a pixel circuit 100a and a light emitting element 100b. The pixel circuit 100a is configured to drive the light emitting element 100b. The pixel circuit 100b includes a driving transistor T1 (see Fig.16A ) and data write transistor T2 (see Fig.16A ), the driving transistor and the data writing transistor are connected.

[0103] For example, see Fig.16A and Fig. 16B The data line DT is connected to the data writing transistor T2 and is configured to provide a data signal to the pixel circuit 100a.

[0104] For example, in a display panel provided in some embodiments of the present disclosure, Fig. 9A and Fig. 9B As shown, the display panel includes a compensation structure 80, which is connected to the data line DT and is located in the peripheral area R3, and the compensation structure 80 includes at least one of a resistance compensation unit and a capacitance compensation unit. The embodiment of the present disclosure is described by taking the compensation structure 80 including both a resistance compensation unit and a capacitance compensation unit as an example.

[0105] In the display panel provided by the embodiment of the present disclosure, by setting a compensation structure, the difference in capacitance / resistance between the data lines can be reduced, so as to improve display defects and reduce or avoid the appearance of dark vertical stripes during display. For example, in the display panel provided by the embodiment of the present disclosure, by setting a compensation structure, the difference in capacitance / resistance between the first type of data lines DTm can be reduced, the difference in capacitance / resistance between the second type of data lines DTn can be reduced, and the difference in capacitance / resistance between the first type of data lines DTm and the second type of data lines DTn can be reduced.

[0106] For example, when setting the compensation structure, the compensation amount of each data line can be determined according to the data line with the largest load in the display panel before compensation. For example, in the display panel provided in some embodiments of the present disclosure, the load difference of each data line is small due to the setting of the compensation structure.

[0107] like Fig. 9A As shown, the second type of data line DTn of the display panel is connected to the compensation structure 80. Fig. 9B As shown, a second type data line DTn of the display panel is connected to a compensation structure 80 (second compensation structure 82).

[0108] like Fig. 9B As shown, a first type data line DTm of the display panel is connected to a compensation structure 80 (first compensation structure 81). For example, the compensation amount of the first compensation structure 81 is different from the compensation amount of the second compensation structure 82. For example, the compensation amount of the first compensation structure 81 is greater than the compensation amount of the second compensation structure 82. For example, the compensation amount of the capacitance of the first compensation structure 81 is different from the compensation amount of the capacitance of the second compensation structure 82.

[0109] For example, the compensation amount of the capacitance of the first compensation structure 81 is greater than the compensation amount of the capacitance of the second compensation structure 82. For example, the compensation amount of the resistance of the first compensation structure 81 is greater than the compensation amount of the resistance of the second compensation structure 82. For example, the compensation amount of the capacitance of the first compensation structure 81 is greater than the compensation amount of the capacitance of the second compensation structure 82, and the compensation amount of the resistance of the first compensation structure 81 is greater than the compensation amount of the resistance of the second compensation structure 82.

[0110] For example, in some embodiments, Fig. 9B As shown, for the plurality of first-type data lines DTm located on one side of the center line a0, each first-type data line DTm is connected to a first compensation structure 81, so that the plurality of first compensation structures 81 are arranged in sequence. For example, the plurality of first compensation structures 81 are arranged along the first direction X. For example, in some embodiments, the first-type data line DTm with the largest capacitance before the compensation structure is set may not be set with a compensation structure.

[0111] Fig. 9B The display panel shown is a rectangular display panel. Fig. 9B As shown, considering the fan-out region FR (reference Fig.15 ) have different lengths of data lines, and the closer to the center line a0, the greater the compensation amount of the first compensation structure 81. That is, the compensation amount of the first compensation structure 81 (first compensation structure 811) close to the center line a0 is greater than the compensation amount of the first compensation structure 81 (first compensation structure 811) far from the center line a0.

[0112] For example, in some embodiments, Fig. 9B As shown, for the plurality of first-type data lines DTm located on one side of the center line a0, relative to the edge of the display panel, the closer the first compensation structure 81 is to the edge of the display panel, the smaller the compensation amount is. That is, the compensation amount of the first compensation structure 81 (first compensation structure 811) close to the edge of the display panel is smaller than the compensation amount of the first compensation structure 81 (first compensation structure 811) far from the edge of the display panel.

[0113] For example, Fig. 9B As shown, for the plurality of second type data lines DTn located on one side of the center line a0, each second type data line DTn is connected to a second compensation structure 82, so that the plurality of second compensation structures 82 are arranged along the first direction X.

[0114] For example, Fig. 9B As shown, the longer the length of the third portion DT03 of the second type data line DTn is, the greater the load of the data line is, and the smaller the compensation amount of the compensation structure is set.

[0115] For example, Fig. 9BAs shown, the farther the first portion DT01 of the second type data line DTn is from the center line a0, the smaller the compensation amount of the compensation structure of the data line.

[0116] Fig. 9C The display panel shown is a display panel with rounded corners. Fig. 9C As shown, the number of pixel units at the data lines corresponding to the rounded corner positions is less than that at other positions, so that for the plurality of first-type data lines DTm located on one side of the center line a0, the compensation amount of the first compensation structure 81 closer to the edge of the display panel is greater relative to the edge of the display panel. That is, the compensation amount of the first compensation structure 81 (first compensation structure 811) close to the edge of the display panel is greater than the compensation amount of the first compensation structure 81 (first compensation structure 811) far from the edge of the display panel.

[0117] Fig.9D for Fig. 9B or Fig. 9C A schematic diagram of a partial compensation structure in a display panel is shown. Fig.9D Only the compensation structure of the second type of data line DTn (the second compensation structure 82) is shown, and the setting of the compensation amount of the compensation structure of the first type of data line DTm (the first compensation structure 81) can refer to the above description. Fig. 9B and Fig.9D As shown, the compensation amount of the second compensation structure 821 is less than the compensation amount of the second compensation structure 822. Fig. 9B In the display panel shown, on one side of the center line a0, for the second type of data line DTn, the compensation amount of the compensation structure 80 (the second compensation structure 82) gradually changes, for example, gradually increases or gradually decreases along the first direction X. That is, on one side of the center line a0, in the direction from a position away from the center line a0 to a position close to the center line a0, the compensation amount of the compensation structure 80 (the second compensation structure 82) gradually increases. In other embodiments, on one side of the center line a0, in the direction from a position away from the center line a0 to a position close to the center line a0, the compensation amount of the compensation structure 80 (the second compensation structure 82) of the second type of data line DTn may also gradually decrease. The setting trend of the compensation amount of the compensation structure 80 (the second compensation structure 82) is related to the length of the third portion DT3.

[0118] In the embodiment of the present disclosure, the compensation amount of the compensation structure of the second type data line DTn is inversely proportional to the length of the third portion DT3 thereof, that is, the longer the length of the third portion DT3 is, the smaller the compensation amount of the compensation structure connected to the second type data line DTn is, so that the capacitance difference of each data line DT is small and the load difference is small. Among the plurality of second type data lines DTn, when the length of the third portion DT3 gradually increases, the compensation amount of the compensation structure connected to the second type data line DTn gradually decreases, and when the length of the third portion DT3 gradually decreases, the compensation amount of the compensation structure connected to the second type data line DTn gradually increases.

[0119] For example, in the embodiment of the present disclosure, the compensation amount of the compensation structure includes the compensation amount of capacitance and / or the compensation amount of resistance. In the case where the capacitance of each data line is greatly different, the capacitance may be mainly compensated.

[0120] like Fig. 10A and Fig. 10B As shown, the first display area R1 surrounds the second display area R2, and the second compensation structure 82 is located at a position of the peripheral area R3 directly opposite to the second display area R2. For the portion of the display panel located on one side of the center line a0, the multiple first compensation structures 81 are adjacent to each other, the multiple second compensation structures 82 are adjacent to each other, the multiple first compensation structures 81 are located on one side of the multiple second compensation structures 82, and the multiple second compensation structures 82 are closer to the center line a0 than the multiple first compensation structures 81. Figures 8 to 9C In the display panel shown, the second compensation structure 82 is located outside the position of the peripheral region R3 directly facing the second display region R2 , and a plurality of second compensation structures 82 are arranged at intervals among the plurality of first compensation structures 81 . Fig. 10A and Fig. 10B Taking the example that the closer the second portion DT02 of the second type data line DTn is to the center line a0, the longer the third portion DT03 of the second type data line DTn is. In other embodiments, the closer the second portion DT02 of the second type data line DTn is to the center line a0, the shorter the third portion DT03 of the second type data line DTn is may be set.

[0121] For example, the capacitance compensation unit includes at least one compensation capacitor to perform capacitance compensation on a data line connected thereto.

[0122] For example, the capacitance compensation unit includes a plurality of compensation capacitors, and the plurality of compensation capacitors are connected in parallel to increase the compensation amount of the capacitance.

[0123] Fig.11 A schematic diagram of the layout of a compensation unit provided in an embodiment of the present disclosure is shown. Fig.12 for Fig.11Sectional view along line A1-B1. Fig.13A for Fig.11 A plan view of the first conductive layer in FIG. Fig. 13B for Fig.11 A plan view of the second conductive layer in FIG. Fig. 13C for Fig.11 A plan view of the third conductive layer in FIG. Fig.13D for Fig.11 A plan view of the fourth conductive layer in FIG. Fig.13E for Fig.11 Plan view of the vias in the . Fig.13F for Fig.11 A plan view of a via hole penetrating at least one of the first insulating layer, the second insulating layer and the third insulating layer. Figure 13G for Fig.11 A plan view of a via hole penetrating the fourth insulating layer and the fifth insulating layer. Fig.11 The display panel shown is described by taking one data line DT connected to one compensation structure 80 as an example, and the embodiments of the present disclosure include but are not limited to this. In other embodiments, one data line DT may also be connected to multiple compensation structures 80 .

[0124] For example, the compensation capacitor includes a compensation portion connected to the data line, and at least one compensation plate that forms a compensation capacitor with the compensation portion. For example, the compensation portion may be at least one of the first compensation portion 801 and the second compensation portion 803 mentioned later. For example, the compensation plate may be at least one of the first plate 802 and the second plate 804 mentioned later.

[0125] For example, refer to Fig.11 , Fig.13A and Fig. 13C The compensation structure 80 includes a resistance compensation unit, and the resistance compensation unit includes a first compensation portion 801 connected to the data line DT and a second compensation portion 803 connected to the first compensation portion 801. Fig.11 and Fig.12 The first compensation part 801 and the second compensation part 803 are located in different layers, and the orthographic projection of the first compensation part 801 on the substrate BS and the orthographic projection of the second compensation part 803 on the substrate BS at least partially overlap. The first compensation part 801 and the second compensation part 803 are equivalent to extending the length of the data line and performing resistance compensation on the data line.

[0126] For example, Fig.12 and Fig.13E As shown, the first compensation portion 801 contacts the second compensation portion 803. For example, the first compensation portion 801 and the second compensation portion 803 are connected through a via hole V1 penetrating the third insulating layer ISL3 and the second insulating layer ISL2.

[0127] For example, refer to Fig.11 , Fig.12 as well as FIG. 13A to FIG. 13D The compensation structure includes a capacitance compensation unit, which includes a first compensation part 801, a first electrode 802, a second compensation part 803 and a second electrode 804. The first compensation part 801 is connected to the data line, the first compensation part 801 is located in the first conductive layer LY1, the first electrode 802 is located in the second conductive layer LY2, the second compensation part 803 is located in the third conductive layer LY3, the second electrode 804 is located in the fourth conductive layer LY4, the first conductive layer LY1 is located on the first insulating layer ISL1, a second insulating layer ISL2 is provided between the first conductive layer LY1 and the second conductive layer LY2, a third insulating layer ISL3 is provided between the second conductive layer LY2 and the third conductive layer LY3, and an insulating layer ISL0 is provided between the third conductive layer LY3 and the fourth conductive layer LY4. For example, the insulating layer ISL0 includes the fourth insulating layer ISL4 and the fifth insulating layer ISL5, or the insulating layer ISL0 includes only one of the fourth insulating layer ISL4 and the fifth insulating layer ISL5. The first insulating layer ISL1 may also be referred to as a first gate insulating layer. The second insulating layer ISL2 may also be referred to as a second gate insulating layer. The third insulating layer ISL3 may also be referred to as an interlayer dielectric layer. The fourth insulating layer ISL4 may also be referred to as a passivation layer. The fifth insulating layer ISL5 may also be referred to as a planarization layer.

[0128] For example, when the display substrate provided by the embodiment of the present disclosure includes a capacitance compensation unit, the compensation effect is better and is more conducive to reducing or eliminating display defects. For example, in some embodiments, the first electrode 802 and the second electrode 804 have the same pattern, but are not limited to this, and can be set as needed. For example, the second electrode 804 and the shielding electrode SE mentioned later are located in the same layer, that is, both are located in the fourth conductive layer LY4. For example, Fig.11 and Fig.12 The first to fourth conductive layers LY1-LY4 are shown in the following FIG. 16B to FIG. 16E , Figure 16G , Fig.16H ,as well as Fig.17 The first to fourth conductive layers LY1-LY4 in the display panel are shown in the figures. The entire structure of the display panel is not shown in each figure.

[0129] For example, refer to Fig.11 , Fig.12 , Fig.13A ,as well as Fig. 13C , the first compensation part 801 and the second compensation part 803 constitute a resistance compensation unit.

[0130] For example, one compensation structure may correspond to one capacitance compensation unit, and one compensation structure may correspond to one resistance compensation unit.

[0131] For example, refer to Fig.11 , Fig.12, Fig.13A ,as well as Fig. 13C , the orthographic projection of the first compensation portion 801 on the substrate BS at least partially overlaps with the orthographic projection BS of the second compensation portion 803 on the substrate BS.

[0132] For example, the width of the first compensation portion 801 in the first direction X is the same as the width of the second compensation portion 803 in the first direction X, and the first direction X intersects with the extension direction of the first compensation portion 801 and the extension direction of the second compensation portion 803. For example, the first direction X is perpendicular to the extension direction of the first compensation portion 801 and the extension direction of the second compensation portion 803, but is not limited thereto.

[0133] For example, Fig.12 As shown, the first compensation part 801 is connected to the second compensation part 803 through a via hole V1 penetrating the third insulating layer ISL3 and the second insulating layer ISL2, so as to form a resistance compensation unit and a capacitance compensation unit.

[0134] For example, the first compensation part 801 overlaps with the first electrode plate 802 to form a first compensation capacitor C1, the second compensation part 803 overlaps with the first electrode plate 802 to form a second compensation capacitor C2, the second compensation part 803 overlaps with the second electrode plate 804 to form a third compensation capacitor C3, and the first compensation capacitor C1, the second compensation capacitor C2, and the third compensation capacitor C3 are connected in parallel to increase the compensation amount of the capacitance.

[0135] For example, refer to Fig.11 and Fig. 13C The third conductive layer LY3 further includes a signal line SL3, which extends along the first direction X. The orthographic projection of the signal line SL3 on the base substrate partially overlaps with the orthographic projection of the first compensation portion 801 on the base substrate.

[0136] For example, refer to Fig.11 and Fig. 13C The third conductive layer LY3 further includes a signal line SL4, which extends along the first direction X. The orthographic projection of the signal line SL4 on the base substrate partially overlaps with the orthographic projection of the first compensation portion 801 on the base substrate.

[0137] For example, one of the signal line SL3 and the signal line SL4 is a high level signal line, and the other of the signal line SL3 and the signal line SL4 is a low level signal line. Neither the signal line SL3 nor the signal line SL4 is connected to the data line DT. The high level signal line is configured to provide a high level, and the low level signal line is configured to provide a low level, and the voltage of the high level is greater than the voltage of the low level.

[0138] For example, refer to Fig.11 , Fig.12 and Fig. 13BIn order to facilitate manufacturing and capacitance compensation, the first plates 802 of the multiple compensation structures are formed as an integrated structure, and the second plates 804 of the multiple compensation structures are formed as an integrated structure.

[0139] For example, in order to facilitate capacitance compensation, the first plate 802 and the second plate 804 are both connected to a constant voltage terminal. Fig.16A As shown, the constant voltage terminal includes at least one of a first power supply terminal TM1 and a second power supply terminal TM2. Fig.16A The first power line PL1 is connected to the second power terminal TM2. Fig.16A The second power line PL2 is shown connected.

[0140] For example, Fig. 9A and Fig. 9B As shown, the display area R0 includes a first display area R1 and a second display area R2 , the first display area R1 is located at least on one side of the second display area R2 , and the data line DT is not located in the second display area R2 .

[0141] refer to Fig.11 and Fig. 13C , the display panel includes a first connection structure 831. Fig.11 and Fig.13E , the first connection structure 831 is connected to the first compensation part 801 through the via hole V2, and the data line DT is connected to the first connection structure 831 through the via hole V3. Fig.12 and Fig.13F , the via hole V2 is used to connect the structure of the first conductive layer LY1 and the third conductive layer LY3, so that the via hole V2 penetrates the third insulating layer ISL3 and the second insulating layer ISL2. Fig.12 and Figure 13G , the via V3 is used to connect the structure of the fourth conductive layer LY4 and the third conductive layer LY3, so that the via V3 penetrates the fourth insulating layer ISL4 and the fifth insulating layer ISL5. Similarly, the via V5 also penetrates the fourth insulating layer ISL4 and the fifth insulating layer ISL5. For example, in some embodiments, the data line DT includes portions located in different layers. In some embodiments, the data line DT includes a portion located in the fourth conductive layer LY4 and a portion located in the third conductive layer LY3. In some embodiments, the third portion DT03 of the data line DT may be located in the second conductive layer LY2, but is not limited thereto. For example, in some embodiments, the first connection structure 831 may not be provided, and the first portion DT01 of the data line is connected to the first compensation portion 801 through a via.

[0142] refer to Fig.11 and Fig.13A , the display panel includes a signal line SL2. Fig.11 and Fig. 13C The display panel includes a signal line 841, and the signal line 841 is connected to the signal line SL2. For example, the signal line 841 may be the first power line PL1 mentioned later, but is not limited thereto. Fig.11 and Fig.13E , the signal line 841 is connected to the signal line SL2 through the via V5.

[0143] refer to Fig.11 and Fig. 13B , the display panel includes a signal line SL1. Fig.11 and Fig. 13C The display panel includes a signal line 832, and the signal line 832 is connected to the signal line SL1. For example, the signal line 832 may be an initialization signal line mentioned later, but is not limited thereto. Fig.11 and Fig.13E The signal line 832 is connected to the signal line SL1 through a via hole V4. For example, the via hole V4 is used to connect the signal line 832 of the third conductive layer LY3 and the signal line SL1 of the second conductive layer LY2, so that the via hole V4 penetrates the third insulating layer ISL3.

[0144] refer to Fig.11 and Fig. 13C , the display panel includes a signal line SL9. Fig. 13C As shown, the signal line SL9 is located in the third conductive layer LY3. Fig.11 and Fig. 13B The display panel further includes signal lines SL5 to SL8. Fig. 13B As shown, the signal lines SL5 to SL8 are connected to the second conductive layer LY2. For example, the signal lines SL5 to SL9 can be crack detection lines, but are not limited thereto. It should be noted that the number and positions of the crack detection lines in the display panel are not limited to those shown in the figure, and can be set as needed. Of course, the display panel may not be provided with crack detection lines.

[0145] It should be noted that the embodiments of the present disclosure are based on Fig.11 The display panel shown in FIG. 1 is used as an example for explanation. Those skilled in the art can Fig.11 Based on the description of the invention, changes and modifications are made to obtain new embodiments. For example, Fig.11 On the basis of the display panel shown, the layer in which the components are arranged can be adjusted, some signal lines can be added or removed, etc.

[0146] FIG. 14A to FIG. 14G Schematic diagrams of compensation structures in some display panels provided for some embodiments of the present disclosure. Fig.14H A schematic diagram of a compensation structure in a display panel provided by an embodiment of the present disclosure. Fig.14I A schematic diagram of a compensation structure in a display panel provided by an embodiment of the present disclosure. Fig.14J for Fig.14I An enlarged schematic diagram of the compensation structure in FIG.

[0147] Fig.14A The display panel shown is Fig.11 Compared with the display panel shown in FIG. 1 , the compensation structure 80 is retained, while the signal lines SL1-SL9 and the structures connected to the signal lines are removed. That is, in the display panel provided in the embodiment of the present disclosure, the surrounding structures of the compensation structure 80 may not be arranged in the same manner. Fig.11 The situation shown.

[0148] Fig. 14B The display panel shown is Fig.11 Compared with the display panel shown in FIG. 1 , one data line DT is connected to three compensation structures 80. Of course, the embodiment of the present disclosure does not limit the number of compensation structures 80 connected to one data line DT. One data line DT may be connected to one compensation structure 80, or one data line DT may be connected to multiple compensation structures 80. When one data line DT is connected to multiple compensation structures 80, the capacitors of the multiple compensation structures are connected in parallel, which can further increase the total capacitance of the compensation structures connected to the data line.

[0149] Fig. 14C The display panel shown is Fig. 14B Compared with the display panel shown in FIG. 1 , the compensation structure 80 is retained, while the signal lines SL1-SL9 and the structures connected to the signal lines are removed. That is, in the display panel provided in the embodiment of the present disclosure, the surrounding structures of the compensation structure 80 may not be arranged in the same manner. Fig.11 The situation shown.

[0150] like Fig.14D As shown, the compensation amount of the compensation structure 80 can be adjusted by adjusting the size of the first electrode plate 802 or the second electrode plate 804 in the second direction Y. Fig.14D As shown, in the two compensation structures 80 with different compensation amounts, the first compensation parts 801 have the same size and shape, and the second compensation parts 803 have the same size and shape.

[0151] Fig.14E Schematic diagram of a display panel provided by an embodiment of the present disclosure. Fig.14E As shown, the compensation amounts of the compensation structures (compensation units) of different data lines may be different. In some embodiments of the present disclosure, in order to facilitate the setting of the compensation structure, the data lines may be grouped, and the compensation amounts of each group of data lines are the same, while the compensation amounts of data lines in different groups are different. For example, each group of data lines may include at least one data line. For example, the data lines in each group are adjacent data lines. For example, each group of first-type data lines includes a plurality of first-type data lines. For example, each group of second-type data lines includes at least one second-type data line.

[0152] Fig.14F A schematic diagram of a display panel provided according to an embodiment of the present disclosure. Figure 14G Schematic diagram of a display panel provided by an embodiment of the present disclosure. Fig.14F and Figure 14G As shown, the compensation amount of the compensation structure 80a (first compensation structure 80a) of the first type data line DTm is different from the compensation amount of the compensation structure 80b (second compensation structure 80b) of the second type data line DTn. Fig.14F and Figure 14G As shown, the compensation amount of the first compensation structure 80a of the first type data line DTm is different from the compensation amount of the second compensation structure 80b of the second type data line DTn adjacent to the first type data line DTm. For example, the compensation amount of the first compensation structure 80a is greater than the compensation amount of the second compensation structure 80b.

[0153] like Fig.14F and Figure 14G As shown, the second type data line DTn includes data line DTa, data line DTb and data line DTc, and the compensation amount of the second compensation unit 80b connected to the second type data line DTn is less than the compensation amount of the first compensation unit 80a connected to the first type data line DTm. Fig.14F and Figure 14G The compensation amounts of the compensation units 80 connected to the data lines DTa, DTb and DTc are the same as an example for description. In other embodiments, the compensation amounts of the compensation units 80 connected to the data lines DTa, DTb and DTc may also be different. Figure 14G The remaining data lines DT except the data line DTa, the data line DTb and the data line DTc are the first type data lines DTm.

[0154] Figure 14G The display panel shown is Fig.14F Compared with the display panel shown in FIG. 1 , in the two compensation structures 80 with different compensation amounts, the size and shape of the first compensation part 801 are the same, and the size and shape of the second compensation part 803 are the same. Figure 14G As shown in FIG. 8 , in two compensation structures 80 with different compensation amounts, the vias V1 are located on a straight line. Fig.14F In the display panel shown, the vias V1 are arranged in a staggered manner.

[0155] FIG. 14H to FIG. 14JIn the display panel shown, the orthographic projection of the first electrode plate 802 on the substrate substrate at least partially overlaps with the orthographic projection of the second electrode plate 804 on the substrate substrate. For example, the orthographic projection of the second electrode plate 804 on the substrate substrate falls within the orthographic projection of the first electrode plate 802 on the substrate substrate. In some embodiments, the orthographic projection of the first electrode plate 802 on the substrate substrate and the orthographic projection of the second electrode plate 804 on the substrate substrate may also overlap. In the display panel provided in the embodiment of the present disclosure, in order to facilitate the application of the signal, the first electrode plate 802 of the different compensation structures 80 is an integral structure, formed as one piece. For example, in the display panel provided in the embodiment of the present disclosure, in order to facilitate the application of the signal, the second electrode plate 804 of the different compensation structures 80 is an integral structure, formed as one piece.

[0156] For example, FIG. 14H to FIG. 14J As shown, on one side of the center line a0 of the display panel, the size of the first electrode plate 802 in the second direction Y gradually changes. For example, the size of the first electrode plate 802 in the second direction Y gradually changes in a step-like manner. FIG. 14H to FIG. 14J As shown, on one side of the center line a0 of the display panel, from a position away from the center line a0 to a position close to the center line a0, the size of the first electrode plate 802 in the second direction Y gradually decreases. Of course, in other embodiments, on one side of the center line a0 of the display panel, from a position away from the center line a0 to a position close to the center line a0, the size of the first electrode plate 802 in the second direction Y may also gradually increase. The second electrode plate 804 may have the same arrangement trend as the first electrode plate 802.

[0157] like Fig.14H As shown, for the second type of data line DTn, the length of the third part DT03 changes gradually. The closer the second part DT02 is to the center line a0, the longer the length of the third part DT03 is. According to the compensation amount of the compensation structure 82 (the second compensation structure 82) is inversely proportional to the length of the third part DT03, the closer the second compensation structure 82 is to the center line a0, the smaller its compensation amount is.

[0158] like FIG. 14H to FIG. 14J As shown, the first electrode plate 802 is symmetrically arranged relative to the center line a0, and the second electrode plate 804 is symmetrically arranged relative to the center line a0.

[0159] like Fig. 10A and Fig.14HAs shown, the second display area R2 is surrounded by the first display area R1. The second type of data line DTn also includes a fourth portion DT04 and a fifth portion DT05. The fourth portion DT04 extends along the second direction Y, the fifth portion DT05 extends along the first direction X, and the first portion DT01 and the fourth portion DT04 are connected through the fifth portion DT05. The fifth portion DT05 is located in the peripheral area R3. For example, in some embodiments, the first portion DT01 and the fourth portion DT04 are located in the same layer, and the fifth portion DT05 is not located in the same layer as the first portion DT01 and the fourth portion DT04. For example, in some embodiments, the fifth portion DT05 is located in the fourth conductive layer or the second conductive layer, and the first portion DT01 and the fourth portion DT04 are located in the third conductive layer, but is not limited thereto.

[0160] The layers where the various parts of the second type of data line DTn are located can be set as needed, as long as the two parts connected by the vias are located in different layers. For example, for the various parts of the second type of data line DTn, two parts with different extension directions are located in different layers. Of course, other methods can also be used, and each of the first part DT01 to the fifth part DT05 shown in the figure can also include sub-parts located in different layers.

[0161] like Fig. 10A and Fig.14H As shown, the fifth portion DT05 is located in the peripheral region R3, and the fourth portion DT04 extends from the display region R0 to the peripheral region R3. Fig. 10A and Fig.14H As shown, the fourth portion DT04 extends from the opposite side of the first display region R1 where the second portion DT02 is disposed in the second display region R2 to the peripheral region R3 .

[0162] like Fig. 10A and Fig.14H As shown, a plurality of first-type data lines DTm and a first portion DT01 of a plurality of second-type data lines DTn are arranged alternately. The number of first-type data lines DTm spaced between adjacent first portions DT01 is not limited to that shown in the figure and can be set as required.

[0163] For example, in the embodiment of the present disclosure, for the second type of data line DTn, the compensation structure is arranged at the position corresponding to the fourth portion DT04 of the peripheral region R3, and the compensation structure of the second type of data line DTn is not arranged at the position corresponding to the first portion DT01 of the second type of data line DTn. For example, at the position corresponding to the first portion DT01 of the second type of data line DTn, the compensation structure of the first type of data line DTn may be arranged. Of course, in a display panel (such as a display panel) where the fourth portion DT04 and the fifth portion DT05 are not arranged, 9A to 9CAs shown in FIG. 1 , for the second type data line DTn, the compensation structure is disposed at a position of the peripheral region R3 corresponding to the first portion DT01.

[0164] like Fig. 14B , Fig. 14C , Fig.14D , Fig.14I ,as well as Fig.14J As shown, the display panel further includes a second connection structure 850, and the data line DT is connected to a plurality of compensation structures 80 through the second connection structure 850. The second connection structure 850 may include a plurality of branches. For example, each branch is connected to a compensation structure 80. For example, the second connection structure 850 may be an integral structure with a portion of the data line DT close to the second connection structure 850, but is not limited thereto, and the second connection structure 850 may also be located at a different layer from a portion of the data line DT close to the second connection structure 850. The second connection structure 850 is made of a conductive material. For example, the second connection structure 850 may be located in the first conductive layer LY1, the second conductive layer LY2, the third conductive layer LY3, or the fourth conductive layer LY4. Fig.14I A portion of the data line DT located within the first display region R1 is not shown.

[0165] In the embodiment of the present disclosure, the compensation amount of the compensation structure can be adjusted by adjusting at least one of the first compensation part 801, the first electrode 802, the second compensation part 803, and the second electrode 804. For example, the compensation amount of the compensation structure can be adjusted by adjusting the length and width of the first compensation part 801 and the second compensation part 803, adjusting the facing area of ​​the first electrode 802 and the first compensation part 801, the facing area of ​​the first electrode 802 and the second compensation part 803, and the facing area of ​​the second electrode 804 and the second compensation part 803.

[0166] Fig.15 Schematic diagram of a display panel provided by an embodiment of the present disclosure. Fig.15 As shown, the compensation structure includes compensation unit 8001 , compensation unit 8002 , compensation unit 8003 , and compensation unit 8004 . Fig.15 In the figure, the compensation amount is represented by the length of the compensation structure 80 in the second direction. Fig.15 As shown, the compensation amounts of the various compensation structures 80 are different. Fig.15 As shown, the compensation amount of the compensation structure 8002 connected to the second type data line DTn is less than the compensation amounts of the compensation structures 8001, 8003 and 8004 connected to the first type data line DTm. Fig.15As shown, due to the difference in the length of the data lines in the fan-out region FR, the compensation amount of the compensation structure 8001 is smaller than the compensation amount of the compensation structure 8003, and the compensation amount of the compensation structure 8003 is smaller than the compensation amount of the compensation structure 8004. For example, for the compensation structure 80 connected to the first type of data line DTm, the closer to the edge of the display panel, the smaller the compensation amount. The closer to the center line a0 of the display panel, the larger the compensation amount.

[0167] Fig.15 Also shown is a data selector M0. Fig.15 As shown, one end of the data transmission line DTL is connected to at least two data lines DT through a data selector M0, and the other end of the data transmission line DTL is connected to an integrated circuit IC, and the data line DT is configured to input data signals to a plurality of pixel units 100. The data transmission line DTL can be regarded as a part of the data line DT. For example, the data line DT is configured to input data signals to a column of pixel units 100. For example, a data transmission line DTL inputs data signals to the data line DT connected thereto at different time periods through the data selector M0. Fig.15 In the figure, a data transmission line DTL is connected to two data lines DT through a data selector M0 as an example, but the present invention is not limited thereto. Fig.15 Components such as a data selector M0, a pixel unit 100, a data line DT and a data transmission line DTL are schematically shown, and the number of each component is not limited to that shown in the figure. Figure 1 The display area R1 and the peripheral area R2 located at least on one side of the display area R1 are shown. Figure 1 As shown, a plurality of data lines DT are arranged along a first direction X, and each data line DT extends along a second direction Y. The arrangement of the data selector M0 is conducive to obtaining a display panel with a high frame rate refresh rate. Fig.15 As shown, the fan-out region FR is located in the peripheral region R3.

[0168] For example, the position of the compensation structure 80 in the display panel provided by the embodiment of the present disclosure may be Fig.15 Of course, the compensation structure 80 can also be set in the same position as shown in the dashed box RP. Fig.14H and Fig.14I As shown. For example, the data line DT may be composed of a plurality of parts located in different layers, and the layers where the parts are located are set as needed. For example, the first part DT01 of the data line DT may be located in the third conductive layer LY3. The third part DT03 of the data line DT may be located in the second conductive layer LY2 or in the fourth conductive layer LY4. The second part DT02 of the data line DT may be located in the third conductive layer LY3.

[0169] For example, Fig.15As shown in FIG. 1 , the data line DT extends from the first display area R1 to the peripheral area R3. In some drawings, only a portion of the data line DT is shown, and the entire data line is not shown. Fig.14H As shown, for the second type data line DTn, the fourth portion DT04 is connected to the compensation structure 80. 9A to 10B As shown, for the second type data line DTn, the first portion DT01 is connected to the compensation structure 80 .

[0170] For example, refer to Figure 3 , the pixel unit 100 includes a first pixel unit 101 and a second pixel unit 102, the pixel circuit (first pixel circuit 10) and the light emitting element (first light emitting element 30) of the first pixel unit 101 are both located in the first display area R1, the pixel circuit (second pixel circuit 20) of the second pixel unit 102 is located in the first display area R1, the light emitting element (second light emitting element 40) of the second pixel unit 102 is located in the second display area R2, and the pixel circuit (second pixel circuit 20) of the second pixel unit 102 is connected to the light emitting element (second light emitting element 40) of the second pixel unit 102 through a conductive line L1. Reference Figure 5E , the orthographic projection of the conductive line L1 on the base substrate BS partially overlaps with the orthographic projection of the pixel circuit (first pixel circuit 10 ) of the first pixel unit 101 on the base substrate BS.

[0171] For example, refer to Figure 5B , the light emitting area of ​​the first light emitting element 30 is greater than the light emitting area of ​​the second light emitting element 40 , and the resolution of the first display area R1 is the same as the resolution of the second display area R2 .

[0172] refer to Figure 6 , Figures 8 to 9C , FIG. 10A to FIG. 10B , Fig.14H as well as Fig.15 As shown, the display panel further includes a dummy data line DM, which is a disconnected data line. The dummy data line DM is disconnected from the first portion DT01 of the second type data line DTn, and is located between two first type data lines DTm, and is disconnected from the first portion DT01 of a second type data line DTn located between the two first type data lines DTm. A portion of the second portion DT02 of the second type data line DTn and the third portion DT03 of the second type data line DTn are not located between the two first type data lines DTm. Fig.15 As shown, the dummy data line DM is not connected to the data selector M0. Fig.15As shown, the dummy data line DM is not connected to the integrated circuit IC. For example, the dummy data line DM can be connected to the constant voltage line, but is not limited thereto. For example, the pixel circuit overlapping the dummy data line DM can be a dummy pixel circuit, and the dummy pixel circuit is not connected to the light emitting element.

[0173] like Fig.9D , Fig.14D , FIG. 14H to FIG. 14J As shown, the orthographic projection of the first electrode plate 802 on the substrate and the orthographic projection of the second electrode plate 804 on the substrate partially overlap, but do not coincide. Of course, the orthographic projection of the first electrode plate 802 on the substrate and the orthographic projection of the second electrode plate 804 on the substrate in these figures can also be set to coincide. In the display panels shown in other figures, the orthographic projection of the first electrode plate 802 on the substrate and the orthographic projection of the second electrode plate 804 on the substrate in the compensation structure coincide, and of course, they can also be set not to coincide.

[0174] The embodiments of the present disclosure are described by taking each compensation structure including three parallel capacitors as an example, but are not limited thereto, and more parallel capacitors may be provided as required. In other embodiments, each compensation structure may include one or two of the three parallel capacitors. Fig.12 As shown, the display panel may include one or two of the first compensation capacitor C1, the second compensation capacitor C2, and the third compensation capacitor C3. For example, the capacitance of the first compensation capacitor C1 is greater than the capacitance of the third compensation capacitor C3, and the capacitance of the second compensation capacitor C2 is greater than the capacitance of the third compensation capacitor C3. For example, the capacitance of the first compensation capacitor C1 is greater than the capacitance of the second compensation capacitor C2. For example, the compensation amount of the compensation capacitor is related to the facing area of ​​the compensation plates and the material and thickness of the insulating layer between the compensation plates.

[0175] Fig.16A It is a schematic diagram of a pixel circuit in a display panel provided by an embodiment of the present disclosure. Fig. 16B It is a layout diagram of a pixel circuit in a display panel provided by an embodiment of the present disclosure. Fig. 16C for Fig. 16B A cross-sectional view along line AB. Fig.16D It is a layout diagram of a pixel circuit in a display panel provided by an embodiment of the present disclosure. Fig.16E for Fig.16D A cross-sectional view along line CD. Fig.16F It is a partial schematic diagram of a display panel provided by an embodiment of the present disclosure.

[0176] Fig.16AThe pixel circuit shown may be a pixel circuit of a low temperature polysilicon (LTPS) AMOLED commonly used in the related art.

[0177] Fig.16A FIG. 4 shows a pixel circuit of a pixel unit of a display panel, such as Fig.16A As shown, the pixel unit 100 includes a pixel circuit 100a and a light-emitting element 100b. The pixel circuit 100a includes six switch transistors (T2-T7), a drive transistor T1 and a storage capacitor Cst. The six switch transistors are respectively a data write transistor T2, a threshold compensation transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, a first reset transistor T6, and a second reset transistor T7. The light-emitting element 100b includes a first pole E1 and a second pole E2 and a light-emitting functional layer located between the first pole E1 and the second pole E2. For example, the first pole E1 is an anode and the second pole E2 is a cathode. Typically, the threshold compensation transistor T3 and the first reset transistor T6 use a dual-gate thin film transistor (TFT) to reduce leakage.

[0178] like Fig.16AAs shown, the display panel includes a gate line GT, a data line DT, a first power line PL1, a second power line PL2, a light-emitting control signal line EML, an initialization signal line INT, a reset control signal line RST, etc. For example, the reset control signal line RST includes a first reset control signal line RST1 and a second reset control signal line RST2. The first power line PL1 is configured to provide a constant first voltage signal VDD to the pixel unit 100, the second power line PL2 is configured to provide a constant second voltage signal VSS to the pixel unit 100, and the first voltage signal VDD is greater than the second voltage signal VSS. The gate line GT is configured to provide a scan signal SCAN to the pixel unit 100, the data line DT is configured to provide a data signal DATA (data voltage VDATA) to the pixel unit 100, the light-emitting control signal line EML is configured to provide a light-emitting control signal EM to the pixel unit 100, the first reset control signal line RST1 is configured to provide a first reset control signal RESET1 to the pixel unit 100, and the second reset control signal line RST2 is configured to provide a scan signal SCAN to the pixel unit 100. The first initialization signal line INT1 is configured to provide a first initialization signal Vinit1 to the pixel unit 100. The second initialization signal line INT2 is configured to provide a second initialization signal Vinit2 to the pixel unit 100. For example, the first initialization signal Vinit1 and the second initialization signal Vinit2 are constant voltage signals, and their magnitudes may be, for example, between the first voltage signal VDD and the second voltage signal VSS, but are not limited thereto, for example, the first initialization signal Vinit1 and the second initialization signal Vinit2 may both be less than or equal to the second voltage signal VSS. For example, in some embodiments, the first initialization signal line INT1 and the second initialization signal line INT1 are connected, and are both configured to provide the initialization signal Vinit to the pixel unit 100, that is, the first initialization signal line INT1 and the second initialization signal line INT2 are both referred to as initialization signal lines INT, and the first initialization signal Vinit1 and the second initialization signal Vinit2 are equal, and are both Vinit.

[0179] like Fig.16A As shown, the driving transistor T1 is electrically connected to the light emitting element 100b, and outputs a driving current to drive the light emitting element 100b to emit light under the control of the scan signal SCAN, the data signal DATA, the first voltage signal VDD, the second voltage signal VSS and other signals.

[0180] For example, the light emitting element 100b includes an organic light emitting diode (OLED), and the light emitting element 100b emits red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit 100a. For example, a pixel includes a plurality of pixel units. A pixel may include a plurality of pixel units that emit light of different colors. For example, a pixel includes a pixel unit that emits red light, a pixel unit that emits green light, and a pixel unit that emits blue light, but is not limited thereto. The number of pixel units included in a pixel and the light emission of each pixel unit can be determined as required.

[0181] For example, Fig.16A As shown, the gate T20 of the data writing transistor T2 is connected to the gate line GT, the first electrode T21 of the data writing transistor T2 is connected to the data line DT, and the second electrode T22 of the data writing transistor T2 is connected to the first electrode T11 of the driving transistor T1.

[0182] For example, Fig.16A As shown, the pixel circuit 100a further includes a threshold compensation transistor T3, a gate T30 of the threshold compensation transistor T3 is connected to the gate line GT, a first electrode T31 of the threshold compensation transistor T3 is connected to the second electrode T12 of the driving transistor T1, and a second electrode T32 of the threshold compensation transistor T3 is connected to the gate T10 of the driving transistor T1.

[0183] For example, Fig.16A As shown, the display panel also includes a light-emitting control signal line EML, and the pixel circuit 100a also includes a first light-emitting control transistor T4 and a second light-emitting control transistor T5, a gate T40 of the first light-emitting control transistor T4 is connected to the light-emitting control signal line EML, a first electrode T41 of the first light-emitting control transistor T4 is connected to the first power line PL1, and a second electrode T42 of the first light-emitting control transistor T4 is connected to a first electrode T11 of the driving transistor T1; a gate T50 of the second light-emitting control transistor T5 is connected to the light-emitting control signal line EML, a first electrode T51 of the second light-emitting control transistor T5 is connected to a second electrode T12 of the driving transistor T1, and a second electrode T52 of the second light-emitting control transistor T5 is connected to a first electrode E1 of the light-emitting element 100b.

[0184] like Fig.16AAs shown, the first reset transistor T6 is connected to the gate T10 of the driving transistor T1 and is configured to reset the gate of the driving transistor T1, and the second reset transistor T7 is connected to the first electrode E1 of the light emitting element 100b and is configured to reset the first electrode E1 of the light emitting element 100b. The first initialization signal line INT1 is connected to the gate of the driving transistor T1 through the first reset transistor T6. The second initialization signal line INT2 is connected to the first electrode E1 of the light emitting element 100b through the second reset transistor T7. For example, the first initialization signal line INT1 and the second initialization signal line INT2 are connected to be input with the same initialization signal, but not limited to this. In some embodiments, the first initialization signal line INT1 and the second initialization signal line INT2 can also be insulated from each other and configured to input signals separately.

[0185] For example, Fig.16A As shown, the first electrode T61 of the first reset transistor T6 is connected to the first initialization signal line INT1, the second electrode T62 of the first reset transistor T6 is connected to the gate T10 of the driving transistor T1, the first electrode T71 of the second reset transistor T7 is connected to the second initialization signal line INT2, and the second electrode T72 of the second reset transistor T7 is connected to the first electrode E1 of the light emitting element 100b. Fig.16A As shown, the gate T60 of the first reset transistor T6 is connected to the first reset control signal line RST1, and the gate T70 of the second reset transistor T7 is connected to the second reset control signal line RST2.

[0186] like Fig.16A As shown, the first power line PL1 is configured to provide a first voltage signal VDD to the pixel circuit 100a; the pixel circuit also includes a storage capacitor Cst, a first electrode Ca of the storage capacitor Cst is connected to the gate T10 of the driving transistor T1, and a second electrode Cb of the storage capacitor Cst is connected to the first power line PL1.

[0187] For example, Fig.16A As shown, the display panel further includes a second power line PL2, and the second power line PL2 is connected to the second electrode 201 of the light emitting element 100b.

[0188] Fig.16A , a first node N1, a second node N2, a third node N3, and a fourth node N4 are shown. For example, in some embodiments, reference Figure 5C , Figure 5E and Fig.16A A capacitor is formed between the first node N1 and the conductive line L1, a capacitor is formed between the conductive line L1 and the fourth node N4, and the conductive line L1 is coupled with the first node N1 and the fourth node N4 respectively, thereby causing brightness differences and forming display defects such as stripes (Mura), which affects the display quality.

[0189] like Fig. 16B As shown, the pixel circuit includes a driving transistor T1, and the driving transistor includes a gate T10. Fig. 16B and Fig. 16C The second electrode Cb of the storage capacitor Cst has an opening OPN1, and one end of the connection electrode CE1 is connected to the gate T10 of the driving transistor T1 through the opening OPN1. The connection electrode CE1 may also be referred to as a first gate signal line SL1. Fig. 16B As shown, the first gate signal line SL1 is connected to the gate T10 of the driving transistor T1.

[0190] like Fig. 16B As shown, the first gate signal line SL1 is connected to the second gate signal line SL2. The gate T10 of the driving transistor T1, the first gate signal line SL1, and the second gate signal line SL2 constitute the gate signal portion PT1. The potential on the gate signal portion PT1 is the same. Of course, in other embodiments, the second gate signal line SL2 may not be provided. In this case, the gate T10 of the driving transistor T1 and the first gate signal line SL1 constitute the gate signal portion PT1. For example, the second gate signal line SL2 is the second electrode T62 of the first reset transistor T6.

[0191] refer to Fig. 16B and Fig. 16C In order to stabilize the potential on the gate signal portion PT1, the display panel provided by the embodiment of the present disclosure provides a shielding electrode SE and a constant voltage line L0, and the constant voltage line L0 is configured to provide a constant voltage to the pixel circuit. The shielding electrode SE is connected to the constant voltage line L0, so that the voltage on the shielding electrode SE is stable, which can play a shielding role and prevent the conductive line L1 from affecting the potential on the gate signal portion PT1. The positive projection of the first gate signal line SL1 on the base substrate BS falls within the positive projection of the shielding electrode SE on the base substrate BS. Fig. 16B As shown, the shielding electrode SE is connected to the first power line PL1 through the via hole H21.

[0192] refer to FIG. 16B to FIG. 16D In order to make the shielding electrode play a better shielding role and increase the shielding amount, the orthographic projection of the first gate signal line SL1 on the base substrate BS completely falls within the orthographic projection of the shielding electrode SE on the base substrate BS.

[0193] For example, in order to reduce display defects (mura) and improve display effects, the distance between the orthographic projection of the first gate signal line SL1 on the substrate BS and the boundary of the orthographic projection of the shielding electrode SE on the substrate BS is greater than or equal to 1.75 μm. Because the area occupied by the pixel unit is limited, the distance of the shielding electrode SE beyond the first gate signal line SL1 can be limited. For example, in some embodiments, in order to obtain a better shielding effect, the distance between the orthographic projection of the first gate signal line SL1 on the substrate BS and the boundary of the orthographic projection of the shielding electrode SE on the substrate BS is greater than or equal to 2.33 μm.

[0194] like Fig. 16B As shown, the display panel further includes a block BK, the block BK is connected to the first power line PL1, the threshold compensation transistor T3 includes a first channel CN1 and a second channel CN2, the first channel CN1 and the second channel CN2 are connected through a conductive connection portion CP; the orthographic projection of the block BK on the base substrate BS at least partially overlaps with the orthographic projection of the conductive connection portion CP of the threshold compensation transistor T3 on the base substrate BS. Fig. 16B As shown, the blocking block BK of the adjacent column of pixel units is used to shield the conductive connection portion CP of the threshold compensation transistor T3 of the pixel unit in the same column.

[0195] For example, Fig. 16B , 6 As shown in G and 6H, in the case where the display panel includes a second gate signal line SL2, the second gate signal line SL2 is connected to the first gate signal line SL1, and the orthographic projection of the second gate signal line SL2 on the substrate substrate BS falls within the orthographic projection of the block BK on the substrate substrate BS. Further, for example, the boundary of the orthographic projection of the block BK on the substrate substrate BS exceeds the boundary of the orthographic projection of the second gate signal line SL2 on the substrate substrate BS. For example, the distance that the boundary of the orthographic projection of the block BK on the substrate substrate BS exceeds the boundary of the orthographic projection of the second gate signal line SL2 on the substrate substrate BS is greater than or equal to 1.75μm. For example, the distance that the boundary of the orthographic projection of the block BK on the substrate substrate BS exceeds the boundary of the orthographic projection of the second gate signal line SL2 on the substrate substrate BS is greater than or equal to 2.33μm. Of course, in other embodiments, the shielding electrode SE may be used to replace the function of the block BK, or the orthographic projection of the second gate signal line SL2 on the base substrate BS falls within both the orthographic projection of the block BK on the base substrate BS and the orthographic projection of the shielding electrode SE on the base substrate BS (e.g. Fig.17 shown).

[0196] For example, the first gate signal line SL1 and the second gate signal line SL2 are made of different materials. For example, the first gate signal line SL1 is made of metal, and the second gate signal line SL2 is made of a conductive material formed by converting a semiconductor material into a conductor.

[0197] For example, Fig. 16B and Fig.16D As shown, in order to save wiring, the first power line PL1 is used as the constant voltage line L0. In other embodiments, in order to save wiring, the first initialization signal line INL1 can also be used as the constant voltage line or the second initialization signal line INL2 can be used as the constant voltage line. The example of the constant voltage line L0 is not limited to the first power line PL1, the first initialization signal line INL1 and the second initialization signal line INL2. As long as it is a signal line that provides a constant voltage in the pixel circuit, it can be used as the constant voltage line L0. The embodiment of the present disclosure is explained by taking the first power line PL1 as the constant voltage line L0 as an example. When a signal line that provides a constant voltage other than the first power line PL1 is used as the constant voltage line L0, the shape of the shielding electrode SE can be adjusted so that it is connected to the signal line that provides the constant voltage.

[0198] like Fig.16F As shown, the conductive line L1 includes a first portion L1a, a second portion L1b and a third portion L1c. The first portion L1a and the third portion L1c both extend along the second direction Y, and the second portion L1b extends along the first direction X. For example, the first portion L1a and the third portion L1c are located in the same conductor pattern layer, and the second portion L1b is located in another conductor pattern layer. Fig.16F The medium grey filled areas represent vias used to connect different parts of the conductive lines.

[0199] Fig.16F The via Ha and the via Hb are shown. The first part L1a and the second part L1b are connected by the via Ha penetrating the insulating layer, and the second part L1b and the third part L1c are connected by the via Hb penetrating the insulating layer. For example, Fig.16F Three conductive lines L1 are shown, and the conductive lines L10 and L100 have similar structures.

[0200] Of course, in other embodiments, the entire conductive line may be located in the same conductor pattern layer. That is, the first portion L1a, the second portion L1b, and the third portion L1c are located in the same conductor pattern layer. For example, in other embodiments, three adjacent conductive lines L1 in the second direction Y are located in the first conductor pattern layer, the second conductor pattern layer, and the third conductor pattern layer, respectively. The arrangement of the conductive lines may be determined as required.

[0201] like Fig.16F As shown, the orthographic projection of the conductive line L1 on the base substrate BS partially overlaps with the orthographic projection of the pixel circuit (first pixel circuit 10) of the first pixel unit 101 on the base substrate BS. Fig.16FAs shown, the shielding electrode SE is located between the conductive line L1 and the first gate signal line SL1. In the embodiment of the present disclosure, after forming the pixel circuit, the shielding electrode SE is formed, and then the conductive line L1 is formed, and then the light emitting element is formed. Thus, the shielding electrode SE is located between the conductive line L1 and the first gate signal line SL1, and the shielding electrode SE is located between the conductive line L1 and the gate T10 of the driving transistor (refer to Figure 16G and Fig.16H ).

[0202] For clarity of illustration, Fig.16F Only a part of the structure of the pixel circuit is shown in FIG. A conductive line L1 is provided in the auxiliary area, and no conductive line L1 is provided in the area of ​​the first display area other than the auxiliary area, so that the orthographic projection of the pixel circuit (first pixel circuit) in the area of ​​the first display area other than the auxiliary area on the base substrate BS does not overlap with the orthographic projection of the conductive line L1 on the base substrate BS.

[0203] like Fig.16F As shown, the orthographic projection of the conductive line L1 on the base substrate BS partially overlaps with the orthographic projection of the first gate signal line SL1 in the pixel circuit of the first pixel unit 101 .

[0204] Fig.16F Via HL and via HE are shown. Fig.16F As shown, one end of the conductive line L10 is connected to the second pixel circuit 20 through the via hole HL, and the other end of the conductive line L10 is connected to the first electrode E1 of the second light emitting element 40 through the via hole HE.

[0205] refer to Fig. 16C and Fig.16EA buffer layer BL is disposed on the substrate BS, an isolation layer BR is disposed on the buffer layer BL, an active layer LY0 is disposed on the isolation layer BR, a first insulating layer ISL1 is disposed on the active layer LY0, a first conductive layer LY1 is disposed on the first insulating layer ISL1, a second insulating layer ISL2 is disposed on the first conductive layer LY1, a second conductive layer LY2 is disposed on the second insulating layer ISL2, a third insulating layer ISL3 is disposed on the second conductive layer LY2, a third conductive layer LY3 is disposed on the third insulating layer ISL3, and the third conductive layer LY3 includes a connecting electrode CE01, and the connecting electrode CE01 passes through the first insulating layer ISL1, the second insulating layer ISL2 and The via hole H3 of the third insulating layer ISL3 is connected to the second electrode T52 of the second light emitting control transistor T5, a fourth insulating layer ISL4 and a fifth insulating layer ISL5 are arranged on the third conductive layer LY3, a fourth conductive layer LY4 is arranged on the fourth insulating layer ISL4 and the fifth insulating layer ISL5, the fourth conductive layer LY4 includes a connecting electrode CE02, the connecting electrode CE02 is connected to the connecting electrode CE01 through a via hole H22 penetrating the fourth insulating layer ISL4 and the fifth insulating layer ISL5, a sixth insulating layer ISL6 is arranged on the fourth conductive layer LY4, and the light emitting element 100b (the second light emitting element 30) is connected to the light emitting element 100b (the second light emitting element 30) through a via hole H31 penetrating the sixth insulating layer ISL6. Fig.16D and Fig.16E The light emitting element 100b includes a first electrode E1, a second electrode E2, and a light emitting functional layer FL located between the first electrode E1 and the second electrode E2. For example, the connecting element CE0 includes a connecting electrode CE01 and a connecting electrode CE02.

[0206] like Fig. 16B As shown, one end of the connection electrode CE1 is connected to the gate T10 of the driving transistor T1 through the via H1, and the other end of the connection electrode CE1 is connected to the second electrode T62 of the first reset transistor T6 through the via H2. One end of the connection electrode CE2 is connected to the first initialization signal line INL1 through the via H4, and the other end of the connection electrode CE2 is connected to the first electrode T61 of the first reset transistor T6 through the via H5. One end of the connection electrode CE3 is connected to the second initialization signal line INL2 through the via H6, and the other end of the connection electrode CE3 is connected to the first electrode T71 of the second reset transistor T7 through the via H7. The first power line PL1 is connected to the first electrode T41 of the first light-emitting control transistor T4 through the via H8. The first power line PL1 is connected to the second electrode Cb of the storage capacitor Cst through the via H9. The first power line PL1 is connected to the block BK through the via Hk. The data line DT is connected to the first electrode T21 of the data writing transistor T2 through the via H0.

[0207] For example, in the manufacturing process of the display panel, a self-alignment process is adopted to conduct the semiconductor pattern layer using the first conductive layer LY1 as a mask. The semiconductor pattern layer can be formed by patterning a semiconductor thin film. For example, the semiconductor pattern layer is heavily doped by ion implantation, so that the portion of the semiconductor pattern layer not covered by the first conductive layer LY1 is conductive, forming the source region (first electrode T11) and drain region (second electrode T12) of the driving transistor T1, the source region (first electrode T21) and drain region (second electrode T22) of the data writing transistor T2, the source region (first electrode T31) and drain region (second electrode T32) of the threshold compensation transistor T3, the source region (first electrode T41) and drain region (second electrode T42) of the first light emission control transistor T4, the source region (first electrode T51) and drain region (second electrode T52) of the second light emission control transistor T5, the source region (first electrode T61) and drain region (second electrode T62) of the first reset transistor T6, and the source region (first electrode T71) and drain region (second electrode T72) of the second reset transistor T7. The portion of the semiconductor pattern layer covered by the first conductive layer LY1 retains semiconductor characteristics, forming a channel region of the driving transistor T1, a channel region of the data writing transistor T2, a channel region of the threshold compensation transistor T3, a channel region of the first light emission control transistor T4, a channel region of the second light emission control transistor T5, a channel region of the first reset transistor T6, and a channel region of the second reset transistor T7. For example, Fig. 16B As shown, the second electrode T72 of the second reset transistor T7 and the second electrode T52 of the second light-emitting control transistor T5 are formed in one piece; the first electrode T51 of the second light-emitting control transistor T5, the second electrode T12 of the driving transistor T1 and the first electrode T31 of the threshold compensation transistor T3 are formed in one piece; the first electrode T11 of the driving transistor T1, the second electrode T22 of the data writing transistor T2 and the second electrode T42 of the first light-emitting control transistor T4 are formed in one piece; the second electrode T32 of the threshold compensation transistor T3 and the second electrode T62 of the first reset transistor T6 are formed in one piece. In some embodiments, Fig. 16B As shown, the first electrode T71 of the second reset transistor T7 and the first electrode T61 of the first reset transistor T6 can be formed integrally.

[0208] For example, the channel region of the transistor used in the embodiment of the present disclosure may be single crystal silicon, polycrystalline silicon (e.g., low temperature polycrystalline silicon) or metal oxide semiconductor material (e.g., IGZO, AZO, etc.). In one embodiment, the transistors are all P-type low temperature polycrystalline silicon (LTPS) thin film transistors. In another embodiment, the threshold compensation transistor T3 and the first reset transistor T6 directly connected to the gate of the driving transistor T1 are metal oxide semiconductor thin film transistors, that is, the channel material of the transistor is a metal oxide semiconductor material (e.g., IGZO, AZO, etc.), and the metal oxide semiconductor thin film transistor has a lower leakage current, which can help reduce the gate leakage current of the driving transistor T1.

[0209] For example, the transistors used in the embodiments of the present disclosure may include a variety of structures, such as top-gate, bottom-gate or dual-gate structures. In one embodiment, the threshold compensation transistor T3 and the first reset transistor T6 directly connected to the gate of the driving transistor T1 are dual-gate thin film transistors, which can help reduce the gate leakage current of the driving transistor T1.

[0210] For example, Fig.16E As shown, the display panel further includes a pixel definition layer PDL and a spacer PS, wherein the pixel definition layer PDL has an opening OPN, and the opening OPN is configured to define the light emitting area (light emitting area, effective light emitting area) of the pixel unit. The spacer PS is configured to support the fine metal mask when forming the light emitting functional layer FL.

[0211] For example, the opening OPN is a light emitting area of ​​the pixel unit. The light emitting function layer FL is located on the first electrode E1 of the light emitting element 100b, and the second electrode E2 of the light emitting element 100b is located on the light emitting function layer FL. Fig.16E As shown, a packaging layer CPS is provided on the light emitting element 100b. The packaging layer CPS includes a first packaging layer CPS1, a second packaging layer CPS2, and a third packaging layer CPS3. For example, the first packaging layer CPS1 and the third packaging layer CPS3 are inorganic material layers, and the second packaging layer CPS2 is an organic material layer. For example, the first electrode E1 is an anode of the light emitting element 100b, and the second electrode E2 is a cathode of the light emitting element 100b, but is not limited thereto.

[0212] Figure 16G It is a partial schematic diagram of a display panel provided by an embodiment of the present disclosure. Figure 16G A plurality of conductive lines L1 are shown. For example, the conductive lines L1 extend along a first direction X, and the plurality of conductive lines L1 are arranged along a second direction Y, but this is not limited thereto. Figure 16G Four conductive lines L1 are shown, however, the conductive lines L1 may be as many as desired. Figure 16G The pixel unit shown is a first pixel unit 101, Figure 16GThe pixel circuit shown is a first pixel circuit 10. The display panel provided by the embodiment of the present disclosure further includes a first pixel unit 101 that does not overlap with the conductive line L1. For example, the first pixel unit 101 that does not overlap with the conductive line L1 is located in the first display area except the auxiliary area. Figure 16G Each conductive line L1 shown is used to connect the second pixel circuit 20 and the second light emitting element 40 located at the left and right sides of the first pixel unit 101 respectively.

[0213] Fig.16H It is a partial schematic diagram of a display panel provided by an embodiment of the present disclosure. Fig.16H A plurality of conductive lines L1 are shown. For example, the conductive lines L1 extend along a first direction X, and the plurality of conductive lines L1 are arranged along a second direction Y, but this is not limited thereto. Figure 16G Four conductive lines L1 are shown, however, the conductive lines L1 may be as many as desired. Figure 16G The pixel unit shown is the second pixel circuit 20 of the second pixel unit 102. Fig.16H As shown, one of the plurality of conductive lines L1 is connected to the second pixel unit 102, and the remaining conductive lines L1 are not connected to the second pixel unit 102. For example, the conductive line L10 (one of the plurality of conductive lines L1) is connected to the connecting element CE0 of the second pixel unit 102 through the via hole HL penetrating the insulating layer. For further example, the conductive line L10 is connected to the connecting electrode CE02 of the connecting element CE0 of the second pixel unit 102 through the via hole HL penetrating the insulating layer. The conductive line L10 is used to be connected to the first electrode E1 of the second light-emitting element 40 located in the second display area.

[0214] Fig.17 A layout diagram of a first pixel circuit or a second pixel circuit in a display panel provided in an embodiment of the present disclosure. Fig.17 As shown, the orthographic projection of the gate T10 of the driving transistor T1 on the substrate BS falls within the orthographic projection of the shielding electrode SE on the substrate BS.

[0215] For example, Fig.17As shown, in the case where the display panel includes a second gate signal line SL2, the second gate signal line SL2 is connected to the first gate signal line SL1, and the orthographic projection of the second gate signal line SL2 on the substrate BS also falls within the orthographic projection of the shielding electrode SE on the substrate BS. For example, the boundary of the orthographic projection of the shielding electrode SE on the substrate BS exceeds the boundary of the orthographic projection of the second gate signal line SL2 on the substrate BS. For example, the distance that the boundary of the orthographic projection of the shielding electrode SE on the substrate BS exceeds the boundary of the orthographic projection of the second gate signal line SL2 on the substrate BS is greater than or equal to 1.75μm. For example, the distance that the boundary of the orthographic projection of the shielding electrode SE on the substrate BS exceeds the boundary of the orthographic projection of the second gate signal line SL2 on the substrate BS is greater than or equal to 2.33μm.

[0216] For example, Fig.17 As shown, the orthographic projections of the gate T10 of the driving transistor T1 , the first gate signal line SL1 , and the second gate signal line SL2 on the base substrate BS all fall within the orthographic projection of the shielding electrode SE on the base substrate BS.

[0217] For example, Fig.17 As shown, the orthographic projection of the shielding electrode SE on the base substrate BS partially overlaps with the orthographic projection of the second gate signal line SL2 on the base substrate BS, and the orthographic projection of the block BK on the base substrate BS partially overlaps with the orthographic projection of the second gate signal line SL2 on the base substrate BS. Fig.17 In the display panel shown, the shielding electrode SE and the block BK form a double-layer shielding for the second gate signal line SL2.

[0218] For example, Fig.17 As shown, the orthographic projection of the shielding electrode SE on the base substrate BS partially overlaps with the orthographic projection of the block BK on the base substrate BS.

[0219] Of course, in other embodiments, the block BK may not be provided, or the orthographic projection of the block BK on the base substrate BS does not overlap with the orthographic projection of the second gate signal line SL2 on the base substrate BS.

[0220] For example, Fig. 16B and Fig.16DAs shown, the orthographic projection of the block BK on the base substrate BS partially overlaps with the orthographic projection of the second gate signal line SL2 on the base substrate BS, and the orthographic projection of the shielding electrode SE on the base substrate BS partially overlaps with the orthographic projection of the first gate signal line SL1 on the base substrate BS, so that the block BK and the shielding electrode SE together play a role in shielding the gate signal portion PT1. Of course, in some other embodiments, the block BK may not be provided, or the orthographic projection of the block BK on the base substrate BS does not overlap with the orthographic projection of the second gate signal line SL2 on the base substrate BS.

[0221] For example, Fig. 16B and Fig.16D As shown, the left block BK extends to the pixel unit on the left side of the pixel unit shown in the figure to block the conductive connection portion CP of its threshold compensation transistor T3, and the right block BK extends from the block BK connected to the pixel unit on the right side of the pixel unit shown in the figure.

[0222] like Fig. 16B , Fig.16D ,as well as Fig.17 As shown, the channels of each transistor and the first and second electrodes on both sides of the channels are located in the active layer LY0; the first reset control signal line RST1, the gate line GT, the gate T10 of the driving transistor (the first electrode Ca of the storage capacitor Cst), the light emitting control signal line EML and the second reset control signal line RST2 are located in the first conductive layer LY1; the first initialization signal line INL1, the second electrode Cb of the storage capacitor Cst, and the second initialization signal line INL2 are located in the second conductive layer LY2; the data line DT, the first power line PL1, the connecting electrode CE1, the connecting electrode CE2, the connecting electrode CE3, and the connecting electrode CE01 are located in the third conductive layer LY3; the shielding electrode SE is located in the fourth conductive layer LY4. Fig. 16B , Fig.16D ,as well as Fig.17 As shown, the first initialization signal line INL1, the first reset control signal line RST1, the gate line GT, the light emitting control signal line EML, the second initialization signal line INL2 and the second reset control signal line RST2 all extend along the first direction X. Fig. 16B , Fig.16D ,as well as Fig.17 As shown, the data line DT and the first power line PL1 both extend along the second direction Y.

[0223] In the embodiments of the present disclosure, the orthographic projection of component A on substrate BS falls within the orthographic projection of component B on substrate BS means that the orthographic projection of component A on substrate BS completely falls within the orthographic projection of component B on substrate BS, that is, the orthographic projection of component A on substrate BS covers the orthographic projection of component B on substrate BS, and the area of ​​the orthographic projection of component A on substrate BS is less than or equal to the area of ​​the orthographic projection of component B on substrate BS.

[0224] For example, in some embodiments of the present disclosure, each pixel circuit 100a is provided with any shielding electrode SE as described above. That is, no matter the first pixel circuit 10 of the first pixel unit 101 or the second pixel circuit 20 of the second pixel unit 102, it is provided with any shielding electrode SE as described above. Fig.16F It is shown that the first pixel circuit 10 of the first pixel unit 101 includes a shielding electrode SE, and the second pixel circuit 20 of the second pixel unit 102 includes a shielding electrode SE. Of course, the shielding electrode SE may also be in other forms, for example, Fig.16F The shield electrode shown can also be replaced by Fig.17 The shield electrode shown or Fig.17 B shows the shield electrode.

[0225] For example, the transistors in the pixel circuit of the embodiment of the present disclosure are all thin film transistors. For example, the first conductive layer LY1, the second conductive layer LY2, the third conductive layer LY3, and the fourth conductive layer LY4 are all made of metal materials. For example, the first conductive layer LY1 and the second conductive layer LY2 are formed of metal materials such as nickel and aluminum, but not limited thereto. For example, the third conductive layer LY3 and the fourth conductive layer LY4 are formed of materials such as titanium and aluminum, but not limited thereto. For example, the third conductive layer LY3 and the fourth conductive layer LY4 are respectively formed of three sub-layers of Ti / AL / Ti, but not limited thereto. For example, the substrate substrate can be a glass substrate or a polyimide substrate, but not limited thereto, and can be selected as needed. For example, the buffer layer BL, the isolation layer BR, the first insulating layer ISL1, the second insulating layer ISL2, the third insulating layer ISL3, the fourth insulating layer IS4, the fifth insulating layer ISL5, and the sixth insulating layer ISL6 are all made of insulating materials. The materials of the first pole E1 and the second pole E2 of the light-emitting element can be selected as needed. In some embodiments, the first pole E1 can be made of at least one of a transparent conductive metal oxide and silver, but not limited thereto. For example, the transparent conductive metal oxide includes indium tin oxide (ITO), but is not limited thereto. For example, the first electrode E1 may adopt a structure in which three sub-layers of ITO-Ag-ITO are stacked. In some embodiments, the second electrode E2 may be a metal with a low work function, and may be at least one of magnesium and silver, but is not limited thereto.

[0226] For example, in an embodiment of the present disclosure, the thickness of the fifth insulating layer ISL5 is greater than the thickness of at least one of the fourth insulating layer ISL4, the third insulating layer ISL3, the second insulating layer ISL2, and the first insulating layer ISL1. In some embodiments, the thickness of the fifth insulating layer ISL5 is greater than the thickness of each of the fourth insulating layer ISL4, the third insulating layer ISL3, the second insulating layer ISL2, and the first insulating layer ISL1. For example, the buffer layer BL, the isolation layer BR, the first insulating layer ISL1, the second insulating layer ISL2, the third insulating layer ISL3, the fourth insulating layer ISL4, and the fifth insulating layer ISL5 are all made of insulating materials. At least one of the materials of the buffer layer BL, the isolation layer BR, the first insulating layer ISL1, the second insulating layer ISL2, the third insulating layer ISL3, and the fourth insulating layer ISL4 is made of an inorganic insulating material, and the fifth insulating layer ISL5 can be made of an organic material. For example, the inorganic insulating material includes at least one of silicon oxide, silicon nitride, and silicon oxynitride, but is not limited thereto. For example, the organic material includes a resin, but is not limited thereto.

[0227] For example, referring to the layout diagram and the cross-sectional diagram of the embodiments of the present disclosure, the display panel provided by at least one embodiment of the present disclosure may be manufactured by the following method.

[0228] (1) A buffer layer BL and a spacer layer BR are formed on a base substrate BS.

[0229] (2) A semiconductor thin film is formed on the isolation layer BR.

[0230] (3) Patterning the semiconductor film to form a semiconductor pattern layer.

[0231] (4) A first insulating film is formed on the semiconductor pattern layer.

[0232] (5) A first conductive film is formed on the first insulating film, and the first conductive film is patterned to form a first conductive layer LY1.

[0233] (6) The semiconductor pattern layer is doped using the first conductive layer LY1 as a mask to form an active layer LY0.

[0234] (7) A second insulating film is formed on the first conductive layer LY1.

[0235] (8) A second conductive film is formed on the second insulating layer ISL2, and the second conductive film is patterned to form a second conductive layer LY2.

[0236] (9) A third insulating film is formed on the second conductive layer LY2.

[0237] (10) At least one of the first insulating film, the second insulating film, and the third insulating film is patterned to form a first insulating layer ISL1, a second insulating layer ISL2, and a third insulating layer ISL3 while forming via holes.

[0238] (11) A third conductive film is formed and patterned to form a third conductive layer LY3. Each component in the third conductive layer LY3 is connected to the components located therebelow through via holes.

[0239] (12) A fourth insulating film and a fifth insulating film are formed, and the fourth insulating film and the fifth insulating film are patterned to form a fourth insulating layer ISL4 and a fifth insulating layer ISL5 while forming via holes.

[0240] (13) A fourth conductive film is formed and patterned to form a fourth conductive layer LY4.

[0241] (14) At least one insulating layer is formed and at least one transparent conductive layer is formed, wherein the transparent conductive layer includes the conductive line L1.

[0242] (15) The first electrode E1 of the light-emitting element is formed.

[0243] (16) A pixel definition layer PDL and a spacer layer PS are formed.

[0244] (17) A light-emitting functional layer FL is formed.

[0245] (18) The second electrode E2 of the light-emitting element is formed.

[0246] (19) Forming a packaging layer CPS.

[0247] At least one embodiment of the present disclosure provides a display device, comprising any one of the above-mentioned display panels.

[0248] Fig.18A and Fig.18B Schematic diagram of a display device provided by an embodiment of the present disclosure. Fig.18A and Fig.18B As shown, the light sensor SS is located on one side of the display panel DS and in the second display area R2. Ambient light can pass through the second display area R2 and be sensed by the light sensor SS. Fig.18B As shown, the side of the display panel where no photosensor SS is provided is the display side, which can display images.

[0249] For example, the display device is a full-screen display device with an under-screen camera. For example, the display device includes OLED or a product including OLED. For example, the display device includes any product or component with a display function, such as a TV, a digital camera, a mobile phone, a watch, a tablet computer, a laptop computer, a navigator, etc., containing the above display panel.

[0250] Fig.19 for Fig.16A The working timing diagram of the pixel circuit is shown in FIG. Fig.19 As shown, in one frame display period, the driving method of the pixel unit includes a first reset stage t1, data writing and threshold compensation, a second reset stage t2, and a light emitting stage t3. When the reset control signal RESET is at a low level, the gate of the driving transistor T1 is reset, and when the scan signal SCAN is at a low level, the first electrode E1 (for example, anode) of the light emitting element 100b is reset. For example, Fig.16A As shown, when the scan signal SCAN is at a low level, the data voltage VDATA is written, and the threshold voltage Vth of the driving transistor T1 is obtained at the same time, and the data voltage VDADA containing the data information on the data line is stored in the capacitor Cst; when the light-emitting control signal line EML is at a low level, the light-emitting element 100b emits light, and the voltage of the first node N1 (gate point) is maintained (the light-emitting stability of the light-emitting element 100b) by the storage capacitor Cst. In the driving process of the pixel circuit 10, in the light-emitting stage, the storage capacitor is used to maintain the voltage signal so that the potential of its signal holding end can be kept constant, and a voltage is formed between the gate and the source of the driving transistor, thereby controlling the driving transistor to form a driving current, and then driving the light-emitting element 100b to emit light.

[0251] like Fig.19 As shown, in the reset stage t1 , the light emitting control signal EM is set to a turn-off voltage, the reset control signal RESET is set to a turn-on voltage, and the scan signal SCAN is set to a turn-off voltage.

[0252] like Fig.19 As shown, in the data writing and threshold compensation stage and the second reset stage t2, the light emitting control signal EM is set to a turn-off voltage, the reset control signal RESET is set to a turn-off voltage, and the scan signal SCAN is set to a turn-on voltage.

[0253] like Fig.19 As shown, in the light emitting stage t3, the light emitting control signal EM is set to an on voltage, the reset control signal RESET is set to an off voltage, and the scan signal SCAN is set to an off voltage.

[0254] like Fig.19As shown, the first voltage signal ELVDD and the second voltage signal ELVSS are both constant voltage signals. For example, the initialization signal Vinit is between the first voltage signal ELVDD and the second voltage signal ELVSS.

[0255] For example, the turn-on voltage in the embodiments of the present disclosure refers to a voltage that can turn on the first and second electrodes of the corresponding transistor, and the turn-off voltage refers to a voltage that can turn off the first and second electrodes of the corresponding transistor. When the transistor is a P-type transistor, the turn-on voltage is a low voltage (e.g., 0V) and the turn-off voltage is a high voltage (e.g., 5V); when the transistor is an N-type transistor, the turn-on voltage is a high voltage (e.g., 5V) and the turn-off voltage is a low voltage (e.g., 0V). Fig.19 The driving waveforms shown are all described by taking a P-type transistor as an example. For example, the turn-on voltage is a low voltage (eg, 0V), and the turn-off voltage is a high voltage (eg, 5V), but it is not limited thereto.

[0256] Please also read Fig.16A and Fig.19 , in the first reset stage t1, the light control signal EM is a turn-off voltage, the reset control signal RESET is a turn-on voltage, and the scan signal SCAN is a turn-off voltage. At this time, the first reset transistor T6 is in a conducting state, while the second reset transistor T7, the data writing transistor T2, the threshold compensation transistor T3, the first light control transistor T4, and the second light control transistor T5 are in a turn-off state. The first reset transistor T6 transmits the first initialization signal (initialization voltage Vinit) Vinit1 to the gate of the driving transistor T1 and is stored by the storage capacitor Cst, resetting the driving transistor T1 and eliminating the data stored in the last (previous frame) light emission.

[0257] In the data writing and threshold compensation and second reset stage t2, the light control signal EM is a turn-off voltage, the reset control signal RESET is a turn-off voltage, and the scan signal SCAN is an on voltage. At this time, the data writing transistor T2 and the threshold compensation transistor T3 are in an on state, the second reset transistor T7 is in an on state, and the second reset transistor T7 transmits the second initialization signal (initialization voltage Vinit) Vinit2 to the first pole E1 of the light emitting element 100b to reset the light emitting element 100b. The first light emitting control transistor T4, the second light emitting control transistor T5, and the first reset transistor T6 are in an off state. At this time, the data writing transistor T2 transmits the data voltage VDATA to the first pole of the driving transistor T1, that is, the data writing transistor T2 receives the scan signal SCAN and the data voltage VDATA and writes the data voltage VDATA to the first pole of the driving transistor T1 according to the scan signal SCAN. The threshold compensation transistor T3 is turned on to connect the driving transistor T1 into a diode structure, thereby charging the gate of the driving transistor T1. After charging is completed, the gate voltage of the driving transistor T1 is VDATA+Vth, where VDATA is the data voltage and Vth is the threshold voltage of the driving transistor T1, that is, the threshold compensation transistor T3 receives the scan signal SCAN and performs threshold voltage compensation on the gate voltage of the driving transistor T1 according to the scan signal SCAN. At this stage, the voltage difference across the storage capacitor Cst is ELVDD-VDATA-Vth.

[0258] In the light-emitting stage t3, the light-emitting control signal EM is the on voltage, the reset control signal RESET is the off voltage, and the scan signal SCAN is the off voltage. The first light-emitting control transistor T4 and the second light-emitting control transistor T5 are in the on state, while the data writing transistor T2, the threshold compensation transistor T3, the first reset transistor T6 and the second reset transistor T7 are in the off state. The first voltage signal ELVDD is transmitted to the first electrode of the driving transistor T1 through the first light-emitting control transistor T4, and the gate voltage of the driving transistor T1 is maintained at VDATA+Vth. The light-emitting current I flows into the light-emitting element 100b through the first light-emitting control transistor T4, the driving transistor T1 and the second light-emitting control transistor T5, and the light-emitting element 100b emits light. That is, the first light-emitting control transistor T4 and the second light-emitting control transistor T5 receive the light-emitting control signal EM, and control the light-emitting element 100b to emit light according to the light-emitting control signal EM. The light-emitting current I satisfies the following saturation current formula:

[0259] K(Vgs-Vth) 2 =K(VDATA+Vth-ELVDD-Vth) 2 =K(VDATA-ELVDD) 2

[0260] in, μ n is the channel mobility of the driving transistor, Cox is the channel capacitance per unit area of ​​the driving transistor T1, W and L are the channel width and channel length of the driving transistor T1 respectively, and Vgs is the voltage difference between the gate and the source (ie, the first electrode of the driving transistor T1 in this embodiment) of the driving transistor T1.

[0261] It can be seen from the above formula that the current flowing through the light emitting element 100b has nothing to do with the threshold voltage of the driving transistor T1. Therefore, the pixel circuit can very well compensate for the threshold voltage of the driving transistor T1.

[0262] For example, the proportion of the duration of the light-emitting stage t3 in one frame display time period can be adjusted. In this way, the light brightness can be controlled by adjusting the proportion of the duration of the light-emitting stage t3 in one frame display time period. For example, the proportion of the duration of the light-emitting stage t3 in one frame display time period can be adjusted by controlling the scanning drive circuit in the display panel or an additional drive circuit.

[0263] For example, the present disclosure is not limited to Fig.16A The specific pixel circuit shown may adopt other pixel circuits that can realize compensation for the driving transistor. Based on the description and teaching of the implementation method disclosed in this disclosure, other configuration methods that can be easily thought of by ordinary technicians in this field without creative work are all within the protection scope of this disclosure.

[0264] The above description is made using a 7T1C pixel circuit as an example, and the embodiments of the present disclosure include but are not limited to this. It should be noted that the embodiments of the present disclosure do not limit the number of thin-film transistors and the number of capacitors included in the pixel circuit. For example, in some other embodiments, the pixel circuit of the display panel may also be a structure including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure or a 9T2C structure, and the embodiments of the present disclosure do not limit this. Of course, the display panel may also include a pixel circuit with less than 7 transistors.

[0265] In the embodiments of the present disclosure, the components located in the same layer may be formed by the same film layer through the same patterning process. For example, the components located in the same layer may be located on the surface of the same component away from the substrate.

[0266] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of the layer or region is exaggerated. It is understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or there may be an intermediate element.

[0267] In the embodiments of the present disclosure, the patterning or patterning process may include only the photolithography process, or include the photolithography process and the etching step, or may include other processes such as printing and inkjetting for forming a predetermined pattern. The photolithography process refers to a process including film formation, exposure, and development, and a pattern is formed using a photoresist, a mask, an exposure machine, etc. The corresponding patterning process can be selected according to the structure formed in the embodiments of the present disclosure.

[0268] In the absence of conflict, features in the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0269] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display panel, include: A substrate having a display area and a peripheral area, wherein the peripheral area is located on at least one side of the display area; A pixel unit, located on the substrate, comprises a pixel circuit and a light-emitting element, wherein the pixel circuit is configured to drive the light-emitting element, the pixel circuit comprises a driving transistor and a data writing transistor, and the driving transistor is connected to the data writing transistor; a data line connected to the data writing transistor and configured to provide a data signal to the pixel circuit; A compensation structure connected to the data line and located in the peripheral area, the compensation structure comprising at least one of a resistance compensation unit and a capacitance compensation unit, The data lines include a first type of data lines and a second type of data lines, the length of the second type of data lines is greater than the length of the first type of data lines, the compensation structure includes a first compensation structure and a second compensation structure, the compensation amount of the first compensation structure connected to the first type of data lines is greater than the compensation amount of the second compensation structure connected to the second type of data lines, The second type of data line includes a first portion, a second portion and a third portion, the first portion and the second portion are connected through the third portion, an extension direction of the third portion is different from an extension direction of the first portion, and an extension direction of the third portion is different from an extension direction of the second portion, and the third portion is located in the display area, The third portion extends along a first direction, and a plurality of third portions are arranged in sequence along a second direction, the first direction intersects with the second direction, and the first portion is located between two adjacent first-type data lines. The extending direction of the first type of data line is the same as the extending direction of the first portion, On one side of the center line of the display panel, a plurality of first-type data lines and a plurality of first compensation structures are provided, and a plurality of second-type data lines and a plurality of second compensation structures are provided. The compensation structure includes a capacitor compensation unit, the capacitor compensation unit includes a first compensation part, a first electrode, a second compensation part and a second electrode, the first compensation part is connected to the data line, the first compensation part overlaps with the first electrode to form a first compensation capacitor, the second compensation part overlaps with the first electrode to form a second compensation capacitor, the second compensation part overlaps with the second electrode to form a third compensation capacitor, the first compensation capacitor, the second compensation capacitor, and the third compensation capacitor are connected in parallel, The first plates of different capacitance compensation units are integrated structures. From a direction away from the center line to a direction close to the center line, a size of the first electrode plate in the second direction changes gradually in steps.

2. The display panel according to claim 1, in, The compensation structure includes a resistance compensation unit, and the resistance compensation unit includes the first compensation part connected to the data line and the second compensation part connected to the first compensation part, the first compensation part and the second compensation part are located in different layers, and the orthographic projection of the first compensation part on the base substrate and the orthographic projection of the second compensation part on the base substrate at least partially overlap.

3. The display panel according to claim 2, in, The first compensation part and the second compensation part are connected through a via hole.

4. The display panel according to claim 1, in, An orthographic projection of the first electrode plate on the base substrate at least partially overlaps with an orthographic projection of the second electrode plate on the base substrate.

5. The display panel according to any one of claims 1 to 4, in, The first compensation portion is located in the first conductive layer, the first electrode plate is located in the second conductive layer, the second compensation portion is located in the third conductive layer, and the second electrode plate is located in the fourth conductive layer.

6. The display panel according to claim 5, in, The first conductive layer is located on the first insulating layer, a second insulating layer is provided between the first conductive layer and the second conductive layer, a third insulating layer is provided between the second conductive layer and the third conductive layer, and a planarization layer is provided between the third conductive layer and the fourth conductive layer.

7. The display panel according to any one of claims 1 to 4, in, The first compensation part and the second compensation part constitute the resistance compensation unit.

8. The display panel according to any one of claims 1 to 4, in, An orthographic projection of the first compensation portion on the base substrate at least partially overlaps with an orthographic projection of the second compensation portion on the base substrate.

9. The display panel according to any one of claims 1 to 4, in, A width of the first compensation portion in the first direction is the same as a width of the second compensation portion in the first direction.

10. The display panel according to any one of claims 1 to 4, in, The first direction intersects with an extension direction of the first compensation portion and intersects with an extension direction of the second compensation portion.

11. The display panel according to claim 6, in, The first compensation part is connected to the second compensation part through a via hole penetrating the third insulating layer and the second insulating layer.

12. The display panel according to any one of claims 1 to 4, further comprising a first connection structure, in, The data line is connected to the first compensation part through the first connection structure.

13. The display panel according to claim 5, in, The third conductive layer further includes a signal line extending along the first direction, and an orthographic projection of the signal line on the base substrate partially overlaps with an orthographic projection of the first compensation portion on the base substrate.

14. The display panel according to any one of claims 1 to 4, in, The first electrode plate and the second electrode plate are both connected to a constant voltage terminal, and the constant voltage terminal includes at least one of a first power supply terminal and a second power supply terminal.

15. The display panel according to any one of claims 1 to 4, further comprising a second connection structure, in, The data line is connected to a plurality of capacitance compensation units via the second connection structure, and the capacitances of the plurality of capacitance compensation units connected to the data line are connected in parallel.

16. The display panel according to any one of claims 1 to 4, in, The second pole plates of different capacitance compensation units are an integrated structure, and the size of the second pole plates in the second direction changes gradually in a step-like manner.

17. The display panel according to any one of claims 1 to 4, in, Multiple capacitor compensation units are arranged in the first direction. On one side of the center line of the display panel, from away from the center line to close to the center line, the size of the first electrode in the second direction gradually decreases in steps, and the size of the second electrode in the second direction gradually decreases in steps, and the center line is parallel to the second direction.

18. The display panel according to any one of claims 1 to 4, in, The display area includes a first display area and a second display area, the first display area is located at least on one side of the second display area, and the data line is not located in the second display area.

19. The display panel according to any one of claims 1 to 4, in, The plurality of first compensation structures are arranged in sequence, the plurality of second compensation structures are arranged in sequence, and the plurality of first compensation structures are located on one side of the plurality of second compensation structures.

20. The display panel according to any one of claims 1 to 4, in, The plurality of first compensation structures are arranged in sequence. Among the plurality of first compensation structures, the closer to the center line of the display panel, the smaller the compensation amount of the first compensation structure.

21. The display panel according to any one of claims 1 to 4, in, The compensation amount of the second compensation structure is inversely proportional to the length of the third portion.

22. The display panel according to claim 18, in, The pixel unit includes a first pixel unit and a second pixel unit. The pixel circuit and the light-emitting element of the first pixel unit are both located in the first display area, The pixel circuit of the second pixel unit is located in the first display area, and the light emitting element of the second pixel unit is located in the second display area. The pixel circuit of the second pixel unit is connected to the light emitting element of the second pixel unit through a conductive line, An orthographic projection of the conductive line on the substrate overlaps partially with an orthographic projection of the pixel circuit of the first pixel unit on the substrate.

23. A display device comprising the display panel according to any one of claims 1-22.

24. The display device according to claim 23, further comprising a light-sensitive sensor, in, The photosensor is located on one side of the display panel.

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