Time compensation method and device for test signals

Abstract

The time compensation method and apparatus for test signals provided in this application can determine the time delay caused by impedance matching of the test signal to the test unit on the test platform when the signal source sends the test signal to the test unit on the test platform. The compensation device can then compensate the clock signal sent by the signal source to different test units according to the time delay, so that the test unit can receive the test signal more accurately, thereby improving the accuracy of testing the device using the test platform.

Description

Technical Field

[0001] This application relates to the field of testing technology, and in particular to a time compensation method and apparatus for testing signals. Background Technology

[0002] With the continuous development of electronic technology, more and more electronic components, chips, and integrated circuits are being widely used in various fields to achieve increasingly rich functions. As manufacturers of these devices, it is necessary to ensure the performance of the devices they produce even with increasingly higher integration levels. The devices need to be tested at the factory, for example, by inputting test signals to the device under test and checking whether the output results of the device under test meet the preset conditions, thereby checking the performance of the device under test.

[0003] In the prior art, in order to improve the detection efficiency of the same device, a common approach is to set up multiple devices simultaneously on a daisy chain test platform. When the signal source inputs a test signal to the test platform, the multiple devices set up on the test platform can receive the same test signal and process the test signal separately. At this time, batch detection of devices can be achieved by detecting whether multiple devices can accurately receive the signal.

[0004] Using existing technology, the transmission path of the test signal from the signal source to the corresponding device is subject to transmission delay caused by impedance matching of the transmission line and other devices. This delay can cause the device to fail to receive the test signal accurately, thus affecting the accuracy of the device test. Summary of the Invention

[0005] This application provides a time compensation method and apparatus for test signals to overcome the technical problem that the device cannot accurately receive the test signal due to the time delay caused by the impedance matching of the transmission line and other devices on the transmission path of the test signal from the signal source to the corresponding device.

[0006] A first aspect of this application provides a time compensation method for a test signal, comprising: when a signal source sends a test signal to test units at multiple test locations on a test platform, acquiring time parameters for each of the test units; wherein the impedance on the transmission path between the signal source and each of the test locations is different, and the time parameters are used to indicate whether the impedance on the transmission path affects the test unit's reception of the test signal; determining compensation parameters corresponding to multiple test locations where the multiple test units are located based on a target time parameter and the time parameters of each of the test units; and sending the multiple compensation parameters corresponding to the multiple test locations to the signal source, so that the signal source performs time compensation on the clock signal sent to the multiple test locations based on the multiple compensation parameters.

[0007] In one embodiment of the first aspect of this application, the target time parameter is used to indicate whether the impedance on the transmission path from the signal source to the target test location affects the target test unit set at the target test location from receiving the test signal; wherein, the target test location is the test location on the test platform that is closest to the signal source.

[0008] In one embodiment of the first aspect of this application, the time parameter includes: a correspondence between multiple frequency clock signals, multiple establishment times of the test signal, and identification information; wherein, the identification information is used to indicate whether the test unit can accurately receive the test signal according to the multiple frequency clock signals when the test unit receives the test signal at the multiple establishment times respectively.

[0009] In one embodiment of the first aspect of this application, the multiple frequency clock signals change according to a first preset rule; the multiple setup times change according to a second preset rule.

[0010] In one embodiment of the first aspect of this application, the identification information includes: a plurality of sub-information, each sub-information used to indicate whether the test unit can accurately receive the test signal when the test unit receives a clock signal of one of the plurality of frequencies at one of the plurality of setup times; when the sub-information is in a first state, it indicates that the test unit can accurately receive the test signal when receiving the test signal at one setup time and according to a clock signal of one frequency; when the sub-information is in a second state, it indicates that the test unit cannot accurately receive the test signal when receiving the test signal at one setup time and according to a clock signal of one frequency.

[0011] In one embodiment of the first aspect of this application, the step of obtaining the time parameters of each test unit, for the first test unit among the plurality of test units, obtaining the first time parameters of the first test unit includes: determining that the signal source sends the test signal and a first clock signal among multiple frequency clock signals to the first test unit; setting the establishment time of the first test unit sequentially to the plurality of establishment times according to the second preset rule; controlling the first test unit to receive the test signal with the first clock signal according to the first establishment time among the plurality of establishment times; and determining the identification information corresponding to the first establishment time and the first clock signal in the first time parameters according to whether the first test unit successfully receives the test signal.

[0012] In one embodiment of the first aspect of this application, for a first test unit among the plurality of test units, a first compensation parameter corresponding to the first test position where the first test unit is located is determined according to a target time parameter and a first time parameter of the first test unit, including: determining a plurality of critical setup times corresponding to a clock signal of each frequency in the first time parameter; wherein, when the first test unit receives a test signal with a clock signal of one frequency, the sub-information corresponding to the setup time greater than the critical setup time is the first state, and the sub-information corresponding to the setup time less than the critical setup time is the second state; the first compensation parameter is obtained by the difference between the plurality of critical setup times corresponding to the clock signal of each frequency in the target time parameter and the plurality of critical setup times of the clock signal of each frequency in the first time parameter.

[0013] In one embodiment of the first aspect of this application, the method further includes: obtaining target time parameters of the target test unit on the test platform.

[0014] In one embodiment of the first aspect of this application, the method further includes: when the standard test unit is located at multiple test positions on the test platform, a signal source sends a test signal and a clock signal to the standard test unit at each of the multiple test positions; at each test position, the standard test unit is controlled to receive the test signal with the clock signal according to a preset setup time; the test position where the standard test unit cannot accurately receive the test signal at the multiple test positions is determined as a position to be compensated, and time compensation is performed on the clock signal at the position to be compensated.

[0015] A second aspect of this application provides a time compensation device for a test signal, comprising: an acquisition module configured to acquire time parameters of each test unit when a signal source sends a test signal to test units at multiple test locations on a test platform; wherein the impedance on the transmission path between the signal source and each test location is different, and the time parameters are used to indicate whether the impedance on the transmission path affects the test unit's reception of the test signal; a processing module configured to determine compensation parameters corresponding to multiple test locations where the multiple test units are located based on a target time parameter and the time parameters of each test unit; and a compensation module configured to send multiple compensation parameters corresponding to the multiple test locations to the signal source, so that the signal source performs time compensation on the clock signal sent to the multiple test locations based on the multiple compensation parameters.

[0016] In one embodiment of the second aspect of this application, the target time parameter is used to indicate whether the impedance on the transmission path from the signal source to the target test location affects the target test unit set at the target test location from receiving the test signal; wherein, the target test location is the test location on the test platform that is closest to the signal source.

[0017] In one embodiment of the second aspect of this application, the time parameter includes: a correspondence between multiple clock signals of multiple frequencies, multiple establishment times of the test signal, and identification information; wherein, the identification information is used to indicate whether the test unit can accurately receive the test signal according to the multiple clock signals of multiple frequencies when the test unit receives the test signal at multiple establishment times respectively.

[0018] In one embodiment of the second aspect of this application, the multiple frequency clock signals change according to a first preset rule; the multiple setup times change according to a second preset rule.

[0019] In one embodiment of the second aspect of this application, the identification information includes: a plurality of sub-information, each sub-information used to indicate whether the test unit can accurately receive the test signal when the test unit receives a clock signal of one of the plurality of frequencies at one of the plurality of setup times; when the sub-information is in a first state, it indicates that the test unit can accurately receive the test signal when receiving the test signal at one setup time and according to a clock signal of one frequency; when the sub-information is in a second state, it indicates that the test unit cannot accurately receive the test signal when receiving the test signal at one setup time and according to a clock signal of one frequency.

[0020] In a second aspect of this application, when determining the time parameters of the first test unit among the plurality of test units, the acquisition module is specifically configured to: determine that the signal source sends the test signal and a first clock signal among multiple frequency clock signals to the first test unit; set the establishment time of the first test unit sequentially to the plurality of establishment times according to the second preset rule; control the first test unit to receive the test signal with the first clock signal according to the first establishment time among the plurality of establishment times; and determine the identification information corresponding to the first establishment time and the first clock signal in the first time parameters according to whether the first test unit successfully receives the test signal.

[0021] In one embodiment of the second aspect of this application, when the determining module determines the first compensation parameter of the first test unit among the plurality of test units, it is specifically configured to determine a plurality of critical setup times corresponding to the clock signal of each frequency in the first time parameter; wherein, when the first test unit receives the test signal with a clock signal of one frequency, the sub-information corresponding to the setup time greater than the critical setup time is the first state, and the sub-information corresponding to the setup time less than the critical TIS is the second state; the first compensation parameter is obtained by the difference between the plurality of critical setup times corresponding to the clock signal of each frequency in the target time parameter and the plurality of critical setup times of the clock signal of each frequency in the first time parameter.

[0022] In a second aspect of this application, the acquisition module is further configured to acquire the target time parameters of the target test unit on the test platform.

[0023] In one embodiment of the second aspect of this application, the acquisition module is further configured to, when the standard test unit is located at multiple test positions on the test platform, send test signals and clock signals to the standard test unit at the multiple test positions respectively; at each test position, control the standard test unit to receive the test signal with the clock signal according to a preset setup time; the processing module is further configured to, determine the test position where the standard test unit cannot accurately receive the test signal at the multiple test positions as the position to be compensated, and perform time compensation on the clock signal at the position to be compensated.

[0024] A third aspect of this application provides an electronic device, including a processor and a memory; wherein the memory stores a computer program, and when the processor executes the computer program, the processor can be used to perform the method as described in any of the second aspects of this application.

[0025] A fourth aspect of this application provides a computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program, which, when executed, can be used to perform the method as described in any of the second aspects of this application.

[0026] The test signal time compensation method and apparatus provided in this application can determine the time delay caused by impedance matching at each test position when the signal source sends a test signal to the test unit on the test platform. Based on the time delay, the clock signal sent by the signal source to different test units is time-compensated to overcome the technical problem of time delay caused by impedance matching of the chip at the test position. This enables the test unit to receive the test signal more accurately, thereby improving the accuracy of testing devices such as DUTs using the test platform. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram illustrating the application scenario of this application;

[0029] Figure 2 This is a schematic diagram of an embodiment of test signals received by the DUT at different test positions on the test platform;

[0030] Figure 3 This is a schematic diagram of another embodiment of the test signals received by the DUT at different test positions on the test platform;

[0031] Figure 4 A flowchart illustrating an embodiment of the time compensation method for test signals provided in this application;

[0032] Figure 5 A schematic diagram of a test state provided for this application;

[0033] Figure 6 A schematic diagram of an embodiment of the time parameters provided in this application;

[0034] Figure 7 A schematic diagram illustrating the process of obtaining time parameters according to an embodiment provided in this application;

[0035] Figure 8 A schematic diagram illustrating another test state provided for this application;

[0036] Figure 9 A schematic diagram of another embodiment of the time parameters provided in this application;

[0037] Figure 10 A schematic diagram illustrating another embodiment of the process for obtaining time parameters provided in this application;

[0038] Figure 11 A schematic diagram of yet another embodiment of the time parameters provided in this application;

[0039] Figure 12 A schematic diagram illustrating the compensation of time parameters provided in this application;

[0040] Figure 13 A diagram illustrating the time compensation method provided for this application;

[0041] Figure 14A schematic diagram of an embodiment of the test signal compensation device provided in this application. Detailed Implementation

[0042] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0043] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0044] Before formally introducing the embodiments of this application, the application scenario and the problems existing in the prior art will be explained in conjunction with the accompanying drawings.

[0045] Figure 1 This is a schematic diagram illustrating the application scenario of this application. In some technologies, to test electronic components, chips, integrated circuits, and other devices, multiple devices under test (DUTs) can be simultaneously placed at multiple test positions on a daisy-chain test platform 20. For example... Figure 1 As an example, DUT1-DUT8 are placed on test positions W1-W8 provided by test platform 20. Then, after the signal source 10 inputs the test signal through the test signal input interface W0 on test platform 20, since multiple test positions on test platform 20 are connected to interface W0, the DUTs set at each test position can receive the same test signal. At this time, batch testing of the equipment can be achieved by detecting whether multiple DUTs have received the test signal, which has high testing efficiency.

[0046] Furthermore, because the test platform can provide a large number of test positions, and the distance between each test position and the signal source is different, this makes... Figure 1In the example shown, after the signal source 10 sends a test signal to the test platform 20 at time T0, there is a certain time delay between the time when the DUT at each test position actually receives the test signal and time T0. This delay is the time loss caused by the transmission of the test signal along the transmission path on the test platform 20. The farther the test position is from the signal source 10 on the test platform 20, the greater the delay in the DUT receiving the test signal. For example, DUT1 and DUT5, set at the test positions W1 and W5, which are closest to the signal source 10, will receive the test signal at time T1 after T0; and so on, DUT4 and DUT8, set at the test positions W4 and W8, which are farthest from the signal source 10, will only receive the test signal at time T4 after T0.

[0047] In some embodiments, since each test position on the test platform is fixed, once the time delay T1-T4 of the received test signal at each test position is determined, the compensation device 30 can perform time compensation for this delay caused by the transmission distance. For example, in Figure 1 In the example shown, the compensation device 30 can be connected to the signal source 10 and the test platform 20, and can control the DUTs set at each test position on the test platform 20. The compensation device 30 can be an electronic device such as a computer, server, or chip capable of performing relevant data processing and control functions. Once the time delay T1-T4 of each test position on the test platform 20 is determined, the compensation device 30 can control each DUT on the test platform 20. When the signal source 10 emits a test signal at time T0, the compensation device 30 controls DUT1 set at test position W1 to receive the test signal at time T1, controls DUT2 set at test position W2 to receive the test signal at time T2, and so on.

[0048] In some embodiments, Figure 2 This is a schematic diagram of an embodiment of the test signals received by DUTs at different test positions on the test platform. After time compensation by the compensation device 30, when the signal source emits test signal L0 at time T0, all DUTs on the test platform 20 can accurately receive test signals L1-L4 with the same waveform as L0, ensuring the smooth completion of subsequent tests.

[0049] However, in actual testing, even after time compensation is performed on the DUT on the test platform 20 by the compensation device 30, some DUTs still fail to accurately receive the test signal. Observation revealed that in the transmission path of the test signal from the signal source 10 to the corresponding DUT on the test platform 20, in addition to the time loss caused by the transmission path, there is also a time delay caused by the impedance matching of the DUT on the test platform 20. The impedance matching of the DUT at each test position is different. The time delay caused by the impedance matching of each DUT is due to the impedance of the DUT at that test position being matched with: ① the signal transmission line at that test position and ② the DUTs at other test positions. The impedance matching of ① and ② will cause a certain time delay in the transmission of the test signal, resulting in the DUTs failing to accurately receive the test signal even after compensation by the compensation device 30, thus affecting the accuracy of testing DUTs and other devices using the test platform.

[0050] For example, Figure 3 This is a schematic diagram of another embodiment of the test signals received by the DUT at different test positions on the test platform. When the signal source emits test signal L0 at time T0, even after time compensation by the compensation device 30, the waveforms received by DUT2 and DUT6 at test positions W2 and W6 are L2', which is different from the waveforms received by the DUT2 and DUT6 at test positions W2 and W6. Figure 2 Compared to the ideal waveform L2, there is a certain time delay (Propagation Delay, abbreviated as Tpd), denoted as Tpd2. Similarly, the waveforms received by DUT3 and DUT7 at test positions W3 and W7 have a time delay Tpd3, and the waveforms received by DUT4 and DUT8 at test positions W4 and W8 have a time delay Tpd4. Furthermore, due to the different impedances at each test position, the impedance along the transmission path from the signal source to each test position is different, resulting in different impedance matching at each test position, which in turn leads to different time delays caused by impedance matching at each test position. Simultaneously, for test positions at different distances from the signal source, the impedance along the transmission path is different; the impedance at test positions at the same distance is considered the same, making the time delay caused by the matching impedance at test positions at the same distance from the signal source the same. Ultimately, as... Figure 3 The time delays shown are caused by impedance matching issues between the impedance of the DUT itself and the impedance on the propagation path and the impedance of other DUT locations. These delays can prevent the DUT under test from accurately receiving the test signal, thus affecting the subsequent test results of the DUT.

[0051] Therefore, this application provides a time compensation method and apparatus for test signals to compensate for the time delay caused by impedance matching problems in each test unit on the test platform, thereby overcoming the technical problem of time delay caused by impedance matching in test signals and improving the accuracy of testing devices such as DUTs using the test platform. The technical solution of this application will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0052] Figure 4 A flowchart illustrating an embodiment of the time compensation method for test signals provided in this application is shown below. Figure 4 The method shown can be applied to, for example Figure 1 In the scenario shown, and performed by the compensation device 30, the method includes:

[0053] S101: When the signal source 10 sends test signals to the test units at multiple test positions on the test platform 20, the compensation device 30 acquires the time parameters of each test unit.

[0054] Specifically, when the compensation device 30 compensates for the impedance present in the transmission path of the test signal, it first needs to determine the time delay Tpd caused by impedance matching at each test position. In order to accurately obtain the time delay Tpd caused by impedance matching at each test position and reduce the impact of differences between different chips at different test positions on the detection results of time delay Tpd, in some embodiments of this application, an identical test unit can be placed at different positions on the test platform, and then the time delay Tpd caused by the corresponding impedance matching at different test positions can be collected when this single test unit receives test signals at different test positions.

[0055] For example, Figure 5 This is a schematic diagram of a test state provided by the present application, wherein a test unit DUT0 to be tested is selected and placed sequentially on each test position W1-W8 on the test platform 20, and then the time parameters of the test unit DUT0 at each test position are collected.

[0056] In some embodiments, the position adjustment of the test unit DUT0 can be achieved by the compensation device 30 controlling the slide rail, robotic arm, or other equipment to place the test unit DUT0 at different test positions according to the test requirements, and then acquiring the time parameters; or, the operator can manually place the test unit DUT0 at different test positions, and after the compensation device 30 determines the position of the test unit DUT0, or acquires the time parameters of the test unit DUT0 at that position.

[0057] In some embodiments, to ensure signal symmetry and stability on the test platform, to obtain time parameters that more closely resemble actual test conditions, and to consider the impedance matching effects caused by the impedance of the DUT at other test locations, when the test unit DUT0 is placed at a test location, in order to Figure 5 The example is placed at test position W1. The DUT can also be set at other test positions W2-W8 simultaneously. However, since the parameters of the DUT at other test positions are not currently available... Figure 5 The DUTs set at other test locations are indicated by dashed lines.

[0058] Then in Figure 5 In the example shown, the test unit DUT0 is placed at test position W1 on the test platform 20. At this time, the signal source 10 can send a test signal to the input interface W0 of the test platform 20. Simultaneously, the signal source 10 also separately sends a clock signal to the DUT0. The clock signal can be configured as follows: Figure 2 The connection relationship for the signal source 10 to send the clock signal to the test unit DUT0 set at test position W1 is predetermined as shown in the figure. Therefore, the test unit DUT0 will receive both the clock signal and the test signal simultaneously. The test signal can be received based on the clock signal, for example, by triggering the receiving action at the rising or falling edge of the clock signal.

[0059] Furthermore, when the test unit DUT0 receives the test signal, an important parameter is the setup time (TIS) for receiving the test signal. The setup time refers to the time during which the test signal arrives at the test unit before the clock signal triggers, ensuring that the received test signal is stable when the test unit is triggered and begins receiving the test signal. This provides a certain amount of time for the test signal to stabilize beforehand, hence the term setup time. If the time difference between the test signal and the clock signal is less than the setup time, the received test signal will not be stable when the test unit is triggered and begins receiving the test signal, leading to test signal reception failure. Therefore, in this application, when the impedance matching delay Tpd at the test location is detected, the setup time of the test signal received by the test unit placed at that test location can be used to quantify the delay Tpd and use this time for subsequent time compensation.

[0060] In some embodiments, when the test unit is set at each test position, the SHMOO method can be used to detect the setup time, thereby obtaining a time characteristic diagram of the setup time at each test position. Each time characteristic diagram is distributed to indicate whether the test unit at a test position can accurately receive the test signal under the influence of impedance matching when receiving the test signal, and the time characteristic diagram can be used as the time parameter obtained in S101.

[0061] For example, Figure 6 A schematic diagram of an embodiment of the time parameters provided in this application is shown, wherein, as illustrated... Figure 5 The scenario shown illustrates the state of the test unit DUT0, located at test position W1, receiving test signals with different clock cycles and setup times. For example... Figure 6 The time parameters shown include clock signals TCK at multiple frequencies, setup times (TIS) for multiple test signals, and the corresponding relationship of identification information. The identification information can be understood as the entire... Figure 6 The color of each small square in the matrix composed of all the small squares.

[0062] More specifically, the time parameters include multiple sub-parameters distributed in a matrix form. Each small square in the diagram represents a sub-parameter, forming a multi-row, multi-column time parameter. The horizontal axis X of the matrix composed of multiple sub-parameters represents the clock signal period TCK, which changes according to a certain first preset rule. The vertical axis Y represents the setup time TIS, which changes according to a certain second preset rule. Each sub-parameter can be understood as a three-dimensional array, including three parameters: the clock signal frequency TCK, the setup time TIS, and the state of the sub-information. The state of each sub-information is used to indicate whether the test unit can accurately receive the test signal based on the setup time TIS and the clock signal TCK. If it can, the state in the sub-information is the first state A. Figure 6 The lighter color of the small square indicates that the state of the sub-information corresponding to that small square is the first state A; if not, the state of the sub-information is the second state B. Figure 6 The darker color of the small square indicates that the state of the sub-information corresponding to that small square is the second state B.

[0063] The following is in conjunction with the appendix Figure 7 ,right Figure 6 The process of obtaining the time parameters shown will be explained. Figure 7 A schematic diagram illustrating an embodiment of obtaining time parameters provided in this application, wherein, in order to obtain such... Figure 5In the scenario shown, the time parameters of the test unit DUT0 set at the test position W1 are adjusted by the compensation device 30 according to the second preset rule when the signal source 10 sends a test signal and a clock signal TCK of a certain frequency to the test platform 20. The device 30 also controls the test unit DUT0 to receive the test signal with multiple TIS and the current clock signal TCK respectively. Finally, the device 30 determines whether the identification information corresponding to a TIS and a TCK is the first state A or the second state B according to whether the test unit DUT0 can successfully receive the test signal based on a TIS and a TCK.

[0064] For example, with Figure 6 In the example, sub-information a, sub-information b, and sub-information c corresponding to a clock signal TCK on the same horizontal axis are used. To obtain sub-information a, when the compensation device 30 and signal source 10 send the test signal and clock signal to the test platform 20, assuming the clock signal triggers the test unit DUT0 at test position W1 to receive the test signal at time T11, and the test signal starts sending at time T10 before T11, and assuming the minimum setup time required for test unit DUT0 to receive the test signal is T20, and T10 is earlier than T20, the test signal has already reached a stable state when test unit DUT0 is triggered by the clock signal to start receiving the test signal at time T11. Therefore, in sub-information a, test unit DUT0 can accurately receive the test signal according to the clock signal. Figure 6 The identification information of the sub-information a corresponding to the clock signal and TIS = (T10-T11) is denoted as the first state A.

[0065] Subsequently, in order to obtain sub-information b, when the compensation device 30 signal source 10 sends the test signal and clock signal to the test platform 20, assuming that TIS is reduced to T20-T11, the following is obtained: Figure 7 The relative positions of the clock signal and the test signal are shown. To obtain this positional relationship, the period of the test signal can be shifted backward, or the period of the clock signal can be shifted forward. It can be understood that these clock signals and test signals should be the same signal, arranged according to different time patterns. When the clock signal triggers the test unit DUT0 at test position W1 to receive the test signal at time T11, the test signal has already reached a stable state when the test unit DUT0 is triggered by the clock signal to start receiving the test signal at time T11. Therefore, [the remaining text is incomplete and requires further context]. Figure 6The identifier information of sub-information b corresponding to the clock signal and TIS = (T20-T11) is denoted as the first state A. Similarly, in order to obtain sub-information c, since the test signal only starts to be transmitted at T30 when the test unit DUT0 is triggered by the clock signal to start receiving the test signal at time T11, it cannot reach a stable state. Therefore, in sub-information c, the test unit DUT0 cannot accurately receive the test signal according to the clock signal, so it is... Figure 6 The identification information of the sub-information c corresponding to the clock signal and TIS = (T30-T10) is denoted as the second state B.

[0066] It is understandable that when the test unit DUT0 at test position W1 receives test signals according to the clock signal and different TIS, multiple units located at... Figure 6 After processing all the sub-information in one column, the frequency TCK of the clock signal is adjusted according to the first preset rule. The above process is repeated with the new clock signal to calculate... Figure 6 After processing all sub-information in multiple columns, complete the entire process. Figure 6 In the test, the time parameter of the test unit DUT0 at test position W1 when receiving the test signal.

[0067] Subsequently, the unit under test (DUT0) is moved from test position W1 to another test position and subjected to the same SHMOO test as at position W1, thereby obtaining the time parameters of the test unit at each test position when receiving the test signal. For example, Figure 8 The diagram illustrates another test state provided for this application, showing a scenario where the test unit DUT0 is set at test position W4 on the test platform. Figure 9 A schematic diagram of another embodiment of the time parameters provided in this application is shown, wherein, as Figure 8 The scenario shown illustrates the state of the test unit DUT0, located at test position W4, receiving test signals with different clock signals and setup times. For details on acquiring the time parameters, please refer to [link / reference needed]. Figure 10 , Figure 10 This is a schematic diagram illustrating another embodiment of the process for obtaining time parameters provided in this application. Figures 8-10 In the embodiment shown, the test unit DUT0 is obtained at test position W4. Figure 9 The process of the time parameters shown can be referred to Figures 5-7 The specific implementation method and principle are the same as those described in the text, so they will not be repeated here.

[0068] Finally, the test unit DUT0 is placed sequentially at each test position W1-W8 on the test platform 20 to obtain the time parameters for each test position. For example, Figure 11This is a schematic diagram of another embodiment of the time parameters provided in this application, showing the time parameters of each test unit DUT0 set at all of the plurality of test positions W1-W8 obtained in S101. Since the time parameters are related to the distance of the test position from the signal source, the time parameters of W1-W4 and W5-W8 correspond one-to-one and are considered to be the same. Figure 11 Only the time parameters for W1-W4 are shown as examples.

[0069] S102: The compensation device 30 determines the compensation parameters corresponding to the test positions of multiple test units on the test platform 20 based on the target time parameters and the time parameters of each test unit.

[0070] Once the time parameters at each test location are determined, the time parameters at other test locations can be compensated based on the target time parameters. The target time parameters for the target test unit can be obtained in advance or preset. Since test locations W1 and W5 are closest to the signal source, the impedance along the transmission path has minimal or negligible impact on the delay of the test signal. Therefore, the target time parameters can be the time parameters corresponding to the test locations W1 and W5 on the test platform 20 that are closest to the signal source. In this embodiment, the target time parameters are taken as... Figure 6 Taking the time parameter of the test unit DUT0 at test position W1 as an example, the time parameters of test positions W2-W4 and W6-W8 can be compared with the target time parameter at test position W1 to obtain the corresponding compensation parameter at each test position W2-W4 and W6-W8.

[0071] Specifically, with Figure 5 The time parameter shown is used as the target parameter, and it is adjusted as follows: Figure 9 Using the time parameters at test position W4 as an example, it can be determined according to... Figure 9 In the time parameters shown, each frequency of the clock signal corresponds to multiple critical setup times, for example, [the following is a list of time parameters]. Figure 9 The multiple critical setup times of the clock signal corresponding to the frequency of the sub-information df shown are the TIS corresponding to the sub-information e. When the period of the clock signal is fixed, and the test signal is received at a TIS greater than that of the sub-information e, the sub-informations above it all correspond to the first state; when the test signal is received at a TIS less than that of the sub-information e, the sub-informations below it all correspond to the second state. The same method can be used to obtain... Figure 9 All clock signals TCK correspond to multiple critical TIS. Then, Figure 9 The critical TIS of all clock signals, and Figure 5The difference between the critical TIS corresponding to the same clock signal TCK in the target time parameters is obtained by subtracting the critical TIS corresponding to multiple clock signals. This difference is the compensation parameter corresponding to the time parameter of the test position W4.

[0072] Finally, following the same method described above, the compensation device 30 can determine the compensation parameters for the time parameters at each test position on the test platform 20. Then, in S103, the compensation device 30 sends the compensation parameters determined in S102 to the signal source 10, so that when the signal source 10 subsequently sends clock signals to the test units on the test platform 20, it performs time compensation on each clock signal according to the compensation parameters, thereby ensuring that the test units receiving the clock signals can accurately receive the test signals.

[0073] For example, Figure 12 This is a schematic diagram illustrating the compensation of time parameters provided in this application, wherein sub-information b corresponds to, for example... Figure 5 In the time parameters, a waveform diagram of the test signal received by the test unit corresponding to a clock signal and the critical TIS = T20 - T11 is shown. Sub-information e corresponds to... Figure 9 In the time parameters, the waveform diagram of the test signal received by the test unit when the same clock signal is at the critical TIS = T40 - T11 is shown. By subtracting the critical TIS of the two time parameters in S102, we can obtain... Figure 9 The compensation parameter for the clock signal in the time parameters is T40-T20. Therefore, when the compensation device 30 sends this compensation parameter to the signal source 10, the signal source 40 can subsequently shift the clock signal sent to the test unit at test position W4 forward by T40-T20 time points. At this time, the waveform received by the test unit is... Figure 12 As shown in the sub-information e', at this time, the distance between T40 and the triggering time T11' is greater than the minimum establishment time, causing the identification information corresponding to sub-information e to switch from the second state B to the first state A of the identification information corresponding to sub-information e'.

[0074] Following the same method described above, after calculating and compensating the time parameters for test locations W2-W4 respectively, the compensated time parameters can be obtained as follows: Figure 11 As shown in W2'-W4', it can be seen that the number of sub-information corresponding to the first state in the modified time parameters has increased. The time parameters for test positions W6-W8 are the same as the states before and after the modification of W2-W4, and will not be described again.

[0075] In some embodiments, the compensation for the time parameter described above can be specifically performed by, for example... Figure 13 The modification of the time parameter LINE1 in the TPD_OFFSET configuration file is implemented, for example... Figure 13The schematic diagram illustrating the time compensation method provided in this application shows that the time parameter of the clock signal output to pin F802 of DUT2 at test position W2 is modified from 362 to 392; the time parameter of the clock signal output to pin F803 of DUT3 at test position W3 is modified from 724 to 784; and the time parameter of the clock signal output to pin F804 of DUT4 at test position W4 is modified from 1086 to 1176, etc. It should be noted that... Figure 13 The document shown is merely an example to illustrate a specific implementation of the time compensation in this application, and is not intended to limit the time compensation method, parameters, or values.

[0076] Therefore, the time compensation method for test signals provided in this application embodiment can determine the time delay caused by impedance matching of the test signal at different test positions to the test unit at each test position when the signal source sends the test signal to the test unit on the test platform. The compensation device can then compensate the clock signal sent by the signal source to different test units according to the time delay, so as to overcome the technical problem of time delay caused by impedance matching to the test signal. This allows the test unit to receive the test signal more accurately, thereby improving the accuracy of testing devices such as DUTs using the test platform.

[0077] In some embodiments, the time parameters corresponding to each test position can be compensated in the manner described above. In other embodiments, the test positions on the test platform that need compensation can be determined first, and then the time parameters of the determined test positions can be compensated, thereby reducing unnecessary calculations and improving efficiency. For example, a standard test unit can be placed at multiple test positions on the test platform. When the signal source sends test signals and clock signals to the standard test unit, it is determined whether the standard test unit can accurately receive the test signal at each test position according to the preset setup time and the received clock signal. Then, the test positions where the standard test unit cannot accurately receive the test signal at multiple test positions are designated as positions to be compensated, and the clock signal at the positions to be compensated is time-compensated. For test positions where the standard test unit can accurately receive the test signal at multiple test positions, no time compensation is performed.

[0078] In some embodiments, in order to obtain the time parameters corresponding to different test positions, the same test unit is placed at different test positions. In other embodiments, if it can be ensured that the impedance of all test units is the same or approximately equivalent to the same, multiple different test units can be used and set at different test positions on the test platform to obtain the time parameters of multiple test units at each test position simultaneously.

[0079] In the foregoing embodiments, the time compensation method for test signals provided in this application has been described. To implement the functions of the methods provided in the embodiments of this application, the compensation device, as the execution entity, may include hardware structures and / or software modules, implementing the above functions in the form of hardware structures, software modules, or a combination of hardware structures and software modules. Whether a particular function is executed in the form of hardware structures, software modules, or a combination of hardware structures and software modules depends on the specific application and design constraints of the technical solution.

[0080] For example, Figure 14 The schematic diagram of an embodiment of the test signal compensation device provided in this application shows a possible implementation of the compensation device 30, wherein the compensation device 30 includes: an acquisition module 301, a processing module 302 and a compensation module 303.

[0081] Specifically, the acquisition module 301 is configured to acquire the time parameters of each test unit when the signal source sends test signals to test units at multiple test locations on the test platform; wherein, the impedance on the transmission path between the signal source and each test location is different, and the time parameters are used to indicate whether the impedance on the transmission path affects the test unit's reception of the test signal; the processing module 302 is configured to determine the compensation parameters corresponding to the multiple test locations where the multiple test units are located based on the target time parameters and the time parameters of each test unit; the compensation module 303 is configured to send the multiple compensation parameters corresponding to the multiple test locations to the signal source, so that the signal source performs time compensation on the clock signals sent to the multiple test locations based on the multiple compensation parameters.

[0082] In some embodiments, the target time parameter is used to indicate whether the impedance on the transmission path from the signal source to the target test location affects the target test unit set at the target test location from receiving the test signal; wherein, the target test location is the test location on the test platform that is closest to the signal source.

[0083] In some embodiments, the time parameters include: a clock signal of multiple frequencies, a set-up time of the test signal, and a correspondence of identification information; wherein, the identification information is used to indicate whether the test unit can accurately receive the test signal according to the clock signal of multiple frequencies when the test unit receives the test signal at multiple set-up times respectively.

[0084] In some embodiments, clock signals of multiple frequencies vary according to a first preset rule; and multiple setup times vary according to a second preset rule.

[0085] In some embodiments, the identification information includes: multiple sub-information, each sub-information indicating whether the test unit can accurately receive the test signal when receiving a clock signal of one frequency among multiple frequencies at one of multiple setup times; when the sub-information is in a first state, it indicates that the test unit can accurately receive the test signal when receiving the test signal at one setup time and according to a clock signal of one frequency; when the sub-information is in a second state, it indicates that the test unit cannot accurately receive the test signal when receiving the test signal at one setup time and according to a clock signal of one frequency.

[0086] In some embodiments, when the acquisition module 301 determines the time parameters of the first test unit among multiple test units, it is specifically configured to: determine the first clock signal among multiple frequency clock signals sent by the signal source to the first test unit; set the setup time of the first test unit to multiple setup times in sequence according to a second preset rule; control the first test unit to receive the test signal with the first clock signal according to the first setup time among multiple setup times; and determine the identification information corresponding to the first setup time and the first clock signal in the first time parameters according to whether the first test unit successfully receives the test signal.

[0087] In some embodiments, when determining the first compensation parameter of the first test unit among multiple test units, the processing module 302 is specifically configured to determine multiple critical setup times corresponding to the clock signal of each frequency in the first time parameter; wherein, when the first test unit receives the test signal with a clock signal of one frequency, the sub-information corresponding to the setup time greater than the critical setup time is a first state, and the sub-information less than the critical TIS is a second state; the first compensation parameter is obtained by the difference between the multiple critical setup times corresponding to the clock signal of each frequency in the target time parameter and the multiple critical setup times of the clock signal of each frequency in the first time parameter.

[0088] In some embodiments, the acquisition module 301 is further configured to acquire the target time parameters of the target test unit on the test platform.

[0089] In some embodiments, the acquisition module 301 is further configured to, when the standard test unit is at multiple test positions on the test platform, send test signals and clock signals to the standard test unit at the multiple test positions respectively; at each test position, control the standard test unit to receive the test signal with a clock signal according to a preset setup time; the processing module 302 is further configured to, determine the test position where the standard test unit cannot accurately receive the test signal at the multiple test positions as the position to be compensated, and perform time compensation on the clock signal at the position to be compensated.

[0090] It should be noted that the division of the various modules in the above device is merely a logical functional division. In actual implementation, they can be fully or partially integrated into a single physical entity, or they can be physically separated. These modules can be implemented entirely in software via processing element calls; they can be fully implemented in hardware; or some modules can be implemented by processing element calls to software, while others are implemented in hardware. They can be separate processing elements, integrated into a chip within the device, or stored as program code in the device's memory, invoked and executed by a processing element. The implementation of other modules is similar. Furthermore, these modules can be fully or partially integrated together, or implemented independently. The processing element described here can be an integrated circuit with signal processing capabilities. In the implementation process, each step of the above method or each of the above modules can be completed through integrated logic circuits in the hardware of the processor element or through software instructions.

[0091] For example, these modules can be one or more integrated circuits configured to implement the above methods, such as one or more application-specific integrated circuits (ASICs), one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs). As another example, when a module is implemented using processing element scheduler code, the processing element can be a general-purpose processor, such as a central processing unit (CPU) or other processor capable of calling program code. Furthermore, these modules can be integrated together to implement a system-on-a-chip (SOC).

[0092] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0093] This application also provides an electronic device, including: a processor and a memory; wherein the memory stores a computer program, and when the processor executes the computer program, the processor can be used to execute a time compensation method for a test signal as described in any of the foregoing embodiments of this application.

[0094] This application also provides a computer-readable storage medium storing a computer program, which, when executed, can be used to perform a time compensation method for a test signal as described in any of the foregoing embodiments of this application.

[0095] This application also provides a chip for executing instructions, the chip being used to perform a time compensation method for a test signal as executed by a compensation device in any of the foregoing embodiments of this application.

[0096] This application also provides a program product, which includes a computer program stored in a storage medium. At least one processor can read the computer program from the storage medium. When the at least one processor executes the computer program, it can implement the time compensation method for test signals executed by an electronic device as in any of the foregoing embodiments of this application.

[0097] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0098] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A time compensation method for a test signal, characterized in that, include: When the signal source sends test signals to test units at multiple test locations on the test platform, the time parameters of each test unit are obtained; wherein, the impedance on the transmission path between the signal source and each test location is different, and the time parameters are used to indicate whether the impedance on the transmission path affects the test unit's reception of the test signal; The time parameters include: clock signals of multiple frequencies, multiple establishment times of the test signal, and the corresponding relationship of identification information; The identification information is used to indicate whether the test unit can accurately receive the test signal according to the clock signals of the multiple frequencies when the test unit receives the test signal at multiple setup times respectively. Based on the target time parameter and the time parameter of each test unit, determine the compensation parameters corresponding to the multiple test positions where the multiple test units are located; Multiple compensation parameters corresponding to the multiple test positions are sent to the signal source so that the signal source performs time compensation on the clock signals sent to the multiple test positions according to the multiple compensation parameters.

2. The method according to claim 1, characterized in that, The target time parameter is used to indicate whether the impedance on the transmission path from the signal source to the target test location affects the target test unit set at the target test location from receiving the test signal; wherein, the target test location is the test location on the test platform that is closest to the signal source.

3. The method according to claim 1, characterized in that, The multiple frequency clock signals change according to a first preset rule; The multiple establishment times vary according to a second preset rule.

4. The method according to claim 3, characterized in that, The identification information includes: multiple sub-information, each sub-information used to indicate whether the test unit can accurately receive the test signal at one of the multiple establishment times, based on a clock signal at one of the multiple frequencies; When the sub-information is in the first state, it instructs the test unit to receive the test signal with a setup time and to accurately receive the test signal according to a clock signal of a certain frequency. When the sub-information is in the second state, it instructs the test unit to receive the test signal with a setup time and according to a clock signal of a frequency, but it cannot accurately receive the test signal.

5. The method according to claim 4, characterized in that, In obtaining the time parameters of each test unit, for the first test unit among the plurality of test units, obtaining the first time parameters of the first test unit includes: The signal source sends the test signal and the first clock signal from a plurality of clock signals to the first test unit. According to the second preset rule, the establishment time of the first test unit is sequentially set to the plurality of establishment times; The first test unit is controlled to receive the test signal using the first clock signal according to the first establishment time among the plurality of establishment times; Based on whether the first test unit successfully receives the test signal, the identification information corresponding to the first establishment time and the first clock signal in the first time parameters is determined.

6. The method according to claim 5, characterized in that, For the first test unit among the plurality of test units, a first compensation parameter corresponding to the first test position of the first test unit is determined based on the target time parameter and the first time parameter of the first test unit, including: In the first time parameter, multiple critical setup times are determined for each frequency of clock signal; wherein, when the first test unit receives the test signal with a clock signal of one frequency, the sub-information corresponding to the setup time that is greater than the critical setup time is the first state, and the sub-information that is less than the critical setup time is the second state. The first compensation parameter is obtained by subtracting the critical setup times of the clock signals at each frequency in the target time parameter from the critical setup times of the clock signals at each frequency in the first time parameter.

7. The method according to claim 6, characterized in that, The method further includes: Obtain the target time parameters of the target test unit on the test platform.

8. The method according to claim 7, characterized in that, The method further includes: When the standard test unit is at multiple test positions on the test platform, the signal source sends test signals and clock signals to the standard test unit at the multiple test positions respectively. At each test location, the standard test unit is controlled to receive the test signal using the clock signal according to a preset setup time; The test position where the standard test unit cannot accurately receive the test signal at the multiple test positions is determined as the position to be compensated, and time compensation is performed on the clock signal at the position to be compensated.

9. A time compensation device for a test signal, characterized in that, include: The acquisition module is configured to acquire time parameters for each test unit when a signal source sends a test signal to test units at multiple test locations on a test platform; wherein the impedance on the transmission path between the signal source and each test location is different, and the time parameters are used to indicate whether the impedance on the transmission path affects the test unit's reception of the test signal. The time parameters include: multiple clock signals of multiple frequencies, multiple establishment times of the test signal, and the corresponding relationship of identification information; wherein, the identification information is used to indicate whether the test unit can accurately receive the test signal according to the multiple clock signals of multiple frequencies when the test unit receives the test signal at multiple establishment times respectively. The processing module is configured to determine the compensation parameters corresponding to the multiple test positions where the multiple test units are located, based on the target time parameter and the time parameter of each test unit; The compensation module is configured to send multiple compensation parameters corresponding to the multiple test positions to the signal source, so that the signal source performs time compensation on the clock signals sent to the multiple test positions according to the multiple compensation parameters.

10. The apparatus according to claim 9, characterized in that, The target time parameter is used to indicate whether the impedance on the transmission path from the signal source to the target test location affects the target test unit set at the target test location from receiving the test signal; wherein, the target test location is the test location on the test platform that is closest to the signal source.

11. The apparatus according to claim 10, characterized in that, The multiple frequency clock signals change according to a first preset rule; The multiple establishment times vary according to a second preset rule.

12. The apparatus according to claim 11, characterized in that, The identification information includes: multiple sub-information, each sub-information used to indicate whether the test unit can accurately receive the test signal when the test unit receives a clock signal of one of the multiple frequencies at one of the multiple establishment times; When the sub-information is in the first state, it instructs the test unit to receive the test signal with a setup time and to accurately receive the test signal according to a clock signal of a certain frequency. When the sub-information is in the second state, it instructs the test unit to receive the test signal with a setup time and according to a clock signal of a frequency, but it cannot accurately receive the test signal.

13. The apparatus according to claim 12, characterized in that, When determining the time parameters of the first test unit among the plurality of test units, the acquisition module is specifically configured as follows: The signal source sends the test signal and the first clock signal from a plurality of clock signals to the first test unit. According to the second preset rule, the establishment time of the first test unit is sequentially set to the plurality of establishment times; The first test unit is controlled to receive the test signal using the first clock signal according to the first establishment time among the plurality of establishment times; Based on whether the first test unit successfully receives the test signal, the identification information corresponding to the first establishment time and the first clock signal in the first time parameters is determined.

14. The apparatus according to claim 13, characterized in that, When determining the first compensation parameter of the first test unit among the plurality of test units, the determining module is specifically configured as follows: In the first time parameter, multiple critical setup times are determined for each frequency of clock signal; wherein, when the first test unit receives the test signal with a clock signal of one frequency, the sub-information corresponding to the setup time when it is greater than the critical setup time is the first state, and the sub-information corresponding to the setup time when it is less than the critical setup time is the second state. The first compensation parameter is obtained by subtracting the critical setup times of the clock signals at each frequency in the target time parameter from the critical setup times of the clock signals at each frequency in the first time parameter.

15. The apparatus according to claim 14, characterized in that, The acquisition module is also used to acquire the target time parameters of the target test unit on the test platform.

16. The apparatus according to claim 15, characterized in that, The acquisition module is further configured to, when the standard test unit is at multiple test positions on the test platform, send test signals and clock signals to the standard test unit at the multiple test positions respectively; at each test position, control the standard test unit to receive the test signal with the clock signal according to a preset setup time; The processing module is further configured to determine the test position where the standard test unit cannot accurately receive the test signal at the plurality of test positions as the position to be compensated, and to perform time compensation on the clock signal at the position to be compensated.

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