Bandgap reference circuit and chip

Abstract

The application discloses a band gap reference circuit, comprising a first MOS transistor, a first resistor, a second resistor, a third resistor, a first triode group, a second triode group and an operational amplifier; the operational amplifier comprises a third triode group, a fourth triode group, a current mirror unit and a current limiting unit. According to the band gap reference circuit of the embodiment of the application, the number ratio of the third triode and the fourth triode is configured as 1:m (m>=2) to form an asymmetric input differential pair transistor, a system misadjustment voltage is generated, the amplification multiple of the PTAT voltage is reduced, and the noise and the misadjustment voltage of the output reference voltage of the band gap reference circuit are reduced.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a bandgap reference circuit and chip. Background Technology

[0002] like Figure 1 As shown, the bandgap reference circuit of this structure has a reference voltage VBG = VBE² + (k+1)*V. T *ln(n), where k=R2 / R3, R2 is the resistance of the second resistor, R3 is the resistance of the third resistor, VBE2 is the voltage between the base and emitter of the second transistor Q2, V T This represents the thermal voltage, V at a temperature of 300K. T ≈26mV. If n=8, then k is approximately equal to 10. At this time, the input noise and offset voltage of the operational amplifier OP1 will be amplified by (R3+R2) / R3=k+1 times.

[0003] The large amplification factor for noise is relatively limited in low-noise scenarios. Assuming the noise frequency is between 0.1Hz and 10Hz, the noise of operational amplifier OP1 is 2μVrms, and the noise obtained at the reference voltage VBG will be 22μVrms.

[0004] A large amplification factor of the input offset voltage of an operational amplifier will result in a relatively discrete reference voltage VBG generated by the same chip. Assuming that the input noise Vos of operational amplifier OP1 corresponds to 1mV at a 1sigma yield, the noise on the reference voltage VBG will reach 11mV at the same 1sigma yield. If the yield is within 3sigma, the range of the reference voltage VBG will reach 1.2±33mV. During single-temperature calibration, the large range of the reference voltage VBG greatly limits the TC performance of the bandgap reference circuit after calibration.

[0005] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a bandgap reference circuit and chip that can reduce the amplification of input noise and offset voltage.

[0007] To achieve the above objectives, embodiments of the present invention provide a bandgap reference circuit, comprising: a first MOS transistor, a first resistor, a second resistor, a third resistor, a first transistor group, a second transistor group, and an operational amplifier.

[0008] The first triode group comprises one first triode or a plurality of first triodes connected in parallel, and the second triode group comprises a plurality of second triodes connected in parallel, the number ratio of the first triodes to the second triodes being 1:n, n≥2.

[0009] The base and the collector of the first triode are connected, and are connected to the first end of the first resistor and the first input end of the operational amplifier at the same time, the base and the collector of the second triode are connected, and are connected to the first end of the third resistor, the emitter of the first triode and the emitter of the second triode are connected to the ground voltage, the second end of the third resistor is connected to the second input end of the operational amplifier and the first end of the second resistor, the output end of the operational amplifier is connected to the gate of the first MOS tube, the source of the first MOS tube is connected to the power supply voltage, and the second end of the first resistor and the second end of the second resistor are connected to the drain of the first MOS tube.

[0010] The operational amplifier comprises a third triode group, a fourth triode group, a current mirror unit and a current limiting unit.

[0011] The third triode group comprises one third triode or a plurality of third triodes connected in parallel, and the fourth triode group comprises a plurality of fourth triodes connected in parallel, the number ratio of the third triodes to the fourth triodes being 1:m, m≥2.

[0012] The emitter of the third triode and the emitter of the fourth triode are connected to the current limiting unit, the collector of the third triode and the collector of the fourth triode are connected to the current mirror unit, and the base of the third triode and the base of the fourth triode are the first input end and the second input end of the operational amplifier respectively.

[0013] In one or more embodiments of the present application, the resistance values of the first resistor, the second resistor and the third resistor satisfy Wherein, R1, R2 and R3 are the resistance values of the first resistor, the second resistor and the third resistor respectively.

[0014] In one or more embodiments of the present application, the current mirror unit comprises a second MOS tube and a third MOS tube, the gate of the second MOS tube and the gate of the third MOS tube are connected, the gate and the drain of the second MOS tube are connected and are connected to the collector of the third triode, the drain of the third MOS tube is connected to the collector of the fourth triode, and the source of the second MOS tube and the source of the third MOS tube are connected to the power supply voltage.

[0015] In one or more embodiments of the present application, the current mirror unit comprises a fifth transistor and a sixth transistor, the bases of the fifth and sixth transistors are connected, the base and the collector of the fifth transistor are connected and connected to the collector of the third transistor, the collector of the sixth transistor is connected to the collector of the fourth transistor, the emitters of the fifth and sixth transistors are connected to the power supply voltage.

[0016] In one or more embodiments of the present application, the current mirror unit further comprises a fourth resistor and a fifth resistor, the first end of the fourth resistor is connected to the source of the second MOS transistor, the first end of the fifth resistor is connected to the source of the third MOS transistor, the second ends of the fourth and fifth resistors are connected to the power supply voltage; the first end of the fourth resistor is connected to the emitter of the fifth transistor, the first end of the fifth resistor is connected to the emitter of the sixth transistor, and the second ends of the fourth and fifth resistors are connected to the power supply voltage.

[0017] In one or more embodiments of the present application, the current limiting unit comprises a current limiting resistor, the first end of the current limiting resistor is connected to the emitters of the third and fourth transistors, and the second end of the current limiting resistor is connected to the ground voltage.

[0018] In one or more embodiments of the present application, the resistance value of the current limiting resistor is Wherein, V T represents the thermal voltage, I1 represents the current on the first resistor, and I2 represents the total drain current of the third transistor group or the total drain current of the fourth transistor group.

[0019] In one or more embodiments of the present application, the bandgap reference circuit further comprises another group or multiple groups of the first transistor group connected in series with the first transistor group, and another group or multiple groups of the second transistor group connected in series with the second transistor group, wherein the number of groups of the first transistor groups connected in series is equal to the number of groups of the second transistor groups connected in series.

[0020] In one or more embodiments of the present application, the base and the collector of the second transistor are connected, and at the same time connected to the second input terminal of the operational amplifier and the first end of the second resistor, the emitter of the second transistor is connected to the first end of the third resistor, and the second end of the third resistor is connected to the ground voltage.

[0021] The present application also discloses a chip comprising the bandgap reference circuit.

[0022] Compared with the prior art, the bandgap reference circuit and the chip according to the embodiment of the application reduce the multiple of the PTAT voltage amplified, reduce the noise and the offset voltage of the bandgap reference circuit output reference voltage by configuring the number ratio of the third transistor and the fourth transistor as 1:m (m≥2) to form an asymmetric input differential pair transistor, and generating a system offset voltage. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 is a circuit schematic diagram of a bandgap reference circuit according to an embodiment of the application.

[0024] Figure 2 is a circuit schematic diagram of an operational amplifier according to an embodiment of the application. DETAILED DESCRIPTION

[0025] The specific embodiments of the application are described below in detail with reference to the accompanying drawings, but the protection scope of the application is not limited by the specific embodiments.

[0026] Unless otherwise clearly indicated, in the entire specification and claims, the term "comprise" or its variants such as "comprises" or "comprising" will be understood to encompass the stated elements or components, but not to exclude the presence of other elements or components.

[0027] As shown in Figure 1 A bandgap reference circuit includes a first MOS transistor MP1, a first resistor R1, a second resistor R2, a third resistor R3, a first transistor group, a second transistor group, and an operational amplifier OP1.

[0028] The first transistor group includes one or more first transistors Q1, and if multiple first transistors Q1 are provided, the multiple first transistors Q1 are connected in parallel (i.e., the bases, the emitters, and the collectors of the first transistors Q1 are connected).

[0029] The first transistors Q1 and the second transistors Q2 are NPN type transistors, and the number ratio of the first transistors Q1 to the second transistors Q2 is 1:n, where n is an integer greater than or equal to 2. In an embodiment, n is 4-10. In this embodiment, one first transistor Q1 is provided, and eight second transistors Q2 are provided, and the number ratio of the first transistors Q1 to the second transistors Q2 is 1:8. In other embodiments, n can take other values in the range of 4-10, and the first transistors Q1 and the second transistors Q2 can also be PNP type transistors.

[0030] Furthermore, the base and collector of the first transistor Q1 are connected to both the first terminal of the first resistor R1 and the first input terminal of the operational amplifier OP1. The base and collector of the second transistor Q2 are connected to both the first terminal of the third resistor R3. The second terminal of the third resistor R3 is connected to both the second input terminal of the operational amplifier OP1 and the first terminal of the second resistor R2. In this embodiment, the first input terminal of the operational amplifier OP1 is a negative input terminal, and the second input terminal of the operational amplifier OP1 is a positive input terminal. In other embodiments, the first input terminal of the operational amplifier OP1 is a positive input terminal, and the second input terminal of the operational amplifier OP1 is a negative input terminal.

[0031] The emitters of the first transistor Q1 and the second transistor Q2 are connected to ground. The output terminal of the operational amplifier OP1 is connected to the gate of the first MOSFET MP1. The source of the first MOSFET MP1 is connected to the power supply voltage. The second terminals of the first resistor R1 and the second resistor R2 are connected to the drain of the first MOSFET MP1 and are used to output the reference voltage VBG.

[0032] In other embodiments, the positions of the second transistor Q2 and the third resistor R3 can be interchanged. Specifically, the base and collector of the second transistor Q2 are connected to the second input terminal of the operational amplifier OP1 and the first terminal of the second resistor R2. The emitter of the second transistor Q2 is connected to the first terminal of the third resistor R3, and the second terminal of the third resistor R3 is connected to ground.

[0033] In other embodiments, one or more first transistor groups are connected in series with the first transistor group, and one or more second transistor groups are connected in series with the second transistor group. The number of first transistor groups connected in series is equal to the number of second transistor groups connected in series. That is, two or more first transistor groups are connected in series between the connection point of the first input terminal of operational amplifier OP1 and the first terminal of the first resistor R1 and ground. Two or more second transistor groups are connected in series between the first terminal of the third resistor R3 and ground. Preferably, connecting two first transistor groups and two second transistor groups in series can achieve a low-noise, low-offset reference voltage VBG output of 2.5V.

[0034] like Figure 2 As shown, the operational amplifier OP1 includes: a third transistor group, a fourth transistor group, a current mirror unit 10, and a current limiting unit 20.

[0035] The third transistor group includes one or more third transistors Q3. If multiple third transistors Q3 are provided, they are connected in parallel. The fourth transistor group includes multiple fourth transistors Q4, which are connected in parallel.

[0036] Both the third transistor Q3 and the fourth transistor Q4 are NPN transistors, and the ratio of the number of third transistors Q3 to the number of fourth transistors Q4 is 1:m, where m is an integer greater than or equal to 2. In one embodiment, m is 4 to 10. In this embodiment, there is one third transistor Q3 and eight fourth transistors Q4, with a ratio of 1:8. In other embodiments, m can take other values ​​from 4 to 10, and m may not be equal to n; the third transistor Q3 and the fourth transistor Q4 may also be PNP transistors.

[0037] The emitters of the third transistor Q3 and the fourth transistor Q4 are connected to the current limiting unit 20, and the collectors of the third transistor Q3 and the fourth transistor Q4 are connected to the current mirror unit 10. The bases of the third transistor Q3 and the fourth transistor Q4 are the first input terminal and the second input terminal of the operational amplifier OP1, respectively.

[0038] like Figure 2 As shown, the current mirror unit 10 includes a fourth resistor R4, a fifth resistor R5, a second MOSFET MP2, and a third MOSFET MP3. The gates of the second MOSFET MP2 and the third MOSFET MP3 are connected. The gate and drain of the second MOSFET MP2 are connected and connected to the collector of the third transistor Q3. The drain of the third MOSFET MP3 is connected to the collector of the fourth transistor Q4. The first terminal of the fourth resistor R4 is connected to the source of the second MOSFET MP2, and the first terminal of the fifth resistor R5 is connected to the source of the third MOSFET MP3. The second terminals of the fourth resistor R4 and the fifth resistor R5 are connected to the power supply voltage. The fourth resistor R4 and the fifth resistor R5 are used to reduce the mismatch and noise of the current mirror unit 10. In other embodiments, the width-to-length ratios of the second MOSFET MP2 and the third MOSFET MP3 can be set to be different, and m and n can be configured to be unequal, which can further increase the PTAT voltage and reduce the amplification factor of input noise and offset voltage.

[0039] In other embodiments, PNP type fifth and sixth transistors can be used in the current mirror unit 10 to replace the second MOSFET MP2 and the third MOSFET MP3, while also optimizing the circuit's noise performance. Specifically, the bases of the fifth and sixth transistors are connected, the base and collector of the fifth transistor are connected and connected to the collector of the third transistor Q3, the collector of the sixth transistor is connected to the collector of the fourth transistor Q4, and the emitters of the fifth and sixth transistors are connected to the power supply voltage. Additionally, the fourth resistor R4 and the fifth resistor R5 can be provided or omitted as needed.

[0040] The current-limiting unit 20 comprises a current-limiting resistor RS, a first end of the current-limiting resistor RS is connected with the emitter of the third transistor Q3 and the fourth transistor Q4, a second end of the current-limiting resistor RS is connected with the ground voltage, and the resistance value of the current-limiting resistor RS is equal to one-eighth to one-half of the resistance value of the third resistor R3. In the embodiment, the resistance value of the current-limiting resistor RS is preferably equal to one-quarter of the resistance value of the third resistor R3.

[0041] In the embodiment, by setting the number ratio of the third transistor Q3 and the fourth transistor Q4 as 1:m, a system offset voltage V T *ln(m) is introduced, at this time, the voltage across the third resistor R3 becomes V T *ln(n)+V T *ln(m), for m=n=8, the voltage across the third resistor R3 is doubled, the compensation coefficient required for realizing zero temperature drift is reduced, thereby reducing the contribution of the operational amplifier to the output voltage noise and offset voltage, and the compensation coefficient can be represented by the value of R2 / R3. For m=n=8, the reference voltage VBG=VBE2+2*V T *ln(8)*(k1+1), where k1=R2 / R3≈5, R2 is the resistance value of the second resistor, R3 is the resistance value of the third resistor, VBE2 is the voltage between the base and the emitter of the second transistor Q2, V T represents the thermal voltage, when the temperature is 300K, V T ≈26mV, then the offset voltage Vos and the noise noise are amplified by about 5 times on the reference voltage VBG.

[0042] That is, assuming that the noise frequency is at 0.1Hz-10Hz, the input noise Vos of the operational amplifier OP1 is 2μVrms, and the noise on the reference voltage VBG is 10μVrms. Assuming that the input noise Vos of the operational amplifier OP1 is 1mV within 1sigma, and the output reference voltage VBG is 5.5mV within 1sigma, if within 3sigma, the voltage range of the reference voltage VBG is 1.2±16.5mV, it can be seen that by configuring the number ratio of the third transistor and the fourth transistor to form an asymmetric input differential pair transistor, the voltage range of the reference voltage VBG is greatly reduced within 1sigma and 3sigma.

[0043] When the input end of the operational amplifier is designed symmetrically, there is no voltage difference between the first end of the first resistor R1 and the first end of the second resistor R2, and only the resistance value of the first resistor R1 needs to be equal to the resistance value of the second resistor R2, so that the bias currents of the first transistor Q1 and the second transistor Q2 are equal. When the input end of the operational amplifier OP1 is designed asymmetrically in the application, the resistance values of the first resistor R1, the second resistor R2 and the third resistor R3 satisfy the following relationship, so that the bias currents of the first transistor Q1 and the second transistor Q2 are equal.

[0044]

[0045] In the formula, R1, R2 and R3 are the resistance values of the first resistor, the second resistor and the third resistor respectively; the application uses the resistance structure to bias the first transistor Q1 and the second transistor Q2, and compared with using a pair of current mirrors to realize the current bias of the first transistor Q1 and the second transistor Q2, the application avoids introducing additional noise and offset voltage by the current mirror.

[0046] Since the input common mode of the input end of the operational amplifier OP1 is lifted by V T In(8), the current limiting resistor RS is set to limit the current, and the currents between the first transistor Q1 and the second transistor Q2 and between the third transistor Q3 and the fourth transistor Q4 are relatively close.

[0047] In the application, the bias current of the operational amplifier OP1 is generated by using the current limiting resistor RS, which avoids the problems of introducing additional bias circuit power consumption and limiting the startup speed of the bias circuit during the power-on startup when the mirror current is introduced from the main part of the bandgap reference circuit, and also avoids the problem that the input tube of the operational amplifier directly introduces the mirror current from the main part of the bandgap reference circuit, which causes the power consumption to increase by m times. When the current of the main part of the bandgap reference circuit, i.e. the current of the first resistor R1 is I1, and the bias current of each branch of the operational amplifier OP1, i.e. the drain current of the third transistor Q3 or the fourth transistor Q4 is I2, the resistance value of the current limiting resistor RS needs to satisfy the following formula:

[0048]

[0049] When I1=I2,

[0050] The application further discloses a chip comprising the bandgap reference circuit.

[0051] The foregoing description of specific exemplary embodiments of the application has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the application to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. It is intended that the scope of the application be limited not with this detailed description, but rather by the claims appended hereto.

Claims

1. A bandgap reference circuit, characterized by, The application relates to a reference voltage generating circuit, which comprises a first MOS transistor, a first resistor, a second resistor, a third resistor, a first triode group, a second triode group and an operational amplifier. The first triode group comprises one first triode or a plurality of first triodes connected in parallel, the second triode group comprises a plurality of second triodes connected in parallel, the number ratio of the first triodes to the second triodes is 1:n, and n>=2. The base and the collector of the first triode are connected, and the first end of the first resistor and the first input end of the operational amplifier are connected; the base and the collector of the second triode are connected, and the first end of the third resistor is connected; the emitters of the first triode and the second triode are connected to the ground voltage; the second end of the third resistor is connected to the second input end of the operational amplifier and the first end of the second resistor; the output end of the operational amplifier is connected to the gate of the first MOS transistor; the source of the first MOS transistor is connected to the power supply voltage; the second end of the first resistor and the second end of the second resistor are connected to the drain of the first MOS transistor to output a reference voltage. The operational amplifier comprises a third triode group, a fourth triode group, a current mirror unit and a current limiting unit. The third triode group comprises one third triode or a plurality of third triodes connected in parallel, the fourth triode group comprises a plurality of fourth triodes connected in parallel, the number ratio of the third triodes to the fourth triodes is 1:m, and m>=2. The emitters of the third triode and the fourth triode are connected to the current limiting unit; the collectors of the third triode and the fourth triode are connected to the current mirror unit; the bases of the third triode and the fourth triode are the first input end and the second input end of the operational amplifier respectively. The current mirror unit comprises a second MOS transistor and a third MOS transistor, the gates of the second MOS transistor and the third MOS transistor are connected, the gate and the drain of the second MOS transistor are connected and connected to the collector of the third triode, the drain of the third MOS transistor is connected to the collector of the fourth triode, and the sources of the second MOS transistor and the third MOS transistor are connected to the power supply voltage. wherein R1, R2, R3 are the resistance values of the first, second, third resistors, respectively; The reference voltage = VBE2 + ×ln(n)+ ×ln(m)×(k1+1), where k1= R2 / R3, R2 is the resistance of the second resistor, R3 is the resistance of the third resistor, and VBE2 is the voltage between the base and emitter of the second transistor. Indicates thermal voltage; The current limiting unit comprises a current limiting resistor, a first end of the current limiting resistor is connected with the emitter of the third transistor and the fourth transistor, a second end of the current limiting resistor is connected with the ground voltage, and the resistance value of the current limiting resistor is wherein, represents the thermal voltage, I1 represents the current on the first resistor, and I2 represents the total drain current of the third transistor group or the total drain current of the fourth transistor group.

2. The bandgap reference circuit of claim 1, wherein, The current mirror unit comprises a fifth triode and a sixth triode, the bases of the fifth triode and the sixth triode are connected, the base and the collector of the fifth triode are connected and connected to the collector of the third triode, the collector of the sixth triode is connected to the collector of the fourth triode, and the emitters of the fifth triode and the sixth triode are connected to the power supply voltage.

3. The bandgap reference circuit of claim 1, wherein, The current mirror unit further comprises a fourth resistor and a fifth resistor, the first end of the fourth resistor is connected to the source of the second MOS transistor, the first end of the fifth resistor is connected to the source of the third MOS transistor, the second end of the fourth resistor and the second end of the fifth resistor are connected to the power supply voltage; the first end of the fourth resistor is connected to the emitter of the fifth triode, the first end of the fifth resistor is connected to the emitter of the sixth triode, and the second end of the fourth resistor and the second end of the fifth resistor are connected to the power supply voltage.

4. The bandgap reference circuit of claim 2 or 3, wherein, The resistance value of the current limiting resistor is equal to one fourth of the resistance value of the third resistor.

5. The bandgap reference circuit of claim 1, wherein, ​ 6. The bandgap reference circuit of claim 1, wherein, The bandgap reference circuit further comprises another group or multiple groups of the first triode groups connected in series with the first triode group, and another group or multiple groups of the second triode groups connected in series with the second triode group, wherein the number of groups of the first triode groups connected in series is equal to the number of groups of the second triode groups connected in series.

7. The bandgap reference circuit of claim 1, wherein, The base of the second triode is connected with the collector and simultaneously connected with the second input of the operational amplifier and the first end of the second resistor, the emitter of the second triode is connected with the first end of the third resistor, and the second end of the third resistor is connected with the ground voltage.

8. A chip, characterized by A bandgap reference circuit as claimed in any one of claims 1 to 7.

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