A Real-Time Super-Resolution Method for Millimeter-Wave TDM-MIMO Radar Based on FPGA

Abstract

This invention discloses a real-time super-resolution method for millimeter-wave TDM-MIMO radar based on FPGA, applied in the field of radar imaging technology. Addressing the problems of high computational complexity and the inability of traditional hardware signal processing platforms to meet rapid computation requirements in existing technologies, this invention utilizes a high-speed interface to send acquired radar data to an FPGA board. The FPGA board parses and caches the radar data, preprocesses it, and sends the valid radar data. Hardware-optimized design is employed for radar data processing to recursively estimate intermediate variables. Auxiliary variables are iteratively updated based on the intermediate variables, and data variables are rapidly cached. This invention achieves rapid angle estimation through iterative updates using loop minimization. This invention overcomes the shortcomings of high algorithm complexity and difficulty in real-time signal processing in existing super-resolution DOA technologies, significantly improving the computational efficiency of the algorithm.

Description

Technical Field

[0001] This invention belongs to the field of radar imaging technology, and specifically relates to a high-throughput super-resolution processing technology for millimeter-wave radar. Background Technology

[0002] Time-division multiplexing multiple-input multiple-output (TDM-MIMO) radar direction-of-arrival (DOA) estimation plays an important role in applications such as battlefield target localization and tracking and automotive assisted driving. The angular resolution of direct digital beamforming DOA estimation methods is limited by the number of physical array elements. Considering factors such as space and cost, the method of increasing the number of array elements to improve angular resolution has great limitations in practical engineering applications. The literature "T.Yardibi, J.Li, P.Stoica, M.Xue and A.B.Baggeroer, Source Localization and Sensing: A Nonparametric Iterative Adaptive Approach Based on Weighted Least Squares, in IEEE Transactions on Aerospace and Electronic Systems.2010,46(1):425-443" proposes an iterative adaptive algorithm (IAA). This method reduces the requirement for the number of snapshots in traditional spectral estimation methods through iterative adaptive updating of the autocorrelation matrix, effectively improving the azimuth resolution of millimeter-wave radar. However, the improvement in resolution of the IAA algorithm comes at the cost of computational efficiency, which severely restricts the real-time requirements of IAA in practical applications. To further improve resolution, the paper "P. Stoica, P. Babu and J. Li, New Method of Sparse Parameter Estimation in Separable Models and Its Use for Spectral Analysis of Irregularly Sampled Data, in IEEE Transactions on Signal Processing, 2011, 59(1):35-47" proposes a sparse iterative estimation algorithm based on covariance (SPICE), which is derived from a covariance fitting criterion. It can accurately reconstruct the target and information in the case of multiple snapshots, has a simple and stable statistical basis, does not require the selection of any parameters, and has the characteristic of global convergence. However, the computational complexity of the SPICE algorithm is still relatively high. The large matrix operations involved in it cannot meet the requirements of fast computation and processing by traditional hardware signal processing platforms. Summary of the Invention

[0003] To address the aforementioned technical problems, this invention proposes a real-time super-resolution method for millimeter-wave TDM-MIMO radar based on FPGA. Field-programmable arrays (FPGAs) can be tailored to project requirements and signal processing algorithms, allowing for repeated programming and reconfiguration without altering the radar hardware system, thus reducing the cost of subsequent algorithm optimization, system updates, and maintenance. To address the high computational complexity of the SPICE algorithm, the parallel architecture of FPGA can be utilized to study the design and implementation of its high-speed processing hardware algorithm.

[0004] The technical solution adopted in this invention is: a real-time super-resolution method for millimeter-wave TDM-MIMO radar based on FPGA, comprising:

[0005] S1. Collect sparse scene target samples and obtain radar data;

[0006] S2. Use the high-speed interface to send radar data to the FPGA board;

[0007] S3, the FPGA board parses and caches radar data, preprocesses and sends valid radar data;

[0008] S4. Adopt hardware optimization design for radar data processing to achieve recursive estimation of intermediate variables;

[0009] S5. Iteratively update auxiliary variables based on intermediate variables and quickly cache data variables;

[0010] S6. Implement iterative updates of fast angle estimates by using loop minimization.

[0011] The beneficial effects of this invention are as follows: The method of this invention overcomes the shortcomings of existing technologies, such as high algorithm complexity, difficulty in implementation on signal processing platforms, or excessively long processing times. This invention employs a simple implementation using loop minimization, achieving efficient computation with constant computational and storage costs even when processing large amounts of data. Furthermore, its recursive estimation method replaces the original batch data processing mode, utilizing a parallel matrix computation structure and a lookup table method to solve floating-point square root operations, significantly shortening computation time and enabling the system to process data in real time. Attached Figure Description

[0012] Figure 1 This is a flowchart of the present invention;

[0013] Figure 2 This is a diagram of the radio frequency board module in this embodiment;

[0014] Figure 3 This is a diagram of the high-speed interface module in this embodiment;

[0015] Figure 4 This is a diagram of the radar data receiving module in this embodiment;

[0016] Figure 5 This is a schematic diagram illustrating the column vector representation of the Toplitz matrix in this embodiment;

[0017] Figure 6 This is a diagram of the Toplitz matrix Γ data output module in this embodiment;

[0018] Figure 7 This is a diagram of the vector ρ calculation module in this embodiment;

[0019] Figure 8 This is the top-level module diagram for calculating auxiliary variables in this implementation method;

[0020] Figure 9 This is a diagram of the operator vector dot product (dot) module in this embodiment;

[0021] Figure 10 This is a diagram of the serial-to-parallel conversion module in this embodiment;

[0022] Figure 11 This is a top-level module diagram for angle estimation in this embodiment;

[0023] Figure 12 This is a diagram of the single-precision floating-point number lookup table and square root module in this embodiment;

[0024] Figure 13 This is a multiple-input multiple-output (MIMO) point target echo map of this embodiment;

[0025] in, Figure 13 (a) is the echo map of the first two point targets before the system processed them; Figure 13 (b) is the echo map of the two point targets after system processing. Detailed Implementation

[0026] To facilitate understanding of the technical content of this invention by those skilled in the art, the following description, in conjunction with the accompanying drawings, further illustrates the invention.

[0027] This invention provides a real-time super-resolution method for millimeter-wave TDM-MIMO radar based on FPGA, overcoming the shortcomings of existing technologies such as high algorithm complexity, difficulty in implementation by signal processing platforms, or excessively long processing times. By combining a hardware signal processing platform and implementing a super-resolution algorithm, the resolution of millimeter-wave MIMO radar is improved, enabling real-time imaging of targets. Even when processing large amounts of data, efficient computation can be achieved with constant computational and storage costs.

[0028] Combined with appendix Figure 1 The specific implementation steps of the present invention are described as follows:

[0029] S1. Collect sparse scene target samples to obtain radar data. For example... Figure 2 As shown, in this embodiment, the number of angle sampling points K is 256, and the angle sampling value is θ=(θ1,θ2,…,θ 256 The millimeter-wave TDM-MIMO radar has 12 transmitting antennas (M) and 16 receiving antennas (N). The radar transmits at a specific pulse repetition frequency (i.e.,...). Figure 2 The linear frequency modulated signal of channel TX[3:1]12 in the radar is received (i.e., during the time interval between adjacent transmitted pulses) by the radar. Figure 2 The RX[4:1]) 16 channel echo signal is converted from digital to analog and then sent from the digital to analog converter buffer to the FPGA via the CSI2 interface.

[0030] S2. Utilize a high-speed interface to send radar data to the FPGA board. The data interface is CSI2, such as... Figure 3 As shown, the CSI2 interface is configured with one clock lane and four data lanes, as well as an additional general-purpose input / output interface configured with a frame synchronization signal (Frame Syn), for a total of six pairs of differential signals. The four data lanes are controlled by the clock lane and Frame Syn for radar data synchronization transmission. The control interface is a Serial Peripheral Interface (SPI), with the radar board acting as the master sending Valid and the FPGA acting as the slave sending Ready. These two signals control the transmission and reception of radar data based on a handshake protocol.

[0031] The S3 and FPGA boards parse and cache radar data, preprocess it, and then send valid radar data. Specifically, for example... Figure 4 As shown, the 4-channel radar data is controlled by a Finite State Machine (FSM) module and transmitted into the MIPI CSI2 Rx module on the FPGA board. The module then parses the incoming radar data packets into a data stream. Specifically, the Differential-to-Single-Ended (IBUFDS) module converts the incoming Differential Signals (LVDS) into single-ended signals. Then, the Serial-to-Parallel (SEP) module converts the serially input single-ended data into 16-bit output data. The Packet Parsing module identifies the frame header flag, frame count, waveform information, chip number, channel information, and frame tail flag to complete data framing. Subsequently, radar data is buffered. Since there are two clock sources—the data synchronization clock and the FPGA's own configuration clock—an asynchronous FIFO is used for cross-clock domain data buffering.

[0032] Specifically, to improve the overall processing system's computational accuracy, all data is processed in single-precision floating-point format. Therefore, the ADC data transmitted from the radar board, after being buffered, needs to be converted from integer to single-precision floating-point in the data conversion module (float convert) before it can be used by subsequent modules. Specifically, the sign bit remains unchanged, the highest non-zero bit is added to an offset of 127 to form an 8-bit floating-point exponent, and all data after the highest bit are padded with zeros to form a 23-bit mantissa, ultimately converting it to a 32-bit single-precision floating-point number.

[0033] S4. Hardware optimization design is used to process radar data, achieving recursive estimation of intermediate variables. The three intermediate variables calculated recursively are as follows:

[0034] κ(m)=κ(m-1)+y(m) H *y(m) (1)

[0035] ρ(m)=ρ(m-1)+h(m) H *y(m) (2)

[0036] Γ(m)=Γ(m-1)+h(m) H *h(m) (3)

[0037] Where κ(0), ρ(0), and Γ(0) are initial zero values, and y(m) is the data from the N receiving antennas corresponding to the m-th (m=1,…,M) transmitting antenna of the TDM-MIMO radar, i.e., the radar data buffered in S3; y(m) H Let y(m) be the conjugate transpose of y(m). h(m) is the manipulation matrix H determined by the array. It is a complex matrix of 192*256. Let H represent the m-th row vector of the complex field, where the manipulation matrix H is stored in the FPGA's memory cell and the matrix data is read to complete the calculation when formula (2).

[0038] Γ(m) is a special toeplitz matrix. To speed up the process and save computational costs, the Γ(m) matrix is ​​replaced with pre-stored data. For example... Figure 5 As shown, based on the characteristics of the toeplitz matrix, the column vector can be obtained by cyclically shifting the previous column vector downwards. This characteristic is consistent with the characteristics of a circular queue. Therefore, the data of the Γ(m) matrix can be expressed by a single column element of the circular queue composed of the FPGA's internal memory Block RAM (BRAM), which can save 256 times the storage resources.

[0039] Specifically, such as Figure 6As shown, this design employs a 32-degree parallelism for a 256*256 matrix. As mentioned above, for a 256*256 matrix, only the first column of elements needs to be selected to represent the entire matrix. This design utilizes eight BRAMs, each storing 2048 bits of data. Each BRAM outputs 32 64-bit complex single-precision floating-point numbers. The first clock cycle outputs the 32 data points from RAM1, the second clock cycle outputs the data from RAM2, and so on, executed eight times via an 8-to-1 data selector to complete the output of the first column of 256 data points. Simultaneously with the output of the eighth clock cycle, data is transferred via a RAM read / write controller to form the second column of the toeplitz matrix. Data output then continues, repeating this cycle until the entire matrix operation is complete.

[0040] like Figure 7 As shown, when calculating ρ(m), the current vector value needs to be stored for the next recursive calculation. The initial value in ρRAM1 is 0. During the first operation, the value in ρRAM1 is read and used to calculate h(m). H The values ​​of *y(m) are added to complete the recursive operation, and the result is stored in ρRAM2. At the end of the entire calculation process, ρcontrol controls the data read / write process between ρRAM1 and ρRAM2, writing the data from ρRAM2 into ρRAM1, completing seamless data transfer. κ(m) has a similar structure, but the difference is that the calculation result of κ(m) is a single numerical value. Therefore, only two registers, reg, are needed to replace RAM1 and RAM2 in the ρ calculation, respectively.

[0041] S5. Calculate and iteratively update the auxiliary variables, and quickly cache the data variables. The calculation steps are as follows:

[0042] η=κ(m)+θ H Γ(m)θ-2real{θ H ρ(m)} (4)

[0043] ζ=ρ(m)-Γ(m)θ (5)

[0044] Where real represents the real part of the complex number. For example... Figure 8 The diagram shows the top-level module diagram for the recursive estimation of intermediate variables in S4 and the calculation of auxiliary variables in S5. χ=Γ(m)θ、ε=θ H ρ(m), δ=θ H χ represents the application of the operator vector dot product (dot) module. Specifically, the design diagram of the operator dot module is shown below. Figure 9 As shown, the data is sequentially processed by complex multiplication with 32 degrees of parallelism, then the 32 numbers are added together by a low-latency adder, and finally passed through the data stream 8 times by an adder to obtain the sum of 256 complex multiplications, which is the final value of the vector dot product.

[0045] Since the subsequent calculations are still 32-bit parallel computations, the calculated vectors χ and ε need to be converted from serial to parallel outputs using a serial-to-parallel conversion module. Specifically, as follows... Figure 10 As shown, the serial-to-parallel conversion module uses a counter to buffer data via BRAM. After buffering, a pull-high control command sends out 32 data points simultaneously. To reduce fan-out, the 32 data points are sequentially merged from the most significant bit to the least significant bit and then sent as a single data point, thus converting the serial data into 32 parallel data outputs. Finally, the calculated auxiliary variables η and ζ are sent to the S6 module for angle estimation.

[0046] S6. Implement iterative updates of the fast angle estimate using loop minimization. The computational steps of the entire algorithm are as follows:

[0047] for m=1,…,M

[0048] κ(m)=κ(m-1)+y(m) H *y(m) (6)

[0049] ρ(m)=ρ(m-1)+h(m) H *y(m) (7)

[0050] Γ(m)=Γ(m-1)+h(m) H *h(m) (8)

[0051] η=κ(m)+θ H Γ(m)θ-2real{θ H ρ(m)} (9)

[0052] ζ=ρ(m)-Γ(m)θ (10)

[0053] for k = 1, ..., K

[0054] n=(m-1)*16+1 (11)

[0055] α k =η+Γ kk |θ k | 2 +2real{θ k ζ k} (12)

[0056] β k =Γ kk (13)

[0057] γ k =|ζ k +Γ kk θ k | (14)

[0058]

[0059]

[0060]

[0061]

[0062]

[0063]

[0064] end for

[0065] end for

[0066] Formulas (6)-(10) represent the calculation processes for S4 and S5, and formulas (11)-(20) represent the calculation process for iteratively updating the fast angle estimate by minimizing the loop in S6. M is set to 12 for the number of transmitting antennas in the millimeter-wave TDM-MIMO radar, K is set to 256 for the number of angle sampling points, and ζ... k and θ k These are the k-th elements of vectors ζ and θ, respectively, and Γ is the k-th element. kk and Γ k These are the k-th diagonal element and the k-th column element of the Γ matrix, respectively. The three variables θ are obtained using formulas (17)-(19). k Estimates of η and ζ And reassign the value to θ in formula (20) k The algorithm iterates through η and ζ to update the data once, and after K iterations, it updates all elements in the θ vector. This process is repeated M times to complete the entire algorithm.

[0067] In particular, the estimation process involves a high number of iterations, making its runtime almost the entire system's total runtime. Therefore, optimizing the speed of even a single iteration can significantly reduce the system's total runtime. For example... Figure 11 As shown, the module design mainly includes data caching and updating of auxiliary variables η and ζ in S6, as well as estimation calculation of θ. In particular, the data update (formulas (18)-(20)) adopts a low-latency design, that is, reducing pipeline registers and reducing the latency of the entire update process to less than a single cycle. The calculation process is mainly occupied by the estimation calculation of θ. The calculation speed of the entire calculation process is excluding the basic calculation processes such as complex number multiplication and addition. However, the division and square root operations involved in formulas (15) and (16) are time-consuming. Speed ​​optimization is performed for this process.

[0068] Specifically, the single-precision floating-point number is expressed as f = s·2. E+127·(1+F), where s is the sign bit, E+127 is the 8-bit exponent plus the offset of 127, and F is the 23 decimal places. In this invention, all square roots are assumed to be positive, so the sign bit is always 0. The square root of a single-precision floating-point number is:

[0069]

[0070] Based on the parity of E, it can be transformed into:

[0071]

[0072] Since division by 2 in binary can be converted to shifting to the right and discarding the least significant bit, the above formula can be simplified to:

[0073]

[0074] like Figure 12 As shown, after obtaining the data, its exponent and mantissa are taken separately. The exponent E is determined to be either odd or even, and the exponent value is obtained through simple calculation. Simultaneously, the mantissa is used as a table address, and the mantissa portion of the square root data is obtained by looking up the table based on the parity of the exponent. Finally, the data is reassembled to obtain the square root data. Specifically, without affecting data precision, the lower 4 bits of the 23-bit mantissa are omitted, and only the higher 19 bits are used for the square root calculation, saving some storage resources.

[0075] Specifically, division can be transformed into multiplying the dividend by the reciprocal of the divisor. To ensure that the divisor f′≠0, a very small quantity Δ is added to allow the division to proceed smoothly; let f = s·2. E+127 ·(1+F), where the actual exponent of the floating-point number is e1=E+127, so taking the exponent of the reciprocal is e2=-E+127=254-e1. Since 1+F is a decimal between 1 and 2, the following relationship exists:

[0076]

[0077] The result is a number less than 1, but in the floating-point representation, the mantissa must be between 1 and 2. Since the highest bit of the mantissa must be 1, the mantissa only needs to be shifted left by one bit, while dividing by 2 keeps the value unchanged. This will give you the correct last digit, as shown in the following formula:

[0078]

[0079] This implementation method compares the computing speed of traditional computing methods and this design on the same platform:

[0080] Table 1 Comparison of Computation Speed

[0081]

[0082] The experimental results above demonstrate that the method provided in this embodiment significantly outperforms other methods in terms of processing time. This method overcomes the shortcomings of existing technologies, such as high algorithm complexity, difficulty in implementation on signal processing platforms, or excessively long processing times.

[0083] Figure 13 (a) shows the echo map of the first two point targets before the system processed them; Figure 13 (b) shows the echo patterns of the two point targets after system processing. It can be seen that before system processing, there was significant main lobe overlap between the echoes of the two MIMO point targets. After system processing, the main lobes almost completely overlapped. These results demonstrate that the resolution of the MIMO echo signal is significantly improved after processing by the system designed in this invention. Figure 13 In the figure, the horizontal axis Angle represents the angle, and the vertical axis Normalized amplitude represents the normalized amplitude.

[0084] Those skilled in the art will recognize that the embodiments described herein are intended to help the reader understand the principles of the invention, and should be understood that the scope of protection of the invention is not limited to such specific statements and embodiments. Various modifications and variations can be made to the invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the scope of the claims of the invention.

Claims

1. A real-time super-resolution method for millimeter-wave TDM-MIMO radar based on FPGA, characterized in that, include: S1. Collect sparse scene target samples and obtain radar data; S2. Use the high-speed interface to send radar data to the FPGA board; S3, the FPGA board parses and caches radar data, preprocesses and sends valid radar data; S4. Using hardware optimization design to process radar data, recursively estimate intermediate variables; the intermediate variables in step S4 are as follows: （1）； （2）； （3）； in, , , There are three intermediate variables. The m-th transmitting antenna of the radar Data from one receiving antenna, m=1,…,M; Manipulation matrix determined for the array The m-th row vector, Manipulation matrix Stored in the FPGA's memory cells; For a special Toplitz matrix, The matrix data is represented by a circular queue of RAM, allowing a single column element to represent the entire Toplitz matrix. calculate At that time, it includes a first control unit and two RAMs, the first control unit being denoted as control, the two RAMs are respectively denoted as RAM1 and RAM2; The initial value in RAM1 is 0, and it is read during the first operation. Values ​​and calculations in RAM1 The values ​​are added together to complete the recursive operation, and the result is stored in [the specified location]. In RAM2; at the end of the entire calculation process, by control RAM1 and The data read / write process between RAM2 will Data written to RAM2 Seamless data transfer is completed in RAM1; calculate At that time, including the second control unit and two registers reg, the second control unit is denoted as control, the two registers reg are respectively denoted as reg1 and reg 2; The initial value in reg1 is 0, and it is read during the first operation. Values ​​and calculations in reg1 The values ​​are added together to complete the recursive operation, and the result is stored in [the specified location]. In reg 2; at the end of the entire calculation process, by control reg1 and The data read / write process between reg 2 will Data writing in reg 2 In reg1, seamless data transfer is completed; S5. Iteratively update auxiliary variables based on intermediate variables and quickly cache data variables; S6. Implement iterative updates of fast angle estimates by using loop minimization.

2. The real-time super-resolution method for millimeter-wave TDM-MIMO radar based on FPGA according to claim 1, characterized in that, The high-speed interface mentioned in step S2 is specifically the CSI2 interface.

3. The real-time super-resolution method for millimeter-wave TDM-MIMO radar based on FPGA according to claim 2, characterized in that, Step S3 specifically involves: the radar data is transmitted into the MIPI CSI2 Rx module of the FPGA board under the control of the finite state machine module, and the sent radar data packets are parsed into a data stream. Then, an asynchronous FIFO is used to perform cross-clock domain data buffering. Finally, integer to single-precision floating-point conversion is performed in the data conversion module.

4. The real-time super-resolution method for millimeter-wave TDM-MIMO radar based on FPGA according to claim 3, characterized in that, The matrix data is represented by a circular queue of RAM, allowing a single column element to represent the entire Toplitz matrix. Specifically, Q-degree of parallelism is used for computation. The matrix data is represented by a circular queue consisting of S FPGA internal BRAMs, allowing a single column element to represent the entire Toplitz matrix; each BRAM stores a certain number of bits of data. Divide the number of data bits in the matrix by Q; Each BRAM outputs Q data points according to the clock sequence, then executes the selection S times via an S-to-1 data selector to complete one column of data output; data is transferred through the BRAM read / write controller to form... Output the subsequent columns of the matrix; Q*S= The number of data entries in a column of a matrix.

5. The real-time super-resolution method for millimeter-wave TDM-MIMO radar based on FPGA according to claim 3, characterized in that, The auxiliary variable update expression in step S5 is: （4）； （5）； , As auxiliary variables, the auxiliary variable update structure includes: Operator vector dot product module Operator vector dot product module Operator vector dot product module, , , .

6. The real-time super-resolution method for millimeter-wave TDM-MIMO radar based on FPGA according to claim 5, characterized in that, Operator vector dot product module Operator vector dot product module The three operator vector dot product modules have the same structure. The calculation process is as follows: the input data is passed through complex multiplication with Q parallelism in sequence, then the Q numbers are added together by a low-latency adder, and finally passed through the data stream S times by an adder to obtain the sum of Q*S complex multiplication data, which is the final value of the vector dot product. The input data for the operator vector dot product module is: and , The input data for the operator vector dot product module is: and , The input data for the operator vector dot product module is: and ; where * indicates multiplication and the superscript H indicates transpose.

7. The real-time super-resolution method for millimeter-wave TDM-MIMO radar based on FPGA according to claim 6, characterized in that, Operator vector dot product module and The vector calculated by the operator vector dot product module is converted into a Q-parallel output form by the serial-to-parallel conversion module.

8. The real-time super-resolution method for millimeter-wave TDM-MIMO radar based on FPGA according to claim 7, characterized in that, The calculation formula for step S6 is: for k=1,…,K; n=(m-1)*16+1 (11) （12）； （13）； （14）； （15）； （16）； （17）； （18）； （19）； （20）； Where K represents the number of iterations, yes The kth element, yes The kth element, and They are The k-th diagonal element and the k-th column element of the matrix; three variables are obtained by formulas (17)-(19). The estimated value , , ; The data update process in the formula adopts a low-latency design; For the square root operation involved in the formula, the single-precision floating-point expression is: , where s is the sign bit, E is the exponent, and M is the 23 decimal places; for the square root data, the exponent value is calculated based on the parity of the exponent; at the same time, the mantissa part is obtained by looking up the table based on the parity of the exponent using the mantissa as the table address; finally, the exponent value and the mantissa part are reassembled to obtain the square root data. For division operations involved in the formula, the division operation is transformed into an operation structure of multiplying the dividend by the reciprocal of the divisor.

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