Photomask and detection method thereof, defect pattern and formation method, device and equipment thereof

Abstract

An embodiment of the present application provides a mask and a method for detecting the same, a defect pattern and a method, device and equipment for forming the same, the method comprising: determining, on a first inspection area of ​​the mask to be inspected, a critical dimension of a first defect existing in a pattern in the first inspection area; obtaining, based on the pattern in the first inspection area and the type of the first defect, an allowable critical dimension range of a target defect in a sample mask with the same pattern and the same defect type, wherein a critical dimension of a target pattern formed by transferring the pattern with the target defect in the sample mask to a wafer is within a critical dimension range of a reference pattern, and the reference pattern is a pattern formed by transferring the pattern of the reference inspection area that is identical to the pattern in the first inspection area but does not contain defects to the wafer; when the critical dimension of the first defect is not within the allowable critical dimension range of the target defect, determining that the mask to be inspected is a defective product.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and is related to, but not limited to, a photomask and a detection method thereof, a defect pattern and a method, device and apparatus for forming the defect pattern. Background Art

[0002] The exposure process in the photolithography department involves transferring a pre-designed mask pattern onto the wafer according to a specific ratio. Therefore, the quality of the pattern on the mask is closely related to the quality of the transfer to the wafer. During actual production, particles can settle on the mask due to factors such as the production environment and mask loading and unloading operations. Furthermore, over time, the mask's surface chemically reacts with the environment, producing scattered haze. When the size of the particles or haze on the mask reaches a certain level, it can affect the quality of the transfer of the designed pattern from the mask to the wafer, resulting in pattern defects.

[0003] When pattern defects on a wafer are significant, they can cause the Statistical Process Control (SPC) chart for the pattern size to exceed control limits. At this point, if the wafer is still in the lithography process, it will be sent for photoresist rework of the pattern layer. If the wafer has already left the lithography department, the defects on the wafer cannot be corrected through photoresist rework, ultimately resulting in the wafer being scrapped and affecting product yield. Both of these situations lead to increased production costs and reduced production efficiency. Summary of the Invention

[0004] In view of this, embodiments of the present application provide a photomask and a method for detecting the same, a defect pattern and a method, device, and apparatus for forming the same.

[0005] In a first aspect, an embodiment of the present application provides a method for inspecting a mask, the method comprising: determining, on a first inspection area of ​​the mask to be inspected, a critical dimension of a first defect existing in a pattern in the first inspection area; obtaining, based on the pattern of the first inspection area and the type of the first defect, an allowable critical dimension range of a target defect in a sample mask with the same pattern and the same defect type, wherein a critical dimension of a target pattern formed by transferring the pattern with the target defect in the sample mask to a wafer is within a critical dimension range of a reference pattern, and the reference pattern is a pattern formed by transferring the pattern of a reference inspection area that is identical to the pattern of the first inspection area but does not contain defects to the wafer; if the critical dimension of the first defect is not within the allowable critical dimension range of the target defect, determining that the mask to be inspected is a defective product.

[0006] In some embodiments, the method further comprises: determining a location of the first defect;

[0007] The method of obtaining the allowable critical size range of the target defect with the same pattern and the same defect type in the sample mask based on the pattern of the first detection area and the type of the first defect includes: obtaining the allowable critical size range of the target defect with the same pattern, the same defect type and the same defect position based on the pattern of the first detection area, the type of the first defect and the position of the first defect.

[0008] In some embodiments, the method further includes: determining a second inspection area on the sample mask having the same pattern as the first inspection area; determining a second defect on the second inspection area having the same type and position as the first defect; determining a critical size of the second defect and a critical size of a defect pattern formed by transferring the pattern of the second inspection area to the wafer; and determining the second defect corresponding to the defect pattern as the target defect when the critical size of the defect pattern is within the critical size range of the reference pattern.

[0009] In some embodiments, the sample mask includes N patterns, and each region where the pattern is located is correspondingly provided with M second detection areas and P reference detection areas, wherein N, M, and P are all integers greater than or equal to 1.

[0010] In some embodiments, the N patterns include patterns of at least two layers of graphics in the wafer.

[0011] In some embodiments, determining a critical size of a defect pattern formed by transferring the pattern of the second detection area to the wafer includes: for each pattern in the sample mask, determining a target reference detection area among the P reference detection areas based on the positions of the P reference detection areas in the area where each pattern is located; using the target reference detection area, determining optimal exposure parameters; the optimal exposure parameters are exposure parameters for transferring the pattern of each second detection area to the wafer to form a defect pattern; for each pattern in the sample mask, determining a critical size of the defect pattern.

[0012] In some embodiments, for each pattern in the sample mask, based on the positions of the P reference detection areas in the area where each pattern is located, a target reference detection area is determined in the P reference detection areas, including: obtaining position information of each reference detection area in the P reference detection areas; based on the position information of each reference detection area, determining, among the P reference detection areas, the reference detection areas located at the edge and center of the area where each pattern is located as the target reference detection area.

[0013] In some embodiments, after determining the optimal exposure parameters, it also includes: determining the critical dimension consistency of the target reference pattern, where the target reference pattern is a pattern formed by transferring the pattern of each target reference detection area to the wafer using the optimal exposure parameters; if the critical dimension consistency does not meet the preset conditions, adjusting the optimal exposure parameters.

[0014] In some embodiments, each of the second detection areas includes a light-transmitting area and a non-light-transmitting area adjacent to the light-transmitting area, and the second defect is located at the following positions of the second detection area: inside the light-transmitting area and not in contact with the edge of the light-transmitting area; inside the light-transmitting area and in contact with one side edge of the light-transmitting area; inside the non-light-transmitting area and in contact with one side edge of the non-light-transmitting area; inside the non-light-transmitting area and not in contact with the edge of the non-light-transmitting area.

[0015] In some embodiments, the method further includes: scanning a first inspection area of ​​the mask to be inspected by a photomask defect inspection device; when the photomask defect inspection device determines that there is a defect on the first inspection area of ​​the mask to be inspected, determining the defect existing on the mask to be inspected as the first defect.

[0016] In some embodiments, the critical dimension of the defect pattern includes line width and spacing of graphics in the defect pattern; the critical dimension of the reference pattern includes line width and spacing of graphics in the reference pattern.

[0017] In the second aspect, an embodiment of the present application also provides a mask, comprising: N patterns, each area where the pattern is located is correspondingly provided with M second detection areas and P reference detection areas, wherein the M second detection areas have at least one second defect, and the type of the second defect includes a particle defect or a foggy defect, the pattern of the reference detection area is the same as the pattern of the second detection area but does not contain defects, and N, M, and P are all integers greater than or equal to 1.

[0018] In some embodiments, the N patterns include patterns of at least two layers of graphics in the wafer.

[0019] In some embodiments, there are second defects of different sizes and different positions in the M second detection areas, and there is at most one second defect in each second detection area; each second detection area includes a light-transmitting area and a non-light-transmitting area adjacent to the light-transmitting area, and the second defect is located at the following positions of the second detection area: inside the light-transmitting area and not in contact with the edge of the light-transmitting area; inside the light-transmitting area and in contact with one side edge of the light-transmitting area; inside the non-light-transmitting area and in contact with one side edge of the non-light-transmitting area; inside the non-light-transmitting area and not in contact with the edge of the non-light-transmitting area.

[0020] In a third aspect, an embodiment of the present application further provides a defect pattern, which is a pattern formed on a wafer after exposure using the above-mentioned mask.

[0021] In a fourth aspect, an embodiment of the present application also provides a method for forming a defect pattern, comprising: providing a substrate, the substrate comprising at least an etching layer and a photoresist layer located on the etching layer; exposing and developing the photoresist layer using the above-mentioned mask to form a photoresist layer having a first pattern; etching the etching layer using the photoresist layer having the first pattern as a mask to form the defect pattern in the etching layer.

[0022] In the fifth aspect, an embodiment of the present application also provides a mask detection device, including: a first determination module, used to determine the critical size of a first defect existing in the pattern of the first detection area on the mask to be detected; an acquisition module, used to obtain the allowable critical size range of the target defect in the same pattern and the same defect type in the sample mask based on the pattern of the first detection area and the type of the first defect, wherein the critical size of the target pattern formed by transferring the pattern with the target defect in the sample mask to the wafer is within the critical size range of the reference pattern, and the reference pattern is a pattern formed by transferring the pattern of the reference detection area that is the same as the pattern of the first detection area but does not contain defects to the wafer; a second determination module, used to determine that the mask to be detected is a defective product when the critical size of the first defect is not within the allowable critical size range of the target defect.

[0023] In a sixth aspect, an embodiment of the present application further provides a computer device comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and when the processor executes the program, some or all of the steps in the above method are implemented.

[0024] In a seventh aspect, an embodiment of the present application provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, some or all of the steps in the above method are implemented.

[0025] In the embodiment of the present application, first, the critical size of the first defect existing in the pattern of the first detection area of ​​the mask to be inspected is determined; then, a pattern identical to the pattern of the first detection area in the sample mask is determined, and the pattern has a defect of the same type as the first defect, and the critical size range allowed for the target defect in the pattern is obtained; finally, by comparing the critical size of the first defect with the critical size range allowed for the target defect, it is possible to determine whether the mask to be inspected is a defective product. In this way, the problem in the related art of needing to produce several test wafers with defective masks, and then judging whether the defects on the mask affect online production by checking the quality of the patterns on the test wafers, and finally determining whether the defective mask is a defective product is solved. It can be seen that the method provided by the embodiment of the present application not only reduces production costs, but also improves production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic flow chart of a method for detecting a photomask provided in an embodiment of the present application;

[0027] Figure 2 A flowchart of a method for determining a target defect provided in an embodiment of the present application;

[0028] Figure 3 A schematic flow chart of a method for determining a critical dimension of a defect pattern provided in an embodiment of the present application;

[0029] Figure 4A A schematic diagram of a mask pattern provided in an embodiment of the present application;

[0030] Figure 4B A schematic diagram of different locations of defects of the same size in a sample mask provided in an embodiment of the present application;

[0031] Figure 4C A schematic diagram of the positions of six measurement points in a reference area provided in an embodiment of the present application;

[0032] Figure 4D A schematic diagram of line widths and grooves near defects in a pattern formed on a wafer provided in an embodiment of the present application;

[0033] Figure 5A A schematic diagram of the correspondence between defects of different sizes and patterns formed on a wafer provided in an embodiment of the present application;

[0034] Figure 5B A scatter plot between defects of different sizes and critical dimensions of patterns formed on a wafer provided in an embodiment of the present application;

[0035] Figure 6 A schematic diagram of the structure of a photomask detection device provided in an embodiment of the present application;

[0036] Figure 7 A hardware entity diagram of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] The exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0038] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0039] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0040] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. And when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part is present in the present application.

[0041] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0042] In related technologies, production workshops use die-to-die (D2D) photomask defect inspection machines to regularly inspect photomasks for defects to prevent them from developing. However, this inspection method has certain limitations. For example, if a D2D machine detects only one defective mask, several test wafers must be produced daily using the defective mask. The quality of the patterns on these test wafers is then checked using a metrology machine to determine whether the defect on the defective mask will affect production. This method not only wastes manpower but also delays production progress.

[0043] Based on this, embodiments of the present application provide a method for inspecting a photomask, which can be executed by a processor of a computer device. The computer device may refer to a server, laptop, tablet computer, desktop computer, smart TV, set-top box, mobile device (e.g., mobile phone, portable video player, personal digital assistant, dedicated messaging device, portable gaming device), or other device with data processing capabilities. Figure 1 A schematic diagram of the implementation process of a mask detection method provided in an embodiment of the present application is shown as follows: Figure 1 As shown, the method includes the following steps S101 to S103:

[0044] Step S101: determining a critical dimension of a first defect in a pattern in a first inspection area of ​​a mask to be inspected;

[0045] Here, the photomask, also known as a photomask or mask, is made of materials including quartz glass, metal chromium, and photoresist. Quartz glass serves as a substrate, upon which a layer of metal chromium and photoresist is plated, creating a photosensitive material. The designed circuit pattern is exposed to the photoresist using an electronic laser. The exposed areas are developed, forming a circuit pattern on the metal chromium, creating a photomask similar to an exposed film negative. This is then used to project and position the integrated circuit. The projected circuit is then photoetched by the integrated circuit's lithography machine, forming the pattern on the wafer. The designed circuit pattern is defined by a layout, so the photomask to be inspected includes the pattern defined by the layout, which includes the designed circuit pattern.

[0046] The mask to be inspected can be divided into a bright field mask (Clear Mask) and a dark field mask (Dark Mask) according to whether the circuit pattern defined in the layout is light-transmissive, wherein the bright field mask is a mask that is not light-transmissive to the circuit pattern defined in the layout, and the dark field mask is a mask that is light-transmissive to the circuit pattern defined in the layout. The first detection area includes a light-transmissive area and a non-light-transmissive area adjacent to the light-transmissive area, wherein the light-transmissive area refers to the area in the mask to be inspected where light can pass through or pass through in large quantities, and the non-light-transmissive area refers to the area in the mask to be inspected where light cannot pass through or pass through in small quantities. For the bright field mask, the light-transmissive area is the area outside the circuit pattern defined in the layout in the mask, and the non-light-transmissive area is the area where the circuit pattern defined in the layout in the mask is located; for the dark field mask, the light-transmissive area is the area where the circuit pattern defined in the layout in the mask is located, and the non-light-transmissive area is the area outside the circuit pattern defined in the layout in the mask.

[0047] The first defect types include particle defects and / or haze defects. In the actual production process, due to the production environment, loading and unloading mask operations and other factors, some particles (Particles) or fibers will fall on the mask; in addition, as the mask is used for a long time, scattered haze points (Haze) will also appear on the mask surface. When the size of these particles (Particles) or fibers, or haze points (Haze) on the mask reaches a certain level, it will affect the quality of the designed graphics on the wafer and cause graphic defects, that is, corresponding to particle defects and haze defects respectively. Because particle defects and haze defects will affect the irradiation of light during exposure, they will affect the graphics transferred to the wafer through the mask.

[0048] The critical dimension of a first defect refers to the dimension of the first defect that affects the pattern transferred to the wafer and is related to the shape of the first defect. For example, if the first defect is circular, the critical dimension is the diameter of the circle; if the first defect is square, the critical dimension is the side length of the square, and so on.

[0049] In some embodiments, a defect detection device (eg, D2D) may be used to measure a critical dimension of the first defect on the first inspection area, thereby determining the critical dimension of the first defect.

[0050] In some embodiments, the method further includes the following steps S201 and S202:

[0051] Step S201: Scanning a first inspection area of ​​a mask to be inspected by a photomask defect inspection device;

[0052] Here, the photomask defect inspection device is a device used to test defects in the mask to be inspected. If other devices have the same function, other devices can also be used for inspection.

[0053] Step S202: when the photomask defect inspection device determines that a defect exists in the first inspection area of ​​the photomask to be inspected, the defect existing in the photomask to be inspected is determined as a first defect.

[0054] That is, the defect detected on the mask to be inspected is the first defect.

[0055] An embodiment of the present application provides a step for defect detection during the actual application of a mask to be detected, wherein the detected defect is the above-mentioned first defect, and a method is provided for determining the first defect.

[0056] Step S102: Based on the pattern in the first inspection area and the type of the first defect, obtaining an allowable critical dimension range for a target defect with the same pattern and the same defect type in a sample reticle, wherein a critical dimension of a target pattern formed by transferring the pattern with the target defect in the sample reticle to the wafer is within a critical dimension range of a reference pattern, where the reference pattern is a pattern formed by transferring the pattern of the reference inspection area that is identical to the pattern in the first inspection area but does not contain the defect to the wafer;

[0057] Here, a sample mask is a mask used to determine the critical size range of defects with the same pattern and defect type. In some embodiments, the sample mask can be a historical mask, i.e., a mask from a previous production process; or it can be a mask specifically used to determine the critical size range of defects with the same pattern and defect type, i.e., a batch of masks customized for this purpose. The number of sample masks can be one, two, or more, each sample mask can include at least one pattern, and each pattern can include at least one defect type.

[0058] The reference detection area is a light-transmitting area with the same pattern as the first detection area but does not contain defects. The pattern formed by transferring the pattern of the reference detection area to the wafer through exposure and development is the reference pattern, that is, the pattern on the wafer. Since the reference detection area is used as a reference for the first detection area, and if there are defects in the first detection area, it will affect the line width and spacing of the graphics formed on the wafer (that is, the distance between the graphics), therefore, the critical dimensions of the reference pattern may include the line width and spacing of the graphics in the reference pattern. The critical dimension range of the reference pattern refers to the range of qualified or internally controlled critical dimensions in the actual production process. In some embodiments, the critical dimension range of the reference pattern can be a range defined when designing the product; it can also be a range of internal control of critical dimensions defined during the production process based on the importance of the critical dimensions and the risk of defects (such as the control limits defined in SPC), which is not limited in the embodiments of the present application.

[0059] The target defect is the defect to be identified in the sample reticle. Methods for identifying the target defect may include: transferring a pattern in the sample reticle that is identical to the pattern in the first inspection area and has the same defect type to the wafer to form a target pattern; when the critical dimension of the target pattern is within the critical dimension range of the reference pattern, the defect corresponding to the pattern in the sample reticle is the target defect. The allowable critical dimension range for the target defect refers to the critical dimension range within which the defect identified as the target defect lies.

[0060] In some embodiments, step S102 includes: first, determining a pattern in the sample reticle that is identical to the pattern in the first inspection area and contains a defect of the same type as the first defect; then, determining a critical dimension range for the defect in the pattern. In some embodiments, a correspondence between the critical dimensions of different defects in different patterns and the critical dimensions of the defect pattern transferred from the pattern to the wafer can be pre-determined; after determining the critical dimension range of the reference pattern, the critical dimension range of different defects in different patterns is determined based on the critical dimension range of the reference pattern.

[0061] Step S103: If the critical dimension of the first defect is not within the critical dimension range allowed by the target defect, determine that the mask to be inspected is a defective product.

[0062] Here, the implementation of step S103 may include comparing the critical dimension of the first defect with the allowable critical dimension range of the target defect. If the critical dimension of the first defect is not within the allowable critical dimension range of the target defect, it indicates that the critical dimension of the first defect is too large. After transfer to the wafer, the pattern formed on the wafer will exceed the critical dimension range of the reference pattern. Therefore, the photomask to be inspected is determined to be defective. If the critical dimension of the first defect is within the allowable critical dimension range of the target defect, it indicates that the critical dimension of the first defect is not large. After transfer to the wafer, the pattern formed on the wafer will not exceed the critical dimension range of the reference pattern. Therefore, the photomask to be inspected is determined to be good.

[0063] In the embodiment of the present application, first, the critical size of the first defect existing in the pattern of the first detection area of ​​the mask to be inspected is determined; then, a pattern identical to the pattern of the first detection area in the sample mask is determined, and the pattern has a defect of the same type as the first defect, and the critical size range allowed for the target defect in the pattern is obtained; finally, by comparing the critical size of the first defect with the critical size range allowed for the target defect, it is possible to determine whether the mask to be inspected is a defective product. In this way, the problem in the related art of needing to produce several test wafers with defective masks, and then judging whether the defects on the mask affect online production by checking the quality of the patterns on the test wafers, and finally determining whether the defective mask is a defective product is solved. It can be seen that the method provided by the embodiment of the present application not only reduces production costs, but also improves production efficiency.

[0064] In some embodiments, the method further includes determining a location of the first defect.

[0065] Correspondingly, the implementation of step S102 of "obtaining the allowable critical dimension range of the target defect with the same pattern and the same defect type in the sample mask based on the pattern of the first inspection area and the type of the first defect" may include:

[0066] Based on the pattern of the first inspection area, the type of the first defect, and the position of the first defect, an allowable critical dimension range of a target defect with the same pattern, the same defect type, and the same defect position is obtained.

[0067] Here, the first detection area includes a light-transmitting area and a non-light-transmitting area adjacent to the light-transmitting area, and the position of the first defect may include one of the following: inside the light-transmitting area and not in contact with the edge of the light-transmitting area; inside the light-transmitting area and in contact with one side edge of the light-transmitting area; inside the non-light-transmitting area and in contact with one side edge of the non-light-transmitting area; inside the non-light-transmitting area and not in contact with the edge of the non-light-transmitting area.

[0068] Because the location of the first defect varies, the shape of the pattern transferred from the inspected reticle to the wafer is affected differently. Therefore, in addition to step S102, the location of the first defect can be used to determine the allowable critical dimension range of the target defect. Specifically, a pattern identical to the pattern in the first inspection area is identified in the sample reticle, containing a defect of the same type and location as the first defect. Based on this pattern, the allowable critical dimension range of the target defect is determined. This allows for a more accurate determination of the allowable critical dimension range of the target defect, thereby improving the accuracy of determining whether the inspected reticle is a good product.

[0069] In some embodiments, as Figure 2 As shown, the method further includes the following steps S201 to S204:

[0070] Step S201: determining a second detection area having the same pattern as the first detection area on the sample mask;

[0071] Here, the second detection area is an area in the sample mask with the same pattern as the first detection area. For example, when the sample mask is a dark field mask, if the first detection area includes the area where the gate is located and the non-light-transmitting area adjacent to the gate, then the second detection area also includes the area where the gate is located and the non-light-transmitting area adjacent to the gate.

[0072] Step S202: determining a second defect of the same type and location as the first defect in the second inspection area;

[0073] Here, the second defect is of the same type and position as the first defect. For example, the first defect is a particle, which is located inside the light-transmitting area in the first detection area and does not contact the edge of the light-transmitting area; then the second defect is also a particle, which is located inside the light-transmitting area in the second detection area and does not contact the edge of the light-transmitting area.

[0074] Since the first defect can be located inside the light-transmitting area of ​​the first detection zone and not in contact with the edge of the light-transmitting area; or inside the light-transmitting area of ​​the first detection zone and in contact with one side edge of the light-transmitting area; or inside the non-light-transmitting area of ​​the first detection zone and in contact with one side edge of the non-light-transmitting area; therefore, when each second detection zone of the sample mask includes a light-transmitting area and a non-light-transmitting area adjacent to the light-transmitting area, the second defect can be located at the following positions in the second detection zone:

[0075] Inside the light-transmitting area and not in contact with the edge of the light-transmitting area;

[0076] Inside the light-transmitting area and in contact with one edge of the light-transmitting area;

[0077] Inside the non-light-transmitting area and in contact with one edge of the non-light-transmitting area;

[0078] The interior of the non-light-transmitting area does not touch the edge of the non-light-transmitting area.

[0079] The position of the second defect is located in a different area of ​​the second inspection zone, so the critical dimension range allowed by the target defect is obtained more accurately.

[0080] In an embodiment of the present application, by setting a second defect at a different position in each pattern of the sample mask, the influence of the second defects at different positions on the pattern transferred to the wafer is taken into account, so that the critical size range allowed by the determined target defect is more accurate, thereby improving the accuracy of judging whether the mask to be inspected is a defective product.

[0081] Step S203: determining a critical dimension of the second defect and a critical dimension of a defect pattern formed by transferring the pattern of the second inspection area onto the wafer;

[0082] Here, the critical dimension of the second defect can be measured by a defect detection device (e.g., D2D). The defect pattern is a pattern formed by transferring the pattern of the second detection area to the wafer. The critical dimension of the defect pattern can be measured by a device for measuring dimensions, such as a scanning electron microscope (SEM). In some embodiments, since the second defect on the second detection area in the sample mask affects the line width of the graphics in the defect pattern and the spacing between the graphics, the critical dimension of the defect pattern may include the line width and spacing of the graphics in the defect pattern.

[0083] In some embodiments, the sample mask may include N patterns, and each pattern area is correspondingly provided with M second detection areas and P reference detection areas, wherein N, M, and P are all integers greater than or equal to 1.

[0084] Here, the values ​​of M and P can be the same, that is, one second detection area corresponds to one reference detection area. In other words, one second detection area uses one reference detection area as a reference. The values ​​of M and P can also be different. For example, the number M of second detection areas can be greater than the number of reference detection areas, that is, multiple second detection areas use one reference detection area as a reference at the same time. In this way, setting the second detection area and the reference detection area on the same mask can not only reduce production costs, but also improve the efficiency of determining the critical size range allowed for the target defect. In some embodiments, the second detection area and the reference detection area can be set adjacent to each other. In this way, it is convenient to compare the difference in patterns formed after the pattern of the second detection area and the pattern of the reference detection area are transferred to the wafer respectively, which is more conducive to determining the target defect.

[0085] In some embodiments, the N patterns can include patterns representing at least two layers of graphics on the wafer, i.e., a sample reticle can contain at least two layers of graphics. In practice, multiple patterns representing representative, critical graphics can be placed on a single sample reticle. This not only saves costs but also makes the resulting data more comprehensive and universal.

[0086] Step S204 : when the critical dimension of the defect pattern is within the critical dimension range of the reference pattern, determining the second defect corresponding to the defect pattern as a target defect.

[0087] Here, since there are a large number of second defects of the same type and position as the first defect on the second inspection area, and only a portion of the pattern of the second inspection area with the second defects is transferred to the wafer to form a defect pattern whose critical dimension is within the critical dimension range of the reference pattern, the second defect corresponding to the defect pattern within the critical dimension range of the reference pattern is determined as the target defect.

[0088] In some embodiments, after obtaining the target defect, the allowable critical size range of the target defect can also be determined based on the critical size of the target defect. In the case where the number of second defects is large and the critical size interval is small, the range of the target defect's critical size can be the allowable critical size range of the target defect. For example, when the critical size of the target defect is 2 nanometers (nm), 4nm, 6nm, 8nm, or 10nm, the critical size of the defect pattern is within the critical size range of the reference pattern. When the critical size of the target defect is 12nm, 14nm, 16nm, or 18nm, the critical size of the defect pattern is not within the critical size range of the reference pattern. Therefore, the allowable critical size range of the target defect can be (0, 10nm).

[0089] When the number of second defects is small and the critical dimension interval is large, the critical dimension range allowed for the target defect can be determined based on the relationship between the critical dimension of the target defect and the critical dimension of the defect pattern. For example, when the critical dimension of the target defect is 2nm, 6nm, and 10nm, the critical dimension of the defect pattern is within the critical dimension range of the reference pattern; and when the critical dimension of the target defect is 14nm, 18nm, and 22nm, the critical dimension of the defect pattern is not within the critical dimension range of the reference pattern. And because there is a linear relationship between the critical dimension of the target defect and the critical dimension of the defect pattern, the critical value of the critical dimension of the target defect when the critical dimension of the defect pattern is within the critical dimension range of the reference pattern can be calculated based on the critical dimension range of the reference pattern and the linear relationship between the critical dimension of the target defect and the critical dimension of the defect pattern, for example, 12nm, and the critical dimension range allowed for the target defect is (0, 12nm). The embodiment of the present application does not limit the method for determining the critical dimension range allowed for the target defect.

[0090] In an embodiment of the present application, a second inspection area having the same pattern as the first inspection area is first determined on the sample mask; then, a second defect having the same type and position as the first defect is determined on the second inspection area; thereafter, a critical size of the second defect and a critical size of a defect pattern formed by transferring the pattern of the second inspection area to the wafer are determined; finally, when the critical size of the defect pattern is within the critical size range of the reference pattern, the second defect corresponding to the defect pattern is determined as a target defect, thereby achieving the determination of the target defect, which is used for the subsequent determination of the allowable critical size range of the target defect.

[0091] In some embodiments, as Figure 3 As shown, the implementation of "determining the critical dimension of the defect pattern formed by transferring the pattern in the second inspection area to the wafer" in step S203 may include the following steps S2031 to S2033:

[0092] Step S2031: for each pattern in the sample mask, based on the positions of the P reference detection areas in the area where each pattern is located, determining a target reference detection area among the P reference detection areas;

[0093] Here, the target reference detection area is the reference detection area used to determine optimal exposure parameters. Because, under the same exposure parameters, the deviations between the patterns formed on the wafer by transferring reference detection areas at different locations and the patterns in the reference detection area vary, during step S2031, a representative reference detection area can be selected as the target reference detection area based on the positions of the P reference detection areas within each pattern region, thereby reducing production costs.

[0094] In some embodiments, the implementation of step S2031 may include the following steps S211 and S212:

[0095] Step S211: obtaining position information of each reference detection area among the P reference detection areas;

[0096] Here, the position information may be coordinate information, such as (x, y). In implementation, a fixed point may be used as the coordinate origin, and the coordinates of the center point of each reference detection area relative to the coordinate origin may be used as the position information of each reference detection area.

[0097] Step S212: Based on the position information of each reference detection area, among the P reference detection areas, the reference detection areas located at the edge and the center of the area where each pattern is located are determined as target reference detection areas.

[0098] Here, due to the different locations of the reference detection areas at the edge and center, and the influence of the surrounding environment, the pattern formed on the wafer after transfer deviates significantly from the pattern in the reference detection areas, making it more representative than reference detection areas at other locations. Therefore, the reference detection areas at the edge and center of each pattern area are identified as target reference detection areas, which are exposed under the same exposure conditions and transferred to the wafer. At this point, if the patterns formed by all target reference detection areas transferred to the wafer are within the critical dimension range, the exposure conditions are suitable. This allows the optimal exposure conditions to be determined while saving costs.

[0099] Step S2032: Determine optimal exposure parameters using the target reference inspection area; the optimal exposure parameters are exposure parameters for transferring the pattern of each second inspection area to form a defect pattern on the wafer;

[0100] Here, the exposure parameters may include energy and focal length during exposure. Step S2032 may include: exposing the target reference detection area using multiple sets of exposure parameters, measuring the critical dimensions of the pattern formed on the wafer, selecting the exposure parameters when the critical dimensions of the pattern formed on the wafer corresponding to all target reference detection areas are within a range, obtaining an exposure parameter range, and selecting the center value of the exposure parameter range to obtain the optimal exposure parameters.

[0101] Step S2033: For each pattern in the sample mask, determine the critical dimension of the defect pattern.

[0102] Here, the implementation of step S2033 may include: exposing the pattern of each second inspection area using optimal exposure parameters, and then measuring the critical dimension of the defect pattern formed by the defect pattern transferred onto the wafer.

[0103] In the embodiment of the present application, a target reference inspection area is first determined among the P reference inspection areas; then, optimal exposure parameters are determined using the target reference inspection area; finally, the pattern in each second inspection area is exposed using the optimal exposure parameters to form a defect pattern on the wafer, thereby determining the critical dimension of the defect pattern. In this way, the optimal exposure parameters can be determined using a relatively small number of reference inspection areas, and the critical dimension of the defect pattern can be determined using the optimal exposure parameters. This facilitates the subsequent determination of the corresponding relationship between the critical dimension of the second defect and the critical dimension of the defect pattern, thereby deriving the allowable critical dimension range of the target defect.

[0104] In some embodiments, after step S2032 “determining optimal exposure parameters” and before step S2033 , the following steps S2034 and S2035 may be further included:

[0105] Step S2034: determining the critical dimension consistency of the target reference pattern, where the target reference pattern is a pattern formed by transferring the pattern of each target reference detection area onto the wafer using optimal exposure parameters;

[0106] Here, Critical Dimension Consistency is used to evaluate the deviation in the critical dimensions of the target reference pattern. If the deviation is too large, it indicates that the optimal exposure parameters used need to be adjusted. If the deviation is within an acceptable range, it indicates that the optimal exposure parameters are appropriate and no adjustment is required.

[0107] Step S2035: If the key dimension consistency does not meet the preset conditions, adjust the optimal exposure parameters.

[0108] Here, the preset conditions can be set according to process requirements. In some embodiments, the implementation of step S2035 may include: comparing the critical dimension consistency with the preset conditions, and adjusting the optimal exposure parameters if the critical dimension consistency is not within the preset condition range. During implementation, the optimal exposure parameters can be adjusted based on process experience, and the adjusted optimal exposure parameters are then used to transfer the pattern of each target reference detection area to the wafer to form a pattern. The critical dimension consistency of the pattern formed on the wafer is then determined until the preset conditions are met, thereby obtaining the final optimal exposure parameters.

[0109] In the embodiment of the present application, because a large number of patterns are formed on a single wafer, factors such as process instability and differences in the surrounding environment of each pattern may affect the critical dimension consistency of the patterns on the wafer, even when the optimal exposure parameters determined by the target reference detection area are used for production. Therefore, after determining the optimal exposure parameters in step S2032, the optimal exposure parameters are further adjusted based on the critical dimension consistency of the target reference pattern to obtain the final optimal exposure parameters, thereby improving the accuracy of the optimal exposure parameters.

[0110] The embodiment of the present application also provides a method for detecting a photomask, which designs the graphics of multiple layers in a semiconductor structure on the same photomask, and designs defects with a certain regularity at a certain position. Then, the process of applying photoresist, exposure, development and measurement is combined to obtain the presentation of defects on the wafer. Finally, the presentation pattern of defects on the wafer is found by analyzing the results. When the D2D machine scans the online mask and finds particles or haze, the presentation of the particles or haze on the mask on the wafer can be predicted based on the results of the solution, and then it can be determined whether it affects the target line width of the product. This solution can greatly save manpower and prevent the problem of online graphic damage. The implementation steps are as follows:

[0111] Part 1: Design the mask (i.e. the sample mask mentioned above):

[0112] Select some key layers (one layer corresponds to one of the above patterns) and design them on the same mask. Figure 4A The following diagram shows a schematic diagram of a mask pattern, where A through H represent patterns corresponding to different key layers. Each key layer pattern includes a reference area (including the aforementioned reference detection area) and a defect area (including the aforementioned second detection area). The reference area corresponds to the normal line width of the key pattern in that layer. The defect area differs from the reference area in that it contains a defect (i.e., the aforementioned second defect).

[0113] like Figure 4B As shown, there are defects of different sizes and positions in different blocks (Block 401) of the defect area, wherein defects of the same size include Figure 4B The three positions are shown in Figures A, B, and C. A represents the first position of defect 406, which is located inside the light-transmitting area 402 and does not contact the edge of the light-transmitting area 402; B represents the second position of defect 407, which is located inside the light-transmitting area 402 and contacts one side edge of the light-transmitting area 402; and C represents the third position of defect 408, which is located inside the light-impermeable area 403 and contacts one side edge of the light-impermeable area 402. In some embodiments, the defect may also be located inside the light-impermeable area 403 and not contact the edge of the light-impermeable area 403 (not shown in the figure).

[0114] Part 2: Trial Production and Critical Dimension (CD) Measurement:

[0115] Using a designed mask and non-production wafers, with the normal production conditions on the line as a reference, use the reference area to determine the exposure energy and focus in the photolithography process (i.e. the optimal exposure conditions mentioned above). During implementation:

[0116] First, a CD measurement method for normal patterns in the reference area is established. Six measurement points are selected in each reference area (i.e., the target reference detection area) to ensure data integrity and obtain the optimal exposure parameter value (i.e., the optimal exposure condition).

[0117] Figure 4C The positions of the six measurement points (i.e., target reference detection area) in the reference area (i.e., reference detection area) are shown, namely A, B, C, D, E, and F. It can be seen that the six measurement points are located at the upper left, lower left, upper right, lower right, and center of the reference area (i.e., the edge and center mentioned above);

[0118] Then, the defective area is exposed using the optimal exposure parameter value to form a pattern (i.e., the above-mentioned defect pattern) on the wafer;

[0119] Finally, combining the measurement method of the critical dimension measurement machine and the coordinate origin of the mask, a CD measurement method for the pattern formed on the wafer is established based on the location of the designed defect. The line width and groove (i.e., the above-mentioned interval) near the defect in the pattern formed on the wafer are measured respectively.

[0120] Figure 4D The figure shows the line width 402 and groove 403 near a defect in a pattern formed on a wafer. The two figures on the right are enlarged views of the pattern 409 in the figure on the left. It can be seen that when a defect exists on the mask, the line width and groove size will change compared to a normal pattern.

[0121] Part III: Result Analysis: Analyze the measurement results to derive the relationship between the critical line width, groove, and defect size, and find the defect size range (i.e., the critical size range allowed for the target defect) that meets the line width and groove requirements (i.e., the critical size range of the reference pattern).

[0122] Figure 5A The corresponding relationship between defects of different sizes and the patterns formed on the wafer is shown. Figure 5A As shown in the figure, when forming patterns on the first row of wafers, as the defect size increases, the line width of the pattern gradually becomes wider and the spacing gradually becomes smaller; when forming patterns on the second and third rows of wafers, bridges are formed between the patterns, connecting them together. It can be seen that when there are defects of different sizes on the mask, the line width and groove size will change differently. Among them, when the defect size is 64nm ( Figure 5A When the size is indicated by 501 in the mask, the defective portion in the mask forms a pattern on the wafer as shown in 502. At this time, the values ​​of the line width and the groove in the pattern shown in 502 are critical values ​​that meet the line width and groove requirements. Figure 5B The scatter plot of defects of different sizes and the critical dimensions of the patterns formed on the wafer is shown. When the line width and spacing are within the range of ±5% of the target value, the size range of the defect is obtained, which is Figure 5B The area enclosed in the box corresponds to the defect size range (0,64nm).

[0123] Part 4: Application: When a D2D machine detects a defect on a mask, the system combines test results to predict the impact of the defect on the production line, allowing for timely repairs. This solution significantly saves manpower and buys time for normal production, thereby creating benefits and minimizing losses.

[0124] An embodiment of the present application also provides a mask, which includes N patterns, and the area where each pattern is located is correspondingly provided with M second detection areas and P reference detection areas, wherein there is at least one second defect in the M second detection areas, and the type of the second defect includes a particle defect or a fog defect, and the pattern of the reference detection area is the same as the pattern of the second detection area but does not contain defects, and N, M, and P are all integers greater than or equal to 1.

[0125] In some embodiments, the N patterns include patterns of at least two layers of graphics in the wafer.

[0126] In some embodiments, second defects of different sizes and positions exist in the M second inspection zones, and at most one second defect exists in each second inspection zone;

[0127] Each second inspection area includes a light-transmitting area and a non-light-transmitting area adjacent to the light-transmitting area, and the second defect is located at the following position in the second inspection area:

[0128] Inside the light-transmitting area and not in contact with the edge of the light-transmitting area;

[0129] Inside the light-transmitting area and in contact with one edge of the light-transmitting area;

[0130] Inside the non-light-transmitting area and in contact with one edge of the non-light-transmitting area;

[0131] The interior of the non-light-transmitting area does not touch the edge of the non-light-transmitting area.

[0132] An embodiment of the present application further provides a defect pattern, which is a pattern formed on a wafer after exposure using the above-mentioned mask.

[0133] The embodiment of the present application further provides a method for forming a defect pattern, the method comprising the following steps S301 to S303:

[0134] Step S301: providing a substrate, wherein the substrate at least comprises an etching layer and a photoresist layer located on the etching layer;

[0135] Here, the etched layer refers to the layer used to form patterns on a wafer through a photolithography process using a photomask. A photoresist layer is formed by coating photoresist. Photoresists can be divided into positive and negative photoresists based on their polarity. The difference between them is that the exposed areas of negative photoresists harden and remain after exposure and development, while the unexposed areas are dissolved by the developer. After exposure, the adhesive polymers in the exposed areas of positive photoresists break and soften due to photolysis, and are eventually dissolved by the developer, while the unexposed areas remain. The embodiments of this application do not limit the polarity of the photoresist.

[0136] Step S302: exposing and developing the photoresist layer using the above-mentioned photomask to form a photoresist layer having a first pattern;

[0137] Here, the photoresist layer is exposed and developed, and a portion of the photoresist layer is dissolved away to form a photoresist layer having a first pattern.

[0138] Step S303 : etching the etched layer using the photoresist layer having the first pattern as a mask to form a defect pattern in the etched layer.

[0139] Here, etching may include dry etching and wet etching, and the embodiment of the present application does not limit the etching process.

[0140] Based on the foregoing embodiments, an embodiment of the present application provides a mask detection device, which includes the various units included and the various modules included in each unit, and can be implemented by a processor in a computer device; of course, it can also be implemented by a specific logic circuit; in the implementation process, the processor can be a central processing unit (CPU), a microprocessor (MPU), a digital signal processor (DSP) or a field programmable gate array (FPGA), etc.

[0141] Figure 6 A schematic diagram of the structure of a photomask detection device provided in an embodiment of the present application is shown in FIG. Figure 6 As shown, the mask detection device 600 includes: a first determination module 610, an acquisition module 620 and a second determination module 630, wherein:

[0142] A first determining module 610 is configured to determine a critical dimension of a first defect present in a pattern in a first inspection area of ​​a mask to be inspected;

[0143] an acquisition module 620 for acquiring, based on the pattern in the first inspection zone and the type of the first defect, an allowable critical dimension range of a target defect with the same pattern and the same defect type in a sample reticle, wherein a critical dimension of a target pattern formed by transferring the pattern having the target defect in the sample reticle to the wafer is within a critical dimension range of a reference pattern, where the reference pattern is a pattern formed by transferring the pattern in the reference inspection zone that is identical to the pattern in the first inspection zone but does not contain the defect to the wafer;

[0144] The second determining module 630 is configured to determine that the mask to be inspected is a defective product if the critical dimension of the first defect is not within the critical dimension range allowed by the target defect.

[0145] In some embodiments, the device also includes: a third determination module for determining the position of the first defect; correspondingly, an acquisition module 620 is also used to obtain the critical size range allowed for the target defect in the same pattern, the same defect type and the same defect position based on the pattern of the first detection area, the type of the first defect and the position of the first defect.

[0146] In some embodiments, the device also includes: a fourth determination module for determining a second detection area having the same pattern as the first detection area on the sample mask; a fifth determination module for determining a second defect having the same type and position as the first defect on the second detection area; a sixth determination module for determining a critical size of the second defect and a critical size of a defect pattern formed by transferring the pattern of the second detection area to the wafer; and a seventh determination module for determining the second defect corresponding to the defect pattern as a target defect when the critical size of the defect pattern is within the critical size range of the reference pattern.

[0147] In some embodiments, the sample mask includes N patterns, and each pattern area is correspondingly provided with M second detection areas and P reference detection areas, wherein N, M, and P are all integers greater than or equal to 1.

[0148] In some embodiments, the N patterns include patterns of at least two layers of graphics in the wafer.

[0149] In some embodiments, the sixth determination module includes: a first determination submodule, used to determine, for each pattern in the sample mask, a target reference detection area among the P reference detection areas based on the positions of the P reference detection areas in the area where each pattern is located; a second determination submodule, used to determine the optimal exposure parameters using the target reference detection areas; the optimal exposure parameters are exposure parameters that transfer the pattern of each second detection area to the wafer to form a defect pattern; and a third determination submodule, used to determine, for each pattern in the sample mask, a critical dimension of the defect pattern.

[0150] In some embodiments, the first determination submodule includes: an acquisition unit for acquiring the position information of each reference detection area in P reference detection areas; a determination unit for determining, based on the position information of each reference detection area, the reference detection areas located at the edge and center of the area where each pattern is located in the P reference detection areas as target reference detection areas.

[0151] In some embodiments, the second determination submodule is further used to determine the critical dimension consistency of the target reference pattern after determining the optimal exposure parameters, where the target reference pattern is a pattern formed by transferring the pattern of each target reference detection area to the wafer using the optimal exposure parameters; if the critical dimension consistency does not meet the preset conditions, the optimal exposure parameters are adjusted.

[0152] In some embodiments, each second detection zone includes a light-transmitting area and a non-light-transmitting area adjacent to the light-transmitting area.

[0153] The second defect is located at the following position in the second inspection area:

[0154] Inside the light-transmitting area and not in contact with the edge of the light-transmitting area;

[0155] Inside the light-transmitting area and in contact with one edge of the light-transmitting area;

[0156] Inside the non-light-transmitting area and in contact with one edge of the non-light-transmitting area;

[0157] The interior of the non-light-transmitting area does not touch the edge of the non-light-transmitting area.

[0158] In some embodiments, the device also includes: a scanning module for scanning the first inspection area of ​​the mask to be inspected through a photomask defect detection device; an eighth determination module for determining the defect existing in the mask to be inspected as a first defect when the photomask defect detection device determines that there is a defect in the first inspection area of ​​the mask to be inspected.

[0159] In some embodiments, the critical dimension of the defect pattern includes the line width and spacing of the pattern in the defect pattern; and the critical dimension of the reference pattern includes the line width and spacing of the pattern in the reference pattern.

[0160] The description of the above device embodiment is similar to the description of the above method embodiment and has similar beneficial effects as the method embodiment. In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to perform the methods described in the above method embodiments. For technical details not disclosed in the device embodiments of this application, please refer to the description of the method embodiments of this application for understanding.

[0161] It should be noted that in the embodiment of the present application, if the above-mentioned mask detection method is implemented in the form of a software function module and is sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application, or the part that contributes to the relevant technology, can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the methods described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a U disk, a mobile hard disk, a read-only memory (ROM), a magnetic disk or an optical disk. In this way, the embodiment of the present application is not limited to any specific hardware, software or firmware, or any combination of hardware, software and firmware.

[0162] An embodiment of the present application provides a computer device, including a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and when the processor executes the program, some or all of the steps in the above method are implemented.

[0163] The present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements some or all of the steps in the above method. The computer-readable storage medium may be transient or non-transient.

[0164] It should be noted that the above descriptions of the various embodiments tend to emphasize the differences between the various embodiments, and their similarities or similarities can be referenced to each other. The descriptions of the above device and storage medium embodiments are similar to the descriptions of the above method embodiments and have similar beneficial effects as the method embodiments. For technical details not disclosed in the device and storage medium embodiments of this application, please refer to the description of the method embodiments of this application for understanding.

[0165] It should be noted that Figure 7 A schematic diagram of a hardware entity of a computer device in an embodiment of the present application is shown in FIG. Figure 7 As shown, the hardware entity of the computer device 700 includes: a processor 701, a communication interface 702 and a memory 703, wherein:

[0166] Processor 701 generally controls the overall operation of computer device 700 .

[0167] The communication interface 702 enables the computer device to communicate with other terminals or servers through a network.

[0168] The memory 703 is configured to store instructions and applications executable by the processor 701. It can also cache data to be processed or processed by the processor 701 and various modules in the computer device 700 (for example, image data, audio data, voice communication data, and video communication data). This can be implemented using flash memory (FLASH) or random access memory (RAM). Data can be transmitted between the processor 701, the communication interface 702, and the memory 703 via a bus 704.

[0169] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned steps / processes does not mean the order of execution, and the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0170] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0171] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0172] The units described above as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units; they may be located in one place or distributed across multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. In addition, the functional units in the various embodiments of the present application may all be integrated into one processing unit, or each unit may be separately used as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0173] Those skilled in the art will understand that all or part of the steps of implementing the above-mentioned method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above-mentioned method embodiment; and the aforementioned storage medium includes: mobile storage devices, read-only memories (ROM), magnetic disks or optical disks, and other media that can store program codes.

[0174] Alternatively, if the above-mentioned integrated unit of the present application is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the relevant technology, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0175] The above is only an implementation method of the present application, but the scope of protection of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, which should be covered by the scope of protection of the present application.

Claims

1. A method for detecting a photomask, characterized in that: include: Determining, on a first inspection area of ​​a mask to be inspected, a critical dimension of a first defect present in a pattern in the first inspection area; Based on the pattern of the first inspection area and the type of the first defect, obtaining an allowable critical dimension range of a target defect with the same pattern and the same defect type in a sample reticle, wherein the critical dimension of a target pattern formed by transferring the pattern having the target defect in the sample reticle to a wafer is within a critical dimension range of a reference pattern, where the reference pattern is a pattern formed by transferring a pattern of a reference inspection area that is identical to the pattern of the first inspection area but does not contain the defect to the wafer; If the critical dimension of the first defect is not within the critical dimension range allowed by the target defect, determining that the photomask to be inspected is a defective product; Determining a second detection area having the same pattern as the first detection area on the sample mask; determining, on the second inspection area, a second defect of the same type and location as the first defect; determining a critical dimension of the second defect and a critical dimension of a defect pattern formed by transferring the pattern of the second inspection area onto the wafer; When the critical dimension of the defect pattern is within the critical dimension range of the reference pattern, a second defect corresponding to the defect pattern is determined as the target defect.

2. The detection method according to claim 1, wherein Also includes: determining a location of the first defect; The step of obtaining an allowable critical dimension range of a target defect with the same pattern and the same defect type in a sample mask based on the pattern of the first inspection area and the type of the first defect includes: Based on the pattern of the first inspection area, the type of the first defect, and the position of the first defect, an allowable critical dimension range of a target defect with the same pattern, the same defect type, and the same defect position is obtained.

3. The detection method according to claim 1, wherein The sample mask includes N patterns, and each area where the pattern is located is correspondingly provided with M second detection areas and P reference detection areas, wherein N, M, and P are all integers greater than or equal to 1.

4. The detection method according to claim 3, characterized in that The N patterns include patterns of at least two layers of graphics in the wafer.

5. The detection method according to claim 3, characterized in that Determining a critical dimension of a defect pattern formed by transferring the pattern in the second inspection area to the wafer includes: For each pattern in the sample mask, determining a target reference detection area among the P reference detection areas based on positions of the P reference detection areas in the area where each pattern is located; Determining optimal exposure parameters using the target reference inspection area; the optimal exposure parameters are exposure parameters for transferring the pattern of each second inspection area to form a defect pattern on the wafer; For each pattern in the sample reticle, a critical dimension of the defect pattern is determined.

6. The detection method according to claim 5, characterized in that For each pattern in the sample mask, determining a target reference detection area among the P reference detection areas based on positions of the P reference detection areas in the area where each pattern is located, comprising: Obtaining position information of each reference detection area among the P reference detection areas; Based on the position information of each reference detection area, among the P reference detection areas, the reference detection areas located at the edge and the center of the area where each pattern is located are determined as the target reference detection areas.

7. The detection method according to claim 5, characterized in that After determining the optimal exposure parameters, the method further includes: Determining a critical dimension consistency of a target reference pattern, wherein the target reference pattern is a pattern formed by transferring a pattern of each of the target reference detection areas onto the wafer using the optimal exposure parameters; When the critical dimension consistency does not meet a preset condition, the optimal exposure parameter is adjusted.

8. The detection method according to any one of claims 3 to 7, characterized in that Each of the second detection areas includes a light-transmitting area and a non-light-transmitting area adjacent to the light-transmitting area. The second defect is located at the following position in the second inspection area: inside the light-transmitting area and not in contact with the edge of the light-transmitting area; inside the light-transmitting area and in contact with one side edge of the light-transmitting area; inside the non-light-transmitting area and in contact with one side edge of the non-light-transmitting area; The interior of the non-light-transmitting area does not contact the edge of the non-light-transmitting area.

9. The detection method according to any one of claims 1 to 7, characterized in that The method further comprises: Scanning a first inspection area of ​​the mask to be inspected by a photomask defect inspection device; When the photomask defect inspection device determines that a defect exists on the first inspection area of ​​the photomask to be inspected, the defect existing on the photomask to be inspected is determined as the first defect.

10. The detection method according to any one of claims 3 to 7, characterized in that: The critical dimension of the defect pattern includes the line width and spacing of the graphics in the defect pattern; the critical dimension of the reference pattern includes the line width and spacing of the graphics in the reference pattern.

11. A photomask, characterized in that: include: There are N patterns, and M second detection areas and P reference detection areas are correspondingly set in the area where each pattern is located, wherein there is at least one second defect in the M second detection areas, and the type of the second defect includes a particle defect or a fog defect, and the pattern of the reference detection area is the same as the pattern of the second detection area but does not contain defects, N, M, and P are all integers greater than or equal to 1, wherein the mask adopts the mask detection method described in any one of claims 1 to 10 to obtain the target defect.

12. The photomask according to claim 11, wherein: The N patterns include patterns of at least two layers of graphics in the wafer.

13. The photomask according to claim 11 or 12, wherein: Second defects of different sizes and positions exist in the M second inspection areas, and there is at most one second defect in each second inspection area; Each of the second inspection areas includes a light-transmitting area and a non-light-transmitting area adjacent to the light-transmitting area, and the second defect is located at the following position in the second inspection area: inside the light-transmitting area and not in contact with the edge of the light-transmitting area; inside the light-transmitting area and in contact with one side edge of the light-transmitting area; inside the non-light-transmitting area and in contact with one side edge of the non-light-transmitting area; The interior of the non-light-transmitting area does not contact the edge of the non-light-transmitting area.

14. A defect pattern, characterized in that The defect pattern is a pattern formed on the wafer after exposure using the mask according to any one of claims 11 to 13.

15. A method for forming a defect pattern, characterized in that: include: Providing a substrate, the substrate comprising at least an etching layer and a photoresist layer located on the etching layer; exposing and developing the photoresist layer using the photomask according to any one of claims 11 to 13 to form a photoresist layer having a first pattern; The etched layer is etched using the photoresist layer having the first pattern as a mask to form the defect pattern in the etched layer.

16. A photomask detection device, characterized in that: include: A first determining module is configured to determine a critical dimension of a first defect existing in a pattern in a first inspection area of ​​a mask to be inspected; an acquisition module, configured to acquire, based on the pattern of the first inspection area and the type of the first defect, an allowable critical dimension range of a target defect in a sample mask with the same pattern and the same defect type, wherein the critical dimension of a target pattern formed by transferring the pattern having the target defect in the sample mask to a wafer is within a critical dimension range of a reference pattern, wherein the reference pattern is a pattern formed by transferring a pattern of a reference inspection area that is identical to the pattern of the first inspection area but does not contain the defect to the wafer; a second determining module, configured to determine that the photomask to be inspected is a defective product if the critical dimension of the first defect is not within an allowable critical dimension range of the target defect; Wherein, the photomask detection device adopts the photomask detection method according to any one of claims 1 to 10 to obtain target defects of the photomask.

17. A computer device comprising a memory and a processor, wherein the memory stores a computer program executable on the processor, wherein: When the processor executes the program, the steps of the method according to any one of claims 1 to 10 are implemented.

18. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 10 are implemented.

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