FPGA-Based Method for Generating OSD Screen of Monitor

Abstract

The present invention relates to the field of liquid crystal displays, and discloses a method for generating an OSD screen of a display based on an FPGA. The method includes the following steps: Step 1, the FPGA receives an external video signal and decodes the video signal to generate a driving timing and external video data; Step 2, an internal clock and an internal driving timing with the same frequency as the external clock are generated in the DCM area; Step 3, with the external clock as the driving source, the external video data is written into the FIFO, and each time a row of the external video data is written, the next FIFO is switched to when writing each row; Step 4, with the internal clock as the driving source, the data in the FIFO is read according to the internal driving timing and an internal video screen is generated; Step 5, an OSD screen is generated using the timing relationship between the internal row signal and the internal field signal; Step 6, the OSD screen and the internal video screen are output after video superposition processing. This method can buffer the external video screen without using an external memory and has a low delay for external input signals.

Description

Technical Field

[0001] The present invention relates to the field of liquid crystal displays, and particularly to a method for generating an OSD screen of a display based on FPGA. Background Art

[0002] When an airborne military liquid crystal display adjusts the brightness and contrast using a button light guide plate, in order to intuitively display the adjustment parameters of the brightness and contrast, the display needs to generate a backlight brightness and contrast adjustment progress bar according to the button trigger value. According to the functional requirements, in addition to displaying the brightness and contrast progress bar information, the display may need to display information such as the current resolution information and the signal source. We call these information screens related to the adjustment parameters of the display the OSD screen. The current OSD generation method on the market is as follows: The FPGA uses an external memory (using SSRAM or DDR) to cache and synchronize the external video screen, and then reads out the OSD screen stored in the FLASH, and superimposes the OSD screen on the cached external video. This method requires the FPGA to use an external memory, which not only increases the complexity of the hardware circuit design but also increases the hardware cost. At the same time, since the signal needs to pass through the external memory, the signal delay is increased, and for some display systems with relatively small required delays, this method obviously does not meet the usage requirements. Summary of the Invention

[0003] In order to overcome the problem of time extension in video display existing in the prior art, the present invention provides a method for generating an OSD screen of a display based on FPGA. This method can buffer the external video screen without using an external memory and has a relatively low delay for external input signals. (The following repeated content is modified as above)

[0004] The present invention provides a method for generating an OSD screen of a display based on FPGA. This method for generating an OSD screen of a display uses an FPGA with internal resources such as ROM, FIFO, and DCM. By means of the above internal resources of the FPGA, a video synchronization and video superposition logic algorithm is used to implement the generation of the OSD screen of the display;

[0005] The method for generating the OSD screen of the display includes the following steps:

[0006] Step 1: The FPGA receives an external video signal, decodes the video signal, and generates a driving timing and external video data. Among them, the driving timing includes an external clock Pixel_CLK, an external row signal Hsync, an external field signal Vsync, and an external data enable signal DE; the external video data includes a red data component R_data, a green data component G_data, and a blue data component B_data;

[0007] Step 2: Use DCM to generate an internal clock Sync_CLK with the same frequency as the external clock Pixel_CLK, and use the internal clock Sync_CLK as the clock driving source to generate an internal driving timing according to the external data enable signal DE. The internal driving timing includes: an internal row signal Sync_Hsync, an internal field signal Sync_Vsync, and an internal data enable signal Sync_DE;

[0008] Step 3: Using the external clock Pixel_CLK as the driving source, the FPGA writes external video data into the FIFO according to the driving timing. Each time, one row of external video data is written, and each time a row is written, it switches to the next FIFO;

[0009] Step 4: Using the internal clock Sync_CLK as the driving source, the FPGA reads the data in the FIFO according to the internal driving timing and generates an internal video picture Syn_Video;

[0010] Step 5: When there is an external key input, use the timing relationship between the internal row signal Sync_Hsync and the internal field signal Sync_Vsync to generate an OSD picture OSD_Frame1;

[0011] Step 6: The OSD picture OSD_Frame1 generated in Step 5 and the internal video picture Syn_Video generated in Step 4 are output after video overlay processing.

[0012] Preferably, the period and high and low level times of the internal driving timing in Step 2 are the same as the period and high and low level times of the driving timing of the external video input.

[0013] Preferably, the FIFO in Step 3 is set as an asynchronous FIFO and the depth of the FIFO is set to at least twice the number of data in one row of the input resolution. At least two asynchronous FIFOs are set.

[0014] Preferably, in Step 3, the external clock Pixel_CLK is used as the driving source, and one row of external video data is written into the first FIFO during the period when the external data enable signal DE is at a high level;

[0015] Then, during the next period when the external data enable signal DE is at a high level, the next row of external video data is written into the second FIFO;

[0016] And so on, writing external video data in multiple FIFOs in a loop in turn. Each time, one row is written, and each time a row is written, it switches to the next FIFO.

[0017] Preferably, two FIFOs are used in step four. Driven by the internal clock Sync_CLK, data in the FIFO is read during the high level of the internal data enable signal Sync_DE, and the read data is staggered from the written data.

[0018] In state State0, during the high level of the external data enable signal DE, one line of external video data is written into the first FIFO driven by the external clock Pixel_CLK. At the same time, during the high level of the internal data enable signal Sync_DE, one line of external video data is read from the second FIFO driven by the internal clock Sync_CLK. In the next line, it switches to state State1. During the high level of the external data enable signal DE, one line of external video data is written into the second FIFO driven by the external clock Pixel_CLK. At the same time, during the high level of the internal data enable signal Sync_DE, one line of external video data is read from the first FIFO driven by the internal clock Sync_CLK. In the next line, it switches back to state State0 and cycles through the states in turn.

[0019] Preferably, in step five, the display position Loc1 of the OSD screen on the display is marked.

[0020] When the video input stops, the OSD screen OSD_Frame2 is generated according to the timing relationship of the internal set line signal Inter_Hsync and the internal set field signal Inter_Vsync, and the position where the OSD screen OSD_Frame2 is generated is adjusted to be consistent with the display position Loc1.

[0021] Preferably, in step six, the method of video overlay processing is a semi-transparent overlay algorithm, using I = I1 + I2 * (1 - α), where I is the overlay output video data, I1 is the internal video screen Syn_Video, I2 is the OSD screen video data, and the α value is adjusted to achieve the transparency of the OSD screen overlay display.

[0022] Preferably, in step five, the FPGA collects the signals input by the external keys and analyzes the collected signals to determine whether to trigger the dynamic change of the OSD screen or whether to display it.

[0023] Special characters in the OSD screen are realized by reading the character font patterns stored in the ROM.

[0024] According to the above technical solution, when there is an external video input, the FPGA generates an internal clock Sync_CLK, an internal line signal Sync_Hsync, an internal field signal Sync_Vsync, and an internal data enable signal Sync_DE that have the same period and high and low level times as the external data based on the external clock Pixel_CLK, external line signal Hsync, external field signal Vsync, and external data enable signal DE of the external video. In this way, the timing correlation between the external video data and the internal video data is achieved. Subsequently, the FPGA writes the external video data into the FIFO area with the external clock Pixel_CLK as the driving source, and at the same time reads the external video data in the FIFO area sequentially with the internal clock Sync_CLK as the driving source and generates an internal video picture Syn_Video.

[0025] When there is an external key input, the FPGA generates an OSD picture OSD_Frame1 based on the timing relationship between the internal line signal Sync_Hsync and the internal field signal Sync_Vsync. This picture is displayed based on the internal video picture and is output after being processed by video overlay with the internal video picture Syn_Video. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings are used to provide a further understanding of the present invention and constitute a part of the specification. They are used together with the following specific embodiments to explain the present invention, but do not constitute a limitation to the present invention. In the drawings:

[0027] Figure 1 is a schematic diagram of the FPGA generating an OSD picture in a preferred embodiment; SPECIFIC EMBODIMENTS

[0028] The following details the specific embodiments of the present invention with reference to the drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present invention and are not used to limit the present invention.

[0029] In the present invention, unless otherwise stated, the directional terms included in the terms only represent the directions of the terms in the normal use state or the common names understood by those skilled in the art, and should not be regarded as a limitation to the terms.

[0030] See Figure 1 A method for generating an OSD picture of a display based on an FPGA as shown. This method for generating an OSD picture of a display uses an FPGA, which has resources such as a ROM, a FIFO, and a DCM inside. With the help of the above internal resources of the FPGA, a video synchronization and video overlay logic algorithm is used to implement the generation of the OSD picture of the display;

[0031] The method for generating an OSD picture of a display includes the following steps:

[0032] Step 1: The FPGA receives an external video signal, decodes the video signal to generate a driving timing sequence and external video data. The driving timing sequence includes an external clock Pixel_CLK, an external line signal Hsync, an external field signal Vsync, and an external data enable signal DE. The external video data includes a red data component R_data, a green data component G_data, and a blue data component B_data.

[0033] Step 2: Use a DCM to generate an internal clock Sync_CLK with the same frequency as the external clock Pixel_CLK, and use the internal clock Sync_CLK as the clock driving source to generate an internal driving timing sequence according to the external data enable signal DE. The internal driving timing sequence includes an internal line signal Sync_Hsync, an internal field signal Sync_Vsync, and an internal data enable signal Sync_DE.

[0034] Step 3: Using the external clock Pixel_CLK as the driving source, the FPGA writes the external video data into the FIFO according to the driving timing sequence, writing one line of external video data each time, and switching to the next FIFO for each line written.

[0035] Step 4: Using the internal clock Sync_CLK as the driving source, the FPGA reads the data in the FIFO according to the internal driving timing sequence and generates an internal video frame Syn_Video.

[0036] Step 5: When there is an external key input, use the timing relationship between the internal line signal Sync_Hsync and the internal field signal Sync_Vsync to generate an OSD frame OSD_Frame1.

[0037] Step 6: The OSD frame OSD_Frame1 generated in Step 5 and the internal video frame Syn_Video generated in Step 4 are output after video overlay processing.

[0038] Based on the implementation of the above technical solution, the FPGA first decodes the external video, generates an external clock Pixel_CLK, an external line signal Hsync, an external field signal Vsync, and an external data enable signal DE. At the same time, an internal clock Sync_CLK with the same frequency as the external clock Pixel_CLK is generated in the DCM area, and using the internal clock Sync_CLK as the clock driving source, an internal line signal Sync_Hsync, an internal field signal Sync_Vsync, and an internal data enable signal Sync_DE are generated according to the external data enable signal DE. Thus, the FPGA has a clock signal synchronized with the external video, which can be used to synchronize the generation of the internal video frame.

[0039] Similarly, when there is an external key input, i.e., when Key_IN is generated, the FPGA can generate the OSD screen OSD_Frame1 according to the timing relationship between the internal line signal Sync_Hsync and the internal field signal Sync_Vsync and in combination with the input information of the external key. All of these are completed simultaneously with the external video processing within the FPGA, thus realizing the synchronous processing of the OSD screen OSD_Frame1 and the external video screen. The OSD screen OSD_Frame1 and the internal video screen Syn_Video are output after video overlay processing.

[0040] Different from the prior art where each frame of the screen is processed each time, in the video synchronization process of the present invention, only one line of external video data is cached each time. Therefore, the video data delay caused by the present invention is the cycle time of one line signal of the external video resolution. Compared with the technical solution where a memory is used to synchronize the external video and the memory caches the entire frame of video, resulting in a delay of the entire frame signal, the present invention greatly reduces the signal delay time.

[0041] In this embodiment, preferably, the period and the high and low level times of the internal driving timing in step two are the same as those of the driving timing of the external video input.

[0042] The internal and external data enable signals have the same high and low level times, which can ensure that all the written external video data can be accurately read.

[0043] Meanwhile, the internal line signal Sync_Hsync and the internal field signal Sync_Vsync having the same period and high and low level times as the external line signal Hsync and the external field signal Vsync can ensure that the externally input video screen is the same as the internal video screen Syn_Video generated within the FPGA.

[0044] In this embodiment, preferably, the FIFO in step three is set as an asynchronous FIFO, and the depth of the FIFO is set to at least twice the number of data in one line of the input resolution. At least two asynchronous FIFOs are set.

[0045] The writing of the FIFO is controlled by the external data enable signal DE, and the reading of the FIFO is controlled by the internal data enable signal Sync_DE. Therefore, the FIFO needs to be set as an asynchronous FIFO.

[0046] The reading and writing of the same FIFO cannot be performed simultaneously. Therefore, at least two asynchronous FIFOs need to be set. By using the ping-pong operation of reading and writing with two FIFOs inside the FPGA and then using the timing generated inside the FPGA to replace the external video timing, the synchronization of the external video data and the internal clock Sync_CLK of the FPGA is achieved.

[0047] In the above-described embodiment, preferably, in step three, an external clock Pixel_CLK is used as a driving source, and during a period when an external data enable signal DE is at a high level, a row of external video data is written into the first FIFO.

[0048] Then, during the next period when the external data enable signal DE is at a high level, the next row of external video data is written into the second FIFO.

[0049] And so on, the external video data is cyclically written into multiple FIFOs in sequence, with one row of external video data written each time, and the next FIFO is switched to each time a row is written.

[0050] In the present invention, only one row of external video data is cached each time, and only the cycle time of one row of signals of the external video resolution is used. In combination with timely video signal reading, the delay time of the video output is the cycle time of one row of signals of the external video resolution, and almost synchronous output of the external video can be achieved.

[0051] In the above-described embodiment, preferably, in step four, two FIFOs are used, with an internal clock Sync_CLK as a driving source, and data in the FIFO is read during a period when an internal data enable signal Sync_DE is at a high level. The data read from the FIFO and the data written should be staggered from each other.

[0052] In state State0, during a period when the external data enable signal DE is at a high level, a row of external video data is written into the first FIFO with the external clock Pixel_CLK as a driving source. At the same time, during a period when Sync_DE is at a high level, a row of data is read from the second FIFO with Sync_CLK as a clock driving source; for the next row, it switches to state State1. During a period when the external data enable signal DE is at a high level, a row of external video data is written into the second FIFO with Pixel_CLK as a driving source. At the same time, during a period when Sync_DE is at a high level, a row of data is read from the first FIFO with Sync_CLK as a clock driving source; for the next row, it switches back to state State0, and the states are cyclically switched in sequence.

[0053] Since the current FIFO data buffering capabilities are sufficient to meet the requirement of caching only one row of external video data in the present invention, from the perspective of economy, only two FIFOs need to be set to meet the usage requirements.

[0054] When two FIFOs are used, there are two states for reading and writing: State0 and State1.

[0055] It starts with the state of State0. During the high level of the external data enable signal DE, the first line of video data is written into the first FIFO with the external clock Pixel_CLK as the driving source. At the same time, during the high level of the internal data enable signal Sync_DE, a line of video data is read from the second FIFO with the internal clock Sync_CLK as the clock driving source. At this time, no data has been written into the second FIFO, so the FPGA does not read any data.

[0056] Next is the state of State1. During the high level of the external data enable signal DE, the second line of video data is written into the second FIFO with the external clock Pixel_CLK as the driving source. At the same time, during the high level of the internal data enable signal Sync_DE, a line of video data is read from the first FIFO with Sync_CLK as the clock driving source. At this time, since the first line of video data has been written into the first FIFO in the State0 state, the FPGA reads out the first video data.

[0057] Then it comes back to the state of State0 again. The third line of video data is written into the first FIFO, and a line of video data is read from the second FIFO. Since the second line of video data is written into the second FIFO at this time, the FPGA reads out the second video data.

[0058] In this way, the FPGA can realize the line-by-line reading of external video data.

[0059] At the same time, the FPGA processes the read video data to form an internal video picture Syn_Video for display.

[0060] At this time, if there is an input of Key_IN, the OSD picture needs to be superimposed on the display picture of the internal video picture Syn_Video. At this time, the display of the OSD picture needs to be generated by controlling the position relationship of data, line, field, and data enable signals under the drive of the internal clock Sync_CLK. In this way, the generated OSD picture is synchronized with the internal clock Sync_CLK, and then the synchronous display of the OSD picture and the internal video picture is realized.

[0061] In the above embodiment, preferably, in step five, mark the display position Loc1 of the OSD picture in the display.

[0062] When the video input stops, the OSD picture OSD_Frame2 is generated according to the timing relationship between the internal set line signal Inter_Hsync and the internal set field signal Inter_Vsync, and the generation position of the OSD picture OSD_Frame2 is adjusted to be consistent with the display position Loc1.

[0063] When the external video input to the FPGA stops while the OSD screen still needs to be continuously displayed, it is necessary to use the built-in screen of the display to overlay and display with the OSD screen. The internal screen of the display is generated by the positional relationship of the internally set line signal Inter_Hsync, the internally set field signal Inter_Vsync, and the internally set data enable signal Inter_DE. Since there may be differences between the positional relationships of the internal line signal Sync_Hsync, the internal field signal Sync_Vsync, and the internal data enable signal Sync_DE corresponding to the external video and the positional relationship of the internally set timing signal, resulting in differences in the display positions of the OSD screens generated using the two timings in the display. Therefore, when there is no external video input, it is necessary to adjust the display position of the OSD screen so that the overlay position of the OSD screen and the built-in screen of the display is the same as the screen position when there is external video input.

[0064] In this embodiment, preferably, in step six, the method of video overlay processing is the variable semi-transparent overlay algorithm, using I = I1 + I2*(1 - α), where I is the video data output by the overlay, I1 is the Syn_Video video data, I2 is the OSD screen video data, and the transparency of the OSD screen overlay display is adjusted by changing the value of α.

[0065] The overlay processing of the OSD screen and the Syn_Video video data is mainly achieved through the semi-transparent overlay algorithm. The OSD screen data and the external video data are operated according to the formula I = I1 + I2*(1 - α). Considering that α is a decimal, all data can be shifted left by 8 bits to be extended to integers for operation, and at the same time, a multi-stage pipeline method should be used to accelerate the data operation speed during the operation.

[0066] In this embodiment, preferably, in step five, the FPGA collects the signals input by the external keys and analyzes the collected signals to determine whether it is necessary to trigger the dynamic change of the OSD screen or whether it is necessary to display.

[0067] The special characters in the OSD screen are realized by reading the character font patterns stored in the ROM.

[0068] The preferred embodiments of the present invention have been described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solutions of the present invention, and these simple modifications all fall within the protection scope of the present invention.

[0069] In addition, it should be noted that, among the various specific technical features described in the above specific embodiments, without contradiction, they can be combined in any appropriate manner. To avoid unnecessary repetition, the present invention will not separately describe various possible combination methods.

[0070] In addition, any combinations can be made among various different embodiments of the present invention, as long as they do not violate the idea of the present invention, and they should also be regarded as the content disclosed by the present invention.

Claims

1. A method for generating an OSD screen of a display based on FPGA, characterized in that, The method for generating the OSD screen of the display uses an FPGA, which has a ROM, a FIFO, and a DCM inside. By means of the internal resources of the above FPGA, the video synchronization and video overlay logic algorithms are used to realize the generation of the OSD screen of the display; The method for generating the OSD screen of the display includes the following steps: Step 1: The FPGA receives an external video signal and decodes the video signal to generate a driving timing and external video data. Among them, the driving timing includes an external clock Pixel_CLK, an external line signal Hsync, an external field signal Vsync, and an external data enable signal DE; the external video data includes: a red data component R_data, a green data component G_data, and a blue data component B_data; Step 2: Use the DCM to generate an internal clock Sync_CLK with the same frequency as the external clock Pixel_CLK, and use the internal clock Sync_CLK as the clock driving source to generate an internal driving timing according to the external data enable signal DE. The internal driving timing includes: an internal line signal Sync_Hsync, an internal field signal Sync_Vsync, and an internal data enable signal Sync_DE; Step 3: With the external clock Pixel_CLK as the driving source, the FPGA writes the external video data into the FIFO according to the driving timing. Each time, one line of the external video data is written, and each time a line is written, it is switched to the next FIFO; Step 4: With the internal clock Sync_CLK as the driving source, the FPGA reads the data in the FIFO according to the internal driving timing and generates an internal video screen Syn_Video; Step 5: When there is an external key input, use the timing relationship between the internal line signal Sync_Hsync and the internal field signal Sync_Vsync to generate an OSD screen OSD_Frame1; Step 6: The OSD screen OSD_Frame1 generated in Step 5 and the internal video screen Syn_Video generated in Step 4 are output after video overlay processing.

2. The method for generating a display OSD screen according to claim 1, wherein The period and high and low level times of the internal driving timing in Step 2 are the same as the period and high and low level times of the driving timing of the external video input.

3. The method for generating a display OSD screen according to claim 1, wherein The FIFO in Step 3 is set as an asynchronous FIFO, and the depth of the FIFO is set to at least twice the number of data in one line of the input resolution. At least two asynchronous FIFOs are set.

4. The method for generating a display OSD screen according to claim 3, wherein In Step 3, use the external clock Pixel_CLK as the driving source, and write one line of the external video data into the first FIFO during the period when the external data enable signal DE is at a high level; Then, during the next period when the external data enable signal DE is at a high level, write the next line of the external video data into the second FIFO; Write the external video data in multiple FIFOs in turn in a loop. Each time, one line is written, and each time a line is written, it is switched to the next FIFO.

5. The method for generating a display OSD screen according to claim 4, characterized in that, In step 4, two FIFOs are used. With the internal clock Sync_CLK as the driving source, data in the FIFO is read during the period when the internal data enable signal Sync_DE is at a high level, and the read data is staggered from the written data. In state State0, during the period when the external data enable signal DE is at a high level, one row of the external video data is written into the first FIFO with the external clock Pixel_CLK as the driving source. Meanwhile, during the period when the internal data enable signal Sync_DE is at a high level, one row of the external video data is read from the second FIFO with the internal clock Sync_CLK as the clock driving source. For the next row, switch to state State1. During the period when the external data enable signal DE is at a high level, one row of the external video data is written into the second FIFO with the external clock Pixel_CLK as the driving source. Meanwhile, during the period when the internal data enable signal Sync_DE is at a high level, one row of the external video data is read from the first FIFO with the internal clock Sync_CLK as the clock driving source. For the next row, switch back to state State0 and cycle through the states in sequence.

6. The method for generating an OSD screen of a display according to claim 1, wherein In step 5, mark the display position Loc1 of the OSD screen on the display. When the video input stops, an OSD screen OSD_Frame2 is generated according to the timing relationship of the internal set line signal Inter_Hsync and the internal set field signal Inter_Vsync, and the generation position of the OSD screen OSD_Frame2 is adjusted to be consistent with the display position Loc1.

7. The method for generating a display OSD screen according to claim 1, wherein In step 6, the method of video overlay processing is a semi-transparent overlay algorithm, using I = I1 + I2 * (1 - α), where I is the overlay output video data, I1 is the internal video picture Syn_Video, I2 is the OSD screen video data, and the transparency of the OSD screen overlay display is achieved by adjusting the α value.

8. The method for generating a display OSD screen according to claim 1, wherein In step 5, the FPGA collects the signals input by the external keys and analyzes the collected signals to determine whether to trigger dynamic changes in the OSD screen or whether to display it. Special characters in the OSD screen are realized by reading the character font stored in the ROM.

Images