A semiconductor device and a manufacturing method thereof

Abstract

The present application discloses a semiconductor device and a manufacturing method thereof. The method includes: providing a semiconductor substrate; patterning the first dielectric layer to form trenches extending along the substrate in the substrate; sequentially forming a first auxiliary layer and a first metal layer in the trenches, the first metal layer being located on a side of the first auxiliary layer facing the first dielectric layer; thinning the substrate on a second surface of the substrate until the first auxiliary layer is exposed; removing the first auxiliary layer to form a first opening; forming a second metal layer on the second surface of the substrate and filling the first opening with the second metal layer. Since the first auxiliary layer is filled at the bottom of the trench after the trench is formed, the substrate will not have cracks due to simultaneous grinding of the substrate and the first metal layer, and copper contamination to the surface of the adjacent silicon layer or the cracks can be prevented, thereby improving the yield of TSV manufacturing.

Description

Technical Field

[0001] This application relates to the field of integrated circuit manufacturing technologies, and particularly to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Through Silicon Vias (TSV) technology can achieve the shortest distance and the smallest pitch between chips for interconnection, so as to achieve better electrical performance.

[0003] However, in related technologies, during the process of fabricating TSV, it is usually necessary to grind until the copper layer is exposed. In this process, it is necessary to grind both silicon material and copper material at the same time. The silicon material is brittle and prone to cracks. And copper is prone to diffuse in the semiconductor silicon wafer under high temperature and applied electric field, and it is easy to have the phenomenon of copper contamination on the surface of the adjacent silicon layer or in the cracks, resulting in a low yield. Summary of the Invention

[0004] An embodiment of this application provides a semiconductor device and a manufacturing method thereof, which can avoid copper contamination into the substrate silicon layer during the process of fabricating TSV and improve the yield of TSV fabrication.

[0005] In a first aspect, this application provides a method for manufacturing a semiconductor device, including:

[0006] Providing a semiconductor substrate, on which a first dielectric layer is formed on a first surface of the substrate;

[0007] Patterning the first dielectric layer to form a trench extending along the substrate in the substrate;

[0008] Sequentially forming a first auxiliary layer and a first metal layer in the trench, the first metal layer being located on a side of the first auxiliary layer facing the first dielectric layer; thinning the substrate on a second surface of the substrate until the first auxiliary layer is exposed;

[0009] Removing the first auxiliary layer to form a first opening;

[0010] Forming a second metal layer on the second surface of the substrate and filling the first opening with the second metal layer.

[0011] The method provided by this embodiment provides a semiconductor substrate, on which a first dielectric layer is formed on a first surface of the substrate; the first dielectric layer is patterned to form trenches extending along the substrate in the substrate; a first auxiliary layer and a first metal layer are sequentially formed in the trenches, and the first metal layer is located on a side of the first auxiliary layer facing the first dielectric layer; the substrate is thinned on a second surface of the substrate until the first auxiliary layer is exposed; the first auxiliary layer is removed to form a first opening; a second metal layer is formed on the second surface of the substrate, and the second metal layer fills the first opening. After the trenches are formed, the first auxiliary layer is filled at the bottom of the trenches first. Since the depths of the trenches are not completely consistent, when the substrate is thinned on the second surface of the substrate until the first auxiliary layer is exposed, the substrate and the first metal layer will not be ground simultaneously, resulting in cracks in the substrate, and copper contamination to the surface of the adjacent silicon layer or cracks can be prevented, thereby improving the yield of TSV manufacturing.

[0012] In an alternative embodiment, before the first auxiliary layer and the first metal layer are sequentially formed in each of the trenches, the method further includes:

[0013] A dielectric layer and a first barrier layer are sequentially formed on the inner walls of the trenches, and the dielectric layer may have the same or different materials from the first auxiliary layer.

[0014] In the above method, a dielectric layer and a first barrier layer are sequentially formed on the inner walls of the trenches. By providing the first barrier layer, a buffering barrier for the substrate during grinding can also be provided, reducing the probability of cracks in the silicon layer, and preventing copper contamination to the surface of the adjacent silicon layer or cracks, further improving the yield of TSV manufacturing.

[0015] In an alternative embodiment, after removing the first auxiliary layer to form a first opening, and before forming the second metal layer, a second dielectric layer is formed on the second surface of the substrate, and the second dielectric layer has a second opening that exposes the first opening.

[0016] In an alternative embodiment, the second metal layer is simultaneously formed in the second opening, and before the second metal layer is formed in the second opening, a second barrier layer is formed on the sidewalls of the second dielectric layer.

[0017] In the above method, a second barrier layer is formed on the inner wall of the second opening, further strengthening the buffering barrier provided for the substrate during grinding and preventing copper contamination to the surface of the adjacent silicon layer or cracks.

[0018] In an alternative embodiment, after forming the second metal layer, the method further includes:

[0019] Etch away the dielectric layer to form an air gap structure; the air gap structure is a gap between the first barrier layer and the inner wall of the trench.

[0020] In the above method, after forming the second metal layer, etch away the dielectric layer to form an air gap structure; the air gap structure is a gap between the first barrier layer and the inner wall of the trench. By providing a dielectric layer, an air gap structure can be formed, which provides a gap between the substrate and the conductive metal layer in the barrier layer, reduces the thermal stress caused by the mismatch of the thermal expansion coefficients between the substrate and the conductive metal layer in the barrier layer, reduces the probability of cracks in the silicon layer, and prevents copper from contaminating the surface or cracks of the adjacent silicon layer, further improving the yield of TSV manufacturing.

[0021] In an alternative embodiment, the etching away of the dielectric layer to form an air gap structure includes:

[0022] Etch away the first dielectric layer and the dielectric layer in the trench;

[0023] Rapidly deposit a third dielectric layer on the first surface of the substrate to form the air gap structure in the trench.

[0024] In an alternative embodiment, the third dielectric layer covers the sidewalls of the first metal layer on the first surface and exposes the top surface of the first metal layer.

[0025] In an alternative embodiment, the first dielectric layer and the dielectric layer are of the same material, and the first barrier layer and the second barrier layer are of the same material.

[0026] In an alternative embodiment, the second metal layer is the same as or different from the first metal layer in material.

[0027] In an alternative embodiment, the second metal layer and the first metal layer are made of copper; after depositing the second metal layer on the second dielectric layer, the method further includes:

[0028] Anneal the second metal layer.

[0029] In the above method, by annealing the second metal layer after depositing the second metal layer on the second dielectric layer, the stress can be released.

[0030] In an alternative embodiment, after forming the air gap structure, the method further includes:

[0031] Anneal the second metal layer.

[0032] In the above method, by annealing the second metal layer after forming the air gap structure, the stress between the substrate and the metal layer can be well relieved.

[0033] In an optional embodiment, in the method, the dielectric layer is silicon nitride; the material of the first barrier layer is titanium nitride.

[0034] In the above method, the dielectric layer is silicon nitride, providing good insulation; the material of the first barrier layer is titanium nitride, which can provide a buffering barrier during grinding of the substrate and prevent copper from contaminating the surface or cracks of the adjacent silicon layer.

[0035] In an optional embodiment, in the method, when removing the first auxiliary layer in the trench through an etching process, the first auxiliary layer has a high selectivity ratio with respect to the substrate.

[0036] In the above method, the first auxiliary layer has a high selectivity ratio with respect to the substrate, enabling the first auxiliary layer to be etched quickly and reducing the impact on the substrate.

[0037] In an optional embodiment, in the method, the first thermal expansion coefficient of the second metal layer is less than the second thermal expansion coefficient of the first metal layer.

[0038] In the above method, the first thermal expansion coefficient of the second metal layer is less than the second thermal expansion coefficient of the first metal layer, reducing the stress borne by the substrate and further reducing the thermal stress caused by the mismatch in thermal expansion coefficients between the substrate and the conductive metal layer in the barrier layer.

[0039] In an optional embodiment, in the method, the material of the first metal layer includes copper.

[0040] In the above method, the material of the first metal layer is copper, providing excellent electrical conductivity.

[0041] In a second aspect, an embodiment of the present application further provides a semiconductor device, including:

[0042] A substrate having a first surface and a second surface;

[0043] A first dielectric layer located on the first surface of the substrate;

[0044] A trench formed in the first dielectric layer and penetrating the substrate, a metal layer being formed in the trench, the metal layer including a first metal layer and a second metal layer formed on the first metal layer; the first metal layer fills the first end of the trench close to the first dielectric layer; the first metal layer has a first height, and the second metal layer has a second height, and the first height is greater than the second height.

[0045] In an alternative embodiment, a barrier layer is further included in the trench, and the barrier layer is formed between the trench and the metal layer.

[0046] In an alternative embodiment, an air gap structure is further included in the trench, and the air gap structure is formed between the trench and the metal layer.

[0047] In an alternative embodiment, a second dielectric layer is further included, and the second dielectric layer is formed on the second surface and has an opening exposing the trench, and the second metal layer is formed in the opening at the same time.

[0048] For the technical effects brought by any implementation manner in the second aspect, reference may be made to the corresponding implementation manner in the first aspect, which will not be elaborated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0050] Figure 1 It is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0051] Figure 2 It is a schematic diagram of a semiconductor substrate and a trench provided by an embodiment of the present application;

[0052] Figure 3 It is a schematic diagram of forming a first auxiliary layer and a first metal layer provided by an embodiment of the present application;

[0053] Figure 4 It is a schematic diagram of substrate thinning provided by an embodiment of the present application;

[0054] Figure 5 It is a schematic diagram of etching the first auxiliary layer in the trench provided by an embodiment of the present application;

[0055] Figure 6 It is a schematic diagram of forming a second metal layer provided by an embodiment of the present application;

[0056] Figure 7 It is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0057] Figure 8 It is a schematic diagram of forming a dielectric layer and a first barrier layer provided by an embodiment of the present application;

[0058] Figure 9 Schematic diagram of forming a second dielectric layer provided by an embodiment of the present application;

[0059] Figure 10 Schematic diagram of forming an air gap structure provided by an embodiment of the present application;

[0060] Figure 11 Schematic diagram of forming a third dielectric layer provided by an embodiment of the present application. Detailed implementation manners

[0061] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present application.

[0062] In the embodiments of the present application, the term "exemplary" means "serving as an example, an embodiment or an illustration". Any embodiment described as "exemplary" is not necessarily to be construed as superior or better than other embodiments.

[0063] The terms "first" and "second" in the text are only used for descriptive purposes, and cannot be construed as explicitly or implicitly indicating relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, unless otherwise specified, the meaning of "a plurality" is two or more.

[0064] Some terms in the embodiments of the present application are explained below to facilitate the understanding of those skilled in the art.

[0065] (1) High selectivity: Selectivity refers to how much faster the etching rate of one material is compared to another under the same etching conditions. It is defined as the ratio of the etching rate of the material to be etched to the etching rate of another material. High selectivity means that only the layer of material that is desired to be etched away is etched. An etching process with high selectivity does not etch the underlying layer of material (stops at the appropriate depth) and the photoresist that is protected is not etched either.

[0066] (2) Annealing: Annealing is a metal heat treatment process, which refers to slowly heating the metal to a certain temperature, maintaining it for a sufficient time, and then cooling it at an appropriate speed. The purpose is to reduce hardness and improve machinability; reduce residual stress, stabilize dimensions, and reduce the tendency of deformation and cracks; refine grains, adjust the structure, and eliminate structural defects. Exactly speaking, annealing is a heat treatment process for materials, including metal materials and non-metallic materials.

[0067] (3) Coefficient of thermal expansion: Objects expand and contract due to temperature changes. Its change ability is expressed by the coefficient of thermal expansion, which is the change in the length value caused by a unit temperature change under constant pressure (p constant). The coefficients of thermal expansion of various objects are different. Generally, the unit of the coefficient of thermal expansion of metals is 1 / degree (Celsius).

[0068] Currently, the through-silicon via technology can achieve the shortest distance and the smallest pitch between chips for interconnection to achieve better electrical performance.

[0069] However, in the related technology, during the process of fabricating TSV, it is usually necessary to grind until the copper layer is exposed. In this process, it is necessary to grind both the silicon material and the copper material at the same time. The silicon material is brittle and prone to cracks. And copper is prone to diffuse in the semiconductor silicon wafer under high temperature and applied electric field, and it is easy to appear the phenomenon of copper contamination on the surface of the adjacent silicon layer or in the cracks, resulting in a low yield.

[0070] This application provides a semiconductor device and a manufacturing method thereof, which solve the problem that in the process of fabricating TSV, it is easy to appear the phenomenon of copper contamination on the surface of the adjacent silicon layer or in the cracks, resulting in a low yield. The method includes: providing a semiconductor substrate, on which a first dielectric layer is formed on a first surface of the substrate; patterning the first dielectric layer to form a trench extending along the substrate in the substrate; sequentially forming a first auxiliary layer and a first metal layer in the trench, the first metal layer being located on a side of the first auxiliary layer facing the first dielectric layer; thinning the substrate on a second surface of the substrate until the first auxiliary layer is exposed; removing the first auxiliary layer to form a first opening; forming a second metal layer on the second surface of the substrate and filling the first opening with the second metal layer. After forming the trench, the first auxiliary layer is first filled at the bottom of the trench. Since the depths of the trenches are not completely the same, when the substrate is thinned on the second surface of the substrate until the first auxiliary layer is exposed later, the substrate will not crack due to grinding the substrate and the first metal layer at the same time, and copper contamination on the surface of the adjacent silicon layer or in the cracks can be prevented, thereby improving the yield of TSV fabrication.

[0071] To further illustrate the technical solutions provided by the embodiments of this application, the manufacturing method of the semiconductor device provided by the embodiments of this application will be further described below.

[0072] Figure 1The flowchart shows a method for fabricating a semiconductor device provided by an embodiment of the present application. As Figure 1 shown, the method for fabricating the semiconductor device includes the following process steps:

[0073] Step S101: Provide a semiconductor substrate.

[0074] A first dielectric layer is formed on the first surface of the semiconductor substrate.

[0075] Specifically, the semiconductor substrate includes a substrate and a first dielectric layer on the front surface of the substrate. The substrate has a front surface and a back surface. A first dielectric layer is formed on the first surface of the substrate.

[0076] Step S102: Pattern the first dielectric layer to form trenches extending along the substrate in the substrate.

[0077] Specifically, pattern the first dielectric layer to form trenches on the semiconductor substrate; the trenches penetrate the first dielectric layer and do not extend to the back surface of the substrate.

[0078] Specifically, the number of trenches can be multiple. During the fabrication of the semiconductor device, the required number of trenches can be provided in appropriate areas of the semiconductor device according to the overall device layout, so as to connect to other semiconductor devices, etc.

[0079] Exemplarily, as Figure 2 shown, provide a semiconductor substrate 200. Among them, the semiconductor substrate 200 includes a substrate 201 and a first dielectric layer 202 on the front surface 201F of the substrate 201. Trenches 203a are provided on the semiconductor substrate 200. The trenches 203a penetrate the first dielectric layer 202 and do not extend to the back surface 201B of the substrate 201. Figure 2 In, the number of trenches 203a is two, only for illustrative purposes, and does not limit the technical solution of the present application. The required number of trenches can be provided in appropriate areas of the semiconductor substrate 200 according to the overall device layout. The number of trenches can be one or multiple. For example, trenches 203a1, 203a2,..., 203aN can be provided to connect to other semiconductor devices, etc. It can be understood that due to manufacturing processes, the depths of the trenches may not be completely consistent.

[0080] Step S103: Sequentially form a first auxiliary layer and a first metal layer in each trench, and the first metal layer is located on the side of the first auxiliary layer facing the first dielectric layer.

[0081] Among them, the material of the first auxiliary layer has less ductility than the material of the first metal layer.

[0082] Exemplarily, as Figure 3As shown, a first auxiliary layer 204 and a first metal layer 205 are sequentially formed in each groove 203a, and the first metal layer 204 is located on the side of the first auxiliary layer 205 facing the first dielectric layer 202.

[0083] In a possible implementation, the material of the first metal layer is copper.

[0084] In a possible implementation, the material of the first auxiliary layer is silicon dioxide, silicon nitride, or a metal with a ductility less than that of the first metal layer.

[0085] Step S104: Thinning the substrate on the second surface of the substrate until the first auxiliary layer is exposed.

[0086] Specifically, when implementing, the substrate is thinned on the back side of the substrate until the first auxiliary layer is exposed.

[0087] Exemplarily, as Figure 4 shown, the substrate 201 is thinned on the back side 201B of the substrate 201 until the first auxiliary layer 205 is exposed, obtaining a thinned substrate 201', and the thinned substrate has a back side 201B' and a front side 201F'. Among them, the front side 201F' of the thinned substrate 201' is the same as the front side 201F of the substrate 201.

[0088] Step S105: Removing the first auxiliary layer to form a first opening.

[0089] Specifically, when implementing, the first auxiliary layer in the groove can be removed through an etching process to form a first opening.

[0090] Exemplarily, as Figure 5 shown, the first auxiliary layer 205 in the groove 203a is removed through an etching process to form a first opening 206.

[0091] In a possible implementation, when removing the first auxiliary layer in the groove through an etching process, the first auxiliary layer and the substrate have a high selectivity ratio.

[0092] Step S106: Forming a second metal layer on the second surface of the substrate and making the second metal layer fill the first opening.

[0093] Exemplarily, as Figure 6 shown, a second metal layer 209 is formed on the back side 201B' of the substrate 201' and the second metal layer 209 is made to fill the first opening 206.

[0094] In a possible implementation, the second metal layer and the first metal layer have the same or different materials.

[0095] In a possible implementation, the first coefficient of thermal expansion of the second metal layer is less than the second coefficient of thermal expansion of the first metal layer.

[0096] In a possible implementation, the materials of the second metal layer and the first metal layer are copper; after depositing the second metal layer on the second dielectric layer, the method further includes:

[0097] Annealing the second metal layer.

[0098] In a possible implementation, the material of the second metal layer is copper; after depositing the second metal layer on the second dielectric layer, the second metal layer is annealed.

[0099] In a possible implementation, there are multiple trenches, and the second metal layer extends to cover each trench.

[0100] Through Figure 1 The method shown fills the first auxiliary layer at the bottom of the trench first after forming the trench. Since the depths of the trenches are not completely consistent, when the substrate is thinned on the second surface of the substrate later until the first auxiliary layer is exposed, it will not cause cracks in the substrate due to grinding the substrate and the first metal layer at the same time, and can prevent copper from contaminating the surface of the adjacent silicon layer or the cracks, thereby improving the yield of TSV production.

[0101] In another alternative embodiment of the present application, as Figure 7 shown, a semiconductor device manufacturing method includes the following process steps:

[0102] Step S701, providing a semiconductor substrate.

[0103] Among them, the semiconductor substrate includes a substrate and a first dielectric layer on the front surface of the substrate; trenches are provided on the semiconductor substrate; the trenches penetrate the first dielectric layer and do not extend to the back surface of the substrate.

[0104] Step S702, patterning the first dielectric layer to form trenches extending along the substrate in the substrate.

[0105] Step S703, sequentially forming a dielectric layer and a first barrier layer on the inner wall of the trench.

[0106] Among them, the materials of the dielectric layer and the first auxiliary layer may be the same or different.

[0107] Specifically, a dielectric layer and a first barrier layer are sequentially deposited on the inner wall of the trench.

[0108] Exemplarily, as Figure 8 shown, a dielectric layer 210 and a first barrier layer 211 are sequentially formed on the inner wall of the trench 203a.

[0109] In a possible implementation, the first dielectric layer and the dielectric layer are made of the same material, and the first barrier layer and the second barrier layer are made of the same material.

[0110] In a possible implementation, the material of the dielectric layer is silicon nitride; the material of the first barrier layer is titanium nitride.

[0111] Step S704: Form a first auxiliary layer and a first metal layer in each trench in sequence, where the first metal layer is located on the side of the first auxiliary layer facing the first dielectric layer.

[0112] Among them, the material of the first auxiliary layer has less ductility than the material of the first metal layer.

[0113] Step S705: Thin the substrate on the second surface of the substrate until the first auxiliary layer is exposed.

[0114] Step S706: Remove the first auxiliary layer to form a first opening.

[0115] Step S707: Form a second dielectric layer on the second surface of the substrate. The second dielectric layer has a second opening, and the second opening exposes the first opening.

[0116] Specifically, form a second dielectric layer on the back surface of the thinned substrate, and form a second opening in the second dielectric layer.

[0117] Among them, the second opening exposes the first opening.

[0118] Exemplarily, as Figure 9 shown, form a second dielectric layer 207 on the back surface 201B' of the thinned substrate 201', and form a second opening 208 in the second dielectric layer 207. Among them, the second opening 208 exposes the first opening 206.

[0119] In a possible implementation, in addition to forming a second dielectric layer on the back surface of the thinned substrate and forming a second opening in the second dielectric layer, a second barrier layer is also formed on the inner wall of the second opening.

[0120] Among them, the second barrier layer is connected to the first barrier layer.

[0121] Step S708: Form a second metal layer on the side of the second dielectric layer away from the back surface of the thinned substrate, and make the second metal layer fill the first opening and the second opening.

[0122] Step S709: Etch and remove the dielectric layer to form an air gap structure.

[0123] Specifically, etch off the dielectric layer in each trench to form an air gap structure. Among them, the air gap structure is the gap between the first barrier layer and the inner wall of the trench.

[0124] Exemplarily, as Figure 10 shown, the dielectric layer is etched away in each trench to form an air gap structure 212. The air gap structure 212 is a gap located between the first barrier layer 211 and the inner wall of the trench 203a.

[0125] In a possible implementation manner, after forming the air gap structure, the method further includes:

[0126] Annealing the second metal layer.

[0127] Figure 7 The manufacturing method of the semiconductor device shown includes sequentially forming a dielectric layer and a first barrier layer on the inner wall of the trench; etching away the dielectric layer in each trench to form an air gap structure; the air gap structure is a gap located between the first barrier layer and the inner wall of the trench. By providing the dielectric layer, the method can form an air gap structure, which provides a gap between the substrate and the conductive metal layer in the barrier layer, and can reduce the thermal stress caused by the mismatch of the thermal expansion coefficients between the substrate and the conductive metal layer in the barrier layer. At the same time, the first barrier layer can also provide a buffering barrier during polishing for the substrate, reduce the probability of cracks in the silicon layer, and prevent copper from contaminating the surface or cracks of the adjacent silicon layer, further improving the yield of TSV manufacturing.

[0128] In another embodiment, etching away the dielectric layer to form an air gap structure is specifically implemented by the following method:

[0129] Etching away the first dielectric layer and the dielectric layer in the trench;

[0130] Rapidly depositing a third dielectric layer on the first surface of the substrate to form an air gap structure in the trench.

[0131] In another embodiment, the third dielectric layer covers the sidewalls of the first metal layer on the first surface and exposes the top surface of the first metal layer.

[0132] Exemplarily, as Figure 11 shown, etching away the dielectric layer to form an air gap structure is specifically implemented by the following method: etching away the first dielectric layer 202 and the dielectric layer 210 in the trench 203a;

[0133] Rapidly depositing a third dielectric layer 213 on the front surface 201F' of the thinned substrate 201' to form an air gap structure 212 in the trench 203a.

[0134] Among them, the third dielectric layer 213 covers the sidewalls of the first metal layer 204 on the front surface 201F' of the thinned substrate 201' and exposes the top surface of the first metal layer 204.

[0135] Based on the same inventive concept, the present application provides a semiconductor device 300, asFigure 6 As shown, it includes:

[0136] A substrate 201', which has a front side 201F' and a back side 201B';

[0137] A first dielectric layer 202, which is located on the side of the front side 201F' of the substrate 201';

[0138] A trench 203a, which is formed in the first dielectric layer 202 and penetrates the substrate 201'. A metal layer is formed in the trench 203a. The metal layer includes a first metal layer 204 and a second metal layer 206 formed on the first metal layer 204. The first metal layer 204 fills the first end of the trench 203a close to the first dielectric layer 202. The second metal layer 206 fills the second end of the trench 203a away from the first dielectric layer 202. The first metal layer 204 has a first height, and the second metal layer 206 has a second height, and the first height is greater than the second height.

[0139] In a possible implementation manner, as Figure 10 shown, a first barrier layer 211 is further included in the trench 203a. The first barrier layer 211 is formed between the trench 203a and the metal layer. The metal layer includes a first metal layer 204 and a second metal layer 206 formed on the first metal layer 204. It can be understood that the first barrier layer 211 may only contact a part of the metal layer, such as the first metal layer 204.

[0140] In a possible implementation manner, an air gap structure 212 is further included in the trench 203a. The air gap structure 212 is formed between the trench 203a and the metal layer, as Figure 10 shown.

[0141] In a possible implementation manner, a second dielectric layer 207 is further included. The second dielectric layer 207 is formed on the back side 201B' of the substrate 201', and the second dielectric layer 207 has an opening exposing the trench 203a. The second metal layer 207 is simultaneously formed in the opening, as Figure 10 shown.

[0142] Obviously, those skilled in the art can make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalent technologies, this application is also intended to include these changes and modifications.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Comprising: Providing a semiconductor substrate, on which a first dielectric layer is formed on a first surface of the substrate; Patterning the first dielectric layer to form a trench extending along the substrate in the substrate; Sequentially forming a first auxiliary layer and a first metal layer in the trench, with the first metal layer located on a side of the first auxiliary layer facing the first dielectric layer; Thinning the substrate on a second surface of the substrate until the first auxiliary layer is exposed; Removing the first auxiliary layer to form a first opening; Forming a second metal layer on the second surface of the substrate and causing the second metal layer to fill the first opening; Wherein, before sequentially forming the first auxiliary layer and the first metal layer in the trench, the method further comprises: Sequentially forming a dielectric layer and a first barrier layer on an inner wall of the trench; Wherein, after removing the first auxiliary layer to form the first opening and before forming the second metal layer, a second dielectric layer is formed on the second surface of the substrate, and the second dielectric layer has a second opening exposing the first opening; Wherein, after forming the second metal layer, the method further comprises: Etching away the dielectric layer to form an air gap structure; the air gap structure is a void between the first barrier layer and an inner wall of the trench; Wherein, etching away the dielectric layer to form the air gap structure includes: Etching away the first dielectric layer and the dielectric layer in the trench; Rapidly depositing a third dielectric layer on the first surface of the substrate to form the air gap structure in the trench.

2. The method according to claim 1, wherein The dielectric layer and the first auxiliary layer may have the same or different materials.

3. The method according to claim 1, wherein The second metal layer is simultaneously formed in the second opening, and a second barrier layer is formed on a side wall of the second dielectric layer before the second metal layer is formed in the second opening.

4. The method according to claim 1, wherein The third dielectric layer covers a side wall of the first metal layer on the first surface and exposes a top surface of the first metal layer.

5. The method according to claim 3, characterized in that, The first dielectric layer and the dielectric layer have the same material, and the first barrier layer and the second barrier layer have the same material.

6. The method according to claim 1, characterized in that The second metal layer and the first metal layer may have the same or different materials.

7. The method according to claim 3, wherein The second metal layer and the first metal layer are made of copper; after depositing the second metal layer on the second dielectric layer, the method further comprises: Annealing the second metal layer.

8. The method according to claim 1, wherein After forming the air gap structure, the method further comprises: Annealing the second metal layer.

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