3D memory device and method of manufacturing the same

Abstract

Disclosed are a 3D memory device and a preparation method thereof, comprising: forming an insulating layer structure with multiple steps, the insulating layer structure comprising alternately stacked sacrificial layers and interlayer insulating layers, the top surface of each step being the interlayer insulating layer; removing at least a portion of the interlayer insulating layer exposed on the top surface of the step to expose the sacrificial layer in the step; disconnecting the exposed sacrificial layer in the same layer from the unexposed sacrificial layer to form a barrier; forming a dielectric layer covering the steps; replacing the sacrificial layer with a gate conductor layer to form a gate stack structure; and forming a conductive channel on the step in communication with the gate conductor layer, the conductive channel passing through the interlayer insulating layer on the corresponding gate conductor layer and the barrier. The present disclosure uses the insulating layer structure as an etching stop layer, reduces the difficulty of etching, and improves the reliability of the device.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and in particular, to a 3D memory device and a preparation method thereof. BACKGROUND

[0002] The improvement of the storage density of a memory device is closely related to the progress of semiconductor manufacturing process. As the feature size of semiconductor manufacturing process becomes smaller and smaller, the storage density of a memory device becomes higher and higher. In order to further improve the storage density, a memory device with a three-dimensional structure (i.e., a 3D memory device) has been developed.

[0003] The 3D memory device includes a stack structure formed by alternately stacking gate layers and interlayer insulating layers, wherein an electrically conductive channel is located at a step region of the stack structure to achieve electrical connection between an external circuit and the gate. In the actual preparation process of the three-dimensional memory, in order to achieve electrical connection between the electrically conductive channel and the gate layer in the stack structure, a contact hole is etched in a dielectric layer covering the stack structure to expose the top surface of each gate layer in the step region, and then a conductive material is filled in the contact hole to form the electrically conductive channel.

[0004] However, as the integration level of the three-dimensional memory increases and the number of stacked layers increases, the thickness of each gate layer and interlayer insulating layer becomes thinner, and thus the gate layer is easily broken during the formation of the contact hole. SUMMARY

[0005] In view of the above problems, the purpose of the present disclosure is to provide a 3D memory device and a preparation method thereof, which uses an insulating stack structure as an etching stop layer to reduce the difficulty of etching and improve the reliability of the device.

[0006] A first aspect of the present disclosure provides a preparation method of a 3D memory device, comprising:

[0007] forming an insulating stack structure having a plurality of steps, the insulating stack structure comprising alternately stacked sacrificial layers and interlayer insulating layers, the top surface of each step being the interlayer insulating layer;

[0008] removing at least a portion of the interlayer insulating layer exposed at the top surface of the step to expose the sacrificial layer in the step;

[0009] disconnecting the exposed sacrificial layer and the unexposed sacrificial layer in the same layer to form a barrier portion;

[0010] forming a dielectric layer covering the step;

[0011] replacing the sacrificial layer with a gate conductor layer to form a gate stack structure;

[0012] forming a conductive channel on the step in communication with the gate conductor layer, the conductive channel penetrating the interlayer insulating layer and the barrier portion on the corresponding gate conductor layer.

[0013] In some embodiments, each step comprises one or more sets of stacked sacrificial layers and interlayer insulating layers.

[0014] In some embodiments, the step of disconnecting the exposed portion of the sacrificial layer on the top surface of the step from the portion of the sacrificial layer covered by the upper step at the sidewall of the upper step comprises:

[0015] forming a lithographic mask on the step;

[0016] etching the sacrificial layer exposed on the top surface of the step at the sidewall of the upper step.

[0017] In some embodiments, the exposed sacrificial layer on the top surface of the step is etched using an anisotropic etch.

[0018] In some embodiments, the portion of the sacrificial layer that is preserved as the barrier portion when the subsequent sacrificial layer is replaced by a gate conductor serves as a stop layer for the conductive channel.

[0019] In some embodiments, the exposed sacrificial layer and the unexposed sacrificial layer in the same layer are disconnected at the step sidewall of the upper step.

[0020] In some embodiments, the exposed sacrificial layer and the unexposed sacrificial layer in the same layer are disconnected at a distance greater than 15 nm.

[0021] In some embodiments, the step of forming the conductive channel comprises:

[0022] forming a first trench through the dielectric layer with the barrier portion on the step as a stop layer;

[0023] etching the barrier portion and the interlayer insulating layer at the bottom of the first trench so that the first trench penetrates to the corresponding gate conductor layer; and

[0024] filling the first trench with a conductive material in contact with the gate conductor layer.

[0025] In some embodiments, the dielectric layer fills the space between the barrier portion and the sidewall of the step.

[0026] A second aspect of the present disclosure provides a 3D memory device, comprising:

[0027] a gate stack structure comprising alternately stacked gate conductor layers and interlayer insulating layers, the gate stack structure having a plurality of steps, the top surface of each of the steps being an interlayer insulating layer;

[0028] a barrier portion on the step;

[0029] a dielectric layer on the barrier portion and covering the gate stack structure;

[0030] a conductive channel through the dielectric layer, the barrier portion, and the interlayer dielectric layer on the step top surface to the gate conductor layer under the interlayer dielectric layer on the step top surface.

[0031] In some embodiments, each of the steps includes one or more sets of the gate conductor layer and the interlayer dielectric layer stacked.

[0032] In some embodiments, the dielectric layer fills the space between the barrier layer and the step sidewall above the step.

[0033] In some embodiments, the barrier portion has a groove between the barrier portion and the step sidewall of the upper step.

[0034] In some embodiments, the width of the groove between the barrier portion and the step sidewall of the upper step is greater than 15 nm.

[0035] The third aspect of the present application provides a storage system including the 3D memory device described above.

[0036] In the present embodiment, the exposed sacrificial layer and the unexposed sacrificial layer in the same layer are disconnected to form a barrier portion, and the barrier portion is separated from the sacrificial layer in the same layer to serve as an etching stop layer for forming a contact hole later.

[0037] Further, since the sacrificial layer of each step and the sacrificial layer of the adjacent step are separated by the intermediate insulating layer, no contact is generated. In the present embodiment, the barrier portion is used as the etching stop layer, avoiding the adhesion between the etching stop layers (i.e. the barrier portions) of the adjacent steps, and further avoiding the leakage of the 3D memory device.

[0038] Further, the thickness of the sacrificial layer at the sidewall of the upper step is relatively thin compared to the thickness of the entire step, overcoming the problem of etching blockage caused by the excessive thickness of the stop layer at the sidewall of the step, reducing the difficulty of etching, and improving the reliability of the device. At the same time, since the stop layer is formed using the already formed stacked structure, the additional step of forming the stop layer is saved. BRIEF DESCRIPTION OF DRAWINGS

[0039] The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure taken in conjunction with the accompanying drawings, in which:

[0040] Figure 1 a and 1bA circuit diagram and a structural schematic diagram of a memory cell string of a 3D memory device are shown, respectively;

[0041] Figure 2 A perspective view of a 3D memory device is shown;

[0042] Figures 3a to 3c Structural diagrams of various stages of a 3D memory device manufacturing method of the first embodiment of the present disclosure are shown;

[0043] Figure 4 A perspective view of a 3D memory device of the second embodiment of the present invention is shown;

[0044] Figures 5a to 11a Perspective views of various stages in a 3D memory device manufacturing process of the first embodiment of the present disclosure are shown;

[0045] Figures 5b to 11b Cross-sectional views of various stages in a 3D memory device manufacturing process of the first embodiment of the present disclosure are shown;

[0046] Figure 12 A perspective view of a 3D memory device of the third embodiment of the present disclosure is shown;

[0047] Figures 13a-17a Perspective views of various stages in a 3D memory device manufacturing process of the third embodiment of the present disclosure are shown;

[0048] Figures 13b to 17b Cross-sectional views of various stages in a 3D memory device manufacturing process of the third embodiment of the present disclosure are shown. DETAILED DESCRIPTION

[0049] The present disclosure will be described in greater detail by referring to the drawings, which are appended hereto. Like numerals refer to like elements throughout the several views. Each portion of the drawings is not drawn to scale for the sake of clarity. Also, certain known elements can not be shown in some of the figures. For the sake of brevity, a semiconductor structure obtained after a number of steps can be described in one figure.

[0050] It should be understood that when a layer, a region, or an element is referred to as being "on" or "above" another layer, another region, or another element, it can be directly on the other layer, region, or element or intervening layers or regions can also be present. In addition, when an element is referred to as being "below" or "under" another element, it can be directly on the other element, or intervening elements can also be present.

[0051] If for the sake of description, a layer, a region, or an element is referred to as being "directly on" or "directly above" another layer, another region, or another element, it is intended to mean that there are no intervening layers or regions present.

[0052] In this application, the term "semiconductor structure" refers to a collective term for the entire semiconductor structure formed in various steps of fabricating a memory device, including all layers or regions that have been formed. Many specific details of the present disclosure are described below, such as the structure, materials, dimensions, processing steps and techniques of the device, in order to provide a more thorough understanding of the present disclosure. But as those skilled in the art will appreciate, the present disclosure can be implemented without these specific details.

[0053] The present disclosure can be presented in various forms, some examples of which will be described below.

[0054] Figure 1 a and 1b respectively show a circuit diagram and a structural schematic diagram of a memory cell string of a 3D memory device. The memory cell string shown in this embodiment includes the case of 4 memory cells. It can be understood that the present disclosure is not limited thereto, and the number of memory cells in the memory cell string can be any number, for example, 32 or 64.

[0055] As shown in Figure 1 a , a first end of the memory cell string 100 is connected to a bit line BL, and a second end is connected to a source line SL. The memory cell string 100 includes a plurality of transistors connected in series between the first end and the second end, including: a first select transistor Q1, memory transistors M1 to M4, and a second select transistor Q2. The gate of the first select transistor Q1 is connected to a string select line SSL, and the gate of the second select transistor Q2 is connected to a ground select line GSL. The gates of the memory transistors M1 to M4 are respectively connected to corresponding word lines of the word lines WL1 to WL4.

[0056] As shown in Figure 1 b , the first select transistor Q1 and the second select transistor Q2 of the memory cell string 100 respectively include gate conductor layers 122 and 123, and the memory transistors M1 to M4 respectively include gate conductor layers 121. The gate conductor layers 121, 122 and 123 are consistent with the stacking order of the transistors in the memory cell string 100, and adjacent gate conductors are separated from each other by an interlayer insulating layer, thereby forming a gate stack structure. Further, the memory cell string 100 includes a channel pillar 110. The channel pillar 110 penetrates the gate stack structure. In the middle part of the channel pillar 110, the gate conductor layer 121 is sandwiched between the channel layer 111 and the tunneling dielectric layer 112, the charge storage layer 113 and the blocking dielectric layer 114, thereby forming the memory transistors M1 to M4. At both ends of the channel pillar 110, the gate conductor layers 122 and 123 are sandwiched between the channel layer 111 and the blocking dielectric layer 114, thereby forming the first select transistor Q1 and the second select transistor Q2.

[0057] In this embodiment, the channel layer 111 is composed of doped polysilicon, the tunneling dielectric layer 112 and the blocking dielectric layer 114 are composed of oxide, such as silicon oxide, and the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals, such as silicon nitride containing metal or semiconductor particles. The gate conductor layers 121, 122 and 123 are composed of metal, such as tungsten. The channel layer 111 is used to provide the channel region of the select transistors and the storage transistors, and the channel layer 111 is doped with the same type of doping as the select transistors and the storage transistors. For example, for N-type select transistors and storage transistors, the channel layer 111 can be N-type doped polysilicon.

[0058] In this embodiment, the core of the channel pillar 110 is the channel layer 111, and the tunneling dielectric layer 112, the charge storage layer 113 and the blocking dielectric layer 114 form a stack structure around the sidewall of the core. In an alternative embodiment, the core of the channel pillar 110 is an additional insulating layer, and the channel layer 111, the tunneling dielectric layer 112, the charge storage layer 113 and the blocking dielectric layer 114 form a stack structure around the core.

[0059] In this embodiment, the first select transistor Ql and the second select transistor Q2, and the storage transistors Ml to M4 use a common channel layer 111 and a common blocking dielectric layer 114. In the channel pillar 110, the channel layer 111 provides the source / drain regions and the channel layer of the plurality of transistors. In an alternative embodiment, the epitaxial layer and the blocking dielectric layer of the first select transistor Ql and the second select transistor Q2, and the epitaxial layer and the blocking dielectric layer of the storage transistors Ml to M4 can be formed in separate steps.

[0060] In a write operation, the memory cell string 100 uses the FN tunneling efficiency to write data into a selected storage transistor among the storage transistors Ml to M4. Taking the storage transistor M2 as an example, while the source line SL is grounded, the ground select line GSL is biased to about zero volts, so that the select transistor Q2 corresponding to the ground select line GSL is turned off, and the string select line SSL is biased to a high voltage VDD, so that the select transistor Ql corresponding to the string select line SSL is turned on. Further, the bit line BIT2 is grounded, and the word line WL2 is biased to a programming voltage VPG, such as about 20V, and the remaining word lines are biased to a low voltage VPSl. Since only the word line of the selected storage transistor M2 is higher than the tunneling voltage, the electrons in the channel region of the storage transistor M2 reach the charge storage layer 113 via the tunneling dielectric layer 112, thereby converting the data into charges stored in the charge storage layer 113 of the storage transistor M2.

[0061] During the read operation, the memory cell string 100 determines the amount of charge in the charge storage layer based on the conduction state of selected memory transistors M1 to M4, thereby obtaining the data represented by that charge amount. Taking memory transistor M2 as an example, word line WL2 is biased at the read voltage VRD, while the other word lines are biased at a high voltage VPS2. The conduction state of memory transistor M2 is related to its threshold voltage, i.e., related to the amount of charge in the charge storage layer, thus the data value can be determined based on the conduction state of memory transistor M2. Memory transistors M1, M3, and M4 are always in the conduction state; therefore, the conduction state of memory cell string 100 depends on the conduction state of memory transistor M2. The control circuit determines the conduction state of memory transistor M2 based on the electrical signals detected on bit line BL and source line SL, thereby obtaining the data stored in memory transistor M2.

[0062] Figure 2 A perspective view of the 3D storage device is shown. For clarity, [the view is shown in the original text]. Figure 2 The individual insulating layers in the 3D storage device are not shown.

[0063] The 3D storage device 200 shown in this embodiment includes 16 4x4 storage cell strings 100, each storage cell string 100 including 4 storage cells, thereby forming a 4x4x4 storage cell array with a total of 64 storage cells. It is understood that this disclosure is not limited thereto; the 3D storage device may include any number of storage cell strings, for example, 1024, and the number of storage cells in each storage cell string may be any number, for example, 32 or 64.

[0064] In the 3D memory device 200, each memory cell string includes its own channel pillar 110 and a common gate conductor layer 121, 122, and 123. The gate conductor layers 121, 122, and 123 are arranged in the same stacking order as the transistors in the memory cell string 100. Adjacent gate conductor layers are separated from each other by an interlayer insulating layer, thereby forming a gate conductor 120 of a gate stack structure. The interlayer insulating layer is not shown in the figure.

[0065] The internal structure of the channel column 110 is as follows Figure 1 b As shown, further details will not be provided here. In the middle portion of the channel pillar 110, the gate conductor layer 121, together with the channel layer 111, tunneling dielectric layer 112, charge storage layer 113, and barrier dielectric layer 114 inside the channel pillar 110, forms storage transistors M1 to M4. At both ends of the channel pillar 110, the gate conductor layers 122 and 123, together with the channel layer 111 and barrier dielectric layer 114 inside the channel pillar 110, form selection transistors Q1 and Q2.

[0066] The channel pillars 110 penetrate the gate conductor 120 and are arranged in an array, the first ends of the channel pillars 110 in the same column are commonly connected to the same bit line (i.e. one of the bit lines BL1 to BL4), and the second ends are commonly connected to the substrate 101, and the second ends form a common source connection via the substrate 100.

[0067] The gate conductor layer 122 of the string selection transistor Q1 is divided into different gate lines by gate line slits. The gate lines of the channel pillars 110 in the same row are commonly connected to the same string selection line (i.e. one of the string selection lines SSL1 to SSL4).

[0068] The gate conductor layers 121 of the storage transistors M1 and M4 are connected in one body at different levels. If the gate conductor layers 121 of the storage transistors M1 and M4 are divided into different gate lines by gate line slits, the gate lines at the same level are interconnected via the respective conductive channels 131 to the interconnection layer 132, and then connected to the same word line (i.e. one of the word lines WL1 to WL4) via the conductive channels 133.

[0069] The gate conductors of the ground selection transistor Q2 are connected in one body. If the gate conductor layer 123 of the ground selection transistor Q2 is divided into different gate lines by gate line slits, the gate lines are interconnected via the respective conductive channels 131 to the interconnection layer 132, and then connected to the same ground selection line GSL via the conductive channels 133.

[0070] As shown in Figure 2 The 3D memory device 200 includes a core region CT and a step region SS adjacent to both sides of the core region CT, wherein the step region SS is formed with a plurality of steps. The core region CT is used to form memory cell strings for storing information; the conductive channels 131 of the word lines are formed in the step region SS and used to transmit control information to the core region CT to realize reading and writing of information in the core region CT.

[0071] Generally, a contact hole needs to be formed in the step region to form the conductive channels 131 in the contact hole; however, as the integration level of the 3D memory increases and the number of stacked layers increases, the thickness of each gate layer and the interlayer insulating layer becomes thinner, and thus the gate layer is easily broken during the formation of the contact hole. In order to reduce the risk of breaking the contact hole, a stop layer is generally formed on the top surface and the sidewall of each step.

[0072] Figures 3a to 3c Structural diagrams showing various stages of the manufacturing method of the 3D memory device are shown, and the cross-sectional view can be taken along the AA line in Figure 2

[0073] As shown in Figure 3a ​As shown in FIG. 1, a stack structure 150 is formed on the substrate 101, the stack structure 150 includes alternately stacked sacrificial layers 152 and interlayer insulating layers 151. The stack structure 150 is etched to form steps 153 in a step region SS of the device. The step region SS includes a plurality of steps 153, each of the steps 153 is composed of an adjacent sacrificial layer 152 and an interlayer insulating layer 151. In the embodiment, in each of the steps 153, the sacrificial layer 152 is located above the interlayer insulating layer 151.

[0074] As shown in FIG. 2, a stop layer 170 is formed on the top surface and the sidewall of each of the steps 153. The stop layer 170 includes a first stop layer 171 covering the exposed part of the sacrificial layer 152 on the top surface of each of the steps 153, and a second stop layer 172 covering the sidewall of each of the steps 153 (i.e. the common sidewall of the sacrificial layer 152 and the interlayer insulating layer 151 exposed by the sidewall of each of the steps 153), wherein the first stop layer 171 and the second stop layer 172 are connected to form an integral whole. Figure 3b As shown in FIG. 3, the second stop layer 172 formed on the sidewall of the step is removed, so that the first stop layer 171 on the top surface of the adjacent steps is spaced apart from each other.

[0075] Figure 3c As shown in FIG. 4, the second stop layer 172 formed on the sidewall of the step is removed by forming an etching window on the surface of the second stop layer 172 above the sidewall of the step 153, and then etching the second stop layer 172.

[0076] In the embodiment, in order to reduce the risk of the contact hole being etched through, the stop layer 170 is formed on the top surface and the sidewall of each of the steps 153. In the complex step structure, the thickness of the stop layer 170 formed on the sidewall of the step 153 is too thick, and the etching window is too small, so that the first stop layer 171 is easily etched to be not transparent. As shown in FIG. 5, the first stop layer 171 is etched to be not transparent, so that the second stop layer 172 of the lower step 153 and the second stop layer 172 of the upper step 153 are connected together. In the subsequent process, the sacrificial layer 152 is replaced to form a gate conductor, and the adhesion between the second stop layers 172 of the different steps will cause the leakage of the 3D memory device.

[0077] Figure 3c As shown in FIG. 6, the first stop layer 171 is etched to be not transparent, so that the second stop layer 172 of the lower step 153 and the second stop layer 172 of the upper step 153 are connected together. In the subsequent process, the sacrificial layer 152 is replaced to form a gate conductor, and the adhesion between the second stop layers 172 of the different steps will cause the leakage of the 3D memory device.

[0078] Figure 4 As shown in FIG. 7, a 3D memory device of a second embodiment of the present application is shown in a perspective view. As shown in FIG. 8, the 3D memory device 300 includes a substrate 301 and a gate stack structure 320a located on the substrate 301, the gate stack structure 320a includes alternately stacked gate conductors 321, 322 and 323 and interlayer insulating layers 351. Figure 4 ​​​

[0079] A plurality of steps 353' are formed in the step region SS of the device, each step 353' being composed of adjacent gate conductors 321, 322 and 323 and an interlayer insulating layer 351 located above the gate conductors 321, 322 and 323. The gate conductors 321, 322 and 323 and the end of the interlayer insulating layer 351 in one step 353' are substantially flush.

[0080] The upper step face of each step 353' has a barrier portion 3522, which serves as an etching barrier for the contact hole 332, separated from the step sidewall of the step 353' in the layer above, i.e. has a groove 3523 between the step sidewall of the step 353' in the layer above. The width of the groove 3523 is greater than 15 nm.

[0081] The step region SS has a dielectric layer 360 above it, which covers at least the barrier portion 3522 above each step 353' and fills the groove 3523 between the barrier portion 3522 and the step sidewall of the step 353' in the layer above. The dielectric layer 360 has a flat surface.

[0082] The dielectric layer 360 has a plurality of contact holes 332 formed therein, each contact hole 332 extending from the flat surface of the dielectric layer 360 to the surface of the gate conductors 321, 322 and 323 in each step 353'. The contact holes 332 are filled with conductive material to form conductive channels 330, which are in contact with the gate conductors 321, 322 and 323 to form electrical connections.

[0083] Figures 5a to 11a The 3D memory device manufacturing process of the second embodiment of the present disclosure is shown in the perspective view of each stage; Figures 5b to 11b The cross-sectional views of each stage in the 3D memory device manufacturing process of the second embodiment of the present disclosure are shown, wherein 5b to Figure 11 b are respectively Figures 5a to 11a are respectively

[0084] The 3D memory device manufacturing method of the embodiments of the present disclosure will be described below in conjunction with Figures 5a to 11a and Figures 5b to 11b .

[0085] As Figure 5a and Figure 5bAs shown, a stack structure 350 is formed on the substrate 301, the stack structure 350 includes alternatingly stacked sacrificial layers 352 and interlayer insulating layers 351. The stack structure 350 is etched to form a plurality of bridge structures W in the step region SS, the plurality of bridges W divide the step region SS into a plurality of step sub-regions B, wherein each step sub-region B forms a plurality of steps 353, each step 353 is composed of an adjacent sacrificial layer 352 and an interlayer insulating layer 351 located above the sacrificial layer 352. The end of the sacrificial layer 352 and the end of the interlayer insulating layer 351 in one step 353 are substantially flush.

[0086] The material of the interlayer insulating layer 351 has a relatively high etching selectivity ratio with the material of the sacrificial layer 352, as described below, the sacrificial layer 352 will be replaced by a gate conductor. In this embodiment, the substrate 301 is, for example, a single crystal silicon substrate, the interlayer insulating layer 351 is, for example, composed of silicon oxide, and the sacrificial layer 352 is, for example, composed of silicon nitride. However, embodiments of the present disclosure are not limited thereto, and those skilled in the art can make other settings to the materials of the substrate 301, the interlayer insulating layer 351 and the sacrificial layer 352 as needed.

[0087] In this step, in the process of etching the stack structure 350 to form the steps 353, one more step 353 is formed, for example, the target number of steps is N, then N+1 steps are formed in this step.

[0088] As shown in Figure 6a and Figure 6b , at least a portion of the interlayer insulating layer 351 exposed on the top surface of the step 353 is removed.

[0089] In one embodiment of the present application, after forming the stepped steps as shown in Figure 5a and Figure 5b , at least a portion of the interlayer insulating layer 351 exposed on the top surface of the step is removed, for example, by wet etching or dry etching, to expose at least a portion of the underlying sacrificial layer 352. Further, a plurality of new steps 353' are obtained in the step region. Each of the new steps 353' includes a sacrificial layer 352 and an interlayer insulating layer 351 located below the sacrificial layer 352 and covered by the sacrificial layer 352, wherein the interlayer insulating layer 351 in each step is flush with the end of the sacrificial layer 352 in the step region. It can be understood that the step structure of the steps 353' formed in this step is different from the steps 353 formed in Figure 5a and Figure 5b .

[0090] As shown in Figure 7a and Figure 7bAs shown, the exposed part of the sacrificial layer 352 at the top surface of the step is disconnected from the part covered by the upper step, so that each layer of the sacrificial layer 352 except the top layer is divided into a sacrificial layer 3521 and a barrier part 3522, and a groove 3523 is formed between the sacrificial layer 3521 and the barrier part 3522. The sacrificial layer 3521 and the intermediate insulating layer 351 of the upper step form a step with the intermediate insulating layer on top and the sacrificial layer on bottom, and the sacrificial layer 3521 will be replaced by a gate conductor in the subsequent process; the barrier part 3522 is disconnected from the sacrificial layer 3521, and is retained as an etching stop layer during the replacement of the sacrificial layer 3521 by a gate conductor in the subsequent process.

[0091] In one specific embodiment, the width of the groove 3523 is greater than 15 nm.

[0092] In this step, a photoresist mask is formed on the surface of the semiconductor structure, and then anisotropic etching is performed to etch through each layer of the sacrificial layer 352 except the top layer.

[0093] The anisotropic etching can be dry etching, such as ion milling etching, plasma etching, reactive ion etching, laser ablation. For example, by controlling the etching time, the etching is stopped near the surface of the interlayer insulating layer 351. The photoresist mask is removed by dissolving or ashing in a solvent after etching.

[0094] In this step, since the thickness of each layer of the sacrificial layer 352 is much smaller than the thickness of the second stop layer 172 at the sidewall of the step in the prior art, it is easy to etch through, solving the problem of not etching through the second stop layer 172 at the sidewall of the step in the prior art, and avoiding the adhesion between the barrier part 3522 and the sacrificial layer of the current layer and adjacent layers, thereby avoiding the leakage of the 3D memory device.

[0095] In this embodiment, the barrier part 3522 is separated from the sacrificial layer 3521 of the same layer by the groove 3523, which is used as an etching stop layer for the subsequent formation of a contact hole; further, the sacrificial layer 352 in each step 353' and the sacrificial layer 352 in the adjacent step 353' are separated by the intermediate insulating layer 351, and there is no contact. Compared with the first stop layer 171 which is adhered together in the first embodiment, the barrier part 3522 is used as an etching stop layer in this embodiment, avoiding the adhesion between the etching stop layers (i.e. the barrier part 3522) between adjacent steps, thereby avoiding the leakage of the 3D memory device.

[0096] As shown in Figure 8a and Figure 8b A dielectric layer 360 is formed above the stack structure 350, and the sacrificial layer 3521 is replaced to form a gate stack structure 320a.

[0097] The medium layer 360 fills the recess 3523 between the sacrificial layer 3521 and the blocking portion 1522 in addition to filling above the step.

[0098] As an example, the medium layer 360 can be formed by deposition of an oxide, which can be selected from, for example, a silicon oxide based material. In one embodiment of the present application, the medium layer 360 can be formed by filling with silicon oxide. The medium layer 360 can be a multi-layer structure, in which a first sub-film layer with good step coverage is formed first, which can be, for example, silicon oxide (SiO2) deposited by high density plasma (HDP) or silicon oxide deposited by atomic layer deposition (ALD), etc.; and then a second sub-film layer with high filling efficiency is formed, which can be, for example, silicon oxide, etc. The density of the first sub-film layer is higher than that of the second sub-film layer, so that the first sub-film layer has good step coverage, and the second sub-film layer has high filling efficiency.

[0099] As an example, the medium layer 360 can be further planarized by a chemical mechanical polishing process or the like, so that the medium layer 360 provides a substantially planar upper surface for the step region SS of the stack structure 350.

[0100] Further, the plurality of channel pillars 310 extending through the gate stack structure 320a are formed, and the sacrificial layer 3521 is replaced to form the gate stack structure 320a.

[0101] Specifically, the plurality of channel pillars 310 extending through the stack structure 350 are formed in the stack structure 350. The specific structure of the channel pillars 310 can be found in the above description of the perspective view, and thus will not be described again here.

[0102] Next, a photoresist mask is formed, for example, on the surface of the semiconductor structure, and then anisotropic etching is performed to form a trench (not shown in the figure) in the stack structure 350 extending to the surface of the substrate 301 near the stack structure 350. The trench is, for example, located between two channel pillars 310.

[0103] Afterwards, the sacrificial layer 3521 in the stack structure 350 along the trench is removed by isotropic etching via the trench to form a cavity (not shown). The isotropic etching can be a selective wet etching or a gas phase etching. In the wet etching, an etching solution is used as the etchant, in which the semiconductor structure is immersed in the etching solution. In the gas phase etching, an etching gas is used as the etchant, in which the semiconductor structure is exposed to the etching gas. In the case that the interlayer insulating layer 351 and the sacrificial layer 3521 in the stack structure 350 are composed of silicon oxide and silicon nitride respectively, a phosphoric acid solution can be used as the etchant in the wet etching, and one or more of C4F8, C4F6, CH2F2 and O2 can be used as the etchant in the gas phase etching. Due to the selectivity of the etchant, the sacrificial layer 3521 is removed with respect to the interlayer insulating layer 351 in the stack structure 350. In some preferred embodiments, after the above-mentioned wet etching step, an additional etching step can be used to remove the etching product (e.g. silicon oxide) attached to the interlayer insulating layer 351, so that the exposed surface of the interlayer insulating layer 351 in the cavity is flat.

[0104] Then, after the above-mentioned wet etching step, a barrier layer (not shown) and a metal layer are sequentially formed on the exposed surface of the cavity along the trench by atomic layer deposition (ALD). The barrier layer is used to isolate the metal layer from the interlayer insulating layer 351 and the channel pillar 310 respectively. In this embodiment, the material of the barrier layer is a high dielectric metal compound, and the barrier layer includes, for example, aluminum trioxide. In this embodiment, the metal layer is composed of, for example, tungsten. The precursor gas used in the atomic layer deposition is, for example, tungsten hexafluoride WF6, and the reducing gas is, for example, silane SiH4 or diborane B2H6. In the step of atomic layer deposition, the deposition process is achieved by the chemical adsorption of the reaction product of tungsten hexafluoride WF6 and silane SiH4. The metal layer includes different layers, thereby forming the gate conductor layers 321, 322 and 323, and in the subsequent process, the gate conductor of each layer is separated into a plurality of gate lines by the gate line gaps. In some preferred embodiments, an adhesion layer (not shown) is further included between the barrier layer and the metal layer to isolate them, which is formed, for example, by atomic layer deposition (ALD) and is composed of, for example, silicide or nitride of titanium. The metal layer is formed on the surface of the adhesion layer, which can improve the chemical adsorption characteristics of the precursor gas on the surface during the atomic layer deposition and can improve the adhesion strength of the metal layer on the interlayer insulating layer 351.

[0105] Then, the gate line gaps (not shown) are formed in the trench. In this embodiment, the formation of the gate line gaps can be achieved by using general manufacturing processes, and thus will not be described in detail.

[0106] The gate conductors 321, 322 and 323 formed in this step are alternately stacked with the interlayer insulating layer 351, thereby forming a gate stack structure 320a. The gate conductor layers 321, 322 and 323 in the gate stack structure 320a replace the sacrificial layers 3521 in the stack structure 350.

[0107] As shown in Figure 9a and Figure 9b , a plurality of first trenches 330a are formed in the step region SS.

[0108] The blocking portions 3522 are used as stop layers, and the dielectric layer 360 along the step region SS is etched downward and through the dielectric layer 360 to form a plurality of first trenches 330a. At least one first trench 330a is formed on each step.

[0109] In this step, a photoresist mask is formed on the surface of the semiconductor structure, and then anisotropic etching is performed to penetrate the dielectric layer 360.

[0110] The anisotropic etching can use dry etching, such as ion milling etching, plasma etching, reactive ion etching, laser ablation. For example, by controlling the etching time, the etching is stopped near the surface of the blocking portion 3522. After etching, the photoresist mask is removed by dissolving in a solvent or ashing.

[0111] As shown in Figure 10a and Figure 10b , the blocking portion 3522 and part of the interlayer insulating layer 351 along the first trench 330a are removed to form a contact hole 330b.

[0112] The at least part of the blocking portion 3522 and the at least part of the interlayer insulating layer 351 at the bottom of the first trench 330a are selectively etched along the first trench 330a to obtain a contact hole 330b, which exposes at least part of the gate conductor.

[0113] As shown in Figure 11 a and Figure 11 b , the contact hole 330b is filled with conductive material to form a conductive channel 331, which is used to electrically connect the gate conductor layer and the external circuit, wherein the conductive material in the conductive channel 331 is in contact with the gate conductor.

[0114] Figure 12 A perspective view of a 3D memory device of a third embodiment of the present disclosure is shown, as shown in Figure 12 The 3D memory device includes a substrate 401 and a gate stack structure 420a on the substrate 401, and the gate stack structure 420a includes alternately stacked gate conductors 421, 422 and 423 and interlayer insulating layers 451.

[0115] A plurality of steps 453' are formed in the step region SS of the device, each step 453' is composed of adjacent gate conductors 421, 422 and 423 and the interlayer insulating layer 451 located above the gate conductors 421, 422 and 423. In this embodiment, each step 453' is composed of two layers of stacked gate conductors and interlayer insulating layers, and the gate conductors 421, 422 and 423 and the end of the interlayer insulating layer 451 in one step 453' are substantially flush.

[0116] Each step 453' has a blocking portion 4522' on the upper step surface, which serves as an etching blocking layer for the contact hole 432, and is separated from the step sidewall of the previous layer of steps 453', i.e. there is a groove 4523 between the step sidewall of the previous layer of steps 453' and the blocking portion 4522'. The width of the groove 4523 is greater than 15 nm.

[0117] The step region SS has a dielectric layer 460 above it, which covers at least the blocking portion 4522' above each layer of steps 453' and fills the groove 4523 between the blocking portion 4522' and the step sidewall of the previous layer of steps 453'. The dielectric layer 460 has a flat surface.

[0118] The dielectric layer 460 has a plurality of contact holes, each of which extends from the flat surface of the dielectric layer 460 to the surface of the gate conductors 421, 422 and 423 in each layer of steps 453', and the contact holes are filled with conductive material to form conductive channels 431, which are in contact with the gate conductors 421, 422 and 423 to form electrical connections.

[0119] Figures 13a-17a The 3D memory device manufacturing process of the second embodiment of the present disclosure is shown in the schematic diagram of the stereoscopic structure at each stage; Figures 13b to 17b The cross-sectional view of the 3D memory device manufacturing process of the second embodiment of the present disclosure is shown in the schematic diagram of the stereoscopic structure at each stage, wherein, Figures 13b to 17b Figures Figures 13a-17a Cross-sectional view along DD.

[0120] As Figure 13a and Figure 13bAs shown, a stacked structure 450 is formed on a substrate 401, the stacked structure 450 including alternately stacked sacrificial layers 452 and interlayer insulating layers 451. The stacked structure 450 is etched to form multiple bridge structures W in the step region SS. The multiple bridges W divide the step region SS into multiple step partitions B. Unlike the first embodiment, in this embodiment, each step partition B includes a main step 453a and a secondary step 453b. Both the main step 453a and the secondary step 453b include multiple steps 453. There is a height difference between the upper step surface of each step 453 in the main step 453a and the upper step surface of each step 453 in the secondary step 453b. In this embodiment, both the main step 453a and the secondary step 453b include two layers of stacked interlayer insulation layer and sacrificial layer. The upper step surface of each step 453 in the main step 453a and the upper step surface of each step 453 in the secondary step 453b are both interlayer insulation layers.

[0121] In this embodiment, the sub-step 453b is used as an example for explanation. Each step 453, for example from top to bottom, includes a first interlayer insulation layer 451', a first sacrificial layer 452', a second interlayer insulation layer 451'', and a second sacrificial layer 452''. The ends of the sacrificial layer and the interlayer insulation layer in a step 453 are substantially flush.

[0122] In this step, during the etching of the stacked structure 450 to form a step 453, one more step 453 is formed. For example, if the target number of steps is N, then N+1 steps are formed in this step.

[0123] like Figure 14a and Figure 14b As shown, after removing the portion of the first interlayer insulation layer 451' exposed on the top surface of the step, the portion on the top surface of the step after removing the first interlayer insulation layer 451' is the first sacrificial layer 452'. Multiple new steps 453' are obtained in the step area, and the steps 453', from top to bottom, are the first sacrificial layer 452', the second interlayer insulation layer 451'', the second sacrificial layer 452'', and the first interlayer insulation layer 451' of the lower step 453, and... Figure 13a and Figure 13b Compared to the step 453 formed in the previous step, the hierarchical structure of the step 453' formed in this step is different.

[0124] In this embodiment, the method for removing the portion of the first interlayer insulation layer 451' exposed on the top surface of the step is the same as in the first embodiment, and will not be described again here.

[0125] Further, the first sacrificial layer 452' is disconnected at the step top surface exposed part and the part covered by the upper layer step, forming the first sacrificial layer 4521' and the blocking part 4522', wherein the first sacrificial layer 4521' and the blocking part 4522' have a groove 4523 therebetween, and the width of the groove 4523 is greater than 15 nm.

[0126] It should be noted that in this embodiment, only the first sacrificial layer 452' exposed on the step surface is disconnected into the first sacrificial layer 4521' and the blocking part 4522', and the second sacrificial layer 452'' is not operated. Among them, the first sacrificial layer 4521' and the second sacrificial layer 452'' will be replaced into the gate conductor in the subsequent process; the blocking part 4522' is separated from the first sacrificial layer 4521', and is retained as an etching stop layer in the subsequent process of replacing the first sacrificial layer 4521' and the second sacrificial layer 452'' into the gate conductor.

[0127] In this step, the method of disconnecting the first sacrificial layer 452' at the step top surface exposed part and the part covered by the upper layer step is the same as that in the first embodiment.

[0128] As shown in Figure 15a and Figure 15b , a dielectric layer 460 is formed above the stack structure 450, the sacrificial layer 452 is replaced to form a gate stack structure 420a and a plurality of first trenches 430a in the step region SS. Among them, the blocking part 4522' is retained in the process of replacing the sacrificial layer 452.

[0129] The method of this step is the same as that in the first embodiment.

[0130] As shown in Figure 16a and Figure 16b , part of the blocking part 4522' and part of the interlayer insulating layer 451 are removed along the first trench 430a to form a contact hole 430b.

[0131] As shown in Figure 17a and Figure 17b , the contact hole 430b is filled with conductive material to form a conductive channel 431, which is used to electrically connect the gate conductor layer and the external circuit, wherein the conductive material in the conductive channel 431 is in contact with the gate conductor layer.

[0132] In this embodiment, the exposed sacrificial layer and the unexposed sacrificial layer in the same layer are disconnected to form a blocking part, which is separated from the sacrificial layer in the same layer and used as an etching stop layer for forming a contact hole in the subsequent process.

[0133] Further, since the sacrificial layer of each step and the sacrificial layer of the adjacent step are isolated by the intermediate insulating layer, no contact is generated, and the blocking part is used as the etching stop layer relative to the whole stop layer, thereby avoiding the adhesion between the etching stop layers (i.e. the blocking part 1522) between the adjacent steps, and further avoiding the leakage of the 3D memory device.

[0134] Further, the thickness of the sacrificial layer at the sidewall of the upper step is relatively thin relative to the thickness of the whole step, thereby overcoming the problem of etching blockage caused by the over-thick stop layer at the sidewall of the step, reducing the difficulty of etching, and improving the reliability of the device; meanwhile, since the stop layer is formed by using the already formed stacked structure, the step of forming the stop layer is saved

[0135] In the above description, the technical details of the patterning, etching, etc. of each layer are not described in detail. However, those skilled in the art should understand that the layers, regions, etc. with the required shape can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above in order to form the same structure. In addition, although each embodiment is described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

Claims

1. A method for fabricating a 3D storage device, comprising: An insulating laminate structure with multiple steps is formed, the insulating laminate structure comprising alternately stacked sacrificial layers and interlayer insulating layers, wherein the top surface of each step is the interlayer insulating layer; At least a portion of the interlayer insulation layer exposed on the top surface of the step is removed to expose the sacrificial layer in the step; The exposed sacrificial layer in the same layer is disconnected from the unexposed sacrificial layer to form a blocking portion; A medium layer is formed covering the steps; The unexposed sacrificial layer is replaced with a gate conductor layer to form a gate stack structure; A conductive channel communicating with the gate conductor layer is formed on the step, and the conductive channel passes through the interlayer insulating layer and the blocking portion on the corresponding gate conductor layer.

2. The method for fabricating a 3D storage device according to claim 1, wherein, Each step includes one or more stacked sacrificial layers and interlayer insulation layers.

3. The method for fabricating a 3D storage device according to claim 1, wherein, The steps of separating the portion of the sacrificial layer exposed at the top of the step from the portion covered by the upper step at the sidewall of the upper step include: A photomask is formed on the step; The sacrificial layer exposed on the top surface of the steps is etched into the side wall of the upper steps.

4. The method for fabricating a 3D storage device according to claim 3, wherein, The sacrificial layer exposed on the top surface of the step is revealed by anisotropic etching.

5. The method for fabricating a 3D storage device according to claim 1, wherein, When the sacrificial layer is subsequently replaced with a gate conductor, the portion of the sacrificial layer that is retained serves as the barrier portion, which in turn serves as the stop layer for the conductive channel.

6. The method for fabricating a 3D storage device according to claim 1, wherein, The exposed sacrificial layer and the unexposed sacrificial layer in the same layer are separated at the step sidewall of the upper step.

7. The method for fabricating a 3D storage device according to claim 1, wherein, The distance between the exposed sacrificial layer and the unexposed sacrificial layer in the same layer is greater than 15 nm.

8. The method for fabricating a 3D storage device according to claim 1, wherein, The steps for forming the conductive channel include: Using the blocking portion on the step as a stopping layer, a first trench is formed that penetrates the medium layer; The blocking portion at the bottom of the first trench and the interlayer insulating layer are etched to allow the first trench to penetrate to the corresponding gate conductor layer; and A conductive material is filled in contact with the gate conductor layer.

9. The method for fabricating a 3D storage device according to claim 1, wherein, The medium layer fills the space above the step and between the blocking part and the side wall of the step.

10. A 3D memory device formed by the fabrication method of any one of claims 1 to 9, comprising: A gate stack structure comprising alternating stacked gate conductor layers and interlayer insulating layers, the gate stack structure having multiple steps, the top surface of each step being an interlayer insulating layer; The blocking part is located on the step; A dielectric layer is located above the blocking portion and covers the gate stack structure; A conductive channel extends through the dielectric layer, the blocking portion, and the interlayer insulating layer located on the top surface of the step to the gate conductor layer located below the interlayer insulating layer on the top surface of the step.

11. The 3D storage device according to claim 10, wherein, Each step includes one or more stacked gate conductor layers and interlayer insulating layers.

12. The 3D storage device according to claim 10, wherein, The medium layer fills the space above the step and between the blocking part and the side wall of the step.

13. The 3D storage device according to claim 10, wherein, The blocking part has a groove between it and the side wall of the upper step.

14. The 3D storage device according to claim 13, wherein, The width of the groove between the blocking part and the side wall of the upper step is greater than 15nm.

15. A storage system comprising a 3D storage device formed by the method of fabricating a 3D storage device according to any one of claims 1 to 9.

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