A pulse collection and flexible pulse generation control circuit

Abstract

The present application relates to a kind of pulse collection and flexible generation pulse control circuit, comprising: pulse transceiver module, for collecting and outputting pulse signal;Hardware trigger module, for restoring pulse signal and at least one other module instantaneously start working by hardware trigger;Storage module, for storing pulse signal data;And central processing module;Pulse transceiver module can collect single first pulse signal or parallel multi-channel second pulse signal by input-output interface, and send several single third pulse signal or parallel multi-channel fourth pulse signal by input-output interface, wherein, several single third pulse signal or parallel multi-channel fourth pulse signal is restored by hardware trigger module or is formed by central processing module coding processing.This application can be used for dynamic acquisition pulse input, and output is formed by hardware to pulse restoration or by central processing unit coding any required pulse, also can output coded pulse according to preset delay.

Description

Technical Field

[0001] This invention relates to the field of pulse acquisition and output technology, and in particular to a control circuit for pulse acquisition and flexible pulse generation. Background Technology

[0002] Pulse techniques are the technologies for generating pulse signals and transforming waveforms. They are widely used in various fields such as electronic computers, communications, radar, television, automatic control, telemetry and remote control, radio navigation, and measurement technology, and have become an important component of various electronic systems.

[0003] The pulse signal acquisition design utilizes a monostable circuit built with discrete components. Pulse acquisition technology primarily uses a fast clock to acquire externally input signals via a general-purpose input / output interface (GPIO), and the pulse width is obtained by analyzing the timing of the edge signal changes. Pulse output refers to pulse output command detection, setting special memory bits for pulse output, and then activating the pulse operation defined by those special memory bits. The pulse output mode is mainly determined by the controller.

[0004] CN104467763A discloses a multi-output synchronous pulse control system, which consists of a control parameter processing unit, a pulse signal generation unit, an 8-channel pulse amplitude adjustment unit, and an 8-channel pulse output drive unit. The control parameter processing unit consists of a microcontroller, a keyboard, and a display screen. The microcontroller includes a network port, a RS-232 serial port, and an SPI interface. The microcontroller is connected to the pulse signal generation unit through a data bus and an address bus. The microcontroller is connected to the 8-channel pulse amplitude adjustment unit through the SPI interface. Each pulse amplitude adjustment unit is connected to a corresponding pulse output drive unit. The pulse signal generation unit uses an FPGA chip to implement the circuit structure. The internal logic control circuit of the FPGA includes a clock signal generation module and 8 pulse control channels.

[0005] CN112332810A discloses a multi-channel high-power synchronous pulse output device, including a device body; the device body includes a synchronous pulse main board; the synchronous pulse main board is provided with: a pulse signal input unit for connecting an external trigger pulse input signal source; a signal input preprocessing unit for preprocessing the external trigger pulse input signal; a CMOS synchronous driver for realizing the output of multiple pulse signals; a dynamic delay adjustment unit for dynamically adjusting the single delay of the multiple pulse signals output by the CMOS synchronous driver; a bias power output drive circuit for realizing high-power pulse drive; and a multi-channel high-power drive pulse output interface for outputting multiple high-power synchronous pulse signals to external industrial equipment.

[0006] CN112332810A discloses a multi-channel high-power synchronous pulse output device, including a synchronous pulse main board with a pulse signal input unit for connecting to an external trigger pulse input signal source; a signal input preprocessing unit electrically connected to the pulse signal input unit for preprocessing the external trigger pulse input signal; a CMOS synchronous driver electrically connected to the signal input preprocessing unit for outputting multiple pulse signals; a dynamic delay adjustment unit electrically connected to the CMOS synchronous driver for dynamically adjusting the single delay of the multiple pulse signals output by the CMOS synchronous driver; a bias power output drive circuit electrically connected to the dynamic delay adjustment unit for driving high-power pulses; and a multi-channel high-power drive pulse output interface electrically connected to the bias power output drive circuit for outputting multiple high-power synchronous pulse signals to external industrial equipment.

[0007] For pulse acquisition and output, existing technologies mainly use a single pulse acquisition module or a common pulse width modulation (PWM) module for output. There is no design that integrates a pulse acquisition module and a coded pulse output module. However, common PWM modules can only generate periodic reverse pulses and periodic pulses with dead time, and cannot perform arbitrarily coded pulse output, nor can they simulate other serial interface protocols, thus lacking flexibility. Secondly, the pulse acquisition and pulse generation modules cannot be linked, resulting in insufficient reusability, and the use of single software programming makes the triggering software interval uncertain. Therefore, existing technologies still have at least one or more technical problems that urgently need to be solved.

[0008] Furthermore, on the one hand, there are differences in understanding among those skilled in the art; on the other hand, the applicant studied a large number of documents and patents when making this invention, but due to space limitations, not all details and contents were listed in detail. However, this does not mean that the present invention does not possess the features of these prior art. On the contrary, the present invention already possesses all the features of the prior art, and the applicant reserves the right to add relevant prior art to the background art. Summary of the Invention

[0009] In view of the shortcomings of the prior art, the present invention provides a control circuit for pulse acquisition and flexible pulse generation, which aims to solve at least one or more technical problems existing in the prior art.

[0010] To achieve the above objectives, the present invention provides a control circuit for pulse acquisition and flexible pulse generation, comprising:

[0011] Pulse transceiver module, used to acquire and output pulse signals;

[0012] The hardware triggering module is used to restore the pulse signal and start working immediately via one or more of the hardware triggering pulse transceiver module, central processing unit module, and storage module;

[0013] Storage module, used to store pulse signal data; and

[0014] Central processing module;

[0015] Its features are,

[0016] The pulse transceiver module can acquire a single first pulse signal or multiple parallel second pulse signals through the input / output interface, and send several single third pulse signals or multiple parallel fourth pulse signals through the input / output interface.

[0017] Among them, several single-channel third pulse signals or parallel multi-channel fourth pulse signals are formed by hardware triggering module restoration processing or by central processing module encoding processing.

[0018] Preferably, the central processing module pre-configures a corresponding first working mode for the restoration processing of the hardware trigger module. In the first working mode,

[0019] When the first pulse transceiver submodule in the pulse transceiver module acquires at least one single-channel pulse signal, the hardware triggering module executes a first operation to trigger the timing task and a second operation to trigger at least one second pulse transceiver submodule to output the pulse signal when the timing task ends, according to the first working mode preset by the central processing module.

[0020] Preferably, the central processing module is pre-configured with a corresponding second operating mode for its encoding processing. In the second operating mode,

[0021] When the first pulse transceiver submodule in the pulse transceiver module acquires at least one single pulse signal, the central processing module encodes the pulse signal into a third pulse signal or multiple parallel fourth pulse signals. The hardware triggering module then executes a third operation to trigger the timing task and a fourth operation to trigger at least one second pulse transceiver submodule to output the pulse signal when the timing task ends, according to the second working mode preset by the central processing module.

[0022] Preferably, the first pulse transceiver submodule and the second pulse transceiver submodule of the pulse transceiver module are different channels from each other.

[0023] Preferably, the pulse signal acquisition and processing system of the present invention further includes a timer, which is used to perform timing tasks for the pulse signal acquisition and transmission process.

[0024] Preferably, the preset transmission delay corresponding to the timer executing the corresponding timing task is greater than the time required for the central processing module to encode the pulse signal data.

[0025] Preferably, when the first pulse transceiver submodule in the pulse transceiver module acquires at least one single-channel pulse signal, the pulse signal acquired by the pulse transceiver module is stored in the storage module.

[0026] Preferably, the pulse signal acquisition and processing system of the present invention further includes a direct storage accessor, which is used to control the reading and writing of pulse signal data by the storage module.

[0027] Preferably, the pulse transceiver module is configured with a period register or a threshold register to generate arbitrary pulse signals.

[0028] Preferably, the pulse transceiver module generates a specific pulse signal by: loading pre-made pulse signal data into the data register of the pulse transceiver module through a direct memory accessor, importing the pulse signal data in the data register into a period comparator and a threshold comparator respectively, and generating a specific pulse signal based on the period comparator and the threshold comparator.

[0029] This system can support hardware (hardware trigger module) to directly restore pulse data to the pulse output module, and it also supports the central processing module (CPU) to process the data through software encoding as needed, convert it into the configuration data required by the pulse output module, and then store it in a specific random access memory (RAM). This process can transfer the configuration data required by the pulse output module through the direct memory access (DMA) module.

[0030] The advantages of this invention are as follows: This invention supports both direct reconstruction of the original waveform via a hardware trigger module and software-based encoding and reconstruction of the acquired pulse signal. Direct hardware reconstruction ensures a fixed and low latency during pulse signal generation. Simultaneously, this system also supports hardware triggering, enabling the output of pulse signal data with a specific protocol, reconstructed by the central processing unit's software encoding, to a general-purpose input / output interface (GPIO) at a specific time point. Therefore, it possesses strong flexibility and can adapt to the generation requirements of any form of pulse signal. Furthermore, the pulse generation module for pulse signal acquisition and transmission in this invention has a high degree of integration, reducing the overall system setup cost and exhibiting excellent reusability and versatility. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the control circuit according to a preferred embodiment of the present invention.

[0032] List of reference numerals

[0033] 10: Central Processing Module; 20: Hardware Trigger Module; 30: Timer; 40: Pulse Transceiver Module; 50: Direct Memory Access Module; 60: Memory Module; 70: Bus. Detailed Implementation

[0034] The following is a detailed explanation with reference to the accompanying drawings.

[0035] This invention provides a control circuit for pulse acquisition and flexible pulse generation, which can be used to dynamically acquire pulse input and directly reconstruct the pulse through hardware or encode it into any desired pulse through central processing unit software for output. Specifically, in this invention, the pulse signal generated by the central processing unit software encoding can be output based on a preset delay.

[0036] Specifically, the present invention provides a control circuit for pulse acquisition and flexible pulse generation, such as... Figure 1 As shown, the control circuit may include a central processing module 10, a hardware trigger module 20, a timer 30, a pulse transceiver module 40, a direct memory accessor 50, and a storage module 60, all electrically connected to each other. The functional modules or hardware and software communicate with each other via a bus 70.

[0037] According to a preferred embodiment, the pulse transceiver module 40 can be used to acquire and transmit pulse signals via a general purpose input / output interface (GPIO). Specifically, the pulse transceiver module 40 can be configured to acquire only specific rising and falling edges for data processing and analysis based on different edge times.

[0038] According to a preferred embodiment, a pulse signal refers to an electrical signal wave (rectangular wave) with a certain width generated in a very short time. Pulse signals have various types. Specifically, a pulse that occurs only once during an event is called a single pulse, and a pulse that occurs repeatedly is called a continuous pulse. Single pulses can be used for pass detection, while continuous pulses can be used for motor speed acquisition.

[0039] According to a preferred embodiment, the time required for one round trip of the pulse signal is called the pulse period. The pulse frequency and the pulse period are inversely related. Typically, the pulse frequency is collected at high frequencies, and the pulse period is collected at low frequencies.

[0040] According to a preferred embodiment, the parameters involved in pulse acquisition include the sampling period and the input frequency bandwidth. Besides the frequency and period of the input pulse, the acquisition content for pulse signals typically includes pulse width, rise time, fall time, duty cycle, and phase difference width. In addition, the acquisition content also includes pulse input type and number of channels, resolution, minimum pulse width, acquisition range, and the range of countable acquisition pulses, among other things.

[0041] According to a preferred embodiment, the storage module 60 can be used to store pulse signal data.

[0042] According to a preferred embodiment, the direct storage access device 50 can be used to control the reading and writing of pulse signal data by the storage module 60. Specifically, the direct storage access device 50 allows direct reading and writing of pulse signal data between external devices and the storage module 60, without requiring the central processing module 10. In detail, the pulse signal data acquired by the pulse transceiver module 40 is temporarily stored at the direct storage access device 50, and then further transferred to the storage module 60 by the direct storage access device 50.

[0043] According to a preferred embodiment, each Direct Memory Access 50 (DMA) channel has its own specific hardware priority and different priority values, with smaller numbers indicating higher priority. When two or more channels are activated simultaneously, the DMA controller will provide services sequentially according to the channel priority order, and lower-priority channels can be interrupted by higher-priority channels during transmission.

[0044] According to a preferred embodiment, the hardware trigger module 20 can be used to receive hardware signals from other system modules, triggering the other modules to start working immediately, so as to ensure a fixed system delay. Furthermore, the hardware trigger module 20 can be driven by preset instructions to output pulse signal data through the pulse transceiver module 40 and output to the corresponding external device through a specific input / output interface.

[0045] According to a preferred embodiment, the hardware trigger module 20 (trigger) typically refers to a memory cell circuit that operates only when triggered by a clock signal. Specifically, practical digital systems often contain a large number of memory cells, and they are frequently required to operate synchronously at the same time. To achieve this, a clock pulse (CLK) is introduced as a control signal into each memory cell circuit. The circuit is triggered and operates only when the clock pulse (CLK) arrives, and changes its output state according to the input signal.

[0046] According to a preferred embodiment, the pulse transceiver module 40 outputs pulse signals through a specific input / output interface, which may include pulse width modulation (PWM) and pulse amplitude modulation (PAM) pulse signals. Specifically, pulse width modulation (PWM) refers to the method of controlling current and voltage by the pulse width (continuous output time) and interval (the interval between on and off). The ratio of the "pulse on time" in a certain period is called the duty cycle, and a suitable voltage can be obtained by changing the duty cycle. By shortening the on / off period, a voltage proportional to the on pulse width can be obtained. Pulse amplitude modulation (PAM) refers to the method of controlling current or voltage by the pulse intensity (amplitude).

[0047] According to a preferred embodiment, timer 30 can be used to perform timing tasks for the pulse signal acquisition and transmission process.

[0048] According to a preferred embodiment, the steps for acquiring and hardware-reproducing pulse signals using the pulse acquisition and flexible pulse generation control circuit provided by the present invention are as follows:

[0049] Step 1.1 Configure the general purpose input / output interface (GPIO) as the input of the pulse signal, configure one or more signal channels of the pulse transceiver module 40 to pulse acquisition mode, configure the corresponding register initial value, and enable the hardware trigger module 20 function.

[0050] Step 1.2 Configure the general purpose input / output interface (GPIO) as the output of pulse signals, configure one or more signal channels of the pulse transceiver module 40 to pulse generation mode, initialize the configuration register, and enable the direct memory accessor 50 function.

[0051] Step 1.3 Enable the pulse transceiver module 40 and wait for the pulse signal data from the direct storage accessor 50.

[0052] Step 1.4 Enable the pulse transceiver module 40. When the pulse signal has acquired the specified amount of data, the direct storage accessor 50 starts to transfer the pulse signal data. The pulse transceiver module 40 outputs the pulse waveform restored by the hardware trigger module 20 to the specified general purpose input / output interface (GPIO).

[0053] According to a preferred embodiment, a general purpose input / output interface (GPIO) is used for the input and output of electrical signals in a circuit to facilitate the control of circuit components.

[0054] According to a preferred embodiment, the signal channel that serves as the input of the pulse signal and the signal channel that serves as the output of the pulse signal are different signal channels from each other.

[0055] According to a preferred embodiment, the steps of acquiring and encoding a pulse signal and outputting it after a preset time delay using the pulse acquisition and flexible pulse generation control circuit provided by the present invention are as follows:

[0056] Step 2.1 Configure the general purpose input / output interface (GPIO) as the input of the pulse signal, configure one or more signal channels of the pulse transceiver module 40 to pulse acquisition mode, configure the corresponding register initial value, and enable the pulse transceiver module 40.

[0057] Step 2.2 Configure the hardware trigger module 20 to make the interrupt trigger timer 30 (TIMER) for pulse signal acquisition count. When the timer 30 (TIMER) counts to the specified time and generates an interrupt, the pulse transceiver module 40 is triggered.

[0058] Step 2.3 Configure the count value of Timer 30.

[0059] Step 2.4 Select the General Purpose Input / Output Interface (GPIO) as the output of the pulse signal, configure one or more signal channels of the pulse transceiver module 40 to pulse generation mode, configure the configuration register of the pulse transceiver module 40, and enable the Direct Memory Access (DMA) function of the direct memory accessor 50.

[0060] Step 2.5 The pulse transceiver module 40 starts to acquire pulse signal input, writes the acquired pulse signal data into the storage module 60 (RAM) through the direct memory accessor 50 (DMA), and generates an interrupt when the corresponding data amount is reached.

[0061] Step 2.6 The central processing module 10 reads the pulse signal data from the storage module 60 (RAM) and encodes the pulse signal data.

[0062] Step 2.7 Wait for the hardware trigger module 20 to trigger the pulse transceiver module 40, and start outputting the pulse signal encoded by the central processing module 10 through the pre-configured general-purpose input / output interface (GPIO).

[0063] According to a preferred embodiment, when the pulse signal data acquired by the pulse transceiver module 40 reaches a specified data amount and the acquisition operation is interrupted, the timer 30 (TIMER) starts counting. Further, during the counting process of the timer 30 (TIMER), the central processing module 10 reads the pulse signal data pre-stored in the storage module 60 via the direct memory accessor 50, and encodes the pulse signal data according to the pulse output requirements. When the timer 30 (TIMER) finishes counting, the hardware trigger module 20 is enabled to trigger the pulse transceiver module 40 to output a single or multiple pulse signals encoded by the central processing module 10 through a specified general purpose input / output interface (GPIO).

[0064] According to a preferred embodiment of the present invention, the count value configured for timer 30 should allow the central processing module 10 (CPU) sufficient time to encode the pulse signal to be output. Specifically, the pre-designed value of timer 30 is preferably greater than the time required for the central processing module 10 to encode the pulse signal data.

[0065] According to a preferred embodiment, in this invention, when acquiring pulse signals, any one or more pulse transceiver submodules (signal channels) of the pulse transceiver module 40 are configured to pulse acquisition mode, initial settings are configured (including initial values ​​of configuration registers), the signal edge to be acquired is determined, and a specific general-purpose input / output interface (GPIO) is selected as the input. Further, a pulse acquisition counter (TIMER) is started to enable pulse acquisition and monitor changes at the general-purpose input / output interface (GPIO).

[0066] According to a preferred embodiment, after a change in the pulse signal input channel is acquired, the pulse signal data is stored in a first-in-first-out (FIFO) queue. The FIFO depth is configurable. When the FIFO depth reaches a set value, the hardware trigger module 20 is enabled to output the acquired pulse signal data in a specific format to an external device through the pulse transceiver module 40, and the pulse signal data is stored in the storage module 60 through the direct storage accessor 50.

[0067] According to a preferred embodiment, the present invention can also notify the central processing module 10 by generating an interrupt, and the central processing module 10 re-encodes the pulse signal data in software and stores it in the storage module 60. Specifically, the present invention supports outputting a pulse signal after a specific time delay following pulse acquisition. Specifically, the hardware trigger module 20 is first configured, and the interrupt of pulse acquisition is set as the first trigger source. The enable of timer 30 (TIMER) is set as the first target task. The timer 30 (TIMER) is set to count to a specified time and generate an interrupt as the second trigger source, and the enable of pulse transceiver module 40 and direct memory accessor 50 are set as the second target tasks.

[0068] According to a preferred embodiment, the count value of timer 30 is configured, and the acquisition task of pulse transceiver module 40 is configured according to the aforementioned steps for acquiring pulse signals. Furthermore, the pulse generation task of pulse transceiver module 40 is configured according to the output of the desired pulse signal. Further, pulse transceiver module 40 is enabled, and the acquired pulse signal data is saved to storage module 60 through hardware trigger module 20 conversion or software encoding by central processing module 10.

[0069] Specifically, configuring the acquisition task of the pulse transceiver module 40 may include configuring one or more channels of the pulse transceiver module 40 to pulse acquisition mode, configuring initial settings (including initial values ​​of configuration registers), selecting the signal edge to be acquired, and selecting a specific general purpose input / output interface (GPIO) as input; and turning on the pulse acquisition counter (timer 30).

[0070] Furthermore, configuring the pulse generation task of the pulse transceiver module 40 may include configuring one or more channels of the pulse transceiver module 40 to pulse output mode, configuring initial settings (including initial values ​​of configuration registers), selecting the acquired signal edge, and selecting a specific general purpose input / output interface (GPIO) as output; and loading the prepared pulse signal data into the data register of the pulse transceiver module 40 through the direct memory accessor 50 (DMA).

[0071] According to a preferred embodiment, in this invention, the pulse transceiver module 40 can generate pulse output of any form by configuring a period register or a threshold register. Specifically, the central processing module 10 is pre-programmed, and based on the pulse signal data acquired and imported into the data register, the central processing module 10 determines the hardware restoration or program encoding processing for the pulse signal data. In particular, each pulse transceiver module 40 can support output from multiple channels.

[0072] According to a preferred embodiment, in this invention, when a specific pulse signal is transmitted or output through the pulse transceiver module 40 based on a desired pulse signal, any one or more pulse transceiver submodules (signal channels) of the pulse transceiver module 40 are configured in pulse output mode, initial settings are configured, and a specific general purpose input / output interface (GPIO) is selected as the output. Further, the prepared pulse signal data is loaded into the data register of the pulse transceiver module 40 via the direct memory accessor 50, and the data in the data register is respectively imported into a period comparator and a threshold comparator to generate pulses based on these two comparators. Subsequently, the pulse transceiver module 40 is enabled according to the configuration of the central processing module 10 or the timer 30 to generate the specified pulse signal to an external device based on the register data.

[0073] According to a preferred embodiment, the present invention supports directly restoring a single-channel pulse signal via the hardware trigger module 20 or generating a single-channel or parallel multi-channel pulse signal via the central processing module 10 through program encoding, and then outputting it through the pulse transceiver module 40. Alternatively, the present invention also supports directly restoring a parallel multi-channel pulse signal via the hardware trigger module 20 or generating a single-channel or parallel multi-channel pulse signal via the central processing module 10 through program encoding, and then outputting it through the pulse transceiver module 40. In particular, the output mode of the pulse signal is preferably determined by the actual needs of the external device.

[0074] In some alternative implementations, the application scenarios of the present invention may include specific forms such as one-to-one (single-channel pulse to single-channel pulse) / one-to-many (single-channel pulse to multiple-channel pulse) or many-to-one (multi-channel pulse to single-channel pulse) / many-to-many (multi-channel pulse to multiple-channel pulse).

[0075] Specifically, for example, in a one-to-many controllable delay transceiver scenario, the pulse transceiver module 40 is enabled to acquire the control pulse signal of one motor. When the amount of pulse data acquired by the pulse transceiver module 40 reaches a threshold, an interrupt is generated and the timer 30 is triggered to count. When the timer 30 counts to a specified time, it triggers the pulse transceiver module 40 to repeatedly forward the pulse signal to the multiplexed motor controller.

[0076] On the other hand, for scenarios involving the conversion between pulse signals from non-standard and standard protocols, the pulse transceiver module 40 first acquires the pulse signals from user-customized proprietary protocols and then re-encodes them through the central processing module 10 to output pulse signals from a standard protocol. Specifically, in fields such as electricity meters and water meters, some protocols are non-standard and proprietary, incompatible with standard interfaces. The pulse signals can be acquired and re-encoded by the central processing module 10 to restore them to pulse signals compatible with standard interface protocols. Alternatively, two local systems can be configured, each performing pulse signal acquisition and transmission tasks separately. During this process, users can flexibly customize communication protocols to encode and decode pulse signals, making the encoded pulse information difficult for others to crack.

[0077] It should be noted that the specific embodiments described above are exemplary. Those skilled in the art can devise various solutions inspired by the disclosure of this invention, and these solutions all fall within the scope of this invention and its protection. Those skilled in the art should understand that this specification and its accompanying drawings are illustrative and not intended to limit the scope of the claims. The scope of protection of this invention is defined by the claims and their equivalents. This specification contains multiple inventive concepts; terms such as "preferredly," "according to a preferred embodiment," or "optionally" indicate that the corresponding paragraph discloses an independent concept. The applicant reserves the right to file divisional applications based on each inventive concept.

Claims

1. A control circuit for pulse acquisition and flexible pulse generation, comprising: A pulse transceiver module (40) is used to acquire and output pulse signals; The hardware trigger module (20) is used to restore the pulse signal and start working immediately via one or more of the hardware trigger pulse transceiver module (40), central processing module (10) and storage module (60); Storage module (60) is used to store pulse signal data; as well as Central processing module (10); Its features are, The pulse transceiver module (40) can acquire a single-channel first pulse signal or multiple parallel second pulse signals through the input / output interface, and send several single-channel third pulse signals or multiple parallel fourth pulse signals through the input / output interface. The original waveform of the plurality of single-channel third pulse signals or the parallel multi-channel fourth pulse signals is restored and output by the hardware trigger module (20) or is formed by the encoding process of the central processing module (10).

2. The control circuit according to claim 1, characterized in that, The central processing module (10) pre-configures a corresponding first working mode for the restored original waveform output by the hardware trigger module (20). In the first working mode, When the first pulse transceiver submodule in the pulse transceiver module (40) acquires at least one single-channel pulse signal, the hardware trigger module (20) performs a first operation to trigger a timing task and a second operation to trigger at least one second pulse transceiver submodule to output a pulse signal when the timing task ends, according to the first working mode preset by the central processing module (10).

3. The control circuit according to claim 1 or 2, characterized in that, The central processing module (10) is pre-configured with a corresponding second working mode for the encoding processing of the central processing module (10). In the second working mode, When the first pulse transceiver submodule in the pulse transceiver module (40) acquires at least one single pulse signal, the central processing module (10) encodes the pulse signal into a third pulse signal or multiple parallel fourth pulse signals. The hardware triggering module (20) executes a third operation to trigger the timing task and a fourth operation to trigger at least one second pulse transceiver submodule to output the pulse signal when the timing task ends, according to the second working mode preset by the central processing module (10).

4. The control circuit according to claim 1, characterized in that, When the first pulse transceiver submodule in the pulse transceiver module (40) acquires at least one single-channel pulse signal, the pulse signal acquired by the pulse transceiver module (40) is stored in the storage module (60).

5. The control circuit according to claim 1, characterized in that, Also includes: A direct storage accessor (50) is used to control the reading and writing of pulse signal data by the storage module (60).

6. The control circuit according to claim 1, characterized in that, Also includes: A timer (30) is used to perform timing tasks for the pulse signal acquisition and transmission process.

7. The control circuit according to claim 6, characterized in that, When the timer (30) executes the corresponding timing task, the pre-designed value is greater than the time required for the central processing module (10) to encode the pulse signal data.

8. The control circuit according to claim 1, characterized in that, The pulse transceiver module (40) is equipped with a period register or a threshold register for generating arbitrary pulse signals.

9. The control circuit according to claim 5, characterized in that, The pulse transceiver module (40) generates specific pulse signals including: The pre-made pulse signal data is loaded into the data register of the pulse transceiver module (40) through the direct storage accessor (50), and the pulse signal data in the data register is respectively imported into the period comparator and the threshold comparator to generate a specific pulse signal according to the period comparator and the threshold comparator.

10. The control circuit according to claim 2, characterized in that, The first pulse transceiver submodule and the second pulse transceiver submodule of the pulse transceiver module (40) are different channels from each other.

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