Data Transmission Method Based on TRDP Protocol and FPGA Chip

Abstract

The present invention discloses a data transmission method and an FPGA chip based on the TRDP protocol, which relate to the technical field of rail vehicle communication networks. The data transmission method based on the TRDP protocol includes: the FPGA receives a publishing instruction from the sending port of the TRDP protocol, and the publishing instruction includes the sending port index of the sending port; the FPGA module determines the sending time slot corresponding to the sending port according to a pre-configured sending time slot table and the sending port index, wherein the sending time slot table includes the corresponding relationship between the sending port index of each sending port of the TRDP protocol and the sending time slot; and TRDP data is sent in the sending time slot. This application can solve the problems that existing software cannot guarantee the real-time requirement of TRDP communication and determine the sending time slot.

Description

Technical Field

[0001] The present invention relates to the technical field of rail vehicle communication networks, and in particular to a data transmission method based on the TRDP protocol and an FPGA chip. Background Art

[0002] By fully adopting industrial Ethernet as the data transmission channel for train communication, the data communication rate can be significantly improved, and the data transmission bandwidth can be greatly broadened. In order to respond to this development trend, the International Electrotechnical Commission has introduced an international standard for the IEC61375 train communication network based on Ethernet. Among them, IEC61375-2-3 stipulates that the train communication protocol adopts the TRDP protocol. TRDP is a technology proposed by Bombardier Inc. of Canada. Due to good technology promotion and complete market applications, this protocol has gradually been recognized by various countries and manufacturers. Currently, the TRDP protocol is the most valuable Ethernet train control protocol in future train communication networks.

[0003] In order to popularize and accelerate the industrial application of TRDP in the rail transit field, companies such as Bombardier, Siemens, Toshiba, and CRRC have established the TCNOpen industry group and contributed relevant open-source codes. In order to quickly and efficiently connect their own data services to the IEC61375 train communication network, vehicle equipment manufacturers usually directly use the TCNOpen source code as the basis for implementing the TRDP data communication protocol.

[0004] According to the provisions of the IEC61375-2-3 protocol, the TRDP communication protocol is essentially a standard Ethernet UDP communication protocol based on a specific port 17224, and specific TRDP header information is defined in the first 40 bytes of the UDP payload.

[0005] The TCNOpen open-source software constructs a TRDP data protocol stack on the basis of the standard TCP / IP protocol stack to complete the implementation of TRDP data services. The design of TCNOpen itself takes into account the diverse requirements of the embedded operating systems of different manufacturers' devices, and it is compatible with the mainstream embedded operating systems on the market, such as linux, qnx, vxworks, etc. Considering generality and cross-platformness, the internal implementation of TCNOpen is relatively complex, but it has opened a series of simple and clear user-side operation interfaces (initialization, port publishing, port subscribing, port un-publishing, port un-subscribing, etc.). Vehicle equipment manufacturers can easily integrate the TCNOpen code into their own business codes, without caring about the internal implementation details, and can directly use the exported operation interfaces to easily implement TRDP data communication.

[0006] Implementing TRDP using the TCNOpen code library can generally meet the usage scenarios of most in-vehicle services, but there are still the following limitations:

[0007] a. It is unable to guarantee high real-time requirements and definite transmission time slots. The TRDP implementation of TCNOpen itself is a software implementation method. Due to its cross-platform design, a series of abstraction layers are required internally to unify the implementations of different operating systems, which will inevitably introduce certain performance losses (including CPU consumption and transmission delay). This is only in the TRDP encapsulation link. In fact, from the time when the user prepares the TRDP service data to the final transmission onto the Ethernet line, it needs to go through a series of path links such as Figure 1 shown. Among them, the delay jitter introduced in the TCP / IP protocol stack and network card driver links is also uncertain, especially when the Ethernet service data traffic is large, it cannot be guaranteed. Moreover, the TCNOpen code implementation can only reach 10 ms for the minimum TRDP communication port period. When the service needs to use more high-communication-rate TRDP ports, the period jitter will be very obvious, usually reaching the millisecond level. In addition, in order to save costs, vehicle equipment manufacturers usually implement the in-vehicle service function and TRDP communication service on the same CPU board. In this case, if the in-vehicle service function needs to occupy a large amount of CPU, even if the TRDP communication ports are used less, the real-time performance and determinacy of TRDP communication still cannot be guaranteed.

[0008] b. Similarly, for in-vehicle devices that integrate in-vehicle service functions and TRDP communication services, when they need to use more short-cycle TRDP transmission ports and receiving ports, the TRDP protocol stack, TCP / IP protocol stack, and network card driver will all consume excessive CPU resources (because the sending and receiving of packets will go through these 3 links), which will also have a certain adverse impact on the in-vehicle service function.

[0009] c. For in-vehicle devices with dual network port redundancy, it is unable to guarantee the synchronization of data transmission on the two network ports. The TCNOpen code design itself does not consider the scenario of simultaneously sending TRDP services on dual network ports. To meet the service requirements of dual network card redundancy, usually 2 TRDP protocol stack instances need to run on the CPU. In this case, it is simply impossible for the packets with the same sequence number on the same TRDP port to be sent simultaneously, and there will be an uncertain delay between them.

[0010] d. It fails to meet the performance requirements of fast port switching. Although TCNOpen provides relevant operation interfaces such as port publication, port subscription, port unpublication, and port unsubscription, the implementation cost of these interfaces is relatively high. For the scenario of CCU master-slave switching, the primary and standby CCUs usually need to use different TRDP port protocols, and the CCU has many sending and interface ports. When the CCU performs master-slave switching, it needs to release the current TRDP protocol first and then load the new TRDP protocol port after the role switch. The overhead and time introduced are relatively large. Summary of the Invention

[0011] To overcome the above-mentioned defects of the prior art, the technical problem to be solved by the embodiments of the present invention is to provide a data transmission method and an FPGA chip based on the TRDP protocol, which can solve the problems that the existing software cannot guarantee the real-time requirements of TRDP communication and the determined sending time slots.

[0012] The specific technical solution of the embodiments of the present invention is as follows:

[0013] A data transmission method based on the TRDP protocol, comprising:

[0014] Receiving a publication instruction of a sending port of the TRDP protocol, where the publication instruction includes a sending port index of the sending port;

[0015] Determining a sending time slot corresponding to the sending port according to a pre-configured sending time slot table and the sending port index, where the sending time slot table includes the corresponding relationship between the sending port indexes of the sending ports of the TRDP protocol and the sending time slots;

[0016] Sending TRDP data of the corresponding port at the sending time slot.

[0017] Preferably, the configuration method of the sending time slot table includes:

[0018] Determining the maximum basic period of the transmission time slot to be allocated;

[0019] Dividing the maximum basic period into multiple minimum time slot periods;

[0020] Dividing each of the minimum time slot periods into an FPGA acceleration time slot and a CPU message time slot, where the FPGA acceleration time slot is used to send the TRDP data, the CPU message time slot is used to send non-TRDP data, and the lengths of the FPGA acceleration time slot and the CPU message time slot satisfy a preset ratio;

[0021] Dividing each of the FPGA acceleration time slots into multiple sub-time slots;

[0022] Allocate the sub - time slots to each sending port of the TRDP protocol respectively to obtain the sending time - slot table.

[0023] Preferably, allocating the sub - time slots to each sending port of the TRDP protocol respectively to obtain the sending time - slot table includes:

[0024] Sort the sending ports according to a preset rule to obtain a sorting table;

[0025] Allocate the sub - time slots to each sending port in ascending order of the sorting numbers in the sorting table to obtain the sending time - slot table.

[0026] Preferably, allocating the sub - time slots to each sending port in ascending order of the sorting numbers in the sorting table to obtain the sending time - slot table includes:

[0027] Determine the number of sub - time slots that each sending port needs to occupy according to the occupation time of each sending port and the length of the sub - time slot;

[0028] Determine the starting sending sub - time slots of each sending port in ascending order of the sorting numbers in the sorting table according to the number of sub - time slots that each sending port needs to occupy;

[0029] Determine all the sub - time slots that each sending port needs to occupy within the maximum basic period according to the starting sending sub - time slots of each sending port and the sending period of each sending port to obtain the sending time - slot table.

[0030] Preferably, sorting the sending ports according to a preset rule to obtain a sorting table of the sending ports includes:

[0031] Sort according to the sending periods of the sending ports in ascending order of the sending periods;

[0032] For sending ports with the same sending period, sort according to the sending lengths of the sending ports in descending order of the sending lengths;

[0033] For sending ports with the same sending period and sending length, sort according to the port numbers of the sending ports in ascending order of the port numbers to obtain the sorting table.

[0034] Preferably, the sending time - slot table is obtained by dividing the interface time - slots on the interface side of the MAC chip and the PHY chip.

[0035] Preferably, the method further includes:

[0036] Record the publishing status of the sending port in the port publishing table as the published status according to the sending port index, where the port publishing table is used to record the publishing status of the sending port.

[0037] Preferably, determining the sending time slot corresponding to the sending port according to a pre-configured sending time slot table includes:

[0038] According to the sending time slot table, send a time slot start signal and the sending port index at the sending time slot corresponding to the sending port;

[0039] Obtain the publishing status of the sending port from the port publishing table according to the sending port index sent in the corresponding time slot;

[0040] Obtain the configuration information of the sending port from a pre-configured port configuration table according to the sending port index sent in the corresponding time slot, where the port configuration table includes the configuration information of each sending port of the TRDP protocol;

[0041] Send a time slot sending enable signal for the sending time slot according to the time slot start signal and the published status.

[0042] Preferably, sending TRDP data in the sending time slot includes:

[0043] In response to the time slot sending enable signal, send TRDP data in the sending time slot through the sending port according to the configuration information.

[0044] Preferably, it further includes:

[0045] Receive a data update instruction, where the data update instruction includes the sending port index of the sending port and the TRDP data to be sent;

[0046] According to the sending port index, store the TRDP data to be sent in the storage area corresponding to the sending port in the TRDP data table, where the TRDP data table includes the storage areas of each sending port, and the storage area is used to store the TRDP data of the corresponding sending port.

[0047] Preferably, sending TRDP data in the sending time slot includes:

[0048] Obtain the TRDP payload data corresponding to the sending port from the TRDP data table;

[0049] Pack the TRDP data into a complete Ethernet frame for sending.

[0050] An FPGA chip includes:

[0051] A publish instruction receiving module, configured to receive a publish instruction of a sending port of the TRDP protocol, where the publish instruction includes a sending port index of the sending port;

[0052] A sending time slot determination module, configured to determine a sending time slot corresponding to the sending port according to a pre-configured sending time slot table and the sending port index, where the sending time slot table includes a correspondence between the sending port indexes of the respective sending ports of the TRDP protocol and the sending time slots;

[0053] A sending module, configured to send TRDP data of the corresponding port during the sending time slot.

[0054] The method for configuring the sending time slot table includes:

[0055] Determine the maximum basic period of the transmission time slots to be allocated;

[0056] Divide the maximum basic period into multiple minimum time slot periods;

[0057] Divide each of the minimum time slot periods into an FPGA acceleration time slot and a CPU message time slot, where the FPGA acceleration time slot is used to send the TRDP data, the CPU message time slot is used to send non-TRDP data, and the lengths of the FPGA acceleration time slot and the CPU message time slot satisfy a preset ratio;

[0058] Divide each of the FPGA acceleration time slots into multiple sub-time slots;

[0059] Allocate the sub-time slots to the respective sending ports of the TRDP protocol respectively to obtain the sending time slot table.

[0060] Preferably, allocating the sub-time slots to the respective sending ports of the TRDP protocol respectively to obtain the sending time slot table includes:

[0061] Sort the respective sending ports according to a preset rule to obtain a sorting table;

[0062] Allocate the sub-time slots to the respective sending ports in ascending order of the sorting numbers in the sorting table to obtain the sending time slot table.

[0063] Preferably, allocating the sub-time slots to the respective sending ports in ascending order of the sorting numbers in the sorting table to obtain the sending time slot table includes:

[0064] Determine the number of sub-time slots that each of the sending ports needs to occupy according to the occupation time of each of the sending ports and the length of the sub-time slots;

[0065] According to the number of sub - time slots required to be occupied by each of the said sending ports, determine the starting sub - time slot for sending of each of the said sending ports in ascending order of the sorting numbers in the said sorting table.

[0066] According to the starting sub - time slot for sending of each of the said sending ports and the sending period of each of the said sending ports, determine all the sub - time slots that each of the said sending ports needs to occupy within the said maximum basic period, and obtain the said sending time - slot table.

[0067] Preferably, the sorting the said sending ports according to a preset rule to obtain a sorting table of the sending ports includes:

[0068] Sort the said sending ports in ascending order according to their sending periods.

[0069] For the sending ports with the same sending period, sort them in descending order according to the sending length of the said sending ports.

[0070] For the sending ports with the same sending period and the same sending length, sort them in ascending order according to the port numbers of the said sending ports to obtain the said sorting table.

[0071] Preferably, it further includes a processing module, which is used to record the publishing status of the said sending port in the port publishing table as the published status according to the sending port index, where the port publishing table is used to record the publishing status of the said sending port.

[0072] Preferably, the said sending time - slot determination module is further configured to:

[0073] According to the said sending time - slot table, send a time - slot start signal and the said sending port index at the sending time - slot corresponding to the said sending port.

[0074] According to the said sending port index sent at the corresponding time - slot, obtain the publishing status of the said sending port from the port publishing table.

[0075] According to the said sending port index sent at the corresponding time - slot, obtain the configuration information of the said sending port from a pre - configured port configuration table, where the port configuration table includes the configuration information of each sending port of the TRDP protocol.

[0076] According to the said time - slot start signal and the said published status, send a time - slot sending enable signal for the said sending time - slot.

[0077] Preferably, the said sending module is further configured to:

[0078] In response to the said time - slot sending enable signal, send TRDP data through the said sending port according to the said configuration information.

[0079] Preferably, it further includes a processing module, which is used for

[0080] receiving a data update instruction, where the data update instruction includes the transmission port index of the transmission port and the TRDP data to be transmitted;

[0081] According to the transmission port index, storing the to-be-transmitted TRDP data into the storage area corresponding to the transmission port in the TRDP data table, where the TRDP data table includes the storage areas of each transmission port, and the storage area is used to store the TRDP data of the corresponding transmission port.

[0082] Preferably, the sending module is further configured to:

[0083] obtain the TRDP payload data corresponding to the transmission port from the TRDP data table;

[0084] pack and send the TRDP data.

[0085] Preferably, the FPGA chip is connected to the CPU through a high-speed bus.

[0086] The technical solution of the present invention has the following remarkable beneficial effects:

[0087] This application realizes controlling the data transceiver of the TRDP port by using an FPGA chip. The FPGA chip determines the transmission time slot corresponding to the transmission port according to the pre-configured transmission time slot table and the transmission port index, and then sends the TRDP data within the transmission time slot. This can ensure the real-time transmission requirement of the TRDP data even when the Ethernet service data traffic is large, and at the same time reduce the occupancy of the CPU chip.

[0088] Referring to the following description and drawings, specific embodiments of the present invention are disclosed in detail, indicating the ways in which the principles of the present invention can be adopted. It should be understood that the embodiments of the present invention are not limited in scope thereby. Features described and / or illustrated for one embodiment can be used in the same or similar way in one or more other embodiments, combined with the features in other embodiments, or replace the features in other embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0089] The drawings described herein are for illustrative purposes only and are not intended to limit the scope of the disclosure of the present invention in any way. In addition, the shapes and proportional dimensions of the components in the drawings are only schematic and are used to help understand the present invention, rather than specifically limiting the shapes and proportional dimensions of the components of the present invention. Those skilled in the art can select various possible shapes and proportional dimensions according to specific circumstances to implement the present invention under the teaching of the present invention.

[0090] Figure 1 This is the sending process of the TRDP protocol using traditional software.

[0091] Figure 2 It is a step flow chart of the data transmission method based on the TRDP protocol in an embodiment of the present invention.

[0092] Figure 3 This is a time slot division rule based on the standard MII interface in an embodiment of the present invention.

[0093] Figure 4 This is an FPGA design architecture for implementing TRDP hardware accelerated transmission in an embodiment of the present invention.

[0094] Figure 5 This is the FPGA design architecture for dual-channel TRDP reception in an embodiment of the present invention.

[0095] Figure 6 This is the FPGA sending state machine based on the TRDP protocol in an embodiment of the present invention.

[0096] Figure 7 Schematic diagram of the structure of the FPGA chip in an embodiment of the present invention. DETAILED DESCRIPTION

[0097] The details of the present invention can be more clearly understood by referring to the accompanying drawings and the description of the specific embodiments of the present invention. However, the specific embodiments of the present invention described herein are only for the purpose of explaining the present invention and are not to be construed as limiting the present invention in any way. Based on the teachings of the present invention, a skilled person can conceive of any possible variations based on the present invention, and such variations should be considered to fall within the scope of the present invention.

[0098] In order to solve the problem that the real-time requirements of TRDP communication and the determined transmission time slot cannot be guaranteed, a data transmission method based on the TRDP protocol is proposed in this application. Figure 2 It is a step flow chart of the data transmission method based on the TRDP protocol in an embodiment of the present invention, such as Figure 2 As shown, the data transmission method based on the TRDP protocol is applied to FPGA chips. The data transmission method based on the TRDP protocol in this application can include the following steps:

[0099] S101: Receive a publishing instruction of a sending port of the TRDP protocol, where the publishing instruction includes a sending port index of the sending port.

[0100] Figure 4 The FPGA design architecture for implementing TRDP hardware acceleration transmission in the embodiment of the present invention is as follows: Figure 4As shown in the figure, the top-level architecture may include a CPU bus processing module, a command parsing and processing module, a transmission control module, a TRDP protocol transmission module, a MAC layer interface protocol shaping module (protocol conversion module), and related dual-port storage tables including a transmission port configuration table, a transmission time slot table, a port publishing table, and a TRDP data table. The CPU bus processing module is responsible for processing read and write operations of a specific CPU bus protocol, internally mapping the corresponding register storage space, with a part used for command registers to process the TRDP operation instructions issued by the CPU, and another part used to store global static configuration information, mainly including source MAC address, source IP address, acceleration enable, MII protocol configuration, etc. of the dual-channel network interface. The command parsing module is responsible for parsing the TRDP operation instructions issued by the CPU and operating on the relevant storage tables according to different TRDP operation instructions. When the CPU chip software sends an initialization time slot table instruction, the command parsing and processing module updates the time slot table information to the transmission time slot table one by one. When the CPU chip software sends a data update instruction, the command parsing and processing module updates the TRDP data to the storage area where the TRDP data table corresponding to the TRDP port is located. The transmission control module generates a time slot start signal and a transmission port index in combination with the transmission time slot table. The port publishing table outputs the TRDP configuration information of the corresponding port according to the transmission port index of each sub-time slot, mainly including relevant information such as COMID, port transmission length, destination IP address of channel 1, destination IP address of channel 2, VLAN of channel 1, VLAN of channel 2, etc. The TRDP data table is responsible for caching the to-be-transmitted TRDP data of all transmission ports, and each port has a corresponding actual storage area. The TRDP protocol transmission module is responsible for packaging and generating a complete TRDP message data stream and providing the CRC check value calculation of relevant header information. The MAC layer interface protocol conversion module is responsible for adapting different MAC layer interface protocols and converting the data stream output by the TRDP protocol module into a specific MAC layer interface protocol (standard MII, RGMII, etc.).

[0101] Figure 5 This is the FPGA design architecture for dual-channel TRDP reception in the embodiment of the present invention, as Figure 5As shown in the figure, the top-level architecture may include a CPU bus processing module and two independent receive processing top-level modules. Each receive processing top-level module contains a protocol conversion module (protocol shaping module), a TRDP protocol identification module, a MAC layer interface protocol recovery module, and a received TRDP data table. All Ethernet packets first pass through the MAC layer interface protocol conversion module to be converted into an Ethernet byte transfer protocol, and then pass through the TRDP protocol identification module to determine whether the packet is a TRDP protocol packet. Combined with the port subscription table, it is determined whether the TRDP packet is in the subscription list. When and only when the received packet is a TRDP protocol packet and exists in the port subscription table, the TRDP port data (including TRDP header data and TRDP payload data) is sampled byte by byte and written into the received TRDP data table in the corresponding storage area. All other packets are converted back to the CPU-side MAC layer interface protocol through the MAC layer interface protocol recovery module.

[0102] The specific process of controlling the TRDP protocol packet sending is as follows. The CPU chip software performs virtual address mapping to obtain the virtual address of the AXI bus. The CPU chip software issues global configuration information, which mainly includes the source MAC address of channel 1, the source MAC address of channel 2, the source IP address of channel 1, and the source IP address of channel 2. The FPGA chip saves the relevant information to the internal register group. The CPU chip software issues the time slot table configuration information through the command interface, and the command ID is 1. The CPU bus processing module of the FPGA chip receives the command issued by the CPU. After parsing and determining that the command ID is 1, the time slot table configuration information is written into the time slot configuration table dual-port RAM one by one according to the 32-bit width. The CPU chip software issues the port configuration information through the command interface, and the command ID is 2. The CPU bus processing module of the FPGA chip receives the command issued by the CPU. After parsing and determining that the command ID is 2, the port configuration information is written into the transmit port configuration table dual-port RAM one by one according to the 32-bit width.

[0103] After that, the CPU chip software issues a publish command for the specified transmit port through the command interface. The publish command includes the transmit port index of the transmit port, that is, the transmit port index of the TRDP port, and the command ID can be 4. The FPGA chip receives the publish instruction of the transmit port of the TRDP protocol through the CPU bus processing module. After parsing and determining that the command ID is 4, it saves the transmit port index of the transmit port.

[0104] Among them, the interaction instruction design between the CPU chip and the FPGA chip and the high-speed bus between the CPU chip and the FPGA chip realize the access control of the global register and command register inside the FPGA chip by mapping the internal physical address of the FPGA to obtain the virtual address.

[0105] S102: According to the sending port index, record the publishing status of the sending port in the port publishing table as the published status, where the port publishing table is used to record the publishing status of the sending port.

[0106] In this step, specifically, a write signal and a write address for the TRDP port in the dual-port RAM of the port publishing table can be generated according to the sending port index, and the value of the corresponding storage unit is changed to 1, so as to record the publishing status of the sending port in the port publishing table as the published status.

[0107] S103: Determine the sending time slot corresponding to the sending port according to the pre-configured sending time slot table and the port index, where the sending time slot table includes the corresponding relationship between the port index and the sending time slot of each sending port of the TRDP protocol.

[0108] In this step, the configuration method of the sending time slot table can be as follows: Determine the maximum basic period of the transmission time slot to be allocated. Divide the maximum basic period into multiple minimum time slot periods. Divide each of the minimum time slot periods into an FPGA acceleration time slot and a CPU message time slot, where the FPGA acceleration time slot is used to send the TRDP data, the CPU message time slot is used to send non-TRDP data, and the lengths of the FPGA acceleration time slot and the CPU message time slot satisfy a preset ratio; Divide each of the FPGA acceleration time slots into multiple sub-time slots. Allocate the sub-time slots to each sending port of the TRDP protocol respectively to obtain the sending time slot table.

[0109] As feasible, allocating the sub-time slots to each sending port of the TRDP protocol respectively to obtain the sending time slot table may specifically include:

[0110] Sort each of the sending ports according to a preset rule to obtain a sorting table.

[0111] In the above step, it is possible to sort according to the sending periods of each of the sending ports in ascending order of the sending periods; for sending ports with the same sending period, according to the sending length of the sending port, sort in descending order of the sending length; for sending ports with the same sending period and sending length, according to the port number of the sending port, sort in ascending order of the port number to obtain the sorting table.

[0112] Allocate the sub-time slots to each of the sending ports in ascending order of the sorting numbers in the sorting table to obtain the sending time slot table.

[0113] The above-mentioned sending time slot table is obtained by dividing the interface time slots on the interface side of the MAC chip and the PHY chip.

[0114] In the above steps, the following process can be specifically adopted to obtain the transmission time slot table: Determine the number of sub-time slots that each of the transmission ports needs to occupy according to the occupation time of each of the transmission ports and the length of the sub-time slots. According to the number of sub-time slots that each of the transmission ports needs to occupy, determine the starting transmission sub-time slots of each of the transmission ports in ascending order of the sequence numbers in the sorting table. Determine all the sub-time slots that each of the transmission ports needs to occupy within the maximum basic period according to the starting transmission sub-time slots of each of the transmission ports and the transmission periods of each of the transmission ports, so as to obtain the transmission time slot table.

[0115] In a specific embodiment, the following description designs the present invention by taking the standard MII interface protocol as a specific embodiment.

[0116] The IEEE802.3U protocol standard defines that the connection between a 100-Mbps Ethernet MAC chip and a physical layer PHY chip adopts the MII interface protocol standard. Through the MII interface, PHY chips of different types and manufacturers can be connected to the standard Ethernet MAC chip, making it independent of the network signal transmission medium. The network data on the MII interface is constructed using the IEEE Ethernet standard. Therefore, the network data on the MII interface consists of a preamble, a start frame delimiter, an Ethernet header, protocol-specific data, and a cyclic redundancy check (CRC). The standard MII interface uses 4-bit nibbles (4 transmit data bits and 4 receive data bits) to transmit network data in each direction. The clock frequency of the data is 25 MHZ to achieve a throughput of 100 Mbit / s. The MII interface can also include a series of derivative interfaces, such as GMII, RGMII, SGMII, XGMII, etc., to support the physical transmission of gigabit networks and 10-gigabit networks.

[0117] Among them, the minimum time slot period is defined as 1 ms. Usually, the characteristic periods of the TRDP protocol ports can include 10 ms, 20 ms, 50 ms, 100 ms, 200 ms, 500 ms, and 1 s. Therefore, the maximum basic period for determining the transmission time slots to be allocated is 1 s.

[0118] Figure 3 For the time slot division rule based on the standard MII interface in the embodiment of the present invention, as Figure 3As shown, each of the minimum time slot periods is divided into an FPGA acceleration time slot and a CPU message time slot. Among them, the FPGA acceleration time slot is used to send the TRDP data, and the CPU message time slot is used to send non-TRDP data. The lengths of the FPGA acceleration time slot and the CPU message time slot satisfy a preset ratio. The time slot marked as FPGA is the FPGA acceleration time slot, and the time slot marked as CPU in the figure is the CPU message time slot. The preset ratio between the lengths of the FPGA acceleration time slot and the CPU message time slot can be dynamically adjusted according to the actual project's TRDP protocol data volume. The non-TRDP protocol messages sent by the CPU chip side through the network protocol stack are cached by the FIFO and sent in the CPU message time slot, which does not affect the other non-real-time service functions responsible by the CPU chip side while ensuring the real-time performance of the TRDP protocol.

[0119] Each of the FPGA acceleration time slots is divided into multiple sub-time slots, such as N sub-time slots. The number N of sub-time slots inside the FPGA acceleration time slot can also be dynamically adjusted according to the actual project's TRDP protocol data volume.

[0120] The implementation process of this application will be described below with the TRDP sending protocol shown in Table 1.

[0121] Table 1

[0122]

[0123]

[0124] The representation method of each sub-time slot can be [X, Y, Z], where X represents the index position of the minimum time slot period (1MS) it belongs to, and the range is 0 - 999. Y represents the position of the minimum sub-time slot period within the minimum time slot period where X is located, and Z represents the number of consecutive minimum sub-time slots it occupies.

[0125] The sub-time slots are allocated to each sending port of the TRDP protocol respectively to obtain the sending time slot table. The specific process is as follows.

[0126] First, sort all the TRDP protocol sending ports according to preset rules to obtain a sorting table. For example, according to the sending periods of the sending ports, sort them in ascending order of the sending period. First is the sending port with a period of 10MS, then the one with 20MS, then the one with 50MS, and finally the one with 100MS. For sending ports with the same sending period, sort them in descending order of the sending length according to the sending length of the sending port. For example, among the sending ports with a period of 10MS, the sorting is in turn the sending port with a length of 1400, the one with a length of 1200, the one with a length of 1000, the one with a length of 600, and the one with a length of 200. If there are sending ports with the same sending period and sending length, they can be sorted in ascending order of the port number according to the port number of the sending port to obtain the sorting table. <(

[0127] After that, allocate the sub-slots to each of the sending ports in ascending order of the sorting numbers in the sorting table to obtain the sending time slot table. First, determine the number of sub-slots that each sending port needs to occupy according to the occupation time of each sending port and the length of the sub-slot. Here, the occupation time of the sending port can be understood as the time required for transmission. According to the number of sub-slots that each sending port needs to occupy, determine the starting sub-slots of each sending port in ascending order of the sorting numbers in the sorting table. Search for the starting sub-slots of the sending port. Starting from each 1S maximum basic period, within the first M minimum basic periods (M = 1000 / port period), search for the minimum basic period with the remaining idle sub-slot number > X (assuming the port period is 10MS, then M = 100, and the minimum number of sub-slots to be occupied is 4. Assume that the remaining idle sub-slot numbers in the first two minimum basic periods are less than 4, and the remaining idle sub-slot number in the third basic period is 6, and the number of sub-slots is configured to 32. Finally, determine that the starting sub-slot of this port is [2, 26, 4]). According to the starting sub-slot of this port being 2 and the port sending period of 10MS, determine all the time slots occupied by this port within the entire 1S maximum basic period in turn, which are [2, 26, 4], [12, 26, 4], [22, 26, 4], [32, 26, 4]...

[0128] Assume that within each 1MS minimum time slot period, the FPGA acceleration time slot configuration time is 125US, and the CPU message time slot time is 875US. Each FPGA acceleration time slot is internally divided into 8 sub-slot slots, that is, the time length of each sub-slot is 15.625US.

[0129] According to the above-determined parameters, the final determined result of the sending time slot table is shown in Table 2.

[0130] Table 2

[0131] Serial number COMID Sub - time - slot list 1 30004 [0,0,8],[10,0,8],[20,0,8],[30,0,8]... 2 30003 [1,0,7],[11,0,7],[21,0,7],[31,0,7]... 3 30002 [2,0,6],[12,0,6],[22,0,6],[32,0,6]... 4 30001 [3,0,4],[13,0,4],[23,0,4],[33,0,4]... 5 30000 [2,6,2],[12,6,2],[22,6,2],[32,6,2]... 6 30006 [3,4,3],[23,4,3],[43,4,3],[63,4,3]... 7 30005 [4,0,2],[24,0,2],[44,0,2],[64,0,2]... 8 30008 [4,2,2],[54,2,2],[104,2,2],[154,2,2]... 9 30007 [1,7,1],[51,7,1],[101,7,1],[151,7,1]... 10 30009 [4,4,2],[104,4,2],[204,4,2],[304,4,2]...

[0132] The above-mentioned step S103 is used to obtain the said transmission time slot table, which is stored in the form of an array.

[0133] According to the pre-configured transmission time slot table, determine the transmission time slot corresponding to the said transmission port. Specifically, it may include: according to the said transmission time slot table, send a time slot start signal and the said transmission port index at the transmission time slot corresponding to the said transmission port.

[0134] According to the said transmission port index sent at the corresponding time slot, obtain the publishing status of the said transmission port from the said port publishing table. Specifically, read the publishing configuration of the corresponding TRDP port, which is 0 or 1, where 1 indicates published and 0 indicates not published.

[0135] According to the said transmission port index sent at the corresponding time slot, obtain the configuration information of the said transmission port from the pre-configured port configuration table, where the said port configuration table includes the configuration information of each transmission port of the said TRDP protocol.

[0136] According to the said time slot start signal and the said published status, send a time slot transmission enable signal for the said transmission time slot. That is, the publishing status (published status) of the said transmission port and the time slot start signal generate the TRDP port time slot transmission enable signal for this transmission time slot. For example, when the publishing configuration is 1, a time slot transmission enable signal 1 is generated.

[0137] S104: Send TRDP data in the said transmission time slot.

[0138] In this step, in response to the said time slot transmission enable signal, according to the said configuration information, send TRDP data through the said transmission port in the said transmission time slot, so as to send the TRDP data out respectively according to the matching sub-time slots in the transmission time slot table.

[0139] Specifically, after the TRDP protocol sending module in the FPGA chip determines that the time slot transmission enable signal is 1, it starts to activate the internal state machine to perform layer-by-layer packaging and sending of Ethernet packets. Figure 6 This is the sending state machine of the FPGA chip based on the TRDP protocol in the embodiment of the present invention, as Figure 6As shown, first, the transmission of 8-byte preamble information starts, which is represented in hexadecimal as 0X55 0X55 0X55 0X55 0X55 0X55 0X55 0XD5. Then, the MAC layer information is packed and sent in sequence: destination MAC address, source MAC address, and Ethernet type. Then, the IP layer header information, UDP header information, and TRDP header information are packed and sent in sequence. The internal sub-state machine is used to control the calculation of the relevant CRC check values for the IP header information, UDP header information, and TRDP header information. In the sub-state of sending TRDP data, the starting address of the TRDP data of the port is located according to the port index in the dual-port RAM of the TRDP data table for the port, and the relevant read signal and read address are generated to read out the TRDP data of the port one by one and pack it into a complete Ethernet frame for transmission.

[0140] S105: Receive a data update instruction, where the data update instruction includes the sending port index of the sending port and the TRDP data to be sent.

[0141] The software on the CPU chip side sends a data update instruction to update the data of the specified TRDP port periodically through the command interface to implement the update operation of the TRDP data. The command ID can be 8. The data update instruction includes the sending port index of the sending port and the TRDP data to be sent. Therefore, after the CPU bus processing module of the FPGA chip receives the data update instruction sent by the CPU chip and parses and determines that the command ID is 8, it is determined as a data update instruction.

[0142] S106: Store the TRDP data to be sent into the storage area corresponding to the sending port in the TRDP data table according to the sending port index, where the TRDP data table includes the storage areas of each sending port, and the storage area is used to store the TRDP data of the corresponding sending port.

[0143] In this step, after the FPGA chip receives the sending port index in the data update instruction sent by the CPU chip, it saves it, and generates a write signal and a write start address for the dual-port RAM of the TRDP data table according to the sending port index, and stores the TRDP data to be sent into the storage area corresponding to the sending port in the TRDP data table.

[0144] In this application, an FPGA chip is also proposed. Figure 7 It is a schematic structural diagram of the FPGA chip in the embodiment of the present invention, as Figure 7As shown in the figure, the FPGA chip may include: a release instruction receiving module 100, configured to receive a release instruction from a sending port of the TRDP protocol, where the release instruction includes a sending port index of the sending port; a sending time slot determining module 300, configured to determine a sending time slot corresponding to the sending port according to a pre-configured sending time slot table and the sending port index, where the sending time slot table includes a correspondence between the sending port indexes of the respective sending ports of the TRDP protocol and the sending time slots; and a sending module 400, configured to send TRDP data of the corresponding port during the sending time slot.

[0145] Further, the method for configuring the sending time slot table includes: determining a maximum basic period of the transmission time slots to be allocated; dividing the maximum basic period into a plurality of minimum time slot periods; dividing each minimum time slot period into an FPGA acceleration time slot and a CPU message time slot, where the FPGA acceleration time slot is used to send TRDP data and the CPU message time slot is used to send non-TRDP data, and the lengths of the FPGA acceleration time slot and the CPU message time slot satisfy a preset ratio; dividing each FPGA acceleration time slot into a plurality of sub-time slots; and respectively allocating sub-time slots to the respective sending ports of the TRDP protocol to obtain the sending time slot table.

[0146] Further, respectively allocating sub-time slots to the respective sending ports of the TRDP protocol to obtain the sending time slot table may include: sorting the respective sending ports according to a preset rule to obtain a sorting table; and sequentially allocating sub-time slots to the respective sending ports in ascending order of the sorting numbers in the sorting table to obtain the sending time slot table.

[0147] Further, sequentially allocating sub-time slots to the respective sending ports in ascending order of the sorting numbers in the sorting table to obtain the sending time slot table may include: determining the number of sub-time slots that each sending port needs to occupy according to the occupation time of each sending port and the length of the sub-time slot; sequentially determining the starting sending sub-time slots of the respective sending ports in ascending order of the sorting numbers in the sorting table according to the number of sub-time slots that each sending port needs to occupy; and determining all the sub-time slots that each sending port needs to occupy within the maximum basic period according to the starting sending sub-time slots of the respective sending ports and the sending periods of the respective sending ports to obtain the sending time slot table.

[0148] Further, sorting the respective sending ports according to a preset rule to obtain a sorting table of the sending ports includes: sorting according to the sending periods of the respective sending ports in ascending order of the sending periods; for sending ports with the same sending period, sorting according to the sending lengths of the sending ports in descending order of the sending lengths; and for sending ports with the same sending period and the same sending length, sorting according to the port numbers of the sending ports in ascending order of the port numbers to obtain the sorting table.

[0149] Among them, the FPGA chip may further include a processing module 200, configured to record the publishing status of the sending port in the port publishing table as the published status according to the sending port index, where the port publishing table is used to record the publishing status of the sending port.

[0150] Further, the sending time slot determination module 300 is further configured to: according to the sending time slot table, send a time slot start signal and the sending port index at the sending time slot corresponding to the sending port; obtain the publishing status of the sending port from the port publishing table according to the sending port index sent at the corresponding time slot; obtain the configuration information of the sending port from a pre-configured port configuration table according to the sending port index sent at the corresponding time slot, where the port configuration table includes the configuration information of each sending port of the TRDP protocol; and send a time slot sending enable signal for the sending time slot according to the time slot start signal and the published status.

[0151] The sending module 400 is further configured to: in response to the time slot sending enable signal, send TRDP data through the sending port according to the configuration information. The processing module is further configured to receive a data update instruction, where the data update instruction includes the sending port index of the sending port and the TRDP data to be sent; and store the TRDP data to be sent in a storage area corresponding to the sending port in the TRDP data table according to the sending port index, where the TRDP data table includes storage areas for each sending port, and the storage area is used to store the TRDP data of the corresponding sending port.

[0152] The sending module 400 is further configured to: obtain the TRDP payload data corresponding to the sending port from the TRDP data table; and pack the TRDP data into a complete Ethernet frame for sending.

[0153] In this application, the FPGA chip and the CPU chip are connected through a high-speed bus, and the sending and receiving of TRDP data are implemented through register mapping. The sending data stream and the receiving data stream do not pass through the TCP / IP protocol stack of the operating system. The software on the CPU chip side only needs to provide the TRDP user data, and all the packet header information packing and CRC calculation are completed by the FPGA chip, greatly reducing the CPU occupancy rate and thus improving the functional stability of the vehicle-mounted terminal.

[0154] In this application, a set of user interfaces for the TRDP protocol is designed, mainly including the following: configuration of the transmission time slot table (after being generated by the host computer software according to the protocol, it is sent from the CPU chip side to the FPGA chip); TRDP transmission protocol configuration, including information such as the number of transmission ports, the ComID of each transmission port, the transmission multicast address of channel 1, the transmission multicast address of channel 2, and the transmission length (sent from the CPU chip side to the FPGA chip); TRDP reception protocol configuration, including information such as the number of reception ports, the ComID of each reception port, the reception multicast address of channel 1, the reception multicast address of channel 2, and the reception length (sent from the CPU chip side to the FPGA chip); enabling publication of a single TRDP transmission port, used to control the start of periodic transmission of a specified TRDP port; canceling publication of a single TRDP transmission port, used to control the shutdown of periodic transmission of a specified TRDP port; enabling subscription of a single TRDP reception port, used to control the reception processing of a specified TRDP port; canceling subscription of a single TRDP reception port, used to control the cancellation of reception processing of a specified TRDP port; updating the data of a specified TRDP transmission port (the CPU chip side only prepares the TRDP data), and the software on the CPU chip side does not need to specify the transmission channel, and the FPGA chip automatically distributes it to 2 Phy for data transmission; obtaining the data of a specified TRDP reception port, the FPGA chip internally caches the received TRDP data of 2 channels, and the software on the CPU chip side does not need to specify the reception channel, and the FPGA chip makes a decision and returns to the user the TRDP data of which channel.

[0155] This application realizes the control of data transmission and reception of TRDP ports using an FPGA chip. The FPGA chip determines the transmission time slot corresponding to the transmission port according to the pre-configured transmission time slot table and the transmission port index, and then transmits TRDP data within the transmission time slot. This can ensure the real-time transmission requirement of TRDP data even when the Ethernet service data traffic is large, and at the same time reduce the occupancy of the CPU chip. Secondly, the time slot allocation and planning of Ethernet packets are implemented on the interface side of the Ethernet MAC chip and the physical layer PHY (hereinafter referred to as the MAC layer interface), and the entire transmission time slot is divided according to the maximum basic period. Each maximum basic period is divided into N minimum time slot periods, and each minimum time slot period is defined as the minimum basic period. Each minimum time slot period is internally divided into an FPGA acceleration time slot and a CPU packet time slot according to a certain ratio, and the ratio allocation of the FPGA acceleration time slot and the CPU packet time slot is allocated according to the TRDP protocol volume of the actual project. All TRDP protocol ports must be transmitted in the FPGA acceleration time slot, and all non-TRDP protocol packets (icmp, arp, other maintenance protocol packets, etc.) must be transmitted in the CPU packet time slot. Combining the flexibility of the TRDP protocol configuration in the actual project (the cycles and lengths of different TRDP ports in the actual project are randomly determined, resulting in different actual required transmission times) and the maximum utilization rate of the MAC layer interface, this application evenly cuts each FPGA acceleration time slot into M sub-time slots, and the number of sub-time slots can be flexibly configured according to the actual protocol data volume to achieve efficient utilization of the MAC layer interface time slot and reduce time slot waste. This application introduces an FPGA acceleration time slot table to define the TRDP port index planned to be transmitted in each sub-time slot and the number of sub-time slots that the port needs to occupy, that is, short packets occupy fewer sub-time slots, and long packets need to occupy more sub-time slots.

[0156] Currently, the implementation of the TRDP function of on-vehicle equipment of EMUs is usually constructed using the TcnOpen open-source software library. This method still uses the traditional UDP-IP Socket mechanism, and internally controls the timed sending of all TRDP ports through a corresponding software timer linked list. Due to its cross-platform implementation characteristics, TcnOpen has a large amount of redundant and inefficient code. Moreover, as the amount of TRDP protocols in the project increases, it not only consumes more CPU resources, but also introduces a large periodic jitter for each TRDP sending port, and cannot guarantee the real-time performance and determinacy of all TRDP ports. Compared with the prior art: The FPGA chip adopted in this application precisely controls the sending time slots of TRDP ports to ensure the periodicity and determinacy of the sending of all TRDP ports, thereby ensuring real-time performance. This application can meet the need for flexibility in project protocol configuration and efficiently utilize the TRDP sending time slot table design method of the MAC layer interface transmission time slots to achieve ensuring the cycle determinacy of all transmission ports while minimizing the waste of MAC layer interface transmission time slots as much as possible. This application designs a publication table and a subscription table for TRDP ports on the FPGA chip side, and compared with the CPU software method, it can achieve rapid protocol switching.

[0157] The above are only illustrative specific embodiments of the present invention and are not intended to limit the scope of the present invention. Any equivalent changes and modifications made by those skilled in the art without departing from the concept and principles of the present invention shall fall within the scope of protection of the present invention. Moreover, it should be noted that the components of the present invention are not limited to the above overall application. Each technical feature described in the specification of the present invention can be used alone according to actual needs or multiple features can be combined for use. Therefore, the present invention naturally covers other combinations and specific applications related to the inventive points of this case.

Claims

1. A data transmission method based on the TRDP protocol, characterized in that, Including: Receiving a publishing instruction for the sending port of the TRDP protocol, where the publishing instruction includes the sending port index of the sending port; Determining the sending time slot corresponding to the sending port according to a pre-configured sending time slot table and the sending port index, where the sending time slot table includes the correspondence between the sending port indexes and sending time slots of each sending port of the TRDP protocol; Sending TRDP data of the corresponding port during the sending time slot; Wherein, the configuration method of the sending time slot table includes: Determining the maximum basic period of the transmission time slot to be allocated; Dividing the maximum basic period into multiple minimum time slot periods; Dividing each of the minimum time slot periods into an FPGA acceleration time slot and a CPU message time slot, where the FPGA acceleration time slot is used to send the TRDP data, the CPU message time slot is used to send non-TRDP data, and the lengths of the FPGA acceleration time slot and the CPU message time slot satisfy a preset ratio; Dividing each of the FPGA acceleration time slots into multiple sub-time slots; Allocating the sub-time slots to each sending port of the TRDP protocol respectively to obtain the sending time slot table.

2. The data transmission method according to claim 1, characterized in that Allocating the sub-time slots to each sending port of the TRDP protocol respectively to obtain the sending time slot table, including: Sorting each of the sending ports according to a preset rule to obtain a sorting table; Allocating the sub-time slots to each of the sending ports in ascending order of the sorting numbers in the sorting table to obtain the sending time slot table.

3. The data transmission method according to claim 2, wherein Allocating the sub-time slots to each of the sending ports in ascending order of the sorting numbers in the sorting table to obtain the sending time slot table, including: Determining the number of sub-time slots that each of the sending ports needs to occupy according to the occupation time of each of the sending ports and the length of the sub-time slots; Determining the starting sending sub-time slot of each of the sending ports in ascending order of the sorting numbers in the sorting table according to the number of sub-time slots that each of the sending ports needs to occupy; Determining all the sub-time slots that each of the sending ports needs to occupy within the maximum basic period according to the starting sending sub-time slot of each of the sending ports and the sending period of each of the sending ports to obtain the sending time slot table.

4. The data transmission method according to claim 2, wherein The sorting each of the sending ports according to a preset rule to obtain a sorting table of the sending ports, including: Sorting according to the sending periods of each of the sending ports in ascending order of the sending periods; For sending ports with the same sending period, sorting according to the sending length of the sending port in descending order of the sending length; For sending ports with the same sending period and sending length, sorting according to the port numbers of the sending ports in ascending order of the port numbers to obtain the sorting table.

5. The data transmission method according to claim 1, wherein The sending time slot table is obtained by dividing the interface time slots on the interface side of the MAC chip and the PHY chip.

6. The data transmission method according to claim 1, characterized in that The method further includes: Recording the publishing status of the sending port in the port publishing table as the published status according to the sending port index, where the port publishing table is used to record the publishing status of the sending port.

7. The data transmission method according to claim 6, characterized in that, Determine the transmission time slot corresponding to the said transmission port according to a pre-configured transmission time slot table, including: According to the said transmission time slot table, send a time slot start signal and the said transmission port index at the transmission time slot corresponding to the said transmission port; Obtain the release status of the said transmission port from the port release table according to the said transmission port index sent at the corresponding time slot; Obtain the configuration information of the said transmission port from a pre-configured port configuration table according to the said transmission port index sent at the corresponding time slot, where the port configuration table includes the configuration information of each transmission port of the TRDP protocol; Send a time slot transmission enable signal for the said transmission time slot according to the said time slot start signal and the said released status.

8. The data transmission method according to claim 7, wherein Transmit TRDP data in the said transmission time slot, including: In response to the said time slot transmission enable signal, transmit TRDP data through the said transmission port in the said transmission time slot according to the said configuration information.

9. The data transmission method according to claim 1, characterized in that, It also includes: Receive a data update instruction, where the said data update instruction includes the transmission port index of the said transmission port and the TRDP data to be transmitted; According to the said transmission port index, store the said TRDP data to be transmitted in the storage area corresponding to the said transmission port in the TRDP data table, where the TRDP data table includes the storage areas of each said transmission port, and the storage area is used to store the TRDP data of the corresponding transmission port.

10. The data transmission method according to claim 9, characterized in that, Transmit TRDP data in the said transmission time slot, including: Obtain the TRDP payload data corresponding to the said transmission port from the said TRDP data table; Pack the said TRDP payload data into a complete Ethernet frame for transmission.

11. An FPGA chip, including: A release instruction receiving module, used to receive a release instruction of a transmission port of the TRDP protocol, where the said release instruction includes the transmission port index of the said transmission port; A transmission time slot determination module, used to determine the transmission time slot corresponding to the said transmission port according to a pre-configured transmission time slot table and the said transmission port index, where the said transmission time slot table includes the corresponding relationship between the transmission port index of each transmission port of the TRDP protocol and the transmission time slot; A transmission module, used to transmit TRDP data of the corresponding port in the said transmission time slot; Among them, the configuration method of the said transmission time slot table includes: Determine the maximum basic period of the transmission time slot to be allocated; Divide the said maximum basic period into multiple minimum time slot periods; Divide each of the said minimum time slot periods into an FPGA acceleration time slot and a CPU message time slot, where the said FPGA acceleration time slot is used to transmit the said TRDP data, the said CPU message time slot is used to transmit non-TRDP data, and the lengths of the said FPGA acceleration time slot and the said CPU message time slot satisfy a preset ratio; Divide each of the said FPGA acceleration time slots into multiple sub-time slots; Allocate the said sub-time slots to each transmission port of the TRDP protocol respectively to obtain the said transmission time slot table.

12. The FPGA chip according to claim 11, characterized in that, Allocate the said sub-time slots to each transmission port of the TRDP protocol respectively to obtain the said transmission time slot table, including: Sort each of the said transmission ports according to a preset rule to obtain a sorting table; Allocate the sub - time slots to each of the said transmission ports in ascending order of the sequence numbers in the said sorting table to obtain the transmission time - slot table.

13. The FPGA chip according to claim 12, characterized in that, Allocating the sub - time slots to each of the said transmission ports in ascending order of the sequence numbers in the said sorting table to obtain the transmission time - slot table includes: Determine the number of sub - time slots required to be occupied by each of the said transmission ports according to the occupation time of each of the said transmission ports and the length of the sub - time slots. According to the number of sub - time slots required to be occupied by each of the said transmission ports, determine the starting transmission sub - time slot of each of the said transmission ports in ascending order of the sequence numbers in the said sorting table. According to the starting transmission sub - time slot of each of the said transmission ports and the transmission period of each of the said transmission ports, determine all the sub - time slots that each of the said transmission ports needs to occupy within the maximum basic period to obtain the transmission time - slot table.

14. The FPGA chip according to claim 12, wherein Said sorting each of the said transmission ports according to a preset rule to obtain a sorting table of the transmission ports includes: Sort in ascending order of the transmission periods of each of the said transmission ports. For transmission ports with the same transmission period, sort in descending order of the transmission lengths according to the transmission lengths of the said transmission ports. For transmission ports with the same transmission period and the same transmission length, sort in ascending order of the port numbers according to the port numbers of the said transmission ports to obtain the sorting table.

15. The FPGA chip according to claim 11, characterized in that, It further includes a processing module for recording the release status of the said transmission port in the port release table as the released status according to the transmission port index, wherein the port release table is used to record the release status of the said transmission port.

16. The FPGA chip according to claim 15, wherein Said transmission time - slot determination module is further configured to: According to the transmission time - slot table, send a time - slot start signal and the transmission port index at the transmission time - slot corresponding to the said transmission port. Obtain the release status of the said transmission port from the port release table according to the transmission port index sent at the corresponding time - slot. Obtain the configuration information of the said transmission port from a pre - configured port configuration table according to the transmission port index sent at the corresponding time - slot, wherein the port configuration table includes the configuration information of each transmission port of the TRDP protocol. Send a time - slot transmission enable signal for the said transmission time - slot according to the time - slot start signal and the released status.

17. The FPGA chip according to claim 16, wherein Said transmission module is further configured to: In response to the time - slot transmission enable signal, send TRDP data through the said transmission port according to the configuration information.

18. The FPGA chip according to claim 11, wherein It further includes a processing module, which is used for Receiving a data update instruction, wherein the data update instruction includes the transmission port index of the said transmission port and the TRDP data to be sent. According to the transmission port index, store the to - be - sent TRDP data into the storage area corresponding to the said transmission port in the TRDP data table, wherein the TRDP data table includes the storage areas of each of the said transmission ports, and the storage area is used to store the TRDP data of the corresponding transmission port.

19. The FPGA chip according to claim 18, wherein Said transmission module is further configured to: Obtain the TRDP payload data corresponding to the said transmission port from the TRDP data table. Pack the TRDP payload data into a complete Ethernet frame for transmission.

20. The FPGA chip according to claim 11, characterized in that, The FPGA chip is connected to the CPU via a high-speed bus.

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