Dual-pixel simultaneous output high response rate linear array CMOS image sensor and method

Abstract

The application discloses a kind of dual-pixel simultaneous output high response rate linear array CMOS image sensor and method, including first pixel array and second pixel array;The pixel area of first pixel array is greater than the pixel area of second pixel array;First pixel array and second pixel array are connected programmable gain amplifier, programmable gain amplifier is connected one end of column buffer drive circuit, the other end of column buffer drive circuit is connected one end of multistage high-speed control switch, the other end of multistage high-speed control switch is connected one end of analog column logic control circuit, the other end of analog column logic control circuit is respectively connected single oblique column level parallel ADC and chip level pipeline ADC;Single oblique column level parallel ADC connects digital column logic;Chip level pipeline ADC and digital column logic are all connected multichannel high-speed LVDS interface module.Simple and effective response rate of linear array CIS can be improved, and it has the dual imaging function that other linear array CIS does not have.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of image sensors, and particularly relates to a dual-pixel simultaneous output high-response-rate linear array CMOS image sensor and method. BACKGROUND

[0002] An image sensor is the core of a modern electronic imaging system, and the image sensor is mainly realized based on two processes, a CMOS process and a charge coupled device (CCD) process. The CMOS image sensor technology has developed rapidly in recent years due to its high integration, small size, low power consumption and other advantages.

[0003] The CMOS image sensor is currently divided into two array modes, one is a planar array two-dimensional imaging, which is also the most widely used array structure at present, and the other is a linear array structure. The linear array structure is divided into single-line and multi-line, and the two kinds of image frame arrays can share a set of readout circuit architecture design. The difference lies in that, when the planar array CIS is used for global exposure, the system exposure time can be tens of microseconds to hundreds of milliseconds due to the long time of row-by-row readout, which makes the planar array CIS meet the application requirements of various environments. The line frequency of the linear array scanning CIS is generally from several kHz to hundreds of kHz, so the exposure time thereof can only be several microseconds to tens of microseconds. Increasing the exposure time will seriously reduce the line frequency, so the response rate has become the biggest bottleneck of limiting the linear array scanning CIS. However, the small size and expandable resolution of the linear array scanning CIS have been applied in some environments. In order to meet the use requirements, it is necessary to improve the response rate. Under the premise of a certain pixel process, the user usually improves the response rate by supplementing light to enhance the incident energy, which limits the application environment.

[0004] In order to realize a high response rate, the traditional linear array scanning CIS adopts a multi-line array accumulation mode (TDI), and the transit time of the mode is long, and the readout circuit is complex and is more used in CCDs. SUMMARY

[0005] In order to solve the problems in the prior art, the application provides a dual-pixel simultaneous output high-response-rate linear array CMOS image sensor and method, which can simply and effectively improve the response rate of the linear array CIS. Meanwhile, the technology is still applicable to the TDICIS, and has a double imaging function which other linear array CISs do not have, and has a high improvement on the complex environment applicability of the linear array CIS.

[0006] To achieve the above object, the application provides the following technical scheme:

[0007] A dual-pixel simultaneous output high-response rate linear array CMOS image sensor, comprising a first pixel array, a second pixel array, a programmable gain amplifier, a column buffer driving circuit, a multi-stage high-speed control switch, an analog column logic control circuit, a single-inclined column-level parallel ADC, a chip-level pipeline ADC, a digital column logic, and a multi-channel high-speed LVDS interface module;

[0008] The pixel area of the first pixel array is greater than the pixel area of the second pixel array.

[0009] The first pixel array and the second pixel array are connected to the programmable gain amplifier, one end of the programmable gain amplifier is connected to one end of the column buffer driving circuit, the other end of the column buffer driving circuit is connected to one end of the multi-stage high-speed control switch, the other end of the multi-stage high-speed control switch is connected to one end of the analog column logic control circuit, the other end of the analog column logic control circuit is connected to the single-inclined column-level parallel ADC and the chip-level pipeline ADC respectively, the single-inclined column-level parallel ADC is connected to the digital column logic, and the chip-level pipeline ADC and the digital column logic are both connected to the multi-channel high-speed LVDS interface module.

[0010] Preferably, when the full well charge of the first pixel array and the second pixel array is the same, the pixel area of the first pixel array is 4 times that of the second pixel array, and the photosensitive area of the first pixel array is 8 times that of the second pixel array.

[0011] Preferably, the first pixel array and the second pixel array are single-line arrays or multi-line arrays.

[0012] Preferably, the first pixel array and the second pixel array are simultaneously exposed and quantitatively output, reflecting different imaging properties of the first pixel array and the second pixel array on the same target.

[0013] Preferably, the first pixel array or the second pixel array is individually scanned for imaging.

[0014] Preferably, it further comprises a ramp integrator for providing a comparison reference level.

[0015] Preferably, the data throughput of the multi-channel high-speed LVDS interface module is the sum of the output data amount of the chip-level pipeline ADC and the digital column logic.

[0016] An imaging method of a dual-pixel simultaneous output high-response rate linear array CMOS image sensor, characterized in that it is based on any one of the above-mentioned dual-pixel simultaneous output high-response rate linear array CMOS image sensors, comprising the following processes,

[0017] When the dual-pixel imaging works, the first pixel array and the second pixel array are exposed by a control signal, the analog signal output by the second pixel array is first transmitted to the input end of the programmable gain amplifier, the programmable gain amplifier samples and amplifies and transmits to the single-ramp column-level parallel ADC, the ramp integrator provides a comparison reference level, and the single-ramp column-level parallel ADC enters a quantization stage;

[0018] Then the analog signal output by the first pixel array is transmitted to the input end of the programmable gain amplifier, the programmable gain amplifier samples and amplifies and transmits to the column buffer driving circuit, the column buffer driving circuit is connected with a multi-stage high-speed control switch, the analog column logic control cascaded switch is turned on from s1 to s4096 one by one, the differential signal output by the column buffer is transmitted to the pipeline ADC for digital quantization, the output code D0-D13 is transmitted to the multi-channel high-speed LVDS interface module, and output is completed.

[0019] When the single-pixel imaging works, the exposure of the first pixel array or the second pixel array is selected and turned on by a control signal, the analog signal output by the pixel is first transmitted to the input end of the programmable gain amplifier, the programmable gain amplifier samples and amplifies and transmits to the single-ramp column-level parallel ADC, the ramp integrator provides a comparison reference level, and the single-ramp column-level parallel ADC transmits to the encoder after quantization is completed; the output is driven by the multi-channel high-speed LVDS interface module after the encoding is completed; or,

[0020] The exposure of the first pixel array or the second pixel array is selected and turned on by a control signal, and then the analog signal output by the pixel is transmitted to the input end of the programmable gain amplifier, the programmable gain amplifier samples and amplifies and transmits to the column buffer driving circuit, the column buffer driving circuit is connected with a multi-stage high-speed control switch, the analog column logic control cascaded switch is turned on from s1 to s4096 one by one, the differential signal output by the column buffer is transmitted to the pipeline ADC for digital quantization, and the output code D0-D13 is transmitted to the multi-channel high-speed LVDS interface module, and output is completed.

[0021] Compared with the prior art, the present application has the following beneficial technical effects:

[0022] The application provides a dual-pixel simultaneous output high-response rate linear array CMOS image sensor, which can improve the response rate by about 8 times while keeping the full well capacity constant, and can realize different full well capacities and achieve higher response rate; the application supports dual-pixel image simultaneous output in the exposure time, and can be used in high dynamic light environment and high response rate dark field environment, and supports two kinds of pixel imaging output contrast for target images in the same line scanning cycle. The application realizes two kinds of pixel simultaneous imaging by using a single image sensor, and is compatible with the contradictory indexes of high dynamic range and high response rate, so that the linear array scanning CMOS image sensor can be more widely applied.

[0023] The application can consider the application requirements of high dynamic range in bright field and high response rate in dark field by integrating two kinds of pixels, and the pixel response rate can be improved to more than 8 times of the normal state (without changing the C FD of the premise, otherwise it can be higher), which reduces the demand for light supplementing equipment; in addition, the linear array scanning has time domain characteristics and cannot implement secondary initial imaging for the dynamic target which has changed, the dual-pixel of the design can be exposed and imaged at the same time to generate two images of high dynamic range and high response rate, which has high contrast. Through the dual-pixel simultaneous imaging high response rate linear array CMOS image sensor architecture design, the application environment of high-speed linear array scanning CIS can be greatly expanded. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 It is a column-level working circuit for dual-pixel simultaneous output;

[0025] Figure 2 It is a timing control schematic diagram for dual-pixel;

[0026] Figure 3 It is a high-speed column buffer circuit schematic diagram;

[0027] Figure 4 It is a high-speed cascade control switch;

[0028] Figure 5 It is a column-level ADC working principle diagram;

[0029] Figure 6 It is a chip-level pipeline ADC structure schematic diagram;

[0030] Figure 7 It is a linear array image sensor structure schematic diagram of the application;

[0031] Figure 8 It is a dual-pixel simultaneous output high-response rate linear array CMOS image sensor structure schematic diagram of the application;

[0032] In the figure: 1 is a first pixel array, 2 is a second pixel array, 3 is a programmable gain amplifier, 4 is a column buffer driving circuit, 5 is a multi-stage high-speed control switch, 6 is an analog column logic control circuit, 7 is a ramp integrator, 8 is a single-ramp column-level parallel ADC, 9 is a chip-level pipeline ADC, 10 is a digital column logic, 11 is a multi-channel high-speed LVDS interface module, 12 is an integral ramp generator, 13 is a comparator, 14 is a first column buffer, and 15 is a second column buffer. DETAILED DESCRIPTION

[0033] The application will be further described in conjunction with specific embodiments, which are an explanation of the application rather than a limitation.

[0034] As Figure 1 shown is a dual-pixel simultaneous output column-level working circuit, Figure 2 is a timing control schematic diagram, including a programmable gain amplifier, a multi-stage pipeline sampling switch array, an integral ramp generator 12, a comparator 13, a counter, an encoder, a first column buffer 14, a second column buffer 15, and a pipeline ADC, a general-purpose LVDS is not described here, and CMOS active pixels PIXEL1 and PIXEL2 are omitted in the figure, only the output connection relationship is described. Two kinds of pixels work simultaneously, and a column-level ADC and a chip-level ADC are required, Figure 1 the integral ramp generator used in the column-level ADC, wherein I-sample is an integral current, Cint is an integral capacitor, the ramp generator precision (12 bits / 14 bits / 16 bits) is adjustable, the clock used by the ramp generator is the clock period (ns) of the counter in the ADC module, and the working process is as Figure 3 shown. Figure 6 is a chip-level pipeline ADC structure schematic diagram, which can work at a sampling rate of hundreds of MHz, and when the output is 14 bits, the quantization period is less than half of that of the column-level ADC, which ensures that there is no time-domain competition relationship in the LVDS output, and only the LVDS needs to be greater than the output frequency of the two kinds of ADCs.

[0035] The column buffer circuit in the application is as Figure 4 shown, which is different from the traditional single-buffer structure, in order to take VR and VS output by the PGA as the differential input of the chip-level pipeline ADC, the switches controlling the buffer to the ADC input must be closed at the same time. In order to reduce the RC time constant and achieve the purpose of high-speed output, a two-stage gating switch structure as Figure 4 shown is adopted in the present application. From Figure 4It can be seen that 1024 column switches are divided into 16 groups, each group having 64 switches, and each group of switches sharing one second-level gating switch, and there are 16 second-level gating switches. When sequentially reading out data of a group, the first-level switches of the group are sequentially turned on, the second-level switch is turned on, and the second-level switches of other groups are turned off. Therefore, the equivalent capacitance of the output end of the first-level switch is the sum of the drain capacitances of the 64 switch tubes, and the equivalent capacitance of the output end of the second-level switch is the sum of the drain capacitances of the 16 switch tubes, thus greatly reducing the parasitic capacitance introduced by the switch tube, effectively reducing the RC time constant, and improving the speed of the column buffer circuit.

[0036] When performing double-pixel simultaneous imaging shooting, after the same exposure time is exposed, the second pixel array 2 first outputs a reset signal, and then outputs an exposure signal. After the two are correlated double-sampled and amplified by the programmable gain amplifier, they are respectively sampled and stored on the capacitors Cr1 and Cs1. The column-level ADC quantizes the sampling signal, and the detailed process is shown in the timing control of Figure 2 First, EN1 and Ss are closed, SD is disconnected, the PGA module is enabled, S1, S2, and S3 are closed, and Cr1 sampling buffer outputs VCM (at this time, the PGA works in the buffer state). After sampling is completed, S2, S3, and S1 are disconnected, S4 is closed, the column-level ADC starts to quantize the first reset voltage, S1 and S5 are closed after the column line signal is stable, the capacitor Cs1 samples the photoelectric signal, S5 is disconnected after sampling is completed, S6 is closed, and the column-level ADC starts to quantize the photoelectric signal. The quantization process is long, and EN2 can be selected to be disconnected to ensure low power consumption. While the column-level ADC is quantizing, EN2 is closed, Ss is disconnected, S0, S2, and S7 are closed, Cr2 sampling buffer outputs VCM (at this time, the PGA works in the buffer state), S7 is disconnected after sampling is completed, S8 and SD are closed, and the signal is sent to the column buffer. After the column line signal is stable, S2 and S9 are closed, the capacitor Cs2 samples the photoelectric signal, S9 is disconnected after sampling is completed, S10 and SD are closed, and the Cs2 sampling photoelectric signal is driven and output by the column buffer. At this time, all 4096 columns have completed signal sampling, and are sent to the chip-level pipeline ADC input end for quantization by the high-speed differential sampling switch S11 and S11' (differential pair switch). After quantization is completed, the signal is driven and output by LVDS, and the exposure of the next row is started and the above operation is repeated. The column buffer and the pipeline ADC can have multiple working implementation modes, such as not quantizing the differential signals of VS and VR after the PGA output, but only quantizing VS, or adding a global buffer after the column buffer. Regardless of the design changes, the simultaneous double-pixel imaging function belongs to the scope of the present application.

[0037] When single-pixel imaging is performed, column-level ADC (integrating type) or chip-level ADC can be selected, which will not be described herein, and the single-pixel imaging readout architecture is not within the scope of the present application, but the on-chip dual-ADC architecture is within the scope of the present application.

[0038] The dual-pixel simultaneous imaging high-response rate linear array CMOS image sensor architecture design described in the present application is generally used for linear array scanning / time delay integration (TDI) based CMOS image sensors.

[0039] As shown in Figure 8 The dual-pixel simultaneous imaging high-response rate linear array CMOS image sensor architecture design of the present application includes a first pixel array 1, a second pixel array 2, a programmable gain amplifier 3 with a correlated double sampling design, a column buffer driving circuit 4, a multi-stage high-speed control switch 5, an analog column logic control circuit 6, a slope integrator 7, a single-slope column-level parallel ADC 8, a chip-level pipeline ADC 9, a digital column logic 10, and a multi-channel high-speed LVDS interface module 11.

[0040] The biggest difference between the present application and the conventional linear array CMOS image sensor includes the first pixel array 1 and the second pixel array 2, the on-chip two ADC quantization single-slope column-level parallel ADC 8 and the chip-level pipeline ADC 9. FD When the full well capacity (C The pixel area of the first pixel array 1 is 4 times that of the second pixel array 2, and the light-sensitive area of the first pixel array 1 can reach about 8 times that of the second pixel array 2, and under the same exposure conditions, the first pixel array 1 has a higher response rate. The analog signal digital quantization uses the single-slope column-level parallel ADC 8 and the side chip-level pipeline ADC 9, the readout interval time of the first pixel array 1 and the second pixel array 2 is very short, the data amount of the first pixel array 1 is only half of that of the second pixel array 2, the analog signal output by the first pixel array 1 is quantized by the chip-level pipeline ADC 9 and output before the quantization is completed by the single-slope column-level parallel ADC 8, the analog signal output by the second pixel array 2 is quantized by the single-slope column-level parallel ADC 8, and the quantization of the next exposure signal of the second pixel array 2 is performed after the quantization is completed, and the pipeline works. The data throughput of the multi-channel high-speed LVDS interface module 11 is the sum of the data output by the chip-level pipeline ADC 9 and the digital column logic 10.

[0041] The first pixel array 1 and the second pixel array 2 can be of any size ratio, and can contain a single linear array or a multi-linear array (TDI CIS), and the size and linear array scale in the figure are only an example; two ADCs exist on the chip at the same time, one is a single slope integration type, and the other can be a pipeline ADC or a SAR ADC.

[0042] The mainstream pixel size of the linear array scanning CIS in the current market is 7*7, and the vertical resolution can reach 4k. The larger pixel area is to improve the light response rate as much as possible, and the 4k vertical resolution is mainly limited by the manufacturing process (mask plate). For a single linear array scanning CIS, drum exposure has better signal-to-noise ratio and does not affect the line frequency. In the present application, the first pixel array 1 and the second pixel array 2 can be selected in multiple sizes, and the ratio can be selected as 1:1, 1:4, 1:9, etc., and the corresponding output will change by the same ratio. Two ADCs on the chip are for double-pixel simultaneous imaging, and the chip area is minimized.

[0043] The first pixel array 1 and the second pixel array 2 can be simultaneously exposed and quantized to output, reflecting the different imaging properties of the two pixels to the same target, or only the first pixel array 1 or the second pixel array 2 can be selected for single scanning imaging. Especially when the first pixel array 1 is scanned alone, because of the halving of the data volume and the high-speed chip-level pipeline ADC 9, the line frequency can be greatly improved.

[0044] The single slope column-level parallel ADC 8 needs to quantize the reset signal and the photoelectric signal output by the pixel twice, and then output the quantized value after quantization. The quantization period is relatively long; the chip-level pipeline ADC 9 takes the reset signal and the photoelectric signal output by the pixel as the differential input, and can complete the quantization of 1 column of analog signals and output within one clock period. It is necessary to ensure that the 8 has not completed the final quantization before the end of its quantization, otherwise it will affect the line frequency speed.

[0045] The column buffer driving circuit 4, the multi-stage high-speed control switch 5, and the analog column logic control circuit 6 are all for providing a working environment for the chip-level ADC 9. The single slope column-level parallel ADC 8 can directly select the programmable gain amplifier 3, the column buffer driving circuit 4, and the multi-stage high-speed control switch 5 and quantize the analog signal.

[0046] Typical dual-pixel simultaneous imaging working process: the first pixel array 1 and the second pixel array 2 are opened by the control signal, the analog signal output by the second pixel array 2 is first transmitted to the PGA input end, the PGA is sampled and amplified to deliver to the single slope column-level parallel ADC 8, the slope integrator 7 provides a comparison reference level, and the single slope column-level parallel ADC 8 enters the quantization stage; then the analog signal output by the first pixel array 1 is transmitted to the PGA input end, the PGA is sampled and amplified to deliver to the column buffer driving circuit 4, the buffer output is connected to the high-speed cascade switch, the analog column logic controls the cascade switch to be turned on from s1 to s4096 one by one, the column buffer output differential signal is delivered to the chip-level pipeline ADC 9 for digital quantization, the output code D0-D13 is transmitted to the multi-channel high-speed LVDS interface module 11, and the output is completed; after the quantization of the chip-level pipeline ADC 9 is completed, the single slope column-level parallel ADC 8 decimal comparison value is output to the multi-channel high-speed LVDS interface module 11 by the counter, and the output is completed. During the quantization process of the pipeline ADC and the single slope ADC, the pixel starts the next exposure control, and the above operation is repeated to form a high-speed flow exposure output. Since the photodiode area of the first pixel array 1 is much larger than that of the second pixel array 2, the image brightness of the first pixel array 1 is higher under the same incident light, which is crucial for dark field applications.

[0047] Single-pixel imaging working process 1: the exposure of the first pixel array 1 or the second pixel array 2 is selected and opened by the control signal, the pixel output analog signal is first transmitted to the PGA input end, the PGA is sampled and amplified to deliver to the single slope column-level parallel ADC 8, the slope integrator 7 provides a comparison reference level, and the single slope column-level parallel ADC 8 delivers to the encoder after quantization. After the encoding is completed, it is output by the multi-channel LVDS drive, and the row frequency in this working state is consistent with the above-mentioned dual-pixel simultaneous imaging;

[0048] Single-pixel imaging working process 2: the exposure of the first pixel array 1 or the second pixel array 2 is selected and opened by the control signal, and then the pixel output analog signal is transmitted to the PGA input end, the PGA is sampled and amplified to deliver to the column buffer driving circuit 4, the buffer output is connected to the high-speed cascade switch, the analog column logic controls the cascade switch to be turned on from s1 to s4096 one by one, the column buffer output differential signal is delivered to the chip-level pipeline ADC 9 for digital quantization, the output code D0-D13 is transmitted to the multi-channel high-speed LVDS interface module 11, and the output is completed. The row frequency in this working state can be more than twice that of working process 1, and has higher column consistency.

[0049] The above is further detailed description of the present application in combination with specific preferred embodiments, and cannot be deemed as limitation of the specific embodiments of the present application. For those skilled in the art of the present application, without departing from the idea of the present application, several simple replacements can be designed, and all should be deemed as falling within the protection scope determined by the claims submitted by the present application.

Claims

1. A dual-pixel simultaneous output high-response-rate linear CMOS image sensor, characterized in that, It includes a first pixel array (1), a second pixel array (2), a programmable gain amplifier (3), a column buffer drive circuit (4), a multi-level high-speed control switch (5), an analog column logic control circuit (6), a single-slope column-level parallel ADC (8), a chip-level pipeline ADC (9), digital column logic (10), and a multi-channel high-speed LVDS interface module (11). The pixel area of ​​the first pixel array (1) is larger than the pixel area of ​​the second pixel array (2); The first pixel array (1) and the second pixel array (2) are connected to a programmable gain amplifier (3). The programmable gain amplifier (3) is connected to one end of a column buffer drive circuit (4). The other end of the column buffer drive circuit (4) is connected to one end of a multi-level high-speed control switch (5). The other end of the multi-level high-speed control switch (5) is connected to one end of an analog column logic control circuit (6). The other end of the analog column logic control circuit (6) is connected to a single-slope column-level parallel ADC (8) and a chip-level pipeline ADC (9), respectively. The single-slope column-level parallel ADC (8) is connected to a digital column logic (10). The chip-level pipeline ADC (9) and the digital column logic (10) are both connected to a multi-channel high-speed LVDS interface module (11). The analog signal output by the first pixel array (1) is controlled by the chip-level pipeline. The ADC (9) performs high-speed quantization and outputs the signal before the single-slope column-parallel ADC (8) completes quantization. The analog signal output by the second pixel array (2) is quantized by the single-slope column-parallel ADC (8). After the quantization is completed, the next exposure signal of the second pixel array (2) is quantized, and the pipeline works.

2. The dual-pixel simultaneous output high-response-rate linear CMOS image sensor according to claim 1, characterized in that, When the full-well charge of the first pixel array (1) and the second pixel array (2) is the same, the pixel area of ​​the first pixel array (1) is 4 times that of the second pixel array (2), and the photosensitive area of ​​the first pixel array (1) is 8 times that of the second pixel array (2).

3. The dual-pixel simultaneous output high-response-rate linear CMOS image sensor according to claim 1, characterized in that, The first pixel array (1) and the second pixel array (2) are single-line arrays or multi-line arrays.

4. The dual-pixel simultaneous output high-response-rate linear CMOS image sensor according to claim 1, characterized in that, The first pixel array (1) and the second pixel array (2) are exposed and quantized simultaneously to reflect the different imaging properties of the first pixel array (1) and the second pixel array (2) on the same target.

5. The dual-pixel simultaneous output high-response-rate linear CMOS image sensor according to claim 1, characterized in that, The first pixel array (1) or the second pixel array (2) is scanned individually for imaging.

6. The dual-pixel simultaneous output high-response-rate linear CMOS image sensor according to claim 1, characterized in that, It also includes a ramp integrator (7) which is used to provide a comparison reference level.

7. A dual-pixel simultaneous output high-response-rate linear CMOS image sensor according to claim 1, characterized in that, The data throughput of the multi-channel high-speed LVDS interface module (11) is the sum of the output data of the chip-level pipeline ADC (9) and the digital column logic (10).

8. An imaging method for a dual-pixel simultaneous output high-response-rate linear CMOS image sensor, characterized in that, A dual-pixel simultaneous output high-response-rate linear CMOS image sensor according to any one of claims 1 to 7 includes the following process. When dual-pixel imaging is working, the exposure of the first pixel array (1) and the second pixel array (2) is turned on by the control signal. First, the analog signal output by the second pixel array (2) is transmitted to the input of the programmable gain amplifier (3). The programmable gain amplifier (3) samples and amplifies the signal and sends it to the single-slope column-parallel ADC (8). The ramp integrator (7) provides the comparison reference level. The single-slope column-parallel ADC (8) enters the quantization stage. Then, the analog signal output from the first pixel array (1) is transmitted to the input of the programmable gain amplifier (3). The programmable gain amplifier (3) samples and amplifies the signal and sends it to the column buffer drive circuit (4). The output of the column buffer drive circuit (4) is connected to the multi-stage high-speed control switch (5). The analog column logic control cascade switches are turned on one by one from s1 to s4096, and the differential signal output from the column buffer is sent to the pipeline ADC (9) for digital quantization. The output codes D0 to D13 are transmitted to the multi-channel high-speed LVDS interface module (11) to complete the output. After the pipeline ADC (9) is quantized, the decimal comparison value of the single-slope column-parallel ADC (8) is encoded by the counter and output to the multi-channel high-speed LVDS interface module (11) to complete the output. When single-pixel imaging is in operation, the control signal selects to enable the exposure of the first pixel array (1) or the second pixel array (2). First, the analog signal output by the pixel is transmitted to the input of the programmable gain amplifier (3). The programmable gain amplifier (3) samples and amplifies the signal and sends it to the single-slope column-parallel ADC (8). The ramp integrator (7) provides the comparison reference level. After quantization, the single-slope column-parallel ADC (8) sends the signal to the encoder. After encoding, the output is driven by the multi-channel high-speed LVDS interface module (11). Or, The exposure of the first pixel array (1) or the second pixel array (2) is selected by the control signal. Then the pixel output analog signal is transmitted to the input of the programmable gain amplifier (3). The programmable gain amplifier (3) samples and amplifies the signal and sends it to the column buffer drive circuit (4). The output of the column buffer drive circuit (4) is connected to the multi-level high-speed control switch (5). The analog column logic control cascade switches are turned on one by one from s1 to s4096. The column buffer output differential signal is sent to the pipeline ADC (9) for digital quantization. The output code D0~D13 is transmitted to the multi-channel high-speed LVDS interface module (11) to complete the output.

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