Active region structure and formation method of vertical channel memory

Abstract

This application provides an active region structure for a vertical channel memory and a method for forming the same. The method includes: providing a substrate having multiple closed-ring mask structures; etching multiple closed-ring active region cells on the substrate using the multiple closed-ring mask structures; depositing an isolation layer on the substrate and planarizing it to expose the surfaces of all the closed-ring active region cells; and cutting off the opposite two sides of each closed-ring active region cell to form mutually isolated first and second active regions. This technical solution, by cutting off the opposite two sides of the closed-ring active region cells to form mutually isolated first and second active regions, ensures that the two ends of the first and second active regions are subjected to balanced forces, thereby avoiding bit line short circuits caused by bottom pattern misalignment at the two ends of the active regions.

Description

Technical Field

[0001] This invention relates to the field of memory manufacturing, and more particularly to an active region structure of a vertical channel memory and a method for forming the same. Background Technology

[0002] Vertical channel memory architecture (VCAT) offers higher storage density compared to traditional architecture (BCAT), with a more compact distribution of active areas (AA). The active areas are manufactured using self-aligned line technology, which increases their depth.

[0003] However, when cutting the active region after the depth is increased, the uneven force at both ends of the active region can easily lead to pattern bending during the cleaning and filling process. Furthermore, due to the etching loading effect, the bottom pattern at both ends of the active region is prone to misalignment, which can lead to short circuits in the bit lines.

[0004] Therefore, how to improve the uneven force distribution at both ends of the active region to avoid bit line short circuits caused by pattern misalignment is a technical problem that needs to be solved. Summary of the Invention

[0005] The technical problem to be solved by this application is to provide an active region structure of a vertical channel memory and a method for forming it, thereby improving the uneven force at both ends of the active region and avoiding bit line short circuits caused by pattern misalignment.

[0006] To address the aforementioned problems, this application provides a method for forming an active region structure of a vertical channel memory. The method includes: providing a substrate having multiple closed-ring mask structures; etching the substrate using the multiple closed-ring mask structures to obtain multiple closed-ring active region cells; depositing an isolation layer on the substrate and planarizing it to expose the surfaces of all the closed-ring active region cells; and cutting off the opposite two sides of each of the closed-ring active region cells to form mutually isolated first and second active regions.

[0007] In some embodiments, the step of cutting off the opposite two sides of each of the closed annular active region units to form mutually isolated first and second active regions further includes: etching at the first side of the closed annular active region unit near the third side and at the second side of the closed annular active region unit near the fourth side, respectively, to form mutually isolated first and second active regions, wherein the first side and the second side are the opposite two sides of the closed annular active region unit, and the etching depth is greater than or equal to the thickness of the isolation layer.

[0008] In some embodiments, the method further includes: depositing an isolation material on the substrate and planarizing it to expose the surfaces of all the first active regions and the second active regions.

[0009] In some embodiments, the first active region and the second active region are centrally symmetrically distributed, with the first end of the second active region located on the extension line of the second end of the first active region, and the second end of the second active region located on the extension line of the first end of the first active region.

[0010] In some embodiments, the step of providing a substrate having a plurality of closed annular mask structures further includes: providing a substrate comprising a substrate body, an isolation layer, a polysilicon layer, a hard mask layer, a protective layer, and a photoresist structure sequentially formed on the substrate body; etching the substrate using the photoresist structure to expose the polysilicon layer to obtain a plurality of strip patterns with substantially the same shape; and removing all the strip patterns after depositing an isolation material on the sidewalls of each strip pattern to obtain a substrate having a plurality of closed annular mask structures.

[0011] In some embodiments, the insulating layer is made of an oxide material.

[0012] In some embodiments, the planarization is achieved using chemical mechanical polishing (CMP).

[0013] This application also provides an active region structure for a vertical channel memory, the structure comprising: a substrate; a first active region and a second active region formed on the substrate and isolated from each other by an isolation layer, wherein a first end of the second active region is located on an extension line of a second end of the first active region, and a second end of the second active region is located on an extension line of a first end of the first active region.

[0014] In some embodiments, the first active region and the second active region are centrally symmetrically distributed.

[0015] In some embodiments, the height of the isolation layer is greater than or equal to the heights of the first active region and the second active region.

[0016] The above technical solution cuts off the opposite two sides of the closed ring active region unit, so that the first and second active regions formed by mutual isolation have a three-sided structure, so that the two ends of the first and second active regions are subjected to balanced forces, thereby avoiding bit line short circuits caused by bottom pattern misalignment at the two ends of the active regions.

[0017] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this application. Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the specific implementation of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figures 1A to 1F This is a schematic diagram of the fabrication process for forming active region structures in existing technologies;

[0020] Figure 2 This is a flowchart of a method for forming the active region structure of a vertical channel memory in one embodiment of this application;

[0021] Figures 3A to 3D This is a schematic diagram of the fabrication process of a substrate forming multiple closed ring mask structures in one embodiment of this application;

[0022] Figures 4A-4B This is a schematic diagram of the fabrication process for forming multiple closed-ring active region units in one embodiment of this application;

[0023] Figures 5A-5B This is a schematic diagram of the fabrication process of depositing and planarizing an isolation layer in one embodiment of this application;

[0024] Figure 6 This is a schematic diagram of cutting off the active region in one embodiment of this application;

[0025] Figure 7 In one embodiment of this application, the trailing edge of the active region is cut off. Figure 6 A schematic diagram of the cross section of line B-B' in the middle;

[0026] Figure 8 This is a schematic diagram of the active region structure of a vertical channel memory in one embodiment of this application. Detailed Implementation

[0027] The technical solutions of the specific embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described specific embodiments are only a part of the specific embodiments of this disclosure, and not all of the specific embodiments. Based on the specific embodiments in this application, all other specific embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0028] Please refer to the following: Figures 1A to 1F This is a schematic diagram of the fabrication process for forming an active region structure in the prior art, where the X, Y, and Z directions are perpendicular to each other. Specifically, a substrate 1 is provided, which includes: a substrate body 11, an isolation layer 12, and a polysilicon layer 13, as shown below. Figure 1A As shown; a patterned polysilicon layer 13, with an annular mask structure 2 formed on the upper surface of the polysilicon layer 13, as shown. Figure 1B As shown; a protective layer 3 is deposited on the upper surface of the polycrystalline silicon layer 13, such as... Figure 1C As shown; the mask structure 2 not covered by the protective layer 3 is removed, and the protective layer 3 is removed to form a strip-shaped mask structure 2, as shown. Figure 1D As shown; using the strip-shaped mask structure 2 as a mask, the polysilicon layer 13 is etched downwards until the isolation layer 12 is reached, as follows. Figure 1E As shown; after removing the isolation layer 12 and the strip-shaped mask structure 2, the polysilicon layer 13 is etched downwards to form the active region 14, as shown. Figure 1F As shown. Because the protective layer 3 is also serrated due to the use of a serrated mask, the active regions 14 in the prior art are arranged in an odd-even, long-short pattern. However, when using the back-side self-aligned bit lines, the depth of the active regions 14 increases, and the forces on both ends of the active regions 14 after cutting are uneven, which makes it easy for the cleaning and filling process to produce pattern bending, further leading to bit line short circuits.

[0029] To improve the uneven force distribution at both ends of the active region and avoid bit line short circuits caused by pattern misalignment, this application provides an active region structure and its formation method for a vertical channel memory. By cutting off the opposite two sides of the closed ring active region cell, the formed mutually isolated first and second active regions are arranged in a three-sided structure, so that the forces at both ends of the first and second active regions are balanced, thereby avoiding bit line short circuits caused by bottom pattern misalignment at both ends of the active region.

[0030] The following section first introduces a method for forming the active region structure of a vertical channel memory provided in a specific embodiment of this application.

[0031] Figure 2This is a flowchart of a method for forming an active region structure of a vertical channel memory according to an embodiment of this application. The method includes: step S201, providing a substrate having multiple closed-ring mask structures; step S202, etching on the substrate using the multiple closed-ring mask structures to obtain multiple closed-ring active region cells; step S203, depositing an isolation layer on the substrate and planarizing it to expose the surface of all the closed-ring active region cells; step S204, cutting off the opposite two sides of each closed-ring active region cell to form a first active region and a second active region that are isolated from each other.

[0032] Please see Figures 3A to 3D This is a schematic diagram illustrating the fabrication process of a substrate forming multiple closed-ring mask structures in one embodiment of this application. Specifically, step S201, which involves providing a substrate with multiple closed-ring mask structures, further includes: providing a substrate 1, wherein the substrate 1 includes a substrate body 11, an isolation layer 12, a polysilicon layer (POLY) 13, a hard mask layer 14, a protective layer 15, and a photoresist structure 16 sequentially formed on the substrate body 11, such as... Figure 3A As shown; the photoresist structure 16 is used to etch the polysilicon layer 13 onto the substrate 1 to expose it, resulting in multiple strip patterns with essentially the same shape, such as... Figure 3B As shown, (a) is a top view of the substrate, and (b) is a cross-sectional view of the film layer corresponding to (a); an isolation material is deposited on the sidewalls of each strip pattern, such as... Figure 3C As shown, (a) is a top view of the substrate, and (b) is a cross-sectional view of the film layer corresponding to (a); all the strip patterns are etched away to obtain a substrate with multiple closed annular mask structures 2, as shown. Figure 3D As shown, (a) is a top view of the base, and (b) is a view along... Figure 3D The cross-sectional view of the film layer corresponding to line A-A' in part (a). In this embodiment, the photoresist structure 16 is a strip pattern extending in the Y direction and spaced apart in the X direction.

[0033] In some embodiments, the substrate body 11 may be a silicon substrate, the photoresist structure 16 may be made of enhanced photoresist (PR), the isolation layer 12 may be made of oxide (OX), the protective layer 15 may be made of silicon oxynitride (SION), and the hard mask layer 14 may be made of carbon film (AC).

[0034] Specifically, in step S202, multiple closed-ring mask structures 2 are used to etch multiple closed-ring active region units 111 on the substrate, as shown in the cross-sectional view of the film layer. Figure 4A As shown, its top view is as follows Figure 4B As shown.

[0035] Specifically, in step S203, an isolation layer 4 is deposited on the substrate and planarized to expose the surfaces of all the closed annular active region units 111, as shown in the cross-sectional view of the film layer. Figure 5A As shown, its top view is as follows Figure 5B As shown. In some embodiments, the material of the isolation layer 4 is an oxide, and the planarization is achieved by chemical mechanical polishing (CMP).

[0036] In some embodiments, the step S204 of cutting off the opposite two sides of each of the closed annular active region units to form mutually isolated first active regions and second active regions further includes: etching at the first side of the closed annular active region unit near the third side and at the second side near the fourth side, respectively, to form mutually isolated first active regions 112 and second active regions 113, wherein the first side and the second side are the opposite two sides of the closed annular active region unit, and the etching depth is greater than or equal to the deposition thickness of the isolation material. Figure 6 This is a schematic diagram of cutting off the active region in one embodiment of this application. Please refer to the following: Figure 6 In this embodiment, the mask used to cut off the active region is a square mask 5. In other embodiments, other shapes of masks may be used. The length of the mask in the X direction is greater than the width of the closed annular active region unit 111 and less than the length from the edge to the center of the closed annular active region unit 111 in the X direction. Figure 7 In one embodiment of this application, the trailing edge of the active region is cut off. Figure 6 A schematic cross-sectional view of line B-B'. Please refer to the following. Figure 7 In this embodiment, the etching depth of the active region is greater than or equal to the thickness of the isolation layer 4.

[0037] In some embodiments, the method further includes: depositing an isolation material on the substrate and planarizing it to expose the surfaces of all the first active regions 112 and the second active regions 113, such as... Figure 8 As shown, (a) is its top view, and (b) is the cross-sectional view of the membrane layer corresponding to (a). In this embodiment, the first active region 112 and the second active region 113 are centrally symmetrically distributed. The first end of the second active region 113 is located on the extension line of the second end of the first active region 112, and the second end of the second active region 113 is located on the extension line of the first end of the first active region 112.

[0038] The above technical solution cuts off the opposite two sides of the closed ring active region unit 111, so that the first active region 112 and the second active region 113 formed by mutual isolation are in a three-sided structure, so that the two ends of the first active region 112 and the second active region 113 are subjected to balanced forces, so as to avoid bit line short circuit caused by bottom pattern misalignment at the two ends of the active region.

[0039] Corresponding to the specific implementation of the above method, this application also provides an active region structure for a vertical channel memory, formed using the method described above. Please refer to the following: Figure 8 In portions (a) and (b) of the above, the active region structure of the vertical channel memory includes: a substrate body 11; a first active region 112 and a second active region 113 formed on the substrate body 11 and isolated from each other by an isolation layer 4, wherein the first end of the second active region 113 is located on the extension line of the second end of the first active region 112, and the second end of the second active region 113 is located on the extension line of the first end of the first active region 112.

[0040] In this embodiment, the first active region 112 and the second active region 113 are centrally symmetrically distributed.

[0041] In some embodiments, the height of the isolation layer 4 is greater than or equal to the height of the first active region 112 and the second active region 113. The isolation layer 4 is used to isolate the first active region 112 and the second active region 113. The formation method of the isolation layer 4 is described above and will not be repeated here.

[0042] The above technical solution cuts off the opposite two sides of the closed ring active region unit 111, so that the first active region 112 and the second active region 113 formed by mutual isolation are in a three-sided structure, so that the two ends of the first active region 112 and the second active region 113 are subjected to balanced forces, so as to avoid bit line short circuit caused by bottom pattern misalignment at the two ends of the active region.

[0043] It should be noted that, in this document, relational terms such as "second" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "also includes a..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0044] The various specific embodiments in this specification are described in a related manner. Similar or identical parts between the different embodiments can be referred to interchangeably. Each specific embodiment focuses on its differences from other embodiments. In particular, the method embodiments are basically similar to the structural embodiments, so the descriptions are relatively simple; relevant parts can be found in the descriptions of the structural embodiments.

[0045] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this invention, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A method of forming an active region structure of a vertical channel memory, characterized by, The method comprises: providing a substrate with a plurality of closed ring mask structures; etching on the substrate using the plurality of closed ring mask structures to obtain a plurality of closed ring active region units; depositing an isolation layer on the substrate and planarizing to expose the surfaces of all the closed ring active region units; cutting off opposite two side edges of each of the closed ring active region units to form a first active region and a second active region isolated from each other, a first end of the second active region being located on an extension line of a second end of the first active region, and a second end of the second active region being located on an extension line of a first end of the first active region.

2. The method of claim 1, wherein, The step of cutting off opposite two side edges of each of the closed ring active region units to form a first active region and a second active region isolated from each other further comprises: etching at a first side edge close to a third side edge and a second side edge close to a fourth side edge of the closed ring active region unit respectively to form a first active region and a second active region isolated from each other, wherein the first side edge and the second side edge are opposite two side edges of the closed ring active region unit, and the etching depth is greater than or equal to the thickness of the isolation layer.

3. The method of claim 1, wherein, The method further comprises: depositing an isolation material on the substrate and planarizing to expose the surfaces of all the first active regions and second active regions.

4. The method of claim 1, wherein, The first active region and the second active region are centrally symmetrically distributed.

5. The method of claim 1, wherein, The step of providing a substrate with a plurality of closed ring mask structures further comprises: providing a base, the base comprising a substrate body, an isolation layer, a polysilicon layer, a hard mask layer, a protective layer and a photoresist structure formed on the substrate body in sequence; etching on the base using the photoresist structure to expose the polysilicon layer to obtain a plurality of strip patterns with substantially the same shape; depositing an isolation material on the sidewall of each of the strip patterns and then removing all the strip patterns to obtain a substrate with a plurality of closed ring mask structures.

6. The method according to any one of claims 1, 3, 5, characterized in that, The material of the isolation layer is an oxide.

7. The method according to any one of claims 1, 3, 5, characterized in that, The planarization is realized by chemical mechanical polishing.

8. An active region structure for a vertical channel memory, comprising: The method comprises: a substrate body; a first active region and a second active region formed on the substrate body and isolated from each other by an isolation layer, the first active region and the second active region being formed in a three-edge structure by cutting off opposite two side edges of a closed ring active region unit, wherein a first end of the second active region is located on an extension line of a second end of the first active region, and a second end of the second active region is located on an extension line of a first end of the first active region.

9. The structure of claim 8, wherein The first active region and the second active region are centrally symmetrically distributed.

10. The structure of claim 8, wherein The height of the isolation layer is greater than or equal to the height of the first active region and the second active region.

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