Parallel processing for vehicle path planning suitable for parking

Abstract

The present disclosure relates to parallel processing for vehicle path planning suitable for parking. To determine a path through a posture configuration space, the trajectory of the posture can be evaluated in parallel based on at least translating the trajectory along at least one axis of the posture configuration space (e.g., an azimuth axis). The trajectory can include at least a portion of a turn with a fixed turning radius. Turns or portions of turns with the same turning radius and initial orientation can be translated along the azimuth axis and processed in parallel because they are translated copies of each other but have different starting points. The trajectory can be evaluated based on at least a processing variable used to evaluate reachability as a bit vector, where threads effectively synchronize the execution of large vector operations. A parallel reduction pattern can be used to interpret dependencies that may exist between various segments of the trajectory for evaluating reachability, thereby allowing these segments to be processed in parallel.

Description

Background Art

[0001] To control a vehicle or other manipulable object, a proposed path can be determined from a current pose (e.g., position and orientation) of the vehicle to a target pose of the vehicle (e.g., for an autonomous parking maneuver). Determining the proposed path for the vehicle can include exploring potential paths in a configuration space under nonholonomic constraints imposed by the vehicle kinematics. Traditional approaches to this problem may use a graph search with heuristics (e.g., A*) to reduce the search space by incentivizing early exploration of promising paths. However, the optimal path may not be immediately apparent and therefore may not be identifiable in the scene. Similarly, environments where heuristics cannot be accurately applied as heuristics may not be applicable in all situations.

[0002] Furthermore, the algorithms used by traditional systems may only be moderately parallelizable. For example, a parallel implementation of A* has been developed that uses eight processing threads to produce a fourfold speedup. However, modern parallel processors offer thousands of processor cores, enabling much higher levels of parallelism. Due to the limited parallelization offered by traditional methods, the density of the configuration space explored is typically relatively sparse, allowing for computationally efficient path determination. That is, if the configuration space is too dense, identifying paths using traditional methods may take too long or consume too many resources to be practical. Therefore, the number of potential paths that can be determined may be limited by the density of the configuration space. Summary of the Invention

[0003] Embodiments of the present disclosure relate to massively parallel vehicle path planning suitable for parking. Disclosed are systems and methods for determining a vehicle's path through a posture configuration space in a highly parallelized manner.

[0004] Compared to conventional methods such as those described above, the disclosed method can be used to rapidly explore paths (e.g., all paths) in a dense pose configuration space in parallel with determining a path through the pose configuration space. Pose trajectories in the pose configuration space can be evaluated in parallel based on at least translating the trajectory along at least one axis of the pose configuration space (e.g., the θ axis representing the vehicle's orientation). In at least one embodiment, the trajectory can include at least a portion of a turn with a fixed turn radius. Turns with the same turn radius and initial orientation can be translated along the θ axis and processed in parallel because they are translated copies of each other but have different starting points (x, y). In a further aspect, the trajectory can be evaluated based on at least a processing variable used to evaluate reachability as a bit vector. Each processing thread can perform logical bitwise operations to control the propagation of reachability while avoiding conditional processing or branching so that threads can efficiently perform large vector operations synchronously. The disclosed method can use a parallel reduction pattern to interpret dependencies that may exist between various segments of the trajectory to evaluate reachability, thereby allowing these segments to be processed in parallel. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The parallel processing system and method for vehicle path planning for parking of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0006] Figure 1A is a diagram of an example including a path planner according to some embodiments of the present disclosure;

[0007] Figure 1B It is shown that some embodiments according to the present disclosure may include Figure 1A Illustration of additional elements in the path planner;

[0008] Figure 2 is a diagram illustrating an example of a pose configuration space that may be used to model vehicle pose according to some embodiments of the present disclosure;

[0009] Figure 3 shows an example of a motion model that may be used to define a vehicle's trajectory through a pose configuration space according to some embodiments of the present disclosure;

[0010] Figure 4 is a diagram illustrating an example of a footprint occupied by a gesture in a captured gesture configuration space according to some embodiments of the present disclosure;

[0011] Figure 5 shows examples of turns of different turn types that may be evaluated in a pose configuration space according to some embodiments of the present disclosure;

[0012] Figure 6Ashows an example of a spiral of turns arranged in a pose configuration space according to some embodiments of the present disclosure;

[0013] Figure 6B Some embodiments of the present disclosure are shown Figure 6A An example of a spiral of a turn together with a spiral of another turn that is a translated copy of the turn arranged in pose configuration space;

[0014] Figure 6C According to some embodiments of the present disclosure, Figure 6B An example of a displacement trajectory formed by a spiral;

[0015] Figure 7 is an illustration of how a straight driving path is conceptually mapped into a pose configuration space according to some embodiments of the present disclosure;

[0016] Figure 8 shows an example of a computational flow chart that may be used to process turns according to some embodiments of the present disclosure, where reachability is encoded using a binary value;

[0017] Figure 9 shows an example of a computational flow chart that may be used for processing turns where reachability is encoded using non-binary values, according to some embodiments of the present disclosure;

[0018] Figure 10 is a flow chart illustrating a method for determining a shift pose of a pose configuration space to determine a path through the pose configuration space according to some embodiments of the present disclosure;

[0019] Figure 11 is a flow chart illustrating a method 1100 for translating a trajectory of a pose in a pose configuration space into a shifted trajectory to determine a path through the pose configuration space, according to some embodiments of the present disclosure;

[0020] Figure 12 is a flow chart illustrating a method 1200 for evaluating the reachability of segments of a trajectory in parallel, according to some embodiments of the present disclosure;

[0021] Figure 13A is an illustration of an example autonomous vehicle according to some embodiments of the present disclosure;

[0022] Figure 13B According to some embodiments of the present disclosure Figure 13A Examples of camera positions and fields of view for autonomous vehicles;

[0023] Figure 13C According to some embodiments of the present disclosure Figure 13A a block diagram of an example system architecture for an example autonomous vehicle;

[0024] Figure 13D is a method for one or more cloud-based servers and Figure 13A System diagram of an example of communication between autonomous vehicles;

[0025] Figure 14 is a block diagram of an example computing device suitable for implementing some embodiments of the present disclosure; and

[0026] Figure 15 is a block diagram of an example data center suitable for implementing some embodiments of the present disclosure. DETAILED DESCRIPTION

[0027] Systems and methods are disclosed related to parallel processing of vehicle path planning suitable for parking. Although the present disclosure may be directed to an example autonomous vehicle 1300 (also referred to herein as "vehicle 1300" or "host vehicle 1300"), its example Figures 13A-13D The present disclosure may be described with respect to path or route planning for autonomous or semi-autonomous driving, but this is not intended to be limiting, and the systems and methods described herein may be used for path planning in augmented reality, virtual reality, mixed reality, robotics, security and surveillance, autonomous or semi-autonomous machine applications, and / or any other technology space where path or route planning may be used.

[0028] In parking applications, the goal may be to maneuver a vehicle into a parking space (e.g., within approximately line of sight) under nonholonomic constraints while avoiding collisions with obstacles (e.g., other vehicles, posts, fences, walls, parking structures, pedestrians, etc.). Disclosed are systems and methods for determining a path for a vehicle from a current pose to a target pose in a pose configuration space (e.g., a multi-point turn suitable for parking or maneuvering in a tight area), where the pose may be in free space or blocked by obstacles (e.g., perceived obstacles based on vehicle sensor data). That is, there may be several different paths from the current pose to the target pose, and each path may consist of a different combination of turns (e.g., sharp left, slight left, straight, slight right, and sharp right) and direction (e.g., forward and reverse). Furthermore, one or more obstacles may be located along one or more paths. The disclosed method can be used to evaluate paths to identify a recommended path around obstacles and the target pose based on one or more criteria (e.g., shortest distance, fastest, fewest number of turns, etc.).

[0029] When determining a recommended path from a current pose to a target pose (e.g., within a set of target poses), the disclosed method can be used to quickly explore paths (e.g., all paths) in a dense pose configuration space in parallel. An iterative approach can be used, where the reachability of a set of trajectories can be evaluated in parallel in an iteration, and the results can be used as input to evaluate the reachability of a set of trajectories (or a different set of trajectories) in a subsequent iteration (effectively expanding the reachable trajectories by additional trajectories). By thoroughly exploring the possibilities of paths, poor quality path recommendations can be avoided. While traditionally this workload may be too large to be practically performed in a dense pose configuration space, the disclosed method allows for massive parallelism and can take advantage of modern parallel processing architectures (e.g., with thousands of cores and / or threads). As a result, a dense pose configuration space can be explored faster, more efficiently, and / or at a much lower granularity (e.g., higher spatial and angular density) than before.

[0030] In at least one embodiment, a pose configuration space can represent the pose of a vehicle in an environment, using at least an x-axis and a y-axis to represent the position of the vehicle and a θ-axis to represent the orientation (e.g., heading) of the vehicle. At least in part, massive parallelism can be generated by evaluating pose trajectories in the pose configuration space in parallel based on at least translating the trajectories along at least one axis (e.g., the θ-axis) of the pose configuration space. This arrangement allows trajectories and / or portions thereof to be processed independently for parallel processing. For example, at least some poses of the trajectory can be shifted (e.g., on the fly or in advance using a common translation function) to form parallel lines, one or more segments of which can be processed independently in parallel to evaluate reachability.

[0031] In one or more embodiments, the trajectory may include at least a portion of a turn having a fixed turn radius. In the case where the trajectory is a turn, it may form a looping trajectory or a straight trajectory (for infinite turn radius). The disclosed method may exploit the property that each turn (or portion thereof) of turns having the same turn radius and initial orientation (same turn type) may be a translated copy of every other turn (or corresponding portion thereof), but with a different starting point (x, y), because the vehicle may behave in the same manner regardless of where it is initially located. Thus, turns (or portions of turns) of turn types corresponding to different trajectories may be translationally shifted along the θ axis and processed in parallel.

[0032] In a further aspect, the variable used to evaluate reachability can include bits representing binary values ​​(e.g., reachable or not, free space or not), with each gesture corresponding to a corresponding bit of the variable. Thus, the trajectory can be evaluated based at least on processing the variable as a bit vector. For example, one trajectory per bit of the bit vector can be evaluated in parallel. Each thread can perform logical bit-by-bit operations to control the propagation of reachability while avoiding conditional processing or branching - which is not conducive to parallel processing - so that the threads can efficiently execute large vector operations in parallel. Therefore, this approach may be suitable for modern parallel processors that thrive on large vector operations that are well aligned in memory in a simultaneous instruction multi-threading (SIMT) manner.

[0033] The present disclosure also provides methods that can be used to divide the processing work for evaluating a trajectory into segments of the trajectory, thereby allowing these segments to be evaluated in parallel rather than the entire trajectory. The various segments of a trajectory may not be independent of each other because reachability may affect the entire trajectory (e.g., the forward and backward directions of a loop trajectory). Such dependencies may pose an obstacle to processing these segments in parallel. The disclosed method can handle such dependencies using a parallel reduction pattern that hierarchically collects results from the segments (e.g., computed in parallel), performs some small amount of processing on the collected results (e.g., in parallel), and then distributes the results back as input to the various segments again for further processing (e.g., in parallel).

[0034] This path planner may offer additional opportunities for parallelism. For example, when processing the reachability of each turn for each turn type, turns can be divided into turn subsegments, and each turn subsegment can be processed semi-independently by a separate thread. Among other things, the option to process turn subsegments independently may allow the work to be spread across more threads (if available). Furthermore, because turn subsegments can be shorter than full turns, memory latency may be reduced because one thread is less likely to be stopped (for a long time) waiting for another thread to complete.

[0035] refer to Figure 1A , Figure 1A 1 is a diagram of an example including a path planner 110 according to some embodiments of the present disclosure. It should be understood that this and other arrangements described herein are set forth by way of example only. Other arrangements and elements (e.g., machines, interfaces, functions, commands, functional groupings, etc.) may be used in addition to or in place of those shown, and some elements may be omitted entirely. Furthermore, many of the elements described herein are functional entities that may be implemented as discrete or distributed components or in combination with other components and in any suitable combination and location. The various functions described herein as being performed by entities may be performed by hardware, firmware, and / or software. For example, the various functions may be performed by a processor executing instructions stored in a memory.

[0036] In at least one embodiment, path planner 110 may include configuration space manager 136, free space manager 120, reachability manager 122, and path evaluator 130. Configuration space manager 136 may manage pose configuration space 112, which represents poses (e.g., poses 114, 116, and 117) that include the position and orientation of a vehicle (or other object) in an environment (e.g., a parking lot).

[0037] The free space manager 120 and the reachability manager 122 can process the pose configuration space 112 to determine one or more paths for maneuvering from a current pose C to a target pose T (or generally between any two poses) in the pose configuration space 112. For example, the free space manager 120 can collision test the vehicle against objects 124 in the environment to determine an occupied space 118, which can capture which poses may be blocked or occupied (e.g., pose 116 and pose 118) and which poses may be free or unoccupied (e.g., pose 114). The reachability manager 122 can analyze at least a portion of the trajectories of poses that the vehicle can traverse in the pose configuration space 112 (e.g., trajectories 126 and 128) to determine a reachability space 102 (which can also be referred to as a cost space), which can capture which poses in the pose configuration space 112 can be reached by trajectories and / or the cost of reaching these poses. The path evaluator 130 can identify one or more suggested or potential paths for the vehicle based at least on the evaluation of the reachability manager 122. For example, the path evaluator 130 may identify and / or evaluate paths or trajectories (eg, paths 132 and 134 ) based on one or more criteria (eg, distance, number of turns, number of gear changes, cost, accessibility, etc.).

[0038] Now refer to Figure 1B , Figure 1B It is shown that some embodiments according to the present disclosure may include Figure 1A14. FIGURE 14 is an illustration of additional elements in the path planner 110 of FIGURE 14. The configuration space manager 136 may include a parameter controller 138, the reachability manager 122 may include a pose translator 146 and a reachability evaluator 148, the free space manager 120 may include an object detector 140 and an occupancy evaluator 142, and the path evaluator 130 may include a trajectory evaluator 150 and a backtracking tracker 152.

[0039] In at least one embodiment, the configuration space manager 136 can use the parameter controller 138 to facilitate operations related to the posture configuration space 112 to configure the parameters of the posture configuration space 112. The posture configuration space 112 can use a space, such as a multi-dimensional space (e.g., a 3D space), to represent the vehicle posture. For example, the vehicle may be in a driving environment (e.g., a parking lot). Each posture in the posture configuration space 112 can include at least the vehicle's position in the driving environment, and the vehicle's orientation at the vehicle's position. In at least one embodiment, the position within the environment can be represented in the posture configuration space 112 using an XY grid (e.g., representing a ground plane), such as Figure 1A The orientation within the environment can be represented in the pose configuration space 112 using an angular orientation component θ (e.g., a rotation about the x-axis). In at least one embodiment, the pose configuration space 112 can be parameterized as a pose P = (x, y, θ).

[0040] Figure 2 is a diagram illustrating an example of a pose configuration space 112 that may be used to model vehicle pose, according to some embodiments of the present disclosure. Figure 2 An example of how a pose grid 210 stored in the pose configuration space 112, each pose P = (x, y, θ), can represent a position 212 of a vehicle in a driving environment is shown. For example, Figure 2 It illustrates that each θ slice 214 and 216 of the pose configuration space 112 may represent a set of (x, y) values ​​in combination with a corresponding angular orientation θ.

[0041] Figure 3 An example of a motion model 300 that may be used to define a trajectory of a vehicle through a pose configuration space 112 is shown in accordance with some embodiments of the present disclosure. Poses captured in the pose configuration space 112 may correspond to points on the trajectory captured by the motion model 300. In the example shown, the motion model 300 includes an Ackermann model for motion. Under the motion model 300, a turn may be performed as a circular body motion 310 with a center 312 of the turn axially aligned with a rear axle 314 of the vehicle at a distance 316 from the center of a rear axle 318. Figure 3As shown, the center of the rear wheel axle 318 may correspond to the x, y coordinates of the pose in the pose configuration space 112. The distance 316 corresponds to the turning radius, which may be determined by the angles of the vehicle's front wheels 320 and 322. Figure 3 As shown, the angles of the vehicle's front wheels 320 and 322 may correspond to the θ coordinate of the pose in the pose configuration space 112 .

[0042] Various parameters can affect the pose configuration space 112, such as the size of the environment represented by the pose configuration space 112 and the spatial and angular cell sizes. Thus, the configuration space manager 136 can use the parameter controller 138 to define these settings. For example, the parameter controller 138 can receive the dimensions of the environment to be evaluated (e.g., 30mx30m) and the cell size (e.g., 0.3m), which can affect the spatial density of the pose configuration space 112 (e.g., the number of cells on the x-axis and y-axis). In addition, the angular cell size (e.g., in radians) or the number of angular cells can also be provided to the parameter controller 138, which can affect the angular density of the pose configuration space 112 (e.g., the number of layers in the θ axis). A pose configuration space with more cells in a given space (e.g., due to a smaller spatial cell size and / or angular cell size in a given area) may present more eligible poses and paths for evaluation and may allow for greater accuracy when aiming at a pose.

[0043] In at least one embodiment, to determine an environment-specific path and / or multi-point turn, the occupancy of the pose configuration space 112 can be calculated, for example, using the free space manager 120. That is, the free space manager 120 can determine which poses in the pose configuration space 112 are perceived as being at least partially occupied by obstacles and which poses are perceived as being open or free. The free space manager 120 can use the object detector 140 to detect and / or identify objects that may occupy or obstruct locations in the environment. The free space manager 120 can additionally or alternatively receive data representing objects from the object detector 140 operating externally to the path planner 110. The free space manager 120 can use the occupancy evaluator 142 to collision test the vehicle's body against the objects. Some expansion of the vehicle's body and / or the objects can be used to provide margin.

[0044] When crash testing, the obstacle and vehicle body representations used as input to the occupancy evaluator 142 may be polygonal or rasterized, and the output may be rasterized. Crash testing may use the center of the vehicle's rear axle at (x, y), rotated θ about the x-axis. Now referring to Figure 4 , Figure 4 is a diagram illustrating an example of a captured pose occupying space 412 in a pose configuration space according to some embodiments of the present disclosure. In particular, Figure 4 At least a portion of an occupancy space 412 is depicted that may be parameterized similarly to the pose configuration space 112 (e.g., using at least x, y, θ). Figure 4 An example obstacle 408 that may be perceived is depicted, and the location of the obstacle 408 relative to a set of (x, y) values ​​414 is depicted, which may be consistent across all θ. Figure 4 Example data values ​​are shown for theta plane 416 and theta plane 418 , each of which may correspond to a respective vehicle angular orientation.

[0045] By way of example and not limitation, occupied space 412 may store one bit per cell, where a 1 may indicate that the corresponding posture is idle, and a 0 may indicate that the corresponding posture is not idle (e.g., occupied). Figure 4 As shown, some poses 420 in theta plane 416 are set to 1 and are free based on the angular orientation of the vehicle. However, corresponding poses 422 in theta plane 418 are set to zero and may be blocked due to the different angles of the vehicle and possible overlap with obstacle 408.

[0046] In at least one embodiment, occupancy evaluator 142 may calculate the occupancy of the poses of pose configuration space 112 and write the results in parallel to occupancy space 412. For example, each pose may be tested individually (e.g., by a thread) and the results written in parallel (e.g., by a thread) to occupancy space 412. The data from occupancy space 412 may be used by reachability usage manager 122 for subsequent processing and path identification and evaluation.

[0047] Using data from the occupied space obtained from the free space manager 120, the path planner 110 can execute an algorithm to find a path from the current pose (x c ,y c ,θ c ) to the target pose set (x min ,y min ,θ min ), (x max ,y max ,θ max Both the current pose and the set of target poses may be provided as input to the path planner 110 from one or more other motion planners (e.g., when a parking space is detected, a location where the robot is allowed to pick up a pallet, etc.).

[0048] In at least one embodiment, the path planner 110 can be configured to evaluate one or more predetermined turn or trajectory types with respect to a current or starting pose in the pose configuration space 112, where the turn or trajectory type can correspond to a given turn radius and direction (e.g., forward or backward). For example, a trajectory type can define multiple trajectories throughout the pose configuration space 112, and the reachability manager 122 can use the reachability evaluator 148 to evaluate all or substantially all of those poses with respect to the initial or current pose. Trajectories that are at least part of a turn are described herein primarily by way of example, but the disclosed embodiments can be more generally applied to other types of trajectories, for example, those that can be constructed from turn primitives.

[0049] In at least one embodiment, the reachability evaluator 148 can determine reachability, e.g., whether a pose within a trajectory is reachable from the vehicle's current or starting pose C (or, in some embodiments, a target pose T or other pose). An iterative approach can be employed in which the reachability manager 122 evaluates the reachability of a set of trajectories (e.g., one or more turn types) and uses the results of the evaluation as input to evaluate the reachability of the set of trajectories (or a different set of trajectories) in a subsequent iteration. For example, a trajectory of a subsequent iteration can be reachable based at least on the fact that it can be reached by (e.g., connected to) at least one trajectory from a previous iteration and that the starting pose can be reached by at least one trajectory from a previous iteration.

[0050] The reachability evaluator 148 can evaluate the reachability of any number of trajectory executions (e.g., until a threshold number of trajectory executions and / or until the target pose is reachable). For example, the reachability manager 122 can evaluate reachability whether the vehicle is executing a single turn or a multi-point turn in the pose configuration space 112 (e.g., reaching a threshold number of turns, such as 8 turns). In at least one embodiment, the reachability evaluator 148 can also evaluate the reachability of a trajectory with respect to whether its pose is free (e.g., using a determination from the free space manager 120). For example, an obstacle in a trajectory may automatically exclude the reachability of any subsequent pose in the trajectory.

[0051] In some embodiments, the reachability evaluator 148 may also determine and / or record a cost associated with reaching a gesture in a trajectory, for example, when evaluating the reachability of a gesture. As described herein, a cost score may be used as an indicator of reachability, e.g., 1 or 0 indicating whether a gesture is reachable, a maximum cost score indicating unreachable, another cost score indicating reachable, and so on. In other examples, the reachability manager 122 may store the cost score separately from the reachability indicator. In various embodiments, one or more obstacles may not necessarily cause a gesture in a trajectory to be found unreachable, but may instead introduce some cost that may be greater than the cost value if the obstacle were not present. Furthermore, different obstacles may have different cost values.

[0052] As described herein, one or more trajectories associated with a pose in pose configuration space 112 may be turns, and each "turn" may include the vehicle moving forward or backward an arbitrary distance while keeping the steering wheel fixed (thereby maintaining the turn radius). For example, Figure 5 The diagram illustrates examples of different turn types that can be evaluated in the attitude configuration space 112, including a sharp left 510, a slight left 512, a straight 514 (θ=0), a slight right 516, and a sharp right 518. Each different turn type can include a respective turn radius, with left turns represented as negative (-) and right turns represented as positive (+). For example, the radius of a sharp left 510 can be -10 meters, and the radius of a slight left 512 can be -20 meters; while the radius of a sharp right 518 can be 10 meters, and the radius of a slight right 516 can be 20 meters.

[0053] In at least one embodiment, when proceeding through a turn type, the vehicle is tracked by a pose trajectory in pose configuration space 112, which may be defined using equation (1):

[0054] P(θ)=(x0+qQsinθ,y0+qQ(cosθ-1),θ), (1)

[0055] is parameterized by θ, where Q is the turning radius, q is the turning direction (e.g., +1 right for forward, -1 left for forward), and (x0, y0) is the position when θ is zero.

[0056] The reachability evaluator 148 can process all possible turn combinations, including any changes in turn type (e.g., forward, then backward). The reachability manager 122 can update the reachability space 102 after each reachability evaluation iteration, indicating whether each pose in the pose configuration space 112 is reachable in that particular iteration (e.g., can return to the starting pose and is not blocked by an obstacle) and / or the cost of reaching the pose. Progressing through each trajectory in each iteration can represent a significant amount of processing, and in some cases, processing can be greatly accelerated through parallel processing.

[0057] In at least one embodiment, to process trajectories in parallel to determine the reachability of poses therein, the reachability evaluator 148 can analyze non-intersecting trajectories within the pose configuration space 112, thereby allowing independent processing. According to the disclosed embodiments, non-intersecting trajectories can include a set of trajectories that share a common trajectory or turn type (e.g., turn radius and direction). When processing a trajectory or a segment thereof (e.g., each processed by a separate thread), the pose translator 146 of the reachability manager 122 can be configured to determine a shifted pose for the pose configuration space 112 based on at least one shifted pose of the non-intersecting trajectory by translating the pose of the pose configuration space 112 along at least one axis of the pose configuration space 112. Parallel processing (e.g., by respective threads) can be used to evaluate non-intersecting trajectories (or segments thereof), thereby allowing the reachability evaluator 148 to quickly evaluate the reachability of the shifted poses.

[0058] Figures 6A-6B An example of a method that the pose translator 146 may use to translate poses in the pose configuration space 112 is described. Figure 6A , Figure 6A An example of a spiral of turn 610 arranged in pose configuration space 112 is shown in accordance with some embodiments of the present disclosure. As shown, turn 610 can be conceptually mapped to a spiral in pose configuration space 112 by tracing the trajectory of the pose defined by equation (1). That is, as the turn progresses through space (e.g., tracing the pose defined by equation (1)), the turn may progress from a current (x,y) coordinate to a next (x,y) coordinate while also progressing along the θ axis through a θ plane, such as θ plane 616. In other words, all of the x, y, and θ coordinates may be present throughout the turn in a θ plane. Figure 6A The spiral pattern shown changes.

[0059] In the pose configuration space 112, each turn with the same turn radius and initial orientation (same turn type) can be a translated copy of each other, but with a different starting point (x,y), which stems from the fact that no matter where the vehicle is initially located, it is likely to behave in the same way. For example, Figure 6A A turn 610 is shown that is associated with a fixed turn radius and that begins at (x,y) coordinates 614 in the θ plane 616. Other turns, each having the same turn radius—but beginning at different (x,y) coordinates in the θ plane 616—may be translated copies of turn 610 in the pose configuration space 112. For example, referring to 6B, Figure 6B Some embodiments of the present disclosure are shown Figure 6A6 along with an example of a spiral of turn 610 as a translated copy of turn 618 arranged in pose configuration space 112. Turns having the same turn radius may have translational parallelism, which may be exploited for parallel processing using pose translator 146. While turns are described, other types of trajectories and / or portions thereof may also have translational parallelism, which may be similarly exploited for the parallel processing described herein.

[0060] In at least one embodiment, attitude translator 146 can translationally shift attitudes of attitude configuration space 112 along at least one axis (e.g., the θ axis), and reachability evaluator 148 can process each attitude in parallel along the at least one axis to evaluate reachability (e.g., one thread per turn, or segment thereof). For example, turn-type parallelism can be exposed by attitude translator 146 performing a translational shift that causes spirals in attitude configuration space 112 corresponding to the same turn radius to be grouped into a bundle of parallel lines along the θ axis. The parallel lines can be advanced in parallel through attitude configuration space 112 as non-intersecting trajectories, allowing them to be processed independently.

[0061] In at least one embodiment, for a given turn radius and direction (turn type), attitude translator 146 may perform a translation shift defined by equation (2):

[0062] t(θ)=(t x (θ),t y (θ))=(qQsinθ,qQ(cosθ-1)) (2)

[0063] As a function of θ and applying the transformation defined by equation (3) (e.g., using warps):

[0064] (x,y,θ)→(xt x (θ),yt y (θ),θ) (3)

[0065] to the pose configuration space 112. This may be equivalent to a translational shift of each constant θ plane of the pose configuration space 112. The transformed version of the turning trajectory of the turn type may be defined by equation (4):

[0066] P(θ)=(x0,y0,θ), (4)

[0067] is a set of lines that are parallel to each other and to the θ axis. For example, Figure 6C , Figure 6C According to some embodiments of the present disclosure, Figure 6B In particular, Figure 6CThe attitude configuration space 112 is conceptually shown along with turns 610 and 618 translated or moved by the attitude translator 146. As shown, turns 610 and 618 (e.g., having the same turn radius and direction) are now parallel lines along the θ axis and can be treated as such. This transformation is possible because the trajectories are translationally invariant with respect to translations along x and y, i.e., follow the operation of turning curves and translational commutes. Trajectories of the turning type can be viewed as translated copies of each other and have the same shape regardless of the starting point (x0, y0) coordinates. Parallelism along the θ axis facilitates the massive parallelism of the path planner 110 in a manner suitable for modern parallel processors. Optionally, the data can be transposed to switch the θ axis and the x axis so that the trajectories are always parallel to the x axis (or the θ axis).

[0068] In one or more embodiments, the attitude translator 146 may transform the attitude configuration space 112 (e.g., virtually by accessing a pattern or physically by copying data) for each turn type (e.g., same radius and direction) such that the turn curves for that turn type form parallel lines. The reachability evaluator 148 and / or other system components may then process each line in parallel. The processing may run parallel to the θ axis along each parallel line selected by (x0, y0) while accessing the original attitude configuration space according to equation (5):

[0069] (x0+t x (θ),y0+t y (θ),θ), (5)

[0070] This can be given by the inverse of the transformation defined above. Such a transformation may be easily reversible and therefore bijective. When using a discrete implementation of the transformation, it may be desirable for this bijective property to remain constant. For example, by using a bijective transformation, it is possible to maintain complete parallel separation between threads processing individual trajectories (or segments thereof) without having to resort to atomic operations or worry about read or write race conditions. This can also enhance the ability of each cell in the discrete pose configuration space to be approached by one of the threads when processing a turn type. For example, the bijective property can be achieved by quantizing t(θ) in the same way within each constant θ plane. The transformation of the pose configuration space 112 performed by the pose translator 246 can then be a translation shift of an integer number of pixels per constant θ plane, viewed as an image. This may be well suited for parallel implementations because the memory accesses after the shifts can be done on the fly as processing is performed, thereby reducing memory accesses that may be a limiting factor. Furthermore, the differences in the translation shifts in consecutive planes can be reduced (e.g., to no more than one pixel or some other threshold) to avoid large jumps in processing along the discretized trajectory. This can be achieved by having sufficient angular resolution of the pose configuration space 112.

[0071] When evaluating reachability, the path planner 110 may evaluate curved turns as well as straight maneuvers (e.g., turns with infinite turning radius). When traversing a pose trajectory along a straight path, the pose may be defined using equation (6):

[0072] P(u)=(x0+u cosθ,y0+u sinθ,θ), (5)

[0073] Parameterized by u, where θ is the now constant heading angle and (x0, y0) is the starting position when u is zero. In the pose configuration space 112, the trajectory can be represented as a line with angle θ in each θ plane. For example, Figure 7 Trajectories 710 and 712 are shown starting from respective (x, y) coordinates and both oriented according to θ associated with a θ plane 714. Additionally, Figure 7 Trajectories 716 and 718 are shown, each starting at (x, y) and both oriented according to a different θ associated with a θ plane 720 .

[0074] The transformation of the straight line case to a parallel line aligned with one of the coordinate axes (e.g., via the attitude translator 146) can be implemented in various ways. For example, in at least one embodiment, each θ plane can be rotated by an angle -θ, and as a continuous transformation, this approach is bijective. For example, a worker warp can be defined where each warp independently rotates each constant θ plane about its center by an angle -θ so that all driven straight lines are aligned parallel to the x-axis. This approach can be efficient in a GPU because the warp has each constant θ plane rotated as an image, which can be done using a "nearest" interpolation method (e.g., maintaining integrity of integers in the warp space). The rotation may rotate some angle outside of the original space, which can be accounted for by using a padded version of the space. All cells outside of the original space may be treated as never being reachable and disallowed, like obstacles or high costs.

[0075] Discretized image rotations may not easily preserve bijective transformation properties, although bijective image rotations can be achieved via three shear coordinate transformations. In an alternative aspect, a single shear transformation may be applied to each θ plane, which may produce less discretization noise and may provide the ability to perform transformations on the fly while being processed via simple translation shifts of memory access vector operations. For example, the pose translator 146 may shear the trajectory to be parallel to the x-axis when the direction of the line is closer to the x-axis than the y-axis (|tanθ|≤1) or some other threshold, and parallel to the y-axis otherwise. In the former case (e.g., closer to the x-axis), the pose translator 146 may set x0=0, while in the latter (e.g., closer to the y-axis), the pose translator 146 may set y0=0 and still consider all lines. These operations may result in the family of trajectories defined by equation (6):

[0076]

[0077] It can also be written as equation (7):

[0078]

[0079] The bijective shear transformation can be defined by equation (8):

[0080]

[0081] After this transformation, the trajectory can be taken in the form of equation (9):

[0082]

[0083] This is a set of lines parallel to the x-axis or y-axis. Similar to the curved turn case, the reachability evaluator 148 can run processing along these lines while accessing the original pose configuration space according to equation (10):

[0084]

[0085] This can be given by the inverse of the shear transformation.

[0086] As described herein, an iterative approach may be employed in which the reachability manager 122 evaluates the reachability of a set of trajectories (e.g., one or more turn types) and uses the evaluation results as input to evaluate the reachability of the set of trajectories (or a different set of trajectories) in a subsequent iteration. To this end, the reachability evaluator 148 may be used to determine whether a pose in the pose configuration space 112 (e.g., as transformed by the pose translator 146) is reachable from the current location by processing one or more trajectories in an iteration and then performing one or more subsequent iterations (e.g., up to a given maximum number of turns) to determine whether the pose becomes reachable in the subsequent iteration. For example, the reachability evaluator 148 may evaluate whether a pose is reachable based on determining whether the pose is blocked or occupied (e.g., using the occupied space 412) and included in one or more trajectories in the iteration (e.g., 510, 512, 514, 516, 518, etc.).

[0087] In at least one embodiment, the reachability evaluator 148 can be configured to determine the reachability of a person from the current or starting pose (x c ,y c ,θ c), only that pose is marked as reachable. In a first iteration, the reachability evaluator 148 may annotate the reachability space 102 for the first iteration to indicate (e.g., mark) whether each pose is reachable from the current pose using a trajectory in the first iteration (e.g., along a turning trajectory with at least one trajectory and no obstacles blocking the current pose). For example, the reachability evaluator 148 may evaluate reachability with respect to each turn type. This may result in a reachability space 102 indicating a set of reachable poses after the first iteration. In a second iteration, the reachability evaluator 148 may annotate a different reachability space 102 (or in some embodiments the same reachability space 120) for the second iteration to indicate (e.g., mark) whether each pose is reachable from the current pose using a trajectory in the second iteration (e.g., for each turn type and / or different turn types). Iterations may continue similarly until the reachability evaluator 148 has reached a maximum number of iterations (e.g., 8 turns), finds a target pose, and / or determines that some other end condition is satisfied. The path evaluator 130 may use the annotated reachability space 102 to identify which path, if any, to recommend based on a cost function (eg, shortest number of turns, shortest distance, or other cost evaluation) or other method.

[0088] The reachability evaluator 148 can process the pose configuration space 112 in various ways as it progresses through the iterations. In at least one embodiment, the reachability evaluator 148 can reference the occupied space 112 parameterized by (x, y, θ) and a separate reachability space 102 for each trajectory type (e.g., reachability) also parameterized by (x, y, θ) (e.g., space 102 for left front hard driving, reachability space 102 for left hard reverse driving, reachability space 102 for straight driving, etc.). In addition, each cell associated with a single pose (x, y, θ) can be updated in the corresponding reachability space 102 as the reachability evaluator 148 evaluates whether the corresponding pose is free and reachable in the iteration.

[0089] Now refer to Figure 8 , Figure 8An example of a computational flow chart 800 that can be used to process turns in which reachability is encoded using binary values ​​according to some embodiments of the present disclosure is shown. The computational flow chart 800 can be applicable to embodiments in which binary values ​​are used to store whether a gesture is reachable or unreachable. In one or more embodiments, for each iteration, the reachability evaluator 148 can start from a shared reachability space and process each turn type in parallel to calculate the corresponding reachability space. For example, for iteration 802A, the reachability evaluator 148 can start from the reachability space 808A and process the sharp left turn type in parallel to generate reachability space 810A, the sharp left turn type to generate reachability space 810A, the slightly left turn type to generate reachability space 812A, the straight turn type to generate reachability space 814A, the slightly right turn type to generate reachability space 816A, and the sharp right turn type to generate reachability space 818A. Although not shown, forward and reverse turn types can be processed.

[0090] Each iteration may also include the reachability evaluator 148 merging the reachability spaces of the turn types to provide a shared reachability space for subsequent iterations. For example, iteration 802A may include the reachability evaluator 148 performing a merge 820A on the reachability spaces 810A, 812a, 814A, 816A, and 818A to generate a reachability space 808B as an input to iteration 802B. In one or more embodiments, the merge 820A may include a logical OR operation. The logical OR may be suitable for reflecting that the reachability space can capture various different ways of reaching a particular unit, each of which may be valid. In at least one embodiment, the shared reachability space may be cached in a shared memory (e.g., a shared memory of a GPU) accessed by each thread.

[0091] In one aspect of the present disclosure, the reachability evaluator 148 propagates reachability along the entire turning trajectory so that along the turning trajectory of a single reachable pose (e.g., Figure 9 Each pose that is not separated from a single reachable pose by an obstacle (the shaded box in the figure) is marked as reachable. To determine which pose or poses from the previous iteration are reachable, the path planner makes turns through each with a turn radius and direction, and since translation shifts have already been applied, this can be performed in parallel. At each pose (x, y, θ), if the path planner finds an obstacle (e.g., based on occupied space), it turns off reachability and turns on reachability if it finds reachability from the previous iteration.

[0092] Therefore, to process through iterations, the reachability evaluator 148 can transform the reachability space from the previous iteration into the reachability space after the iteration. In at least one embodiment, the reachability evaluator 148 can apply a rule such that if a pose on the trajectory being processed (e.g., a specific turn of a turn type) is previously reachable (as indicated by the reachability space), then all poses along the trajectory that are not separated from any previously reachable point by an obstacle will be reachable. In this way, reachability can be propagated along the trajectory until blocked by an obstacle.

[0093] Figure 8 Pseudo code 830 is included to illustrate how a thread of reachability evaluator 148 processes M pose cells of a trajectory using a core loop that turns off reachability represented by a local variable r for pose cell i when the thread finds an obstacle represented by an element of occupancy space input F, and turns on reachability for pose cell i when the thread finds reachability from a previous iteration represented by reachability space input Ri and then writes reachability r to reachability space output Ro. As described herein, pose translator 146 can be used to move poses in advance or on the fly for processing.

[0094] In one or more embodiments, all variables r, F, Ri, Ro can be processed as bit vectors. For example, if the variables are declared as 32-bit unsigned integers, then 32 bits and therefore 32 parallel traces can be processed in parallel as bit vectors. This processing may not include any conditional processing or branching - just a logical AND operation to stop propagation when free space stops and a logical OR operation to start or restart propagation when the input indicates reachability from the previous iteration. In addition, the processing of this core loop may be parallel and precisely synchronized between multiple threads, each thread responsible for one trace, so that the threads can effectively synchronize the execution of large vector operations.

[0095] Therefore, this approach may be suitable for modern parallel processors that thrive on large vector operations that are well aligned in memory in a simultaneous instruction multiple threading (SIMT) manner, similar to but different from simultaneous instruction multiple data (SIMD). For example, some parallel processing architectures may include basic units of parallel processing, such as a warp or wavefront of 32 threads (as an example), which strive to execute simultaneously to improve efficiency. When a warp is mentioned in this article, it can be more generally referred to as a basic unit of parallel processing. Each streaming multiprocessor can process one or more basic units simultaneously, and there can be many multiprocessors. A single thread can process 32 trajectories (e.g., turns) as bit vectors simultaneously, so that each basic unit (e.g., warp) can process 32x32=1024 trajectories in parallel. In addition, there may be eight or more multiprocessors, each multiprocessor processing many basic units simultaneously to achieve tens of thousands of parallelism. By allowing each trajectory (e.g., turn) to be evaluated in each iteration, the path planner 110 is able to do all the work instead of applying heuristics to hopefully start a promising path. Thus, the path planner 110 can avoid recommendations produced by inappropriate heuristics that attempt to constrain operations to those that work best in the first place.

[0096] The path planner 110 may perform one or more iterations, and the path evaluator 130 may use the results of the one or more iterations to identify and / or recommend at least one path for maneuvering the vehicle to the target pose. To this end, an output reachability space from each iteration may be maintained to support backtracking, as described herein. Since the reachability space may require only one bit per cell, each cell in the pose configuration space may require only N bits. With a reasonable number of iterations, this is equivalent to representing the space using 8, 16, or 32-bit integers or floating point numbers.

[0097] To identify and / or select a path, the path evaluator 130 may include a trajectory evaluator 150 that evaluates one or more costs associated with a trajectory (e.g., a turn), and there are many cost functions of varying complexity that can be used to identify a recommended path. A simpler cost function may consider the number of trajectories (e.g., turns) required to reach a certain pose and rank paths that reach that pose in fewer trajectories higher. More complex cost functions may consider how much resources may be spent to follow a path. For example, the trajectory evaluator 150 may apply a cost function that models the amount of time it takes to traverse a trajectory, which may include a penalty for changing from forward to reverse or backward, and evaluates the time it takes to traverse the trajectory based on the distance of the trajectory. In a more complex example, the state space can be used by adding the curvature and sign of the turn (the base state may be steering and wheel position and gear) as well as the speed. This may reduce the modeling costs associated with needing to slow down to a stop when changing to reverse or making significant changes to the steering wheel position.

[0098] The trajectory evaluator 150 can apply a variety of different cost models depending on the goals and application of the path planner 110. For example, a cost model can remove the explicit speed component and instead have a cost that depends at least in part on the distance traveled through the turn, with changes in turn type (including going into reverse) incurring a penalty depending on the turn type before and after the switch. This approach approximates the understanding that turns are traversed at a fixed low speed that can be reached relatively quickly, and that changes between turn types incur additional penalties due to having to slow down to move the steering wheel and / or change gears. This cost model can be handled by having a reachability space 102 that provides a cost quantity parameterized by (x, y, θ) for each turn type (e.g., including turn radius and gear—forward / reverse), where the minimum cost to reach the attitude state with the corresponding turn type as the last turn is maintained. This model can essentially function using a four-dimensional state space, where the fourth dimension holds the possible turn radius multiplied by two gears.

[0099] The path planner 110 may continue to perform update steps that execute one turn at a time, updating the state space from considering all paths up to n turns to having considered n+1. For each turn type used for the (n+1)th turn, the trajectory evaluator 150 may consider starting from any other turn type and paying the cost of the transition first. The smallest of those possibilities may be considered the lowest cost to prepare for starting a turn of this type from this posture, and the path planner 110 may only need to consider the most efficient. The path planner 110 may then process the turns to achieve the lowest cost after completing the (n+1)th turn using this turn type. In one example, processing N turns with a K turn radius may require processing 2NK turns (e.g., assuming that reversing requires a separate processing step). Therefore, before each turn, the trajectory evaluator 150 may find the minimum value of transitioning from the 2K cost amount to starting the turn. In one aspect of the present disclosure, this step may be performed for all 2K turn types simultaneously, reading the 2K amount, calculating the (2K) 2 The transition finds the 2KB minimum and writes it back to the volume simultaneously. This process escalates the cost from the "back" turn to the "front" turn, resulting in a 4KB memory access for the next turn. Each turn also reads back the cost, reads the free space, and writes the new cost, resulting in an additional 6KB memory access for the volume. This approach can result in a total of 10KB accesses for the volume.

[0100] The cost function can be further simplified, for example, by evaluating the transition cost between turn types as the same regardless of the types of turns involved in the transition. Furthermore, the cost model may assume that the cost of traversing a turn is negligible compared to the transition cost. Under this approach, the cost can be evaluated based on the number of turns. While this approach significantly simplifies operations and doesn't account for certain situations (for example, transitioning between two short turns takes less time than a single long turn, or transitioning between two turns of similar radius in the same gear is faster than a larger change in direction or gear), this cost model still provides a reasonable heuristic. Under this simpler model, a three-dimensional state space can be used instead of a four-dimensional state space. A single state volume can now store whether the corresponding pose can be reached through n turns, similar to or equivalent to the approach reflected in pseudocode 830. Using this simpler cost model, each turn's processing is read from a common previous cost volume. Since the transition penalty is always paid, there's no need to remember the last turn type. The footprint is still read, and a new cost is written for the first turn type and combined with the previous result for the subsequent turn type via a logical OR, resulting in a read and write. This represents a total of 8NK - 2N memory accesses. Furthermore, depending on the resolution of the cost function, the cost can be represented with a single bit per cell (reachable or unreachable) rather than 8, 16, or even 32 bits. The processing speed of many modern cores depends heavily on the amount of memory access, and this approach can potentially reduce the amount of memory access.

[0101] Now refer to Figure 9 , Figure 9 An example of a computational flow chart 900 that may be used to process turns where reachability is encoded using non-binary values ​​is shown in accordance with some embodiments of the present disclosure. The computational flow chart 900 may be suitable for use by the reachability evaluator 148 using a ratio Figure 8 The calculation flow chart 800 is for the more general case of a cost function.

[0102] Similar to computational flow chart 800, computational flow chart 900 can be iterated N times, such as iteration 902A and iteration 902B, each time considering K trajectory types (e.g., sharp left, slight left, straight, slight right, sharp right, etc.). Unlike using a shared reachability space, each iteration can include a cost update to the post-trajectory cost output of the previous iteration to generate the pre-trajectory cost of the iteration. For example, iteration 802B can include a cost update 820 from the post-trajectory cost output space 910A, 912A, 914A, 916A, and 918A of iteration 902A to generate the pre-trajectory cost output space 910B, 912B, 914B, 916B, and 918B for iteration 902B. In one or more embodiments, the post-trajectory cost can represent the minimum cost to reach a posture that ends with the corresponding trajectory type, and the pre-trajectory cost can represent the minimum cost to reach the posture and prepare the corresponding turning trajectory without penalty. Then, the iterative core turning process can convert the pre-trajectory cost into the post-trajectory cost, and the process can be repeated. For example, iteration 902B may include converting the pre-trajectory cost output spaces 910B, 912B, 914B, 916B, and 918B into corresponding post-trajectory cost output spaces, as shown. Figure 9 In , each vertical line represents the evaluation of one trajectory type.

[0103] Figure 9 Pseudocode 930 is included to illustrate how the reachability evaluator 148 thread can process M pose units through a trajectory using a core loop that uses a more general cost function than pseudocode 830, involving a cost c. Here, the variables are no longer bit vectors in order to capture non-binary cost values. In addition, logical operations are replaced by maximum / minimum operations. Obstacles can be represented by some maximum cost that cannot be changed, or they can be proportional to the size of the obstacle (e.g., an obstacle does not necessarily block the vehicle). In addition, the cost may double with each step.

[0104] In one or more embodiments, an iteration may process each trajectory in both the forward and reverse directions. If it is looping, which is the case unless it is straight, in which case it turns, then it may also be processed in two loops. This is because knowing a priori where to start a loop is not trivial, and in the worst case the reachability from the last cell may need to be propagated throughout the second loop, although certain heuristics can be developed to account for this. Therefore, the trajectory may be processed in four passes using code that does not have any long-running branch divergences between threads to avoid thread divergence that would hinder parallelism. However, much of this processing can be avoided while exposing more parallelism by splitting each trajectory into an arbitrary number of parts that can be processed in parallel.

[0105] Using the disclosed method to divide a trajectory into parts that can be processed in parallel can avoid much of the cost incurred by running forward and backward through a loop turn and through both loops. In one or more embodiments, the reachability manager 122 divides the processing of one or more trajectories into independent, parallel parts. The results may not be completely independent between the parts of a turn, as reachability may fluctuate throughout the trajectory for both loops, both forward and backward. The disclosed method can handle such dependencies using a parallel reduction pattern that hierarchically collects results, performs some minor processing on the collected results, and then distributes the results back out as input to the various parts.

[0106] The results for a segment can be independent of other segments, except for the reachability into a segment at its beginning (or at the end when processing in the backward direction). The disclosed method can calculate forward and / or backward reachability into a segment at the beginning or end, allowing the segments to be processed independently using these inputs. For small segments, the input footprint and reachability space can be loaded once, and the forward and backward passes can be processed simultaneously, reducing global memory accesses by half. This can be desirable because keeping data in local registers or shared memory close to the processing core is often much faster than accessing global memory.

[0107] To determine forward and backward reachability into each segment, a processing pass can be performed that (e.g., in parallel) computes for each segment the forward reachability in the forward direction out of the segment, such as originating from the segment (SRf), the backward reachability in the backward direction out of the segment, such as originating from the segment (SRb), and the segment free space, indicating whether the segment consists entirely of free space (SF).

[0108] The forward and backward reachability over the segment from this scan is the reachability originating from within the segment. It may not be possible to detect reachability that propagates from outside the segment, for example, reachability that enters at the beginning of the segment and completely passes through it, because the segment consists entirely of free space. This can be addressed by computing partial free space, allowing the effects of those global propagations to be determined in a smaller processing scan that applies to the segment rather than a single cell.

[0109] Here's a pseudocode example of a processing pass, which omits the backward pass that is blended with the forward pass:

[0110]

[0111] Where m represents the segment length and s is the index of a segment.

[0112] Another processing pass can be used that is similar to the one within a segment, but uses segment reachability and segment free space instead. This processing pass may loop over the segment output twice (in the case of a loop turn). The first loop can warm up the reachability for possible propagation. The second loop can complete the full propagation of the loop turn and write the results back. Below is a pseudocode example of the processing pass, which only shows the forward pass, as the backward pass is exactly the same:

[0113]

[0114] Although this process passes the segment output four times (eg, in parallel), there is only a total of 4 / m times the amount of work in this step, decreasing as the segment gets longer (choose a larger m).

[0115] Another processing pass for section processing might be almost identical to the basic loop, except that it uses section reachability as input instead of starting reachability from zero. Here is a pseudocode example of a processing pass, omitting the backward pass:

[0116]

[0117] The processing pass that writes back the results can be changed to a logical OR, where all but the first turn type are already present. Segment processing with a more general cost function works similarly, except that the reachability r may correspond to the minimum cost of leaving or entering the segment.

[0118] Using the parallel reduction mode as described herein can include 2 reads and 3 / m writes for each cell of the posture configuration space 112 for processing passes that include computational reachability from within a segment. For processing passes that include propagating segment outputs, this may include 8 / m reads and 2 / m writes. Processing passes using segment reachability as input may include 2 (or 3) reads and 1 write. Thus, the parallel reduction mode can be completed in (5+8) / m reads and (1+5) / m writes, or a total of (6+13) / m accesses. This can be compared to processing without segments, which may include 2 reads and 1 write x3 passes and 3 reads and 1 write for the last pass, or a total of 9 reads, 4 writes, and 13 memory accesses. Therefore, segment processing can save more than twice the memory accesses. Furthermore, further savings can be achieved by caching the free space or occupancy and reachability inputs in shared memory between the first and third passes, saving two read operations in the third pass and resulting in (4+13) / m accesses to save more than three times the memory accesses. The parallel reduction mode approach also exhibits more parallelism since there are M / m segments that can be worked on in parallel in each turn.

[0119] As described herein, the trajectory evaluator 150 of the path evaluator 130 can use the reachability space annotated by the reachability evaluator 148 in one or more iterations to identify and / or select a path using a backtracker 152. In one or more embodiments, the backtracker 152 can backtrack to find a path that reaches a goal with the fewest number of trajectories or turns (or more generally, the lowest cost path). The backtracker 152 can be executed by a CPU and / or by parallel processing (e.g., using at least one GPU).

[0120] In at least one embodiment, the backtracker 152 can search for one or more cells in a target set of one or more poses, whose final reachability output is set in the reachability space. For example, the backtracker 152 can loop over a set of target poses, or use parallel reduction if parallelism is required. If there is more than one cell with a reachability set, one or more poses can be selected by some preference function, such as based on proximity to a selected pose. If there are no such poses, this may indicate that there is no N-turn path plan that reaches the target set, in which case an (N+1)-turn plan can be evaluated.

[0121] Once a cell is selected to start backtracing, it can be assumed that the cell is reached after i iterations and that one of the turn types arrives at a pose from another pose reached one iteration ago (on iteration i-1). Therefore, the backtracer 152 can backtrace all K turn types from that cell, and somewhere along them, it will find a cell that is set to be reachable in the output reachability space from iteration i-1. Since turns may have repeatable coordinate definitions, they can be backtraced accurately based on the evaluation. This backtracing of K turns can be done sequentially by the CPU or by parallel reduction. There may be loop ambiguities because the turn may have been used in the forward or backward direction. Ambiguities can be resolved by checking the free space along the backtraced turns and stopping the backtracing when an obstacle is found (in embodiments where the obstacle may completely block the path).

[0122] In the case of a more general cost function, the criterion might be to find the lowest cost cell among those cells whose cost reduction is equal to the cost of the backtracking turn. If there is more than one cell that meets the criterion, a heuristic method can be used to select a cell, such as picking the cell that requires the shortest turn to reach. If the target set is reached in less than N turns, some initial backtracking steps will find a reachable cell from the previous iteration as the same cell (because the turn step is not required). The backtracker 152 can determine that the criterion is met and remove the turn from the path solution. Once a cell is found, the process can be repeated from that cell until a reachable cell is found after iteration 1. The backtracking can end with a current pose representing the reachability space before any turn, and the backtracking can be performed with the current pose to resolve loop ambiguities.

[0123] Now refer to Figure 10 , each block of method 1000 and other methods described herein comprises a computational process that can be performed using any combination of hardware, firmware, and / or software. For example, various functions can be performed by a processor executing instructions stored in a memory. The methods can also be embodied as computer-usable instructions stored on a computer storage medium. The methods can be provided by a standalone application, a service, or a hosted service (standalone or in combination with another hosted service), or a plug-in to another product, to name a few. Furthermore, by way of example, with respect to Figure 1A and 1B These methods are described with reference to the path planner 110 of FIG. However, these methods may additionally or alternatively be performed by any one system or any combination of systems, including but not limited to those described herein.

[0124] Figure 10 1 is a flow chart illustrating a method 1000 for determining a displacement pose of a pose configuration space to determine a path through the pose configuration space in accordance with some embodiments of the present disclosure. The method 1000 includes, at block B1002, determining a displacement pose based on at least translating a pose of the pose configuration space to generate a displacement trajectory including the displacement pose. For example, the pose translator 146 of the reachability manager 122 may determine a displacement pose based on at least translating a set of poses in the pose configuration space 112 corresponding to the trajectory (e.g., Figure 6B 618 and 610 in the environment) to determine a displacement pose of the pose configuration space 112 representing the pose of the object (e.g., the vehicle 1300) in the environment to generate a displacement pose (e.g., Figure 6C The shift trajectory of turns 618 and 610).

[0125] At block B1004, method 1000 includes determining a path through the pose configuration space based at least on evaluating reachability of the shift pose using parallel processing of the shift trajectories. For example, path evaluator 130 may determine a path through the pose configuration space based at least on evaluating reachability of the shift pose of the shift trajectories from the first pose based at least on evaluating reachability of the shift pose of the shift trajectories from the first pose by reachability evaluator 148 using parallel processing of the shift trajectories (e.g., according to pseudo-code 830 or 930). Figure 1A The current posture C in Figure 1A The path to the target pose T in .

[0126] Now refer to Figure 11 , Figure 11 1 is a flow chart illustrating a method 1100 for translating a trajectory of a pose in a pose configuration space into a displaced trajectory to determine a path through the pose configuration space, according to some embodiments of the present disclosure. At block B1102, method 1100 includes translating a pose trajectory in the pose configuration space into a displaced trajectory, the displaced trajectory comprising one or more segments that are parallel to each other and to at least one axis of the pose configuration space. For example, pose translator 146 may translate a trajectory formed by a pose in pose configuration space 112 into a displaced trajectory comprising at least segments that are parallel to each other and to at least one axis of the pose configuration space 112.

[0127] The method 1100 includes processing at least a plurality of segments of the displacement trajectory in parallel along at least one axis to calculate a reachability indicator associated with the displacement trajectory at block B1104. For example, the reachability evaluator 148 may process at least a plurality of segments of the displacement trajectory in parallel along at least one axis to calculate a reachability indicator associated with the displacement trajectory (e.g., according to pseudo-code 830 or 930).

[0128] Method 1100 includes determining a path through the pose configuration space based at least on the indicator of reachability at block B 1106 .For example, path evaluator 130 may determine a path through pose configuration space 112 based at least on the indicator of reachability.

[0129] Figure 12 is a flow chart illustrating a method 1200 for concurrently evaluating the reachability of segments of trajectories according to some embodiments of the present disclosure. At block B 1202, the method 1200 includes calculating, for a first segment of the segments of a posture trajectory in a posture configuration space, an indicator of reachability from the first segment. For example, the reachability evaluator 148 may calculate, for a first segment of the segments of a posture trajectory in a posture configuration space, an indicator of reachability from the first segment. Figure 6B and 6C For a first segment of the segments of turn 618 , an indicator of reachability is calculated leaving the first segment.

[0130] Method 1200 includes, at block B 1204, calculating an indicator of reachability into a second of the segments using the indicator of reachability out of the first segment. For example, reachability evaluator 148 may calculate an indicator of reachability into a second of the segments using the indicator of reachability out of the first segment.

[0131] Method 1200 includes, at block B1206, calculating an indicator of reachability for gestures within the first segment using the indicator of reachability into the second segment. For example, reachability evaluator 148 may calculate one or more gestures within the first segment (e.g., relative to the first segment) using the indicator of reachability into the second segment. Figure 1A Method 1200 may be performed in parallel for multiple trajectories using parallel processing as part of a parallel reduction mode.

[0132] Example autonomous vehicle

[0133] Figure 13A 1 is an illustration of an example autonomous vehicle 1300 according to some embodiments of the present disclosure. Autonomous vehicle 1300 (alternatively referred to herein as "vehicle 1300") may include, but is not limited to, a passenger vehicle such as a car, a truck, a bus, a first responder vehicle, a shuttle, an electric or motorized bicycle, a motorcycle, a fire truck, a police vehicle, an ambulance, a boat, a construction vehicle, an underwater vessel, a drone, a vehicle coupled to a trailer, and / or another type of vehicle (e.g., a vehicle that is unmanned and / or accommodates one or more passengers). Autonomous vehicles are generally described according to the levels of automation defined by the National Highway Traffic Safety Administration (NHTSA), a division of the U.S. Department of Transportation, and the Society of Automotive Engineers (SAE), "Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles" (Standard No. J3016-201806, issued on June 15, 2018, Standard No. J3016-201609, issued on September 30, 2016, and previous and future versions of such standards). The vehicle 1300 may be capable of implementing functionality consistent with one or more of autonomous driving levels 3 to 5. For example, depending on the embodiment, the vehicle 1300 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5).

[0134] Vehicle 1300 may include components such as a chassis, a body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. Vehicle 1300 may include a propulsion system 1350, such as an internal combustion engine, a hybrid power plant, an all-electric engine, and / or another type of propulsion system. Propulsion system 1350 may be connected to a drivetrain of vehicle 1300, which may include a transmission, to achieve propulsion of vehicle 1300. Propulsion system 1350 may be controlled in response to receiving a signal from throttle / accelerator 1352.

[0135] A steering system 1354, which may include a steering wheel, may be used to steer vehicle 1300 (e.g., along a desired path or route) when propulsion system 1350 is operating (e.g., while the vehicle is in motion). Steering system 1354 may receive signals from steering actuator 1356. For fully automated (Level 5) functionality, a steering wheel may be optional.

[0136] Brake sensor system 1346 may be used to operate vehicle brakes in response to receiving signals from brake actuator 1348 and / or brake sensors.

[0137] May include one or more system on chip (SoC) 1304 ( Figure 13C ) and / or one or more GPUs can provide signals (e.g., representing commands) to one or more components and / or systems of vehicle 1300. For example, one or more controllers can send signals to operate vehicle brakes via one or more brake actuators 1348, to operate steering system 1354 via one or more steering actuators 1356, and to operate propulsion system 1350 via one or more throttles / accelerators 1352. One or more controllers 1336 can include one or more onboard (e.g., integrated) computing devices (e.g., supercomputers) that process sensor signals and output operational commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving vehicle 1300. One or more controllers 1336 can include a first controller 1336 for autonomous driving functionality, a second controller 1336 for functional safety functionality, a third controller 1336 for artificial intelligence functionality (e.g., computer vision), a fourth controller 1336 for infotainment functionality, a fifth controller 1336 for redundancy in emergency situations, and / or other controllers. In some examples, a single controller 1336 may handle two or more of the above functions, two or more controllers 1336 may handle a single function, and / or any combination thereof.

[0138] The one or more controllers 1336 may provide signals for controlling one or more components and / or systems of the vehicle 1300 in response to sensor data (e.g., sensor inputs) received from one or more sensors. The sensor data may be received from, for example and without limitation, a global navigation satellite system sensor 1358 (e.g., a global positioning system sensor), a RADAR sensor 1360, an ultrasonic sensor 1362, a LIDAR sensor 1364, an inertial measurement unit (IMU) sensor 1366 (e.g., an accelerometer, a gyroscope, a magnetic compass, a magnetometer, etc.), a microphone 1396, a stereo camera 1368, a wide-angle camera 1370 (e.g., a fisheye camera), an infrared camera 1372, a surround camera 1374 (e.g., a 360-degree camera), a long-range and / or mid-range camera 1398, a speed sensor 1344 (e.g., for measuring the velocity of the vehicle 1300), a vibration sensor 1342, a steering sensor 1340, a brake sensor (e.g., as part of a brake sensor system 1346), and / or other sensor types.

[0139] One or more of the controllers 1336 may receive input (e.g., represented by input data) from the instrument cluster 1332 of the vehicle 1300 and provide output (e.g., represented by output data, display data, etc.) via a human machine interface (HMI) display 1334, an audible annunciator, a speaker, and / or via other components of the vehicle 1300. These outputs may include information such as vehicle speed, velocity, time, map data (e.g., Figure 13C The HMI display 1334 may display information such as an HD map 1322 of the vehicle 1300, position data (e.g., the position of the vehicle 1300 on the map), direction, the positions of other vehicles (e.g., an occupancy grid), information about objects and object states as sensed by the controller 1336, etc. For example, the HMI display 1334 may display information about the presence of one or more objects (e.g., street signs, warning signs, traffic light changes, etc.) and / or information about driving maneuvers that the vehicle has made, is making, or will make (e.g., changing lanes now, leaving 34B in two miles, etc.).

[0140] The vehicle 1300 also includes a network interface 1324 that can communicate over one or more networks using one or more wireless antennas 1326 and / or a modem. For example, the network interface 1324 can be capable of communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, etc. The one or more wireless antennas 1326 can also enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using one or more local area networks such as Bluetooth, Bluetooth LE, Z-wave, ZigBee, etc. and / or one or more low power wide area networks (LPWANs) such as LoRaWAN, SigFox, etc.

[0141] Figure 13B For use according to some embodiments of the present disclosure Figure 13A 13. Example camera positions and fields of view for autonomous vehicle 1300. The cameras and respective fields of view are an example embodiment and are not intended to be limiting. For example, additional and / or alternative cameras may be included and / or located at different locations on vehicle 1300.

[0142] The camera type used for the camera may include, but is not limited to, a digital camera that may be suitable for use with components and / or systems of the vehicle 1300. The camera may operate at Automotive Safety Integrity Level (ASIL) B and / or at another ASIL. The camera type may have any image capture rate, such as 60 frames per second (fps), 120fps, 240fps, and the like, depending on the embodiment. The camera may be capable of using a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In some examples, the color filter array may include a red-white-white-white (RCCC) color filter array, a red-white-white-blue (RCCB) color filter array, a red-blue-green-white (RBGC) color filter array, a Foveon X3 color filter array, a Bayer sensor (RGGB) color filter array, a monochrome sensor color filter array, and / or another type of color filter array. In some embodiments, a clear pixel camera such as a camera with an RCCC, RCCB, and / or RBGC color filter array may be used in an effort to improve light sensitivity.

[0143] In some examples, one or more of the cameras can be used to perform advanced driver assistance system (ADAS) functions (e.g., as part of a redundant or fail-safe design). For example, a multi-function monocular camera can be installed to provide functions including lane departure warning, traffic sign assistance, and intelligent headlight control. One or more of the cameras (e.g., all of the cameras) can simultaneously record and provide image data (e.g., video).

[0144] One or more of the cameras can be mounted in a mounting assembly, such as a custom-designed (3-D printed) assembly, to cut off stray light and reflections from within the car (e.g., reflections from the dashboard reflected in the windshield mirror) that could interfere with the camera's ability to capture image data. With respect to the wing mirror mounting assembly, the wing mirror assembly can be custom 3-D printed so that the camera mounting plate matches the shape of the wing mirror. In some examples, one or more cameras can be integrated into the wing mirror. For side-view cameras, one or more cameras can also be integrated into the four pillars at each corner of the cab.

[0145] A camera (e.g., a front-facing camera) having a field of view that includes a portion of the environment in front of the vehicle 1300 can be used for surround vision to help identify the forward path and obstacles, as well as assist in providing information critical to generating an occupancy grid and / or determining a preferred vehicle path with the help of one or more controllers 1336 and / or control SoCs. The front-facing camera can be used to perform many of the same ADAS functions as LIDAR, including emergency braking, pedestrian detection, and collision avoidance. The front-facing camera can also be used for ADAS functions and systems, including lane departure warning ("LDW"), autonomous cruise control ("ACC"), and / or other functions such as traffic sign recognition.

[0146] A variety of cameras can be used in the front-facing configuration, including, for example, a monocular camera platform including a CMOS (complementary metal oxide semiconductor) color imager. Another example could be a wide-angle camera 1370, which can be used to sense objects entering the field of view from the periphery (e.g., pedestrians, intersection traffic, or bicycles). Figure 13B The figure shows only one wide-angle camera, but any number of wide-angle cameras 1370 can be present on vehicle 1300. In addition, long-range cameras 1398 (e.g., a long-view stereo camera pair) can be used for depth-based object detection, especially for objects for which neural networks have not yet been trained. Long-range cameras 1398 can also be used for object detection and classification, as well as basic object tracking.

[0147] One or more stereo cameras 1368 may also be included in the front configuration. The stereo camera 1368 may include an integrated control unit including a scalable processing unit that may provide a multi-core microprocessor and programmable logic (FPGA) with an integrated CAN or Ethernet interface on a single chip. Such a unit may be used to generate a 3-D map of the vehicle environment, including distance estimates for all points in the image. An alternative stereo camera 1368 may include a compact stereo vision sensor that may include two camera lenses (one on the left and one on the right) and an image processing chip that may measure the distance from the vehicle to the target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. Other types of stereo cameras 1368 may be used in addition to or alternatively to those described herein.

[0148] Cameras with a field of view that includes portions of the environment to the sides of the vehicle 1300 (e.g., side-view cameras) can be used for surround viewing, providing information used to create and update occupancy grids and generate side impact collision warnings. For example, surround cameras 1374 (e.g., Figure 13BFour surround cameras 1374 (shown in FIG) can be placed on vehicle 1300. Surround cameras 1374 can include wide-angle camera 1370, fisheye camera, 360-degree camera, and / or the like. For example, four fisheye cameras can be placed on the front, rear, and sides of the vehicle. In an alternative arrangement, the vehicle can use three surround cameras 1374 (e.g., left, right, and rear), and can utilize one or more other cameras (e.g., a forward-facing camera) as a fourth surround-view camera.

[0149] A camera having a field of view that includes a portion of the environment behind the vehicle 1300 (e.g., a rearview camera) can be used to assist with parking, surround view, rear collision warning, and creating and updating an occupancy grid. A variety of cameras can be used, including but not limited to cameras that are also suitable as front-facing cameras as described herein (e.g., long-range and / or mid-range cameras 1398, stereo cameras 1368, infrared cameras 1372, etc.).

[0150] Figure 13C For use according to some embodiments of the present disclosure Figure 13A 13. Block diagram of an example system architecture for an example autonomous vehicle 1300. It should be understood that this arrangement and other arrangements described herein are set forth merely as examples. Other arrangements and elements (e.g., machines, interfaces, functions, sequences, functional groupings, etc.) may be used in addition to or in place of those shown, and some elements may be omitted entirely. Further, many of the elements described herein are functional entities that may be implemented as discrete or distributed components or in conjunction with other components, and in any appropriate combination and location. The various functions described herein as being performed by entities may be implemented by hardware, firmware, and / or software. For example, the various functions may be implemented by a processor executing instructions stored in a memory.

[0151] Figure 13C Each of the components, features, and systems of vehicle 1300 is illustrated as being connected via bus 1302. Bus 1302 may include a controller area network (CAN) data interface (alternatively, referred to herein as a "CAN bus"). CAN may be a network internal to vehicle 1300 that assists in controlling various features and functions of vehicle 1300, such as actuation of brakes, acceleration, braking, steering, windshield wipers, and the like. The CAN bus may be configured to have tens or even hundreds of nodes, each with its own unique identifier (e.g., CAN ID). The CAN bus may be read to find steering wheel angle, ground speed, engine revolutions per minute (RPM), button positions, and / or other vehicle status indicators. The CAN bus may be ASIL B compliant.

[0152] Although bus 1302 is described here as a CAN bus, this is not intended to be limiting. For example, FlexRay and / or Ethernet may be used in addition to or in lieu of a CAN bus. Furthermore, although bus 1302 is represented by a single line, this is not intended to be limiting. For example, there may be any number of buses 1302, which may include one or more CAN buses, one or more FlexRay buses, one or more Ethernet buses, and / or one or more other types of buses using different protocols. In some examples, two or more buses 1302 may be used to perform different functions and / or may be used for redundancy. For example, a first bus 1302 may be used for collision avoidance functionality, and a second bus 1302 may be used for drive control. In any example, each bus 1302 may communicate with any component of vehicle 1300, and two or more buses 1302 may communicate with the same component. In some examples, each SoC 1304 , each controller 1336 , and / or each computer within the vehicle may have access to the same input data (e.g., input from sensors of the vehicle 1300 ) and may be connected to a common bus such as a CAN bus.

[0153] The vehicle 1300 may include one or more controllers 1336, such as those described herein. Figure 13A Controller 1336 may be used for a variety of functions. Controller 1336 may be coupled to any of the other various components and systems of vehicle 1300 and may be used for control of vehicle 1300, artificial intelligence of vehicle 1300, infotainment for vehicle 1300, and / or the like.

[0154] The vehicle 1300 may include one or more system-on-chips (SoCs) 1304. The SoCs 1304 may include a CPU 1306, a GPU 1308, a processor 1310, a cache 1312, an accelerator 1314, a data store 1316, and / or other components and features not shown. The SoCs 1304 may be used to control the vehicle 1300 in a variety of platforms and systems. For example, the one or more SoCs 1304 may be combined with an HD map 1322 in a system (e.g., a system of the vehicle 1300), which may be downloaded from one or more servers (e.g., a vehicle) via a network interface 1324. Figure 13D one or more servers 1378) to obtain map refreshes and / or updates.

[0155] The CPU 1306 may include a CPU cluster or CPU complex (alternatively, referred to herein as a "CCPLEX"). The CPU 1306 may include multiple cores and / or L2 caches. For example, in some embodiments, the CPU 1306 may include eight cores in a coherent multiprocessor configuration. In some embodiments, the CPU 1306 may include four dual-core clusters, each with a dedicated L2 cache (e.g., a 2MB L2 cache). The CPU 1306 (e.g., CCPLEX) may be configured to support simultaneous cluster operations such that any combination of CPU 1306 clusters can be active at any given time.

[0156] CPU 1306 may implement power management capabilities including one or more of the following features: each hardware block may be automatically clock gated when idle to conserve dynamic power; each core clock may be gated when the core is not actively executing instructions due to the execution of WFI / WFE instructions; each core may be independently power gated; each core cluster may be independently clock gated when all cores are clock gated or power gated; and / or each core cluster may be independently power gated when all cores are power gated. CPU 1306 may further implement an enhanced algorithm for managing power states, in which allowed power states and expected wakeup times are specified, and hardware / microcode determines the optimal power state to enter for the core, cluster, and CCPLEX. The processing core may support a simplified power state entry sequence in software, with this work being offloaded to the microcode.

[0157] GPU 1308 may include an integrated GPU (alternatively referred to herein as an "iGPU"). GPU 1308 may be programmable and efficient for parallel workloads. In some examples, GPU 1308 may use an enhanced tensor instruction set. GPU 1308 may include one or more streaming microprocessors, each of which may include an L1 cache (e.g., an L1 cache with at least 96KB of storage capacity), and two or more of these streaming microprocessors may share an L2 cache (e.g., an L2 cache with 512KB of storage capacity). In some embodiments, GPU 1308 may include at least eight streaming microprocessors. GPU 1308 may use a computing application programming interface (API). In addition, GPU 1308 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA).

[0158] In the case of automotive and embedded use, GPU 1308 can be power optimized to achieve optimal performance. For example, GPU 1308 can be manufactured on fin field effect transistors (FinFETs). However, this is not intended to be limiting, and GPU 1308 can be manufactured using other semiconductor manufacturing processes. Each streaming microprocessor can incorporate several mixed precision processing cores divided into multiple blocks. For example and without limitation, 64 PF32 cores and 32 PF64 cores can be divided into four processing blocks. In such an example, each processing block can be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed precision NVIDIA tensor cores for deep learning matrix arithmetic, L0 instruction cache, warp scheduler, dispatch unit and / or 64KB register file. In addition, the streaming microprocessor may include independent parallel integer and floating point data paths to provide efficient execution of workloads using a mix of computation and addressing calculations. The streaming microprocessor may include independent thread scheduling capabilities to allow for finer-grained synchronization and cooperation between parallel threads. The streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0159] GPU 1308 can include high bandwidth memory (HBM) and / or a 16GB HBM2 memory subsystem that provides a peak memory bandwidth of approximately 900 GB / s in some examples. In some examples, synchronous graphics random access memory (SGRAM), such as fifth generation graphics double data rate synchronous random access memory (GDDR5), can be used in addition to or in lieu of HBM memory.

[0160] The GPU 1308 may include unified memory technology that includes access counters to allow memory pages to be more accurately migrated to the processor that accesses them most frequently, thereby improving the efficiency of memory ranges shared between processors. In some examples, address translation services (ATS) support may be used to allow the GPU 1308 to directly access the CPU 1306 page tables. In such an example, when the GPU 1308 memory management unit (MMU) experiences a miss, an address translation request may be transmitted to the CPU 1306. In response, the CPU 1306 may look up the virtual-to-physical mapping for the address in its page table and transmit the translation back to the GPU 1308. In this way, unified memory technology may allow a single unified virtual address space to be used for memory of both the CPU 1306 and the GPU 1308, thereby simplifying GPU 1308 programming and porting of applications to the GPU 1308.

[0161] Additionally, GPU 1308 may include access counters that can track how often GPU 1308 accesses the memory of other processors. The access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses them most frequently.

[0162] SoC 1304 may include any number of caches 1312, including those described herein. For example, cache 1312 may include an L3 cache available to both CPU 1306 and GPU 1308 (e.g., connected to both CPU 1306 and GPU 1308). Cache 1312 may include a write-back cache that can track the state of lines, for example, using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). Depending on the embodiment, the L3 cache may include 4MB or more, although smaller cache sizes may also be used.

[0163] The SoC 1304 may include an arithmetic logic unit (ALU) that may be utilized in performing any of a variety of tasks or operations related to the vehicle 1300, such as processing a DNN. Furthermore, the SoC 1304 may include a floating point unit (FPU) (or other math coprocessor or digital coprocessor type) for performing mathematical operations within the system. For example, the SoC 1304 may include one or more FPUs integrated as execution units within the CPU 1306 and / or GPU 1308.

[0164] SoC 1304 may include one or more accelerators 1314 (e.g., hardware accelerators, software accelerators, or a combination thereof). For example, SoC 1304 may include a hardware accelerator cluster, which may include optimized hardware accelerators and / or large on-chip memory. The large on-chip memory (e.g., 4MB SRAM) may enable the hardware accelerator cluster to accelerate neural networks and other calculations. The hardware accelerator cluster may be used to supplement GPU 1308 and offload some tasks of GPU 1308 (e.g., freeing up more cycles of GPU 1308 to perform other tasks). As an example, accelerator 1314 may be used for targeted workloads (e.g., perception, convolutional neural networks (CNNs), etc.) that are stable enough to easily control acceleration. When used herein, the term "CNN" may include all types of CNNs, including region-based or regional convolutional neural networks (RCNNs) and fast RCNNs (e.g., for object detection).

[0165] Accelerator 1314 (e.g., a hardware accelerator cluster) may include a deep learning accelerator (DLA). The DLA may include one or more tensor processing units (TPUs) that can be configured to provide an additional 10 trillion operations per second for deep learning applications and reasoning. The TPU may be an accelerator configured to perform image processing functions (e.g., for CNN, RCNN, etc.) and optimized for performing image processing functions. The DLA may be further optimized for a specific set of neural network types and floating-point operations and reasoning. The design of the DLA may provide higher performance per millimeter than a general-purpose GPU and far exceed the performance of the CPU. The TPU may perform several functions, including a single-instance convolution function, support for INT8, INT16, and FP16 data types for both features and weights, and post-processor functions.

[0166] DLA can quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for any of a wide variety of functions, such as, but not limited to: CNNs for object recognition and detection using data from camera sensors; CNNs for distance estimation using data from camera sensors; CNNs for emergency vehicle detection and recognition and detection using data from microphones; CNNs for facial recognition and vehicle owner identification using data from camera sensors; and / or CNNs for safety and / or security-related events.

[0167] The DLA can perform any function of the GPU 1308, and by using an inference accelerator, for example, the designer can target any function to either the DLA or the GPU 1308. For example, the designer can focus the processing of CNNs and floating-point operations on the DLA and leave other functions to the GPU 1308 and / or other accelerators 1314.

[0168] The accelerator 1314 (e.g., a hardware accelerator cluster) may include a programmable vision accelerator (PVA), which may be referred to herein alternatively as a computer vision accelerator. The PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (ADAS), autonomous driving, and / or augmented reality (AR) and / or virtual reality (VR) applications. The PVA may provide a balance between performance and flexibility. For example, each PVA may include, for example and without limitation, any number of reduced instruction set computer (RISC) cores, direct memory access (DMA), and / or any number of vector processors.

[0169] The RISC core can interact with an image sensor (e.g., an image sensor of any camera described herein), an image signal processor, and / or the like. Each of these RISC cores can include any amount of memory. Depending on the embodiment, the RISC core can use any of a number of protocols. In some examples, the RISC core can execute a real-time operating system (RTOS). The RISC core can be implemented using one or more integrated circuit devices, application specific integrated circuits (ASICs), and / or memory devices. For example, the RISC core can include an instruction cache and / or tightly coupled RAM.

[0170] The DMA can enable components of the PVA to access system memory independently of the CPU 1306. The DMA can support any number of features used to provide optimizations for the PVA, including, but not limited to, support for multi-dimensional addressing and / or circular addressing. In some examples, the DMA can support addressing in up to six or more dimensions, which can include block width, block height, block depth, horizontal block stride, vertical block stride, and / or depth stride.

[0171] A vector processor can be a programmable processor that can be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In some examples, the PVA can include a PVA core and two vector processing subsystem partitions. The PVA core can include a processor subsystem, one or more DMA engines (e.g., two DMA engines), and / or other peripherals. The vector processing subsystem can operate as the main processing engine of the PVA and can include a vector processing unit (VPU), an instruction cache, and / or a vector memory (e.g., VMEM). The VPU core can include a digital signal processor, such as, for example, a single instruction multiple data (SIMD), a very long instruction word (VLIW) digital signal processor. The combination of SIMD and VLIW can enhance throughput and speed.

[0172] Each of the vector processors can include an instruction cache and can be coupled to dedicated memory. As a result, in some examples, each of the vector processors can be configured to execute independently of the other vector processors. In other examples, the vector processors included in a particular PVA can be configured to employ data parallelism. For example, in some embodiments, multiple vector processors included in a single PVA can execute the same computer vision algorithm, but on different regions of an image. In other examples, the vector processors included in a particular PVA can execute different computer vision algorithms simultaneously on the same image, or even execute different algorithms on sequential images or portions of images. Among other things, any number of PVAs can be included in a hardware accelerator cluster, and any number of vector processors can be included in each of these PVAs. In addition, the PVAs can include additional error correction code (ECC) memory to enhance overall system security.

[0173] The accelerator 1314 (e.g., a hardware accelerator cluster) may include an on-chip computer vision network and SRAM to provide high bandwidth, low latency SRAM for the accelerator 1314. In some examples, the on-chip memory may include at least 4MB of SRAM consisting of, for example and without limitation, eight field-configurable memory blocks that can be accessed by both the PVA and the DLA. Each pair of memory blocks may include an advanced peripheral bus (APB) interface, configuration circuitry, a controller, and a multiplexer. Any type of memory may be used. The PVA and DLA may access the memory via a backbone that provides high-speed memory access to the PVA and DLA. The backbone may include an on-chip computer vision network that interconnects the PVA and DLA to the memory (e.g., using APB).

[0174] The on-chip computer vision network can include an interface that ensures that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. Such an interface can provide separate phases and separate channels for transmitting control signals / addresses / data, as well as burst-based communication for continuous data transmission. This type of interface can comply with ISO 26262 or IEC 61508 standards, but other standards and protocols can also be used.

[0175] In some examples, SoC 1304 may include a real-time ray tracing hardware accelerator, such as that described in U.S. patent application Ser. No. 16 / 101,232, filed on Aug. 10, 2018. The real-time ray tracing hardware accelerator may be used to quickly and efficiently determine the position and extent of objects (e.g., within a world model) to generate real-time visualization simulations for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for SONAR system simulations, for general wave propagation simulations, for comparison with LIDAR data for positioning and / or other functions, and / or for other uses. In some embodiments, one or more tree traversal units (TTUs) may be used to perform one or more ray tracing related operations.

[0176] The accelerator 1314 (e.g., a hardware accelerator cluster) has a wide range of uses in autonomous driving. The PVA can be a programmable vision accelerator that can be used in key processing stages in ADAS and autonomous vehicles. The capabilities of the PVA are a good match for algorithmic domains that require predictable processing, low power, and low latency. In other words, the PVA performs well on semi-intensive or intensive rule computations, and even on small data sets that require predictable runtimes with low latency and low power. Therefore, in the context of platforms for autonomous vehicles, the PVA is designed to run classic computer vision algorithms because they are efficient at object detection and integer math operations.

[0177] For example, according to one embodiment of the technology, PVA is used to perform computer stereo vision. In some examples, a semi-global matching-based algorithm can be used, but this is not intended to be limiting. Many applications for Level 3-5 autonomous driving require on-the-fly motion estimation / stereo matching (e.g., structure from motion, pedestrian recognition, lane detection, etc.). PVA can perform computer stereo vision functions on input from two monocular cameras.

[0178] In some examples, PVA can be used to perform dense optical flow, by processing raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR. In other examples, PVA is used for time-of-flight depth processing, by processing raw time-of-flight data to provide processed time-of-flight data.

[0179] DLA can be used to run any type of network to enhance control and driving safety, including, for example, a neural network that outputs a confidence measure for each object detection. Such confidence values ​​can be interpreted as probabilities, or as providing a relative "weight" of each detection compared to other detections. This confidence value enables the system to make further decisions about which detections should be considered true positive detections rather than false positive detections. For example, the system can set a threshold for the confidence level and only consider detections that exceed the threshold as true positive detections. In an automatic emergency braking (AEB) system, a false positive detection would cause the vehicle to automatically perform emergency braking, which is obviously undesirable. Therefore, only the most confident detections should be considered as triggers for AEB. DLA can run a neural network for regressing confidence values. The neural network may take as its input at least some subset of parameters, such as bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), inertial measurement unit (IMU) sensor 1366 output related to the orientation and range of the vehicle 1300, 3D position estimates of objects obtained from the neural network and / or other sensors (e.g., LIDAR sensor 1364 or RADAR sensor 1360), etc.

[0180] SoC 1304 may include one or more data stores 1316 (e.g., memory). Data store 1316 may be on-chip memory of SoC 1304 that may store neural networks to be executed on the GPU and / or DLA. In some examples, data store 1316 may be large enough to store multiple instances of the neural network for redundancy and safety. Data store 1312 may include an L2 or L3 cache 1312. References to data store 1316 may include references to memory associated with the PVA, DLA, and / or other accelerators 1314 as described herein.

[0181] SoC 1304 may include one or more processors 1310 (e.g., embedded processors). Processor 1310 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions and related safety implementations. The boot and power management processor may be part of the SoC 1304 boot sequence and may provide runtime power management services. The boot power and management processor may provide clock and voltage programming, assist system low-power state transitions, SoC 1304 thermal and temperature sensor management, and / or SoC 1304 power state management. Each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and SoC 1304 may use the ring oscillator to detect the temperature of CPU 1306, GPU 1308, and / or accelerator 1314. If the temperature is determined to exceed a threshold, the boot and power management processor may enter a temperature fault routine and place SoC 1304 in a lower power state and / or place vehicle 1300 in a driver safety parking mode (e.g., to safely park vehicle 1300).

[0182] The processor 1310 may also include a set of embedded processors that can be used as an audio processing engine. The audio processing engine can be an audio subsystem that allows for full hardware support for multi-channel audio through multiple interfaces and a wide range of flexible audio I / O interfaces. In some examples, the audio processing engine is a dedicated processor core having a digital signal processor with dedicated RAM.

[0183] The processor 1310 may also include an always-on processor engine that can provide the necessary hardware features to support low-power sensor management and wake-up use cases. The always-on processor engine may include a processor core, tightly coupled RAM, supporting peripherals (such as timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0184] Processor 1310 may also include a safety cluster engine, which includes a dedicated processor subsystem that handles safety management of automotive applications. The safety cluster engine may include two or more processor cores, tightly coupled RAM, supporting peripherals (such as timers, interrupt controllers, etc.), and / or routing logic. In safety mode, the two or more cores can operate in lockstep mode and act as a single core with comparison logic to detect any differences between their operations.

[0185] Processor 1310 may also include a real-time camera engine, which may include a dedicated processor subsystem for handling real-time camera management.

[0186] Processor 1310 may also include a high dynamic range signal processor, which may include an image signal processor, which is a hardware engine that is part of the camera processing pipeline.

[0187] The processor 1310 may include a video image compositer, which may be a processing block (e.g., implemented on a microprocessor) that implements the video post-processing functions required by the video playback application to produce the final image for the player window. The video image compositer may perform lens distortion correction for the wide-angle camera 1370, the surround camera 1374, and / or for the in-cab monitoring camera sensor. The in-cab monitoring camera sensor is preferably monitored by a neural network running on another instance of the advanced SoC and is configured to recognize in-cab events and respond accordingly. The in-cab system may perform lip reading to activate mobile phone service and place calls, dictate emails, change vehicle destinations, activate or change the vehicle's infotainment system and settings, or provide voice-activated web surfing. Certain functions are only available to the driver when the vehicle is operating in autonomous mode and are disabled in other circumstances.

[0188] The video image compositer can include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in the presence of motion in the video, the noise reduction appropriately weights spatial information and downweights information provided by neighboring frames. In the case where an image or portion of an image does not include motion, the temporal noise reduction performed by the video image compositer can use information from previous images to reduce noise in the current image.

[0189] The video image compositor can also be configured to perform stereo rectification on the input stereo footage frames. The video image compositor can further be used for user interface composition when the operating system desktop is in use and the GPU 1308 does not need to continuously render new surfaces. Even when the GPU 1308 is powered on and active for 3D rendering, the video image compositor can be used to offload the GPU 1308 to improve performance and responsiveness.

[0190] The SoC 1304 may also include a Mobile Industry Processor Interface (MIPI) camera serial interface, a high-speed interface for receiving video and input from a camera, and / or a video input block that may be used for camera and related pixel input functions. The SoC 1304 may also include an input / output controller that may be controlled by software and may be used to receive I / O signals that are not assigned to a specific role.

[0191] SoC 1304 may also include a wide range of peripheral interfaces to enable communication with peripherals, audio codecs, power management, and / or other devices. SoC 1304 may be used to process data from cameras (connected via Gigabit multimedia serial links and Ethernet), sensors (e.g., LIDAR sensor 1364, RADAR sensor 1360, etc., which may be connected via Ethernet), data from bus 1302 (e.g., vehicle 1300 speed, steering wheel position, etc.), and data from GNSS sensor 1358 (connected via Ethernet or CAN bus). SoC 1304 may also include dedicated high-performance mass storage controllers, which may include their own DMA engines and which may be used to free up CPU 1306 from routine data management tasks.

[0192] SoC 1304 can be an end-to-end platform with a flexible architecture that spans levels 3-5 of automation, providing a comprehensive functional safety architecture that leverages and efficiently uses computer vision and ADAS technologies for diversity and redundancy, along with deep learning tools to provide a platform for a flexible and reliable driving software stack. SoC 1304 can be faster, more reliable, and even more energy- and space-efficient than conventional systems. For example, when combined with CPU 1306, GPU 1308, and data storage 1316, accelerator 1314 can provide a fast and efficient platform for Level 3-5 autonomous vehicles.

[0193] This technology therefore provides capabilities and functionality that cannot be achieved with conventional systems. For example, computer vision algorithms can be executed on CPUs, which can be configured using high-level programming languages ​​such as the C programming language to execute a wide variety of processing algorithms across a wide variety of visual data. However, CPUs often fail to meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In particular, many CPUs are unable to execute complex object detection algorithms in real time, a requirement for in-vehicle ADAS applications and practical Level 3-5 autonomous vehicles.

[0194] In contrast to conventional systems, by providing a CPU complex, a GPU complex, and a cluster of hardware accelerators, the technology described herein allows multiple neural networks to be executed simultaneously and / or sequentially, and the results to be combined to achieve Level 3-5 autonomous driving capabilities. For example, a CNN executed on a DLA or dGPU (e.g., GPU 1320) can include text and word recognition, allowing the supercomputer to read and understand traffic signs, including signs for which a neural network has not been specifically trained. The DLA can also include a neural network that can recognize, interpret, and provide semantic understanding of the signs, and pass that semantic understanding to a path planning module running on the CPU complex.

[0195] As another example, as required for Level 3, 4, or 5 driving, multiple neural networks can run simultaneously. For example, a warning sign consisting of "Caution: Flashing lights indicate icing conditions" along with a light can be interpreted by several neural networks, either independently or collectively. The sign itself can be identified as a traffic sign by a first neural network deployed (e.g., a trained neural network), and the text "Flashing lights indicate icing conditions" can be interpreted by a second neural network deployed, which informs the vehicle's path planning software (preferably executing on a CPU complex) that icing conditions exist when the flashing lights are detected. The flashing lights can be identified by operating a third neural network deployed over multiple frames, which informs the vehicle's path planning software of the presence (or absence) of the flashing lights. All three neural networks can run simultaneously, for example, within the DLA and / or on GPU 1308.

[0196] In some examples, a CNN for facial recognition and owner recognition can use data from a camera sensor to identify the presence of an authorized driver and / or owner of the vehicle 1300. The always-on sensor processing engine can be used to unlock the vehicle and turn on the lights when the owner approaches the driver's door, and in security mode, disable the vehicle when the owner leaves the vehicle. In this way, the SoC 1404 provides security against theft and / or carjacking.

[0197] In another example, a CNN for emergency vehicle detection and identification can use data from microphone 1396 to detect and identify emergency vehicle sirens. In contrast to conventional systems that use general classifiers to detect sirens and manually extract features, SoC 1304 uses CNNs to classify environmental and urban sounds as well as visual data. In a preferred embodiment, the CNN running on the DLA is trained to identify the relative closing speed of emergency vehicles (for example, by using the Doppler effect). The CNN can also be trained to identify emergency vehicles specific to the local area in which the vehicle is operating, as identified by the GNSS sensor 1358. Thus, for example, when operating in Europe, the CNN will seek to detect European sirens, and when in the United States, the CNN will seek to identify only North American sirens. Once an emergency vehicle is detected, with the assistance of the ultrasonic sensor 1362, the control program can be used to execute emergency vehicle safety routines, slowing the vehicle, pulling to the side of the road, stopping the vehicle, and / or idling the vehicle until the emergency vehicle passes.

[0198] The vehicle may include a CPU 1318 (e.g., a discrete CPU or dCPU) that may be coupled to the SoC 1304 via a high-speed interconnect (e.g., PCIe). The CPU 1318 may include, for example, an X86 processor. The CPU 1318 may be used to perform any of a variety of functions, including, for example, arbitrating potentially inconsistent results between ADAS sensors and the SoC 1304, and / or monitoring the status and health of the controller 1336 and / or the infotainment SoC 1330.

[0199] The vehicle 1300 may include a GPU 1320 (e.g., a discrete GPU or dGPU) that may be coupled to the SoC 1304 via a high-speed interconnect (e.g., NVIDIA's NVLINK). The GPU 1320 may provide additional artificial intelligence functionality, for example, by executing redundant and / or different neural networks, and may be used to train and / or update the neural network based at least in part on input from sensors of the vehicle 1300 (e.g., sensor data).

[0200] The vehicle 1300 may also include a network interface 1324, which may include one or more wireless antennas 1326 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). The network interface 1324 can be used to enable wireless connections to the cloud (e.g., to a server 1378 and / or other network devices), to other vehicles, and / or to computing devices (e.g., a passenger's client device) via the Internet. To communicate with other vehicles, a direct link can be established between the two vehicles, and / or an indirect link can be established (e.g., across a network and through the Internet). The direct link can be provided using a vehicle-to-vehicle communication link. The vehicle-to-vehicle communication link can provide the vehicle 1300 with information about vehicles approaching the vehicle 1300 (e.g., vehicles in front of, to the sides of, and / or behind the vehicle 1300). This functionality can be part of the cooperative adaptive cruise control functionality of the vehicle 1300.

[0201] The network interface 1324 may include a SoC that provides modulation and demodulation functionality and enables the controller 1336 to communicate over a wireless network. The network interface 1324 may include an RF front-end for up-conversion from baseband to RF and down-conversion from RF to baseband. The frequency conversion may be performed by well-known processes and / or may be performed using a super-heterodyne process. In some examples, the RF front-end functionality may be provided by a separate chip. The network interface may include wireless functionality for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0202] The vehicle 1300 may also include data storage 1328, which may include off-chip storage (e.g., outside the SoC 1304). The data storage 1328 may include one or more storage elements, including RAM, SRAM, DRAM, VRAM, flash memory, a hard disk, and / or other components and / or devices that can store at least one bit of data.

[0203] The vehicle 1300 may also include a GNSS sensor 1358. The GNSS sensor 1358 (e.g., GPS, assisted GPS sensor, differential GPS (DGPS) sensor, etc.) is used to assist with mapping, perception, occupancy grid generation, and / or path planning functions. Any number of GNSS sensors 1358 may be used, including, for example and without limitation, GPS using a USB connector with an Ethernet to serial (RS-232) bridge.

[0204] The vehicle 1300 may also include a RADAR sensor 1360. The RADAR sensor 1360 may be used by the vehicle 1300 for remote vehicle detection even in darkness and / or in adverse weather conditions. The RADAR functional safety level may be ASIL B. The RADAR sensor 1360 may use CAN and / or bus 1302 (e.g., to transmit data generated by the RADAR sensor 1360) for control and access to object tracking data, and in some examples access Ethernet to access raw data. A variety of RADAR sensor types may be used. For example and without limitation, the RADAR sensor 1360 may be suitable for front, rear, and side RADAR use. In some examples, a pulsed Doppler RADAR sensor is used.

[0205] The RADAR sensor 1360 can include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, and so on. In some examples, long-range RADAR can be used for adaptive cruise control functions. The long-range RADAR system can provide a wide field of view (e.g., within a range of 250m) achieved through two or more independent scans. The RADAR sensor 1360 can help distinguish between static objects and moving objects and can be used by the ADAS system for emergency braking assistance and forward collision warning. The long-range RADAR sensor can include a single-station multimode RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In the example with six antennas, the central four antennas can create a focused beam pattern that is designed to record the surroundings of the vehicle 1300 at a higher rate with minimal traffic interference from adjacent lanes. The other two antennas can expand the field of view, making it possible to quickly detect vehicles entering or leaving the lane of the vehicle 1300.

[0206] As an example, a medium-range RADAR system may include a range of up to 1360m (front) or 80m (rear) and a field of view of up to 42 degrees (front) or 1350 degrees (rear). A short-range RADAR system may include, but is not limited to, a RADAR sensor designed to be mounted on both ends of the rear bumper. When mounted on both ends of the rear bumper, such a RADAR sensor system can create two beams that continuously monitor the blind spots behind and beside the vehicle.

[0207] Short-range RADAR systems can be used in ADAS systems for blind spot detection and / or lane change assistance.

[0208] Vehicle 1300 may also include ultrasonic sensors 1362. Ultrasonic sensors 1362, which may be located on the front, rear, and / or sides of vehicle 1300, may be used for parking assistance and / or for creating and updating an occupancy grid. A variety of ultrasonic sensors 1362 may be used, and different ultrasonic sensors 1362 may have different detection ranges (e.g., 2.5 m, 4 m). Ultrasonic sensors 1362 may operate at functional safety level ASIL B.

[0209] Vehicle 1300 may include a LIDAR sensor 1364. LIDAR sensor 1364 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. LIDAR sensor 1364 may be ASIL B functional safety level. In some examples, vehicle 1300 may include multiple LIDAR sensors 1364 (e.g., two, four, six, etc.) that may use Ethernet (e.g., to provide data to a Gigabit Ethernet switch).

[0210] In some examples, LIDAR sensor 1364 may be capable of providing a list of objects and their distances for a 360-degree field of view. Commercially available LIDAR sensors 1364 may have, for example, an advertised range of approximately 1300 meters, an accuracy of 2-3 cm, and support for 1300 Mbps Ethernet connections. In some examples, one or more non-obtrusive LIDAR sensors 1364 may be used. In such examples, LIDAR sensor 1364 may be implemented as a small device that can be embedded in the front, back, sides, and / or corners of vehicle 1300. In such examples, LIDAR sensor 1364 may provide a field of view of up to 120 degrees horizontally and 35 degrees vertically, even for low-reflectivity objects, with a range of 200 meters. Front-mounted LIDAR sensor 1364 may be configured for a horizontal field of view between 45 and 135 degrees.

[0211] In some examples, LIDAR technologies such as 3D flash LIDAR may also be used. 3D flash LIDAR uses flashes of laser light as an emission source to illuminate the vehicle's surroundings up to about 200 m. The flash LIDAR unit includes a receiver that records the laser pulse transmission time and reflected light on each pixel, which in turn corresponds to the range from the vehicle to the object. Flash LIDAR can allow a highly accurate and distortion-free image of the surrounding environment to be generated with each laser flash. In some examples, four flash LIDAR sensors may be deployed, one on each side of the vehicle 1300. Available 3D flash LIDAR systems include solid-state 3D staring array LIDAR cameras (e.g., non-scanning LIDAR devices) with no moving parts other than a fan. The flash LIDAR device may use 5 nanosecond Class I (eye-safe) laser pulses per frame and may capture the reflected laser light in the form of a 3D range point cloud and co-registered intensity data. By using flash LIDAR, and because flash LIDAR is a solid-state device with no moving parts, the LIDAR sensor 1364 may be less susceptible to motion blur, vibration, and / or shock.

[0212] The vehicle may also include an IMU sensor 1366. In some examples, the IMU sensor 1366 may be located at the center of the rear axle of the vehicle 1300. The IMU sensor 1366 may include, for example and without limitation, an accelerometer, a magnetometer, a gyroscope, a magnetic compass, and / or other sensor types. In some examples, such as in a six-axis application, the IMU sensor 1366 may include an accelerometer and a gyroscope, while in a nine-axis application, the IMU sensor 1366 may include an accelerometer, a gyroscope, and a magnetometer.

[0213] In some embodiments, the IMU sensor 1366 can be implemented as a miniature, high-performance GPS-assisted inertial navigation system (GPS / INS) that combines micro-electromechanical systems (MEMS) inertial sensors, a high-sensitivity GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude. Thus, in some examples, the IMU sensor 1366 can enable the vehicle 1300 to estimate heading without input from a magnetic sensor by directly observing and correlating velocity changes from the GPS to the IMU sensor 1366. In some examples, the IMU sensor 1366 and the GNSS sensor 1358 can be combined into a single integrated unit.

[0214] The vehicle may include microphones 1396 positioned in and / or around the vehicle 1300. The microphones 1396 may be used for, among other things, emergency vehicle detection and identification.

[0215] The vehicle may also include any number of camera types, including stereo cameras 1368, wide angle cameras 1370, infrared cameras 1372, surround cameras 1374, long and / or medium range cameras 1398, and / or other camera types. These cameras may be used to capture image data around the entire periphery of the vehicle 1300. The type of camera used depends on the embodiment and the requirements of the vehicle 1300, and any combination of camera types may be used to provide the necessary coverage around the vehicle 1300. Additionally, the number of cameras may vary depending on the embodiment. For example, the vehicle may include six cameras, seven cameras, ten cameras, twelve cameras, and / or another number of cameras. As an example and not limitation, the cameras may support Gigabit Multimedia Serial Link (GMSL) and / or Gigabit Ethernet. Each of the cameras described herein may include a GMSL and / or Gigabit Ethernet network. Figure 13A and Figure 13B Described in more detail.

[0216] Vehicle 1300 may also include a vibration sensor 1342. Vibration sensor 1342 can measure vibrations of vehicle components, such as axles. For example, changes in vibration can indicate changes in the road surface. In another example, when two or more vibration sensors 1342 are used, the difference between the vibrations can be used to determine friction or slippage of the road surface (e.g., when there is a vibration difference between a powered drive shaft and a freely rotating shaft).

[0217] The vehicle 1300 may include an ADAS system 1338. In some examples, the ADAS system 1338 may include a SoC. The ADAS system 1338 may include autonomous / adaptive / automatic cruise control (ACC), cooperative adaptive cruise control (CACC), forward collision warning (FCW), automatic emergency braking (AEB), lane departure warning (LDW), lane keeping assist (LKA), blind spot warning (BSW), rear cross traffic warning (RCTW), collision warning system (CWS), lane centering (LC), and / or other features and functions.

[0218] The ACC system can utilize RADAR sensors 1360, LIDAR sensors 1364, and / or cameras. The ACC system can include longitudinal ACC and / or lateral ACC. Longitudinal ACC monitors and controls the distance to the vehicle immediately in front of vehicle 1300, automatically adjusting the vehicle speed to maintain a safe distance from the vehicle in front. Lateral ACC maintains distance and, when necessary, recommends that vehicle 1300 change lanes. Lateral ACC is related to other ADAS applications such as LCA and CWS.

[0219] CACC uses information from other vehicles, which can be received from other vehicles indirectly via a wireless link via the network interface 1324 and / or the wireless antenna 1326 or via a network connection (e.g., via the Internet). A direct link can be provided by a vehicle-to-vehicle (V2V) communication link, while an indirect link can be an infrastructure-to-vehicle (I2V) communication link. Typically, the V2V communication concept provides information about the vehicle immediately ahead (e.g., the vehicle immediately ahead of the vehicle 1300 and in the same lane as it), while the I2V communication concept provides information about traffic further ahead. The CACC system can include either or both of the I2V and V2V information sources. Given information about the vehicle ahead of the vehicle 1300, CACC can be more reliable, and it has the potential to improve the smoothness of traffic flow and reduce road congestion.

[0220] The FCW system is designed to alert the driver to hazards so that the driver can take corrective action. The FCW system uses a front-facing camera and / or RADAR sensor 1360 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to driver feedback such as a display, speaker, and / or vibrating component. The FCW system can provide warnings in the form of, for example, audible, visual warnings, vibrations, and / or rapid brake pulses.

[0221] The AEB system detects an impending forward collision with another vehicle or other object and can automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. The AEB system can use a front-facing camera and / or RADAR sensor 1360 coupled to a dedicated processor, DSP, FPGA and / or ASIC. When the AEB system detects a hazard, it typically first alerts the driver to take corrective action to avoid the collision, and if the driver does not take corrective action, the AEB system can automatically apply the brakes in an effort to prevent or at least mitigate the effects of the predicted collision. The AEB system can include technologies such as dynamic brake support and / or collision approach braking.

[0222] The LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver when the vehicle 1300 crosses a lane marking. When the driver indicates an intention to leave the lane by activating a turn signal, the LDW system is deactivated. The LDW system may utilize a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC that is electrically coupled to driver feedback such as a display, speaker, and / or vibration components.

[0223] The LKA system is a variation of the LDW system. If the vehicle 1300 begins to leave the lane, the LKA system provides steering input or braking to correct the vehicle 1300.

[0224] The BSW system detects and warns the driver of vehicles in the car's blind spot. The BSW system can provide visual, audible, and / or tactile alerts to indicate that merging or changing lanes is unsafe. The system can provide additional warnings when the driver uses a turn signal. The BSW system can use a rear-facing camera and / or RADAR sensor 1360 coupled to a dedicated processor, DSP, FPGA, and / or ASIC that is electrically coupled to driver feedback such as a display, speaker, and / or vibration component.

[0225] The RCTW system can provide visual, audible, and / or tactile notifications when an object is detected outside the range of the rear-mounted camera while the vehicle 1300 is in reverse. Some RCTW systems include automatic emergency braking (AEB) to ensure that the vehicle brakes are applied to avoid a collision. The RCTW system can use one or more rear-mounted RADAR sensors 1360 coupled to a dedicated processor, DSP, FPGA, and / or ASIC that is electrically coupled to driver feedback such as a display, speaker, and / or vibration component.

[0226] Conventional ADAS systems can be prone to false positive results, which can be annoying and distracting to the driver, but are typically not catastrophic because the ADAS system alerts the driver and allows the driver to decide whether a safety condition actually exists and act accordingly. However, in the autonomous vehicle 1300, in the event of conflicting results, the vehicle 1300 itself must decide whether to heed the results from the primary computer or the auxiliary computer (e.g., the first controller 1336 or the second controller 1336). For example, in some embodiments, the ADAS system 1338 can be a backup and / or auxiliary computer for providing perception information to the backup computer rationality module. The backup computer rationality monitor can run redundant and diverse software on hardware components to detect failures in perception and dynamic driving tasks. The output from the ADAS system 1338 can be provided to the supervisory MCU. If the outputs from the primary and auxiliary computers conflict, the supervisory MCU must determine how to reconcile the conflict to ensure safe operation.

[0227] In some examples, the primary computer can be configured to provide a confidence score to the supervisory MCU, indicating the primary computer's confidence in the selected result. If the confidence score exceeds a threshold, the supervisory MCU can follow the primary computer's direction, regardless of whether the secondary computer provides conflicting or inconsistent results. In the event that the confidence score does not meet the threshold and the primary and secondary computers indicate different results (e.g., a conflict), the supervisory MCU can arbitrate between these computers to determine the appropriate result.

[0228] The supervisory MCU can be configured to run a neural network that is trained and configured to determine conditions under which the secondary computer provides a false alarm based, at least in part, on outputs from the primary and secondary computers. Thus, the neural network in the supervisory MCU can learn when the output of the secondary computer can be trusted and when it cannot. For example, when the secondary computer is a RADAR-based FCW system, the neural network in the supervisory MCU can learn when the FCW system is identifying a metal object that is not actually a danger, such as a drain grate or manhole cover, which triggers an alarm. Similarly, when the secondary computer is a camera-based LDW system, the neural network in the supervisory MCU can learn to disregard the LDW when a cyclist or pedestrian is present and lane departure is actually the safest strategy. In embodiments that include a neural network running on the supervisory MCU, the supervisory MCU can include at least one of a DLA or a GPU suitable for running the neural network with associated memory. In a preferred embodiment, the supervisory MCU can include and / or be included as a component of the SoC 1304.

[0229] In other examples, the ADAS system 1338 may include an auxiliary computer that uses traditional computer vision rules to perform ADAS functions. In this way, the auxiliary computer can use classic computer vision rules (if-then), and the presence of a neural network in the supervisory MCU can improve reliability, safety, and performance. For example, diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially with respect to failures caused by software (or software-hardware interface) functions. For example, if there is a software vulnerability or bug in the software running on the main computer and the non-identical software code running on the auxiliary computer provides the same overall result, the supervisory MCU can be more confident that the overall result is correct and that the vulnerability in the software or hardware on the main computer did not cause a substantial error.

[0230] In some examples, the output of ADAS system 1338 can be fed into the primary computer's perception block and / or the primary computer's dynamic driving task block. For example, if ADAS system 1338 indicates a forward collision warning due to an object immediately ahead, the perception block can use this information when identifying the object. In other examples, the secondary computer can have its own neural network that is trained and thus reduces the risk of false positives as described herein.

[0231] The vehicle 1300 may also include an infotainment SoC 1330 (e.g., an in-vehicle infotainment system (IVI)). Although illustrated and described as an SoC, the infotainment system may not be an SoC and may include two or more separate components. The infotainment SoC 1330 may include a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., a navigation system, rear parking assistance, radio data system, vehicle-related information such as fuel level, total distance covered, brake fuel level, oil level, door open / closed, air filter information, etc.) to the vehicle 1300. For example, the infotainment SoC 1330 may include a radio, a disc player, a navigation system, a video player, USB and Bluetooth connectivity, an onboard computer, in-car entertainment, WiFi, steering wheel audio controls, hands-free voice controls, a head-up display (HUD), an HMI display 1334, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. The infotainment SoC 1330 may further be used to provide information (e.g., visual and / or auditory) to a user of the vehicle, such as information from an ADAS system 1338, autonomous driving information such as planned vehicle maneuvers, trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0232] The infotainment SoC 1330 may include GPU functionality. The infotainment SoC 1330 may communicate with other devices, systems, and / or components of the vehicle 1400 via a bus 1302 (e.g., a CAN bus, Ethernet, etc.). In some examples, the infotainment SoC 1330 may be coupled to a supervisory MCU so that in the event of a failure of a primary controller 1336 (e.g., a primary and / or backup computer of the vehicle 1300), the infotainment system's GPU may perform some self-driving functions. In such an example, the infotainment SoC 1330 may place the vehicle 1300 in a driver-safe parking mode as described herein.

[0233] The vehicle 1300 may also include an instrument cluster 1332 (e.g., a digital instrument panel, an electronic instrument cluster, a digital instrument panel, etc.). The instrument cluster 1332 may include a controller and / or a supercomputer (e.g., a separate controller or a supercomputer). The instrument cluster 1332 may include a set of instruments, such as a speedometer, fuel level, oil pressure, a tachometer, an odometer, a turn indicator, a shift position indicator, a seat belt warning light, a parking brake warning light, an engine check light, airbag (SRS) system information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between the infotainment SoC 1330 and the instrument cluster 1332. In other words, the instrument cluster 1332 may be included as part of the infotainment SoC 1330, or vice versa.

[0234] Figure 13D For cloud-based servers and Figure 13A 13. System diagram of communication between an example autonomous vehicle 1300. System 1376 may include a server 1378, a network 1390, and a vehicle including vehicle 1300. Server 1378 may include multiple GPUs 1384(A)-1384(H) (collectively referred to herein as GPUs 1384), PCIe switches 1382(A)-1382(H) (collectively referred to herein as PCIe switches 1382), and / or CPUs 1380(A)-1380(B) (collectively referred to herein as CPUs 1380). GPUs 1384, CPUs 1380, and PCIe switches may be interconnected with a high-speed interconnect such as, for example and without limitation, NVLink interface 1388 developed by NVIDIA and / or PCIe connection 1386. In some examples, GPU 1384 is connected via NVLink and / or NVSwitch SoC, and GPU 1384 and PCIe switch 1382 are connected via a PCIe interconnect. Although eight GPUs 1384, two CPUs 1380, and two PCIe switches are shown, this is not intended to be limiting. Depending on the embodiment, each of the servers 1378 may include any number of GPUs 1384, CPUs 1380, and / or PCIe switches. For example, each of the servers 1378 may include eight, sixteen, thirty-two, and / or more GPUs 1384.

[0235] Server 1378 can receive image data from a vehicle via network 1390, the image data representing images showing unexpected or changed road conditions, such as recently begun road construction. Server 1378 can transmit neural network 1392, updated neural network 1392, and / or map information 1394, including information about traffic and road conditions, to the vehicle via network 1390. Updates to map information 1394 can include updates to HD map 1322, such as information about construction sites, potholes, curves, flooding, or other obstacles. In some examples, neural network 1392, updated neural network 1392, and / or map information 1394 can be generated from new training and / or data received from any number of vehicles in the environment and / or based on experience from training performed at a data center (e.g., using server 1378 and / or other servers).

[0236] Server 1378 can be used to train a machine learning model (e.g., a neural network) based on training data. The training data can be generated by the vehicle and / or can be generated in simulation (e.g., using a game engine). In some examples, the training data is labeled (e.g., in cases where the neural network benefits from supervised learning) and / or undergoes other preprocessing, while in other examples, the training data is not labeled and / or preprocessed (e.g., in cases where the neural network does not require supervised learning). Training can be performed according to any one or more categories of machine learning techniques, including but not limited to the following categories: supervised training, semi-supervised training, unsupervised training, self-learning, reinforcement learning, joint learning, transfer learning, feature learning (including principal component and cluster analysis), multilinear subspace learning, manifold learning, representation learning (including alternative dictionary learning), rule-based machine learning, anomaly detection, and any variants or combinations thereof. Once the machine learning model is trained, the machine learning model can be used by the vehicle (e.g., transmitted to the vehicle via network 1390), and / or the machine learning model can be used by server 1378 to remotely monitor the vehicle.

[0237] In some examples, server 1378 can receive data from the vehicle and apply the data to the latest real-time neural network for real-time intelligent reasoning. Server 1378 can include a deep learning supercomputer and / or a dedicated AI computer powered by GPU 1384, such as the DGX and DGX Station machines developed by NVIDIA. However, in some examples, server 1378 can include the deep learning infrastructure of a data center using only CPU power.

[0238] The deep learning infrastructure of server 1378 may be capable of rapid real-time inference and may use this capability to assess and verify the health of the processors, software, and / or associated hardware in vehicle 1300. For example, the deep learning infrastructure may receive periodic updates from vehicle 1300, such as an image sequence and / or objects located in the image sequence that vehicle 1300 has located (e.g., via computer vision and / or other machine learning object classification techniques). The deep learning infrastructure may run its own neural networks to identify objects and compare them to the objects identified by vehicle 1300, and if the results do not match and the infrastructure concludes that the AI ​​in vehicle 1300 has malfunctioned, server 1378 may transmit a signal to vehicle 1300 instructing the vehicle's 1300 fail-safe computer to take control, notify passengers, and complete a safe parking maneuver.

[0239] For inference, server 1378 may include a GPU 1384 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT). The combination of GPU-powered servers and inference acceleration can enable real-time responses. In other examples, such as where performance is less important, CPU, FPGA, and other processor-powered servers can be used for inference.

[0240] Example computing device

[0241] Figure 14 1400 is a block diagram of an example computing device 1400 suitable for implementing some embodiments of the present disclosure. Computing device 1400 may include an interconnect system 1402 that directly or indirectly couples the following devices: memory 1404, one or more central processing units (CPUs) 1406, one or more graphics processing units (GPUs) 1408, a communication interface 1410, input / output (I / O) ports 1412, I / O components 1414, a power supply 1416, one or more presentation components 1418 (e.g., display(s)), and one or more logic units 1420. In at least one embodiment, computing device(s) 1400 may include one or more virtual machines (VMs), and / or any of its components may include virtual components (e.g., virtual hardware components). For non-limiting examples, one or more of GPUs 1408 may include one or more vGPUs, one or more of CPUs 1406 may include one or more vCPUs, and / or one or more of logic units 1420 may include one or more virtual logic units. As such, computing device(s) 1400 may include discrete components (e.g., a full GPU dedicated to computing device 1400), virtual components (e.g., a portion of a GPU dedicated to computing device 1400), or a combination thereof.

[0242] although Figure 14 The various blocks of are shown as being connected via interconnect system 1402 using wires, but this is not intended to be limiting and is provided for clarity only. For example, in some embodiments, presentation component 1418 (such as a display device) may be considered to be I / O component 1414 (e.g., if the display is a touch screen). As another example, CPU 1406 and / or GPU 1408 may include memory (e.g., memory 1404 may represent a storage device in addition to the memory of GPU 1408, CPU 1406, and / or other components). In other words, Figure 14 The computing devices are illustrative only. No distinction is made between such categories as "workstation," "server," "laptop," "desktop," "tablet," "client device," "mobile device," "handheld device," "game console," "electronic control unit (ECU)," "virtual reality system," and / or other device or system types, as all are considered Figure 14 within the range of computing devices.

[0243] Interconnect system 1402 can represent one or more links or buses, such as an address bus, a data bus, a control bus, or a combination thereof. Interconnect system 1402 can include one or more bus or link types, such as an Industry Standard Architecture (ISA) bus, an Extended Industry Standard Architecture (EISA) bus, a Video Electronics Standards Association (VESA) bus, a Peripheral Component Interconnect (PCI) bus, a Peripheral Component Interconnect Express (PCIe) bus, and / or another type of bus or link. In some embodiments, there is a direct connection between components. As an example, CPU 1406 can be directly connected to memory 1404. Further, CPU 1406 can be directly connected to GPU 1408. In the case where there is a direct or point-to-point connection between components, interconnect system 1402 can include a PCIe link to perform the connection. In these examples, the PCI bus does not need to be included in computing device 1400.

[0244] Memory 1404 may include any of a variety of computer-readable media. Computer-readable media can be any available media that can be accessed by computing device 1400. Computer-readable media can include volatile and non-volatile media, as well as removable and non-removable media. By way of example and not limitation, computer-readable media can include computer storage media and communication media.

[0245] Computer storage media may include volatile and nonvolatile media and / or removable and non-removable media implemented in any method or technology for storage of information such as computer-readable instructions, data structures, program modules, and / or other data types. For example, memory 1404 may store computer-readable instructions (e.g., representing (one or more) programs and / or (one or more) program elements, such as an operating system). Computer storage media may include, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage devices or other magnetic storage devices, or any other medium that can be used to store the desired information and that can be accessed by computing device 1400. As used herein, computer storage media does not include signals themselves.

[0246] Computer storage media can embody computer-readable instructions, data structures, program modules, and / or other data types in a modulated data signal such as a carrier wave or other transport mechanism, and includes any information delivery media. The term "modulated data signal" may refer to a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. By way of example, and not limitation, computer storage media can include wired media (such as a wired network or direct-wired connection) and wireless media (such as acoustic, RF, infrared, and other wireless media). Combinations of any of the above should also be included within the scope of computer-readable media.

[0247] The CPU 1406 may be configured to execute at least some of the computer-readable instructions to control one or more components of the computing device 1400 to perform one or more of the methods and / or processes described herein. The CPUs 1406 may each include one or more cores (e.g., one, two, four, eight, twenty-eight, seventy-two, etc.) capable of handling numerous software threads simultaneously. The CPU 1406 may include any type of processor and may include different types of processors depending on the type of computing device 1400 being implemented (e.g., a processor with fewer cores for a mobile device and a processor with more cores for a server). For example, depending on the type of computing device 1400, the processor may be an Advanced RISC Machine (ARM) processor implemented using Reduced Instruction Set Computing (RISC) or an x86 processor implemented using Complex Instruction Set Computing (CISC). The computing device 1400 may also include one or more CPUs 1406 in addition to one or more microprocessors or supplemental coprocessors (such as a math coprocessor).

[0248] In addition to or in lieu of CPU(s) 1406, GPU(s) 1408 may be configured to execute at least some of the computer-readable instructions to control one or more components of computing device 1400 to perform one or more of the methods and / or processes described herein. One or more of GPUs 1408 may be integrated GPUs (e.g., with one or more of CPUs 1406) and / or one or more of GPUs 1408 may be discrete GPUs. In embodiments, one or more of GPUs 1408 may be coprocessors for one or more of CPUs 1406. GPU 1408 may be used by computing device 1400 to render graphics (e.g., 3D graphics) or perform general-purpose computations. For example, GPU 1408 may be used for general-purpose computing on a GPU (GPGPU). GPU 1408 may include hundreds or thousands of cores capable of handling hundreds or thousands of software threads simultaneously. GPU 1408 may generate pixel data for an output image in response to rendering commands (e.g., rendering commands received from CPU 1406 via a host interface). GPU 1408 may include graphics memory (e.g., display memory) for storing pixel data or any other suitable data (e.g., GPGPU data). Display memory may be included as part of memory 1404. GPU 1408 may include two or more GPUs operating in parallel (e.g., via a link). The link may directly connect the GPUs (e.g., using NVLINK) or may connect the GPUs through a switch (e.g., using NVSwitch). When combined, each GPU 1408 may generate pixel data or GPGPU data for a different portion of an output or for different outputs (e.g., a first GPU for a first image and a second GPU for a second image). Each GPU may include its own memory or may share memory with other GPUs.

[0249] In addition to or in lieu of the CPU 1406 and / or GPU 1408, the logic unit 1420 may be configured to execute at least some of the computer-readable instructions to control one or more components of the computing device 1400 to perform one or more of the methods and / or processes described herein. In embodiments, the CPU(s) 1406, the GPU(s) 1408, and / or the logic unit(s) 1420 may execute any combination of methods, processes, and / or portions thereof, either discretely or jointly. One or more of the logic units 1420 may be part of and / or integrated into one or more of the CPU 1406 and / or GPU 1408, and / or one or more of the logic units 1420 may be discrete components or otherwise external to the CPU 1406 and / or GPU 1408. In embodiments, one or more of logic units 1420 may be a co-processor to one or more of CPUs 1406 and / or one or more of GPUs 1408 .

[0250] Examples of logic unit 1420 include one or more processing cores and / or components thereof, such as a data processing unit (DPU), a tensor core (TC), a tensor processing unit (TPU), a pixel vision core (PVC), a vision processing unit (VPU), a graphics processing cluster (GPC), a texture processing cluster (TPC), a streaming multiprocessor (SM), a tree transverse unit (TTU), an artificial intelligence accelerator (AIA), a deep learning accelerator (DLA), an arithmetic logic unit (ALU), an application-specific integrated circuit (ASIC), a floating point unit (FPU), an input / output (I / O) element, a peripheral component interconnect (PCI) or a peripheral component interconnect express (PCIe) element, etc.

[0251] The communication interface 1410 may include one or more receivers, transmitters, and / or transceivers that enable the computing device 1400 to communicate with other computing devices via an electronic communication network (including wired and / or wireless communications). The communication interface 1410 may include components and functionality that implement communication over any of a number of different networks, such as a wireless network (e.g., Wi-Fi, Z-Wave, Bluetooth, Bluetooth LE, ZigBee, etc.), a wired network (e.g., via Ethernet or Wi-Fi), a low-power wide-area network (e.g., LoRaWAN, SigFox, etc.), and / or the Internet. In one or more embodiments, the logic unit 1420 and / or the communication interface 1410 may include one or more data processing units (DPUs) to transmit data received over the network and / or through the interconnect system 1402 directly to the one or more GPUs 1408 (e.g., memory of the one or more GPUs 1408).

[0252] I / O ports 1412 can enable computing device 1400 to be logically coupled to other devices including I / O components 1414, (one or more) presentation components 1418, and / or other components, some of which may be built into (e.g., integrated into) computing device 1400. Illustrative I / O components 1414 include a microphone, a mouse, a keyboard, a joystick, a game pad, a game controller, a satellite dish, a scanner, a printer, a wireless device, and the like. I / O components 1414 can provide a natural user interface (NUI) that processes air gestures, voice, or other physiological input generated by a user. In some cases, the input can be transmitted to an appropriate network element for further processing. The NUI can implement any combination of voice recognition, stylus recognition, facial recognition, biometric recognition, gesture recognition on and near the screen, air gestures, head and eye tracking, and touch recognition (as described in more detail below) associated with the display of computing device 1400. Computing device 1400 may include a depth camera for gesture detection and recognition, such as a stereo camera system, an infrared camera system, an RGB camera system, touch screen technology, and combinations thereof. Additionally, computing device 1400 may include an accelerometer or gyroscope that enables detection of motion (e.g., as part of an inertial measurement unit (IMU)). In some examples, computing device 1400 may use the output of the accelerometer or gyroscope to render immersive augmented or virtual reality.

[0253] The power supply 1416 may include a hardwired power supply, a battery power supply, or a combination thereof. The power supply 1416 may provide power to the computing device 1400 to enable the components of the computing device 1400 to operate.

[0254] The presentation component 1418 may include a display (e.g., a monitor, a touch screen, a television screen, a head-up display (HUD), other display types, or a combination thereof), speakers, and / or other presentation components. The presentation component 1418 may receive data from other components (e.g., the GPU 1408, the CPU 1406, etc.) and output the data (e.g., as images, video, sound, etc.).

[0255] Sample Data Center

[0256] Figure 15 An example data center 1500 that may be used in at least one embodiment of the present disclosure is shown. The data center 1500 may include a data center infrastructure layer 1510, a framework layer 1520, a software layer 1530, and / or an application layer 1540.

[0257] like Figure 15 As shown, the data center infrastructure layer 1510 may include a resource coordinator 1512, grouped computing resources 1514, and node computing resources ("node CRs") 1516(1)-1516(N), where "N" represents any complete positive integer. In at least one embodiment, the node CRs 1516(1)-1516(N) may include, but is not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors or graphics processing units (GPUs), etc.), memory devices (e.g., dynamic read-only memories), storage devices (e.g., solid-state or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules and / or cooling modules, etc. In some embodiments, one or more of the node CRs 1516(1)-1516(N) may correspond to a server having one or more of the above-mentioned computing resources. Furthermore, in some embodiments, node CRs 1516(1)-15161(N) may include one or more virtual components, such as vGPUs, vCPUs, etc., and / or one or more of node CRs 1516(1)-1516(N) may correspond to a virtual machine (VM).

[0258] In at least one embodiment, the grouped computing resources 1514 may include separate groups of node CRs 1516 housed in one or more racks (not shown), or multiple racks housed in data centers at different geographical locations (also not shown). Separate groups of node CRs 1516 within the grouped computing resources 1514 may include grouped computing, network, memory, or storage resources that can be configured or allocated to support one or more workloads. In at least one embodiment, several node CRs 1516 including CPUs, GPUs, DPUs, and / or other processors may be grouped in one or more racks to provide computing resources to support one or more workloads. One or more racks may also include any number of power modules, cooling modules, and / or network switches in any combination.

[0259] Resource coordinator 1522 may configure or otherwise control one or more node CRs 1516(1)-1516(N) and / or grouped computing resources 1514. In at least one embodiment, resource coordinator 1522 may comprise a software design infrastructure ("SDI") management entity for data center 1500. Resource coordinator 1522 may comprise hardware, software, or some combination thereof.

[0260] In at least one embodiment, Figure 15 As shown, the framework layer 1520 may include a job scheduler 1533, a configuration manager 1534, a resource manager 1536 and / or a distributed file system 1538. The framework layer 1520 may include a framework that supports software 1532 of the software layer 1530 and / or one or more applications 1542 of the application layer 1540. The software 1532 or the application 1542 may include network-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. The framework layer 1520 may be, but is not limited to, a free and open source software network application framework (such as Apache Spark) that can utilize the distributed file system 1538 for large-scale data processing (e.g., "big data"). TM(hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 1532 may include a Spark driver to facilitate scheduling workloads supported by the different layers of the data center 1500. The configuration manager 1534 may be capable of configuring the different layers, such as the software layer 1530 and the framework layer 1520 (which includes Spark and a distributed file system 1538 for supporting large-scale data processing). The resource manager 1536 may be capable of managing clustered or grouped computing resources that are mapped to the distributed file system 1538 and the job scheduler 1533 or allocated to support the distributed file system 1538 and the job scheduler 1533. In at least one embodiment, the clustered or grouped computing resources may include the grouped computing resources 1514 at the data center infrastructure layer 1510. The resource manager 1536 may coordinate with the resource coordinator 1512 to manage these mapped or allocated computing resources.

[0261] In at least one embodiment, the software 1532 included in the software layer 1530 may include software used by at least a portion of the node CRs 1516(1)-1516(N), the grouped computing resources 1514, and / or the distributed file system 1538 of the framework layer 1520. The one or more types of software may include, but are not limited to, Internet web search software, email virus scanning software, database software, and streaming video content software.

[0262] In at least one embodiment, the applications 1542 included in the application layer 1540 may include one or more types of applications used by at least a portion of the node CRs 1516(1)-1516(N), the grouped computing resources 1514, and / or the distributed file system 1538 of the framework layer 1520. The one or more types of applications may include, but are not limited to, any number of genomic applications, cognitive computing, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), and / or other machine learning applications used in conjunction with one or more embodiments.

[0263] In at least one embodiment, any of configuration manager 1534, resource manager 1536, and resource coordinator 1512 can implement any number and type of self-modification actions based on any amount and type of data acquired in any technically feasible manner. The self-modification actions can save a data center operator of data center 1500 from making potentially poor configuration decisions and potentially avoiding underutilized and / or poorly performing portions of the data center.

[0264] According to one or more embodiments described herein, data center 1500 may include tools, services, software, or other resources to train one or more machine learning models or use one or more machine learning models to predict or infer information. For example, the machine learning model(s) may be trained by computing weight parameters according to a neural network architecture using the software and / or computing resources described above with respect to data center 1500. In at least one embodiment, a trained or deployed machine learning model corresponding to one or more neural networks may be used to infer or predict information using the resources described above with respect to data center 1500 using weight parameters computed using one or more training techniques, such as, but not limited to, those described herein.

[0265] In at least one embodiment, data center 1500 may use a CPU, an application-specific integrated circuit (ASIC), a GPU, an FPGA, and / or other hardware (or virtual computing resources corresponding thereto) to perform training and / or inference using the aforementioned resources. In addition, one or more of the software and / or hardware resources described above may be configured to allow a user to train or perform inference services on information, such as image recognition, speech recognition, or other artificial intelligence services.

[0266] Sample network environment

[0267] A network environment suitable for implementing embodiments of the present disclosure may include one or more client devices, servers, network attached storage (NAS), other backend devices, and / or other device types. The client devices, servers, and / or other device types (e.g., each device) may be configured to: Figure 14 The backend devices 1500 may be implemented on one or more instances of the computing device(s) 1400 - for example, each device may include similar components, features, and / or functionality of the computing device(s) 1400. In addition, in the case of implementing backend devices (e.g., servers, NAS, etc.), the backend devices may be included as part of the data center 1500, examples of which are discussed herein with respect to FIG. Figure 15 Describe in more detail.

[0268] The components of the network environment can communicate with each other via a network, which can be wired, wireless, or both. The network can include multiple networks or one of multiple networks. For example, the network can include one or more wide area networks (WANs), one or more local area networks (LANs), one or more public networks (such as the Internet and / or the Public Switched Telephone Network (PSTN)), and / or one or more private networks. In the case where the network includes a wireless telecommunications network, components such as base stations, communication towers, or even access points (and other components) can provide wireless connectivity.

[0269] Compatible network environments may include one or more peer-to-peer network environments (in which case the server may not be included in the network environment) and one or more client-server network environments (in which case one or more servers may be included in the network environment). In a peer-to-peer network environment, the functionality described herein for the server may be implemented on any number of client devices.

[0270] In at least one embodiment, the network environment may include one or more cloud-based network environments, distributed computing environments, combinations thereof, and the like. The cloud-based network environment may include a framework layer, a job scheduler, a resource manager, and a distributed file system implemented on one or more servers, which may include one or more core network servers and / or edge servers. The framework layer may include software supporting the software layer and / or a framework for one or more applications at the application layer. The software or application may include network-based service software or applications, respectively. In an embodiment, one or more client devices may use network-based service software or applications (e.g., by accessing the service software and / or application via one or more application programming interfaces (APIs)). The framework layer may be, but is not limited to, a free and open source software network application framework that can use a distributed file system for large-scale data processing (e.g., "big data").

[0271] A cloud-based network environment can provide cloud computing and / or cloud storage that performs any combination of the computing and / or data storage functions described herein (or one or more portions thereof). Any of these different functions can be distributed across multiple locations from a central or core server (e.g., one or more data centers that can be distributed across a state, region, country, global, etc.). If the connection to the user (e.g., client device) is relatively close to an edge server, the core server can assign at least a portion of the functionality to the edge server. A cloud-based network environment can be private (e.g., limited to a single organization), public (e.g., available to many organizations), and / or a combination thereof (e.g., a hybrid cloud environment).

[0272] The client device(s) may include the Figure 14At least some of the components, features, and functionality of the described example computing device(s) 1400. By way of example and not limitation, the client device may be implemented as a personal computer (PC), a laptop computer, a mobile device, a smartphone, a tablet computer, a smartwatch, a wearable computer, a personal digital assistant (PDA), an MP3 player, a virtual reality headset, a global positioning system (GPS) or device, a video player, a camera, a surveillance device or system, a vehicle, a boat, a spacecraft, a virtual machine, a drone, a robot, a handheld communication device, a hospital device, a gaming device or system, an entertainment system, a vehicle computer system, an embedded system controller, a remote control, an appliance, a consumer electronic device, a workstation, an edge device, any combination of the depicted devices, or any other suitable device.

[0273] The present disclosure can be described in the general context of machine-usable instructions or computer code executed by a computer or other machine such as a personal digital assistant or other handheld device, including computer-executable instructions such as program modules. Generally, program modules including routines, programs, objects, components, data structures, etc. refer to code that performs a specific task or implements a specific abstract data type. The present disclosure can be practiced in a variety of system configurations, including handheld devices, consumer electronics, general-purpose computers, more specialized computing devices, etc. The present disclosure can also be practiced in a distributed computing environment where tasks are performed by remote processing devices linked through a communication network.

[0274] As used herein, the phrase "and / or" with respect to two or more elements should be interpreted as referring to only one element or combination of elements. For example, "element A, element B, and / or element C" may include only element A, only element B, only element C, element A and element B, element A and element C, element B and element C, or elements A, B, and C. In addition, "at least one of element A or element B" may include at least one of element A, at least one of element B, or at least one of element A and at least one of element B. Further, "at least one of element A and element B" may include at least one of element A, at least one of element B, or at least one of element A and at least one of element B.

[0275] The subject matter of the present disclosure is described in detail herein to meet statutory requirements. However, the description itself is not intended to limit the scope of the present disclosure. On the contrary, the present inventors have contemplated that the claimed subject matter may also be embodied in other ways to include steps that are different from the steps described herein in conjunction with other current or future technologies, or combinations of similar steps. Moreover, although the terms "step" and / or "block" may be used herein to imply different elements of the method employed, these terms should not be interpreted as implying any particular order among or between the various steps disclosed herein, unless the order of the steps is explicitly described.

Claims

1. A method comprising: determining a shift pose of a pose configuration space representing a pose of a machine in an environment based on at least translating a set of poses corresponding to a trajectory in a pose configuration space along at least one axis to produce a shift trajectory, the translating comprising accessing the pose configuration space using a memory access pattern defining the shift pose of the shift trajectory; determining a path from the first one of the poses to a second one of the poses based at least on evaluating reachability of the displacement pose from a first pose using parallel processing of the displacement trajectory; as well as One or more operations of the machine are caused based on the determined path.

2. The method of claim 1, wherein the displacement trajectories are parallel to each other along the at least one axis.

3. The method of claim 1, wherein the at least one axis comprises an axis representing an orientation of the machine in the environment. 4 . The method of claim 1 , wherein each of the trajectories includes turns having a fixed turn radius throughout the trajectory. 5 . The method of claim 1 , wherein the parallel processing comprises evaluating a first subset of the displacement gestures of the displacement trajectories in parallel with a second subset of the displacement gestures of the displacement trajectories. 6 . The method of claim 1 , wherein the parallel processing comprises evaluating a first subset of the shift gestures of a first one of the shift trajectories in parallel with a second subset of the shift gestures of a second one of the shift trajectories. 7 . The method of claim 1 , wherein the reachability is processed by a thread of a processor into a bit vector, and each bit of the bit vector corresponds to a pose in the shift pose and a trajectory in the shift trajectory. The method of claim 1 , wherein the translating is performed while performing the evaluating of the reachability.

9. The method of claim 1 , wherein translating the set of poses comprises generating a transition pose configuration space from a pose configuration space, the transition pose configuration space comprising the shift poses of the shift trajectory in a memory, and performing the evaluation of the reachability of the shift poses using the transition pose configuration space in the memory.

10. A system comprising: one or more processors; as well as one or more memory devices storing instructions that, when executed by the one or more processors, cause the one or more processors to perform a method comprising: translating a trajectory of a machine in the posture configuration space into a shifted trajectory based at least on accessing a posture configuration space using a memory access pattern defining a shifted trajectory, the shifted trajectory comprising at least a plurality of segments of the trajectory of the machine that are parallel to each other and to at least one axis of the posture configuration space; processing at least a plurality of segments of the displacement trajectory in parallel along the at least one axis to compute an indicator of reachability associated with the displacement trajectory; determining a path through the pose configuration space based at least on the indicator of reachability; and One or more operations corresponding to the behavior of the machine are performed based on the determined path.

11. The system of claim 10, wherein the pose configuration space is parameterized by at least (x, y, θ), where (x, y) represents the position of the machine in a two-dimensional (2D) plane and θ represents the heading angle of the machine at that position.

12. The system of claim 10, wherein the indicator of reachability comprises costs stored in one or more cost spaces parameterized by at least a pose of the pose configuration space, and determination of the path comprises backtracing from a first pose of the path to a second pose of the path using the one or more cost spaces.

13. The system of claim 10, further comprising: determining a free space for a pose in the pose configuration space based at least on collision information of a body of the machine having the pose against one or more obstacles; as well as An indicator of the free space is stored in one or more occupied spaces parameterized by at least the pose of the pose configuration space, wherein the indicator of reachability is based at least on evaluating the indicator of the free space in the one or more occupied spaces for the displacement trajectory.

14. The system of claim 10, wherein determining the path comprises: computing a first set of reachability indicators in a first iteration corresponding to a first traversal of the displacement trajectory; as well as A second set of indicators of reachability in a second iteration corresponding to a second traversal of the shift trajectory is calculated from the first set of indicators of reachability.

15. The system of claim 10, wherein the system comprises at least one of: control systems for autonomous or semi-autonomous machines; Perception systems for autonomous or semi-autonomous machines; a system for performing simulation operations; Systems for performing deep learning operations; Systems implemented using edge devices; Systems implemented using robots; A system for merging one or more virtual machines VM; A system implemented at least in part in a data center; or A system implemented at least in part using cloud computing resources.

16. A non-transitory computer-readable storage device having stored thereon instructions that, when executed by one or more processors, cause the one or more processors to: For evaluating reachability of an object at a shift posture of the shift trajectory based at least on translating a posture of a posture configuration space corresponding to a trajectory along at least one axis, using parallel processing of segments of the shift trajectory, to generate the shift trajectory based at least on accessing the posture configuration space using a memory access pattern that defines the shift posture of the shift trajectory, and for determining a path of the object from a first posture in the posture configuration space to a second posture in the posture configuration space based at least on the reachability of the shift posture of the shift trajectory.

17. The non-transitory computer-readable storage device of claim 16, wherein the parallel processing of the segments comprises: calculating, for a first one of the segments, an indicator of the reachability out of the first segment as initiated within the first segment; calculating an indicator of the reachability into a second one of the segments using the indicator of the reachability out of the first segment; as well as Indicators of the reachability of one or more of the displacement gestures within the first segment from the first gesture are calculated using the indicator of the reachability into the second segment.

18. The non-transitory computer-readable storage device of claim 16, wherein determining the path is based at least on the one or more indicators of the reachability of one or more of the displacement poses, the one or more indicators comprising one or more costs associated with the object reaching the displacement pose.

19. The non-transitory computer-readable storage device of claim 16, wherein the reachability of the displacement gesture is evaluated relative to the first gesture.

20. The non-transitory computer readable storage device of claim 16, wherein the trajectory comprises a circle formed by turns in a ground plane of an environment, the turns having a constant turn radius throughout the trajectory.

Images