Backplane, riser card and server

Abstract

The embodiment of the present application provides a backboard, a riser card and a server, which comprise at least one D flip-flop, a first crystal oscillator and at least two output pins, the first crystal oscillator is connected with one output pin, the at least one D flip-flop is connected with the remaining output pins, and each output pin is connected with a cable. The first crystal oscillator is used for generating a base frequency signal, and transmitting the base frequency signal to one output pin connected with the first crystal oscillator and one D flip-flop. The at least one D flip-flop is used for generating a frequency division signal according to the base frequency signal, and transmitting the frequency division signal to the remaining output pins. One output pin connected with the first crystal oscillator transmits the base frequency signal to a mainboard, and the remaining output pins transmit the frequency division signal to the mainboard. The mainboard can judge whether the cables between the backboard are correctly connected according to the base frequency signal and / or the frequency division signal, so that the detection of multiple cables is realized, and a CPLD does not need to be placed on the backboard, the D flip-flop and the crystal oscillator occupy a smaller layout space on the backboard, and the cost of the backboard is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of servers, and in particular to a backboard, a riser card and a server. BACKGROUND

[0002] With the continuous development of the computer industry, the rate of data communication is getting faster and faster, and the requirement for signal transmission rate is getting higher and higher. In order to meet the higher signal transmission rate requirement, more and more high-speed cables are used between the internal mainboard and the backboard of the server, and between the mainboard and the riser card.

[0003] Since the mainboard interface, the backboard interface and the riser card interface are mostly consistent, the cables are easily inserted incorrectly in the assembly link, resulting in data transmission problems.

[0004] Therefore, how to detect whether the cables in the server are inserted incorrectly is currently a more important problem. SUMMARY

[0005] The embodiments of the present application provide a backboard, a riser card and a server, which can effectively detect whether the cables in the server are inserted incorrectly.

[0006] In a first aspect, the embodiments of the present application provide a backboard, comprising:

[0007] a first crystal oscillator, at least one D flip-flop and at least two output pins;

[0008] The first crystal oscillator is connected with one D flip-flop and one output pin, the at least one D flip-flop is connected with the remaining output pins, and each output pin is connected with a cable.

[0009] The first crystal oscillator is configured to generate a base frequency signal and transmit the base frequency signal to the one D flip-flop and the one output pin, and the at least one D flip-flop is configured to generate a frequency division signal according to the base frequency signal and transmit the frequency division signal to the remaining output pins.

[0010] The one output pin is configured to transmit the base frequency signal to a mainboard, the remaining output pins are configured to transmit the frequency division signal to the mainboard, and the mainboard is configured to determine whether the cables between the mainboard and the backboard are correctly connected according to the base frequency signal and / or the frequency division signal.

[0011] The backboard provided by the embodiment of the application comprises a first crystal oscillator, at least one D flip-flop and at least two output pins, each of which is connected with a cable, the first crystal oscillator generates a base frequency signal, and then transmits the base frequency signal to one output pin and one D flip-flop, the D flip-flop can generate a frequency division signal according to the base frequency signal and transmit the frequency division signal to the remaining output pins, one output pin transmits the base frequency signal to the mainboard, and the remaining output pins also transmit the frequency division signal to the mainboard, so that the mainboard can determine whether the cables between the mainboard and the backboard are correctly connected according to the base frequency signal and / or the frequency division signal, thereby realizing the detection of multiple lines, and without placing a CPLD on the backboard, the layout space and cost of the backboard are reduced.

[0012] Optionally, the at least two output pins comprise a first output pin, a second output pin and a third output pin.

[0013] The first crystal oscillator is connected with the first output pin, the at least one D flip-flop is connected with the second output pin and the third output pin, the first output pin is connected with a first cable, the second output pin is connected with a second cable, and the third output pin is connected with a third cable.

[0014] The first crystal oscillator is configured to transmit the base frequency signal to the first output pin, and the at least one D flip-flop is configured to generate a two-division frequency signal and a four-division frequency signal according to the base frequency signal, transmit the two-division frequency signal to the second output pin, and transmit the four-division frequency signal to the third output pin.

[0015] The first output pin transmits the base frequency signal to the mainboard through the first cable, the second output pin transmits the two-division frequency signal to the mainboard through the second cable, and the third output pin transmits the four-division frequency signal to the mainboard through the third cable.

[0016] The mainboard is configured to determine whether the first cable between the mainboard and the backboard is correctly connected according to the base frequency signal, determine whether the second cable between the mainboard and the backboard is correctly connected according to the two-division frequency signal, and determine whether the third cable between the mainboard and the backboard is correctly connected according to the four-division frequency signal.

[0017] The backboard provided in the embodiment comprises a first output pin, a second output pin and a third output pin, the first output pin is connected with a first cable, the second output pin is connected with a second cable, and the third output pin is connected with a third cable; a first crystal oscillator transmits a base frequency signal to the first output pin; a D flip-flop transmits a two-divided frequency signal to the second output pin and a four-divided frequency signal to the third output pin; the first output pin transmits the base frequency signal to a mainboard, the second output pin transmits the two-divided frequency signal to the mainboard, and the third output pin transmits the four-divided frequency signal to the mainboard; the mainboard can determine whether the first cable between the mainboard and the backboard is correctly connected according to the base frequency signal, whether the second cable between the mainboard and the backboard is correctly connected according to the two-divided frequency signal, and whether the third cable between the mainboard and the backboard is correctly connected according to the four-divided frequency signal, so that the detection of the three cables is realized.

[0018] Optionally, the at least one D flip-flop comprises a first flip-flop and a second flip-flop;

[0019] The first flip-flop comprises a first clock pin, a first trigger pin, a first non-inverted output pin and a first inverted output pin, and the second flip-flop comprises a second clock pin, a second trigger pin, a second non-inverted output pin and a second inverted output pin;

[0020] The first inverted output pin is connected with the first trigger pin, the first non-inverted output pin is connected with the second clock pin, and the second inverted output pin is connected with the second trigger pin;

[0021] The first clock pin receives the base frequency signal;

[0022] The first non-inverted output pin outputs a two-divided frequency signal of the base frequency signal to the second clock pin and the second output pin;

[0023] The second non-inverted output pin outputs a four-divided frequency signal of the base frequency signal to the third output pin.

[0024] The backboard provided in the embodiment comprises a first flip-flop and a second flip-flop, which can generate a two-divided frequency signal and a four-divided frequency signal according to a base frequency signal, so that a mainboard can detect whether a cable between the mainboard and the backboard is correctly connected according to the divided frequency signal.

[0025] In a second aspect, the application provides a Riser card, comprising:

[0026] a second crystal oscillator, at least one D flip-flop and at least two output pins;

[0027] The second crystal oscillator is connected with a D flip-flop and an output pin, the at least one D flip-flop is connected with the remaining output pins, and each of the output pins is connected with a cable;

[0028] The second crystal oscillator is configured to generate a base frequency signal and transmit the base frequency signal to the D flip-flop and the output pin, and the at least one D flip-flop is configured to generate a divided frequency signal according to the base frequency signal and transmit the divided frequency signal to the remaining output pins.

[0029] The output pin is configured to transmit the base frequency signal to a mainboard, and the remaining output pins are configured to transmit the divided frequency signal to the mainboard, and the mainboard is configured to determine whether the cables between the mainboard and the Riser card are correctly connected according to the base frequency signal and / or the divided frequency signal.

[0030] The Riser card provided by the embodiment of the present application comprises a second crystal oscillator, at least one D flip-flop and at least two output pins, each of the output pins is connected with a cable, the second crystal oscillator generates a base frequency signal and transmits the base frequency signal to an output pin and a D flip-flop, the D flip-flop can generate a divided frequency signal according to the base frequency signal and transmit the divided frequency signal to the remaining output pins, the output pin transmits the base frequency signal to a mainboard, and the remaining output pins also transmit the divided frequency signal to the mainboard, so that the mainboard can determine whether the cables between the mainboard and the Riser card are correctly connected according to the base frequency signal and / or the divided frequency signal, thereby realizing multi-line detection and reducing the layout space and cost of the backboard without placing a CPLD on the backboard.

[0031] Optionally, the at least two output pins comprise a fourth output pin, a fifth output pin and a sixth output pin.

[0032] The second crystal oscillator is connected with the fourth output pin, the at least one D flip-flop is connected with the fifth output pin and the sixth output pin, the fourth output pin is connected with a fourth cable, the fifth output pin is connected with a fifth cable, and the sixth output pin is connected with a sixth cable.

[0033] The second crystal oscillator is configured to transmit the base frequency signal to the fourth output pin, and the at least one D flip-flop is configured to generate a two-divided frequency signal and a four-divided frequency signal according to the base frequency signal, transmit the two-divided frequency signal to the fifth output pin and transmit the four-divided frequency signal to the sixth output pin.

[0034] The fourth output pin transmits the base frequency signal to the mainboard through the fourth cable, the fifth output pin transmits the two-divided frequency signal to the mainboard through the fifth cable, and the sixth output pin transmits the four-divided frequency signal to the mainboard through the sixth cable.

[0035] The mainboard is configured to determine whether the fourth cable between the mainboard and the Riser card is correctly connected according to the base frequency signal, to determine whether the fifth cable between the mainboard and the Riser card is correctly connected according to the half frequency signal, and to determine whether the sixth cable between the mainboard and the Riser card is correctly connected according to the quarter frequency signal.

[0036] The Riser card provided by the embodiment comprises a fourth output pin, a fifth output pin and a sixth output pin, the fourth output pin is connected with the fourth cable, the fifth output pin is connected with the fifth cable, and the sixth output pin is connected with the sixth cable; the second crystal oscillator transmits the base frequency signal to the fourth output pin, the D flip-flop transmits the half frequency signal to the fifth output pin and transmits the quarter frequency signal to the sixth output pin; the fourth output pin transmits the base frequency signal to the mainboard, the fifth output pin transmits the half frequency signal to the mainboard, and the sixth output pin transmits the quarter frequency signal to the mainboard; the mainboard can determine whether the fourth cable between the mainboard and the Riser card is correctly connected according to the base frequency signal, determine whether the fifth cable between the mainboard and the Riser card is correctly connected according to the half frequency signal, and determine whether the sixth cable between the mainboard and the Riser card is correctly connected according to the quarter frequency signal, thereby realizing the detection of three cables.

[0037] In a third aspect, the present application provides a server, comprising:

[0038] at least one of a backboard and a Riser card, and a mainboard;

[0039] The backboard and the Riser card comprise:

[0040] a crystal oscillator, at least one D flip-flop and at least two output pins;

[0041] The crystal oscillator is connected with one D flip-flop and one output pin, the at least one D flip-flop is connected with the remaining output pins, and each output pin is connected with a cable;

[0042] The crystal oscillator is configured to generate a base frequency signal and transmit the base frequency signal to the one D flip-flop and the one output pin, and the at least one D flip-flop is configured to generate a frequency division signal according to the base frequency signal and transmit the frequency division signal to the remaining output pins;

[0043] The one output pin is configured to transmit the base frequency signal to the mainboard, the remaining output pins are configured to transmit the frequency division signal to the mainboard, and the mainboard is configured to determine whether the cables between the backboard and / or the Riser card are correctly connected according to the base frequency signal and / or the frequency division signal.

[0044] The server provided by the embodiment of the present application comprises at least one of a backboard and a riser card and a mainboard, the backboard and the riser card each comprise a crystal oscillator, at least one D flip-flop and at least two output pins, the crystal oscillator generates a base frequency signal, and then transmits the base frequency signal to one output pin and one D flip-flop, the D flip-flop can generate a frequency division signal according to the base frequency signal and transmit the frequency division signal to the remaining output pins, one output pin transmits the base frequency signal to the mainboard, and the remaining output pins also transmit the frequency division signal to the mainboard, so that the mainboard can determine whether the cables between the mainboard and the backboard and / or the mainboard and the riser card are correctly connected according to the base frequency signal and / or the frequency division signal, thereby realizing detection of multiple lines in the server, and without placing a CPLD on the backboard and / or the riser card, the layout space and the cost of the backboard and / or the riser card are reduced.

[0045] Optionally, the backboard comprises:

[0046] a first crystal oscillator, a first output pin, a second output pin and a third output pin;

[0047] The first crystal oscillator is connected with the first output pin, the at least one D flip-flop is connected with the second output pin and the third output pin, the first output pin is connected with a first cable, the second output pin is connected with a second cable, and the third output pin is connected with a third cable;

[0048] The first crystal oscillator is configured to transmit the base frequency signal to the first output pin, and the at least one D flip-flop is configured to generate a two-division frequency signal and a four-division frequency signal according to the base frequency signal, transmit the two-division frequency signal to the second output pin and transmit the four-division frequency signal to the third output pin;

[0049] The first output pin transmits the base frequency signal to the mainboard through the first cable, the second output pin transmits the two-division frequency signal to the mainboard through the second cable, and the third output pin transmits the four-division frequency signal to the mainboard through the third cable;

[0050] The mainboard is configured to determine whether a first cable between the mainboard and the backboard is correctly connected according to the base frequency signal, determine whether a second cable between the mainboard and the backboard is correctly connected according to the two-division frequency signal, and determine whether a third cable between the mainboard and the backboard is correctly connected according to the four-division frequency signal.

[0051] The server provided by the embodiment comprises a backboard, the backboard comprises a first output pin, a second output pin and a third output pin, the first output pin is connected with a first cable, the second output pin is connected with a second cable, and the third output pin is connected with a third cable; a first crystal oscillator transmits a base frequency signal to the first output pin; a D flip-flop transmits a two-divided frequency signal to the second output pin and a four-divided frequency signal to the third output pin; the first output pin transmits the base frequency signal to a mainboard; the second output pin transmits the two-divided frequency signal to the mainboard; and the third output pin transmits the four-divided frequency signal to the mainboard; the mainboard can determine whether the first cable between the mainboard and the backboard is correctly connected according to the base frequency signal, whether the second cable between the mainboard and the backboard is correctly connected according to the two-divided frequency signal, and whether the third cable between the mainboard and the backboard is correctly connected according to the four-divided frequency signal, so as to realize detection of multiple cables in the server.

[0052] Optionally, the Riser card comprises:

[0053] a second crystal oscillator, a fourth output pin, a fifth output pin and a sixth output pin;

[0054] The second crystal oscillator is connected with the fourth output pin, the at least one D flip-flop is connected with the fifth output pin and the sixth output pin, the fourth output pin is connected with a fourth cable, the fifth output pin is connected with a fifth cable, and the sixth output pin is connected with a sixth cable;

[0055] The second crystal oscillator is configured to transmit the base frequency signal to the fourth output pin; the at least one D flip-flop is configured to generate a two-divided frequency signal and a four-divided frequency signal according to the base frequency signal, transmit the two-divided frequency signal to the fifth output pin, and transmit the four-divided frequency signal to the sixth output pin;

[0056] The fourth output pin transmits the base frequency signal to the mainboard through the fourth cable, the fifth output pin transmits the two-divided frequency signal to the mainboard through the fifth cable, and the sixth output pin transmits the four-divided frequency signal to the mainboard through the sixth cable;

[0057] The mainboard is configured to determine whether the fourth cable between the mainboard and the Riser card is correctly connected according to the base frequency signal, whether the fifth cable between the mainboard and the Riser card is correctly connected according to the two-divided frequency signal, and whether the sixth cable between the mainboard and the Riser card is correctly connected according to the four-divided frequency signal.

[0058] The server provided in the embodiment comprises a riser card, the riser card comprises a fourth output pin, a fifth output pin and a sixth output pin, the fourth output pin is connected with the fourth cable, the fifth output pin is connected with the fifth cable, and the sixth output pin is connected with the sixth cable; the second crystal oscillator transmits the base frequency signal to the fourth output pin, the D flip-flop transmits the two-divided frequency signal to the fifth output pin and transmits the four-divided frequency signal to the sixth output pin; the fourth output pin transmits the base frequency signal to the mainboard, the fifth output pin transmits the two-divided frequency signal to the mainboard, and the sixth output pin transmits the four-divided frequency signal to the mainboard; the mainboard can determine whether the fourth cable between the mainboard and the riser card is correctly connected according to the base frequency signal, whether the fifth cable between the mainboard and the riser card is correctly connected according to the two-divided frequency signal, and whether the sixth cable between the mainboard and the riser card is correctly connected according to the four-divided frequency signal, so that the detection of the multiple cables in the server is realized.

[0059] Optionally, the mainboard comprises a complex programmable logic device, and the complex programmable logic device is used for determining whether the cables between the backboard and / or the riser card are correctly connected according to the base frequency signal and / or the divided frequency signal.

[0060] The server provided in the embodiment comprises a mainboard, and the mainboard comprises a complex programmable logic device, which can determine whether the cables between the backboard and / or the riser card are correctly connected according to the base frequency signal and / or the divided frequency signal, so that the detection of the cables between the mainboard and the backboard and / or the mainboard and the riser card is realized.

[0061] Optionally, the server further comprises:

[0062] A baseboard management controller connected with the mainboard, and the baseboard management controller is used for displaying the misconnection or missing information of the mainboard when the misconnection or missing information of the mainboard is received.

[0063] The server provided in the embodiment comprises a baseboard management controller, which can receive the misconnection or missing information of the mainboard and display the misconnection or missing information to inform the user of the connection information of the cables.

[0064] The backboard provided in the application comprises at least one D flip-flop, a first crystal oscillator and at least two output pins, the first crystal oscillator is connected with one of the at least two output pins, the at least one D flip-flop is connected with the remaining output pins of the at least two output pins, and each output pin is connected with a cable. The first crystal oscillator is used to generate a fundamental frequency signal and transmit the fundamental frequency signal to one of the output pins connected with the first crystal oscillator and one D flip-flop connected with the first crystal oscillator. The at least one D flip-flop generates a frequency division signal according to the fundamental frequency signal after receiving the fundamental frequency signal and transmits the frequency division signal to the remaining output pins. The one of the output pins connected with the first crystal oscillator transmits the fundamental frequency signal to a mainboard, and the remaining output pins connected with the at least one D flip-flop transmit the frequency division signal to the mainboard. The mainboard can determine whether the cables between the backboard are correctly connected according to the fundamental frequency signal and / or the frequency division signal, so that the detection of multiple cables can be realized, and a CPLD does not need to be placed on the backboard, the D flip-flop and the crystal oscillator occupy a smaller layout space on the backboard, and the cost of the backboard is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0065] These and other aspects, implementations and advantages of the exemplary embodiments will become apparent from the detailed description and accompanying drawings, which are depicted by way of example, and not limitation. As will be appreciated, the specification and drawings are not intended to limit the application to the specific forms disclosed, but on the contrary, the application is intended to cover such alternatives, modifications and equivalents as can be included within the spirit and scope of the application as defined by the appended claims. Other aspects and advantages of the application will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the application.

[0066] Figure 1 is a structural schematic diagram of a server;

[0067] Figure 2 is a structural schematic diagram of a backboard provided by an embodiment of the application;

[0068] Figure 3 is a structural schematic diagram of a double D flip-flop provided by an embodiment of the application;

[0069] Figure 4 is a structural schematic diagram of a Riser card provided by an embodiment of the application;

[0070] Figure 5 is a structural schematic diagram of a server provided by an embodiment of the application;

[0071] Figure 6 is a structural schematic diagram of another server provided by an embodiment of the application;

[0072] Figure 7 is a structural schematic diagram of another server provided by an embodiment of the application. DETAILED DESCRIPTION

[0073] The terms used in the embodiment part of the present application are only used for explaining the specific embodiments of the present application, and are not intended to limit the present application.

[0074] For the convenience of understanding, first, the related technical terms involved in the embodiments of the present application are explained and described.

[0075] Riser card: a functional expansion card or adapter card plugged into the PCIE (peripheral component interconnect express, high-speed serial computer expansion bus standard) interface.

[0076] CPLD: a programmable logic device with high density, high speed and low power consumption.

[0077] Currently, CPLD (Complex programmable logic device) is mainly used to detect whether the cable in the server is inserted incorrectly. For the backboard, a CPLD is placed on the backboard, and the CPLD on the backboard sends a serial code to the CPLD on the mainboard. After receiving the serial code, the CPLD on the mainboard compares the serial code sent by the CPLD on the backboard with the data pre-written in the register. If they are consistent, it indicates that the cable connection between the mainboard and the backboard is correct. If they are inconsistent, it indicates that the cable connection between the mainboard and the backboard is incorrect. If the CPLD on the mainboard does not receive the serial code, it indicates that the cable between the mainboard and the backboard is missing. For the Riser card, a CPLD is placed on the Riser card, and the CPLD on the Riser card sends a serial code to the CPLD on the mainboard. After receiving the serial code, the CPLD on the mainboard compares the serial code sent by the CPLD on the Riser card with the data pre-written in the register. If they are consistent, it indicates that the cable connection between the mainboard and the Riser card is correct. If they are inconsistent, it indicates that the cable connection between the mainboard and the Riser card is incorrect. If the CPLD on the mainboard does not receive the serial code, it indicates that the cable between the mainboard and the Riser card is missing.

[0078] When the cable between the mainboard and the backboard or the Riser card is inserted incorrectly or missing, the CPLD on the mainboard can send the incorrect or missing information to the BMC (Baseboard Management Controller). The BMC can alarm the incorrect or missing information on the management page to inform the user.

[0079] Reference Figure 1As shown, when the A port of the backplane / riser card 101 is connected to the A port of the mainboard 102 through the A cable, the A cable between the backplane / riser card 101 and the mainboard 102 is correctly connected; when the B port of the backplane / riser card 101 is connected to the B port of the mainboard 102 through the B cable, the B cable between the backplane / riser card 101 is correctly connected; when the C port of the backplane / riser card 101 is connected to the C port of the mainboard 102 through the C cable, the C cable between the backplane / riser card 101 is correctly connected.

[0080] The CPLD in the backplane / riser card 101 sends a serial code to the CPLD on the mainboard 102 via cable A. The CPLD on the mainboard 102 compares the serial code sent via cable A with the data corresponding to cable A written in the register, thereby detecting whether cable A between the backplane / riser card 101 and the mainboard 102 is correctly connected. The CPLD in the backplane / riser card 101 sends a serial code to the CPLD on the mainboard 102 via cable B. The CPLD on the mainboard 102 compares the serial code sent via cable B with the data corresponding to cable B written in the register, thereby detecting whether cable B between the backplane / riser card 101 and the mainboard 102 is correctly connected. The CPLD in the backplane / riser card 101 sends a serial code to the CPLD on the mainboard 102 via cable B. The CPLD on the mainboard 102 compares the serial code sent via cable B with the data corresponding to cable B written in the register, thereby detecting whether cable B between the backplane / riser card 101 and the mainboard 102 is correctly connected.

[0081] However, if the backplane or riser card does not have a CPLD, it cannot detect whether the cable is plugged in incorrectly. In addition, placing a CPLD on the backplane or riser card consumes space on the backplane or riser card, increasing costs.

[0082] Based on this, the application provides a backboard, comprising at least one D flip-flop, a first crystal oscillator, and at least two output pins, the first crystal oscillator is connected with one of the at least two output pins, the at least one D flip-flop is connected with the remaining output pins of the at least two output pins, and each output pin is connected with a cable. The first crystal oscillator is used to generate a base frequency signal and transmit the base frequency signal to the one output pin connected with the first crystal oscillator and the one D flip-flop connected with the first crystal oscillator. The at least one D flip-flop generates a frequency division signal according to the base frequency signal after receiving the base frequency signal and transmits the frequency division signal to the remaining output pins. The one output pin connected with the first crystal oscillator transmits the base frequency signal to a mainboard, and the remaining output pins connected with the at least one D flip-flop transmit the frequency division signal to the mainboard. The mainboard can determine whether the cable between the backboard and the mainboard is correctly connected according to the base frequency signal and / or the frequency division signal, so that the detection of multiple cables can be realized, and a CPLD does not need to be placed on the backboard, the D flip-flop and the crystal oscillator occupy a smaller layout space on the backboard, and the cost of the backboard is reduced.

[0083] The test program generation method provided by the embodiment of the application is described in detail below through a specific implementation manner.

[0084] Figure 2 The structure diagram of the backboard provided by the embodiment of the application is shown in FIG. 1. Figure 2 As shown in FIG. 1, the backboard 1011 comprises a first crystal oscillator 112, a first double D flip-flop 111, a first output pin 113, a second output pin 114, and a third output pin 115. The first crystal oscillator 112 is connected with the double D flip-flop 111 and the first output pin 113, the double D flip-flop 111 is connected with the second output pin 114 and the third output pin 115, the first output pin 113 is connected with a first cable, the second output pin 114 is connected with a second cable, and the third output pin 115 is connected with a third cable.

[0085] The first crystal oscillator 112 generates a base frequency signal and transmits the base frequency signal to the first output pin 113 and the double D flip-flop 111. The first output pin 113 transmits the base frequency signal to a CPLD on a mainboard through the first cable. The CPLD on the mainboard can determine whether the first cable between the mainboard and the backboard 1011 is correctly connected according to the base frequency signal after receiving the base frequency signal transmitted through the first cable.

[0086] The first double D flip-flop 111 generates a two-divided frequency signal and a four-divided frequency signal according to the base frequency signal after receiving the base frequency signal, and transmits the two-divided frequency signal to the second output pin 114 and the four-divided frequency signal to the third output pin 115. The second output pin 114 transmits the two-divided frequency signal to the CPLD on the mainboard through the second cable, and the CPLD on the mainboard determines whether the second cable between the mainboard and the backboard 1011 is correctly connected according to the two-divided frequency signal received through the second cable. The third output pin 115 transmits the four-divided frequency signal to the CPLD on the mainboard through the third cable, and the CPLD on the mainboard determines whether the third cable between the mainboard and the backboard 1011 is correctly connected according to the four-divided frequency signal received through the third cable.

[0087] For example, when the first output pin 113 on the backboard 1011 is connected to the first output pin on the mainboard through the first cable, the first cable between the backboard 1011 and the mainboard is correctly connected; when the second output pin 114 on the backboard 1011 is connected to the second output pin on the mainboard through the second cable, the second cable between the backboard 1011 and the mainboard is correctly connected; and when the third output pin 115 on the backboard is connected to the third output pin on the mainboard through the third cable, the third cable between the backboard 1011 and the mainboard is correctly connected.

[0088] Therefore, if the first output pin 113 on the backboard 1011 transmits the base frequency signal through the first cable, the CPLD on the mainboard compares the signal received by the first output pin on the mainboard with the first preset signal when the first output pin on the mainboard receives the signal. If the comparison is consistent, it is determined that the first cable between the mainboard and the backboard 1011 is correctly connected, and if the comparison is inconsistent, it is determined that the first cable between the mainboard and the backboard 1011 is incorrectly connected. If the CPLD on the mainboard determines that the first cable between the mainboard and the backboard 1011 is missing when the first output pin on the mainboard does not receive the signal. The first preset signal is the base frequency signal.

[0089] If the second output pin 114 on the backboard 1011 transmits the two-divided frequency signal through the second cable, the CPLD on the mainboard compares the signal received by the second output pin on the mainboard with the second preset signal when the second output pin on the mainboard receives the signal. If the comparison is consistent, it is determined that the second cable between the mainboard and the backboard 1011 is correctly connected, and if the comparison is inconsistent, it is determined that the second cable between the mainboard and the backboard 1011 is incorrectly connected. If the CPLD on the mainboard determines that the second cable between the mainboard and the backboard 1011 is missing when the second output pin on the mainboard does not receive the signal. The second preset signal is the two-divided frequency signal.

[0090] If the third output pin 115 on the backboard 1011 transmits the quarter frequency signal through the third cable, the CPLD on the mainboard compares the signal received by the third output pin on the mainboard with the third preset signal when the third output pin on the mainboard receives the signal, and determines that the third cable between the mainboard and the backboard 1011 is correctly connected when the comparison is consistent, determines that the third cable between the mainboard and the backboard 1011 is incorrectly connected when the comparison is inconsistent, and determines that the third cable between the mainboard and the backboard 1011 is missed when the CPLD on the mainboard does not receive the signal. The third preset signal is the quarter frequency signal.

[0091] In some embodiments, Figure 3 The circuit diagram of the first double D flip-flop is shown in Figure 3 As shown in the figure, the first double D flip-flop 111 includes a first flip-flop 1111 and a second flip-flop 1112, the first flip-flop 1111 is provided with a first clock pin 1CP, a first trigger pin 1D, a first non-inverted output pin 1Q, a first inverted output pin The second flip-flop 1112 is provided with a second clock pin 2CP, a second trigger pin 2D, a second non-inverted output pin 2Q, and a second inverted output pin The first inverted output pin is connected with the first trigger pin 1D, the first non-inverted output pin 1Q is connected with the second clock pin 2CP, and the second inverted output pin is connected with the second trigger pin 2D.

[0092] After the first crystal oscillator 112 generates the base frequency signal, the base frequency signal can be transmitted to the first clock pin 1CP of the first flip-flop 1111. Since the first inverted output pin is connected with the first trigger pin 1D, the signal output by the first non-inverted output pin 1Q is the quarter frequency signal of the base frequency signal received by the first clock pin 1CP, and then the quarter frequency signal output by the first non-inverted pin 1Q is transmitted to the second clock pin 2CP. Since the second inverted output pin is connected with the second trigger pin 2D, the signal output by the second non-inverted output pin 2Q is the quarter frequency signal of the quarter frequency signal received by the second clock pin 2CP, that is, the base frequency signal.

[0093] For example, when the first clock pin 1CP receives the base frequency signal with a rising edge, the first non-inverted output pin 1Q outputs the first level of the first trigger pin 1D, the first inverted output pin outputs the second level, the level of the second clock pin 2CP is the first level, the second level is opposite to the first level, at this time, the level of the first trigger pin 1D is the second level, the level of the second non-inverted output pin 2Q is the first level, and the level of the second inverted output pin the level of the second trigger foot 2D is the second level;

[0094] When the next base frequency signal is a rising edge, the first in-phase output foot 1Q outputs the second level of the first trigger foot 1D, and then the first in-phase output foot 1Q outputs opposite levels in two clock periods, realizing the halving of the base frequency signal. At this time, the level of the first reverse output foot 1B is the first level, the level of the first trigger foot 1D is the first level, and the level of the second clock foot 2CP is the second level.

[0095] When the next base frequency signal is a rising edge, the first in-phase output foot 1Q outputs the first level of the first trigger foot 1D, and the level of the second clock signal foot 2CP is the first level. At this time, the level of the first reverse output foot 1B is the second level, the level of the first trigger foot 1D is the second level, the level of the second in-phase output foot 2Q is the second level, and the level of the second reverse output foot 2B is the first level.

[0096] When the next base frequency signal is a rising edge, the first in-phase output foot 1Q outputs the second level of the first trigger foot 1D, and the level of the second clock foot 2CP is the second level. Then the second in-phase output foot 2Q outputs opposite levels in four clock periods, realizing the quartering of the base frequency signal. The first level is, for example, 1, and the second level is, for example, 0.

[0097] It should be noted that the base frequency signal transmitted to the first output foot 113 on the backboard 1011 can be the signal generated by the first crystal oscillator 112 in multiple periods. Correspondingly, the halved frequency signal transmitted to the second output foot 114 on the backboard 1011 can be the halved frequency signal in multiple periods, and the quartered frequency signal transmitted to the third output foot 115 on the backboard 1011 can be the quartered frequency signal in multiple periods. Then the base frequency signal transmitted to the first output foot 113, the halved frequency signal transmitted to the second output foot 114, and the quartered frequency signal transmitted to the third output foot 115 are serial codes.

[0098] The first trigger also has a first reset foot and a first set foot The first reset foot sets the first trigger to 0 with a low level, and the first set foot sets the first trigger to 1 with a low level. The second trigger also has a second reset foot and a second set foot The second reset foot sets the second trigger to 0 with a low level, and the second set foot​​​ Use a low level to set the second flip-flop to 1.

[0099] It should be noted that the above-mentioned backplane 1011 may also include a third trigger, a fourth trigger, etc. When the backplane 1011 includes the first trigger, the second trigger, and the third trigger, a two-frequency signal, a four-frequency signal, and an eight-frequency signal can be obtained according to the baseband signal, so that the baseband signal can be transmitted through the first cable, the two-frequency signal can be transmitted through the second cable, the four-frequency signal can be transmitted through the third cable, and the eight-frequency signal can be transmitted through the fourth cable, thereby achieving detection of four cables. Similarly, when the backplane 1011 includes the first trigger, the second trigger, the third trigger, and the fourth trigger, a two-frequency signal, a four-frequency signal, an eight-frequency signal, and a sixteen-frequency signal can be obtained according to the baseband signal, so that the baseband signal can be transmitted through the first cable, the two-frequency signal can be transmitted through the second cable, the four-frequency signal can be transmitted through the third cable, the eight-frequency signal can be transmitted through the fourth cable, and the sixteen-frequency signal can be transmitted through the fifth cable, thereby achieving detection of five cables, and so on, thereby achieving detection of more cables.

[0100] Figure 4 This is a schematic diagram of the structure of the riser card 1012 provided in an embodiment of the present application, refer to Figure 4 As shown, the riser card 1012 provided in this embodiment of the present application includes: a second crystal oscillator 122, a second dual D flip-flop 121, a fourth output pin 123, a fifth output pin 124, and a sixth output pin 125. The second crystal oscillator 122 is connected to the second dual D flip-flop 121 and the fourth output pin 123, the second dual D flip-flop 121 is connected to the fifth output pin 124 and the sixth output pin 125, the fourth output pin 123 is connected to the fourth cable, the fifth output pin 124 is connected to the fifth cable, and the sixth output pin 125 is connected to the sixth cable.

[0101] Second crystal oscillator 122 generates a baseband signal and transmits the baseband signal to fourth output pin 123 and second dual D flip-flop 121. Fourth output pin 123 transmits the baseband signal to the CPLD on the mainboard via a fourth cable. After receiving the baseband signal transmitted via the fourth cable, the CPLD on the mainboard can determine whether the fourth cable between the mainboard and riser card 1012 is correctly connected based on the baseband signal. It should be noted that second crystal oscillator 122 and first crystal oscillator can be the same crystal oscillator.

[0102] The second double D flip-flop 121 generates a two-divided frequency signal and a four-divided frequency signal according to the base frequency signal after receiving the base frequency signal, and transmits the two-divided frequency signal to the fifth output pin 124 and the four-divided frequency signal to the sixth output pin 125. The fifth output pin 124 transmits the two-divided frequency signal to the CPLD on the mainboard through the fifth cable, and the CPLD on the mainboard determines whether the fifth cable between the mainboard and the Riser card 1012 is correctly connected according to the two-divided frequency signal received through the fifth cable. The sixth output pin 125 transmits the four-divided frequency signal to the CPLD on the mainboard through the sixth cable, and the CPLD on the mainboard determines whether the sixth cable between the mainboard and the Riser card 1012 is correctly connected according to the four-divided frequency signal received through the sixth cable.

[0103] For example, when the fourth output pin 123 on the Riser card 1012 is connected to the first output pin on the mainboard through the fourth cable, the fourth cable between the Riser card 1012 and the mainboard is correctly connected; when the fifth output pin 124 on the Riser card 1012 is connected to the second output pin on the mainboard through the fifth cable, the fifth cable between the Riser card 1012 and the mainboard is correctly connected; and when the sixth output pin 125 on the Riser card is connected to the third output pin on the mainboard through the sixth cable, the third cable between the Riser card 1012 and the mainboard is correctly connected.

[0104] Therefore, if the fourth output pin 123 on the Riser card 1012 transmits the base frequency signal through the fourth cable, the CPLD on the mainboard compares the signal received by the first output pin on the mainboard with the first preset signal when the first output pin on the mainboard receives the signal. If the comparison is consistent, it is determined that the fourth cable between the mainboard and the Riser card 1012 is correctly connected, and if the comparison is inconsistent, it is determined that the fourth cable between the mainboard and the Riser card 1012 is incorrectly connected. If the CPLD on the mainboard does not receive the signal at the first output pin on the mainboard, it is determined that the fourth cable between the mainboard and the Riser card 1012 is missing. The first preset signal is the base frequency signal.

[0105] If the fifth output pin 124 on the Riser card 1012 transmits the two-divided frequency signal through the fifth cable, the CPLD on the mainboard compares the signal received by the second output pin on the mainboard with the second preset signal when the second output pin on the mainboard receives the signal. If the comparison is consistent, it is determined that the fifth cable between the mainboard and the Riser card 1012 is correctly connected, and if the comparison is inconsistent, it is determined that the fifth cable between the mainboard and the Riser card 1012 is incorrectly connected. If the CPLD on the mainboard does not receive the signal at the second output pin on the mainboard, it is determined that the fifth cable between the mainboard and the Riser card 1012 is missing. The second preset signal is the two-divided frequency signal.

[0106] If the sixth output pin 125 on the Riser card transmits the quarter frequency signal through the sixth cable, the CPLD on the mainboard compares the signal received by the third output pin on the mainboard with the third preset signal when the third output pin on the mainboard receives the signal, and determines that the sixth cable between the mainboard and the Riser card 1012 is correctly connected when the comparison is consistent, determines that the sixth cable between the mainboard and the Riser card 1012 is incorrectly connected when the comparison is inconsistent, and determines that the sixth cable between the mainboard and the Riser card 1012 is missed when the CPLD on the mainboard does not receive the signal from the third output pin on the mainboard. The third preset signal is the quarter frequency signal.

[0107] Figure 5 A structural schematic diagram of a server provided by an embodiment of the present application is shown in FIG. 1. The server provided by the embodiment of the present application includes: Figure 5

[0108] The mainboard 102 includes a CPLD 132, a first output pin 133, a second output pin 134 and a third output pin 135, and the backboard 1011 includes a first double D flip-flop 111, a first crystal oscillator 112, a first output pin 113, a second output pin 114 and a third output pin 115. The first output pin 113 of the backboard 1011 is connected with the first cable 201, the second output pin 114 of the backboard 1011 is connected with the second cable 202, and the third output pin 115 of the backboard 1011 is connected with the third cable 203.

[0109] The first crystal oscillator 112 generates a base frequency signal and transmits the base frequency signal to the first output pin 113 and the first double D flip-flop 111. The first output pin 113 transmits the base frequency signal to the CPLD 132 on the mainboard 102 through the first cable 201. The CPLD 132 on the mainboard 102 can determine whether the first cable 201 between the mainboard 102 and the backboard 1011 is correctly connected according to the base frequency signal after receiving the base frequency signal transmitted through the first cable 201.

[0110] ​When the first output pin 133 on the mainboard 102 receives a signal, the CPLD 132 on the mainboard 102 compares the signal received by the first output pin 133 with a first preset signal, and if they are consistent, it is determined that the first cable 201 between the first output pin 133 on the mainboard 102 and the first output pin 113 on the backboard 1011 is correctly connected, and if they are inconsistent, it is determined that the first cable 201 between the first output pin 133 on the mainboard 102 and the first output pin 113 on the backboard 1011 is incorrectly connected. When the first crystal oscillator 112 generates a base frequency signal, and the first output pin 133 on the mainboard 102 does not receive a signal, the CPLD 132 on the mainboard 102 determines that the first cable 201 between the first output pin 133 on the mainboard 102 and the first output pin 113 on the backboard 1011 is missed. The first preset signal is the base frequency signal output by the first output pin 113 on the backboard 1011.

[0111] When the second output pin 134 on the mainboard 102 receives a signal, the CPLD 132 on the mainboard 102 compares the signal received by the second output pin 134 with a second preset signal, and if they are consistent, it is determined that the second cable 202 between the second output pin 134 on the mainboard 102 and the second output pin 114 on the backboard 1011 is correctly connected, and if they are inconsistent, it is determined that the second cable 202 between the second output pin 134 on the mainboard 102 and the second output pin 114 on the backboard 1011 is incorrectly connected. When the first crystal oscillator 112 generates a base frequency signal, and the second output pin 134 on the mainboard 102 does not receive a signal, the CPLD 132 on the mainboard 102 determines that the second cable 202 between the second output pin 134 on the mainboard 102 and the second output pin 114 on the backboard 1011 is missed. The second preset signal is the halved frequency signal output by the second output pin 114 on the backboard 1011.

[0112] When the third output pin 135 on the mainboard 102 receives a signal, the CPLD 132 on the mainboard 102 compares the signal received by the third output pin 135 with a third preset signal, and if they are consistent, it is determined that the third cable 203 between the third output pin 135 on the mainboard 102 and the third output pin 115 on the backboard 1011 is correctly connected, and if they are inconsistent, it is determined that the third cable 203 between the third output pin 135 on the mainboard 102 and the third output pin 115 on the backboard 1011 is incorrectly connected. When the first crystal oscillator 112 generates a base frequency signal, and the third output pin 135 on the mainboard 102 does not receive a signal, the CPLD 132 on the mainboard 102 determines that the third cable 203 between the third output pin 135 on the mainboard 102 and the third output pin 115 on the backboard 1011 is missed. The third preset signal is the quartered frequency signal output by the third output pin 115 on the backboard 1011.

[0113] Figure 6 A structural schematic diagram of a server provided by an embodiment of the present application is shown in FIG. 1. The server provided by the embodiment of the present application includes: Figure 5

[0114] The mainboard 102 includes a CPLD 132, a first output pin 133, a second output pin 134, and a third output pin 135. The Riser card 1012 includes a second double D flip-flop 121, a second crystal oscillator 122, a fourth output pin 123, a fifth output pin 124, and a sixth output pin 125. The fourth output pin 123 of the Riser card 1012 is connected with the fourth cable 211. The fifth output pin 125 of the Riser card 1012 is connected with the fifth cable 212. The sixth output pin 125 of the Riser card 1012 is connected with the sixth cable 213.

[0115] The second crystal oscillator 122 generates a base frequency signal and transmits the base frequency signal to the fourth output pin 123 and the second double D flip-flop 121. The fourth output pin 123 transmits the base frequency signal to the CPLD 132 on the mainboard 102 through the fourth cable 211. The CPLD 132 on the mainboard 102 can determine whether the fourth cable between the mainboard 102 and the Riser card 1012 is correctly connected according to the base frequency signal received through the fourth cable.

[0116] When the first output pin 133 on the mainboard 102 receives a signal, the CPLD 132 on the mainboard 102 compares the signal received by the first output pin 133 with a first preset signal. If they are consistent, it is determined that the fourth cable 211 between the first output pin 133 on the mainboard 102 and the fourth output pin 123 on the Riser card 1012 is correctly connected. If they are not consistent, it is determined that the fourth cable 211 between the first output pin 133 on the mainboard 102 and the fourth output pin 123 on the Riser card 1012 is incorrectly connected. When the second crystal oscillator 122 generates a base frequency signal and the first output pin 133 on the mainboard 102 does not receive a signal, the CPLD 132 on the mainboard 102 determines that the fourth cable 211 between the first output pin 133 on the mainboard 102 and the fourth output pin 123 on the Riser card 1012 is missed. The first preset signal is the base frequency signal output by the fourth output pin 123 on the Riser card 1012.

[0117] ​When the second output pin 134 on the mainboard 102 receives a signal, the CPLD 132 on the mainboard 102 compares the signal received by the second output pin 134 with a second preset signal. If the two signals are consistent, it is determined that the fifth cable 212 between the second output pin 134 on the mainboard 102 and the fifth output pin 124 on the Riser card 1012 is correctly connected. If the two signals are not consistent, it is determined that the fifth cable 212 between the second output pin 134 on the mainboard 102 and the fifth output pin 124 on the Riser card 1012 is incorrectly connected. When the second crystal oscillator 122 generates a base frequency signal and the second output pin 134 on the mainboard 102 does not receive a signal, the CPLD 132 on the mainboard 102 determines that the fifth cable 212 between the second output pin 134 on the mainboard 102 and the fifth output pin 124 on the Riser card 1012 is missed. The second preset signal is a divided-by-two signal output by the fifth output pin 124 on the Riser card 1012.

[0118] When the third output pin 135 on the mainboard 102 receives a signal, the CPLD 132 on the mainboard 102 compares the signal received by the third output pin 135 with a third preset signal. If the two signals are consistent, it is determined that the sixth cable 213 between the third output pin 135 on the mainboard 102 and the sixth output pin 125 on the Riser card 1012 is correctly connected. If the two signals are not consistent, it is determined that the sixth cable 213 between the third output pin 135 on the mainboard 102 and the sixth output pin 125 on the Riser card 1012 is incorrectly connected. When the second crystal oscillator 122 generates a base frequency signal and the third output pin 135 on the mainboard 102 does not receive a signal, the CPLD 132 on the mainboard 102 determines that the sixth cable 213 between the third output pin 135 on the mainboard 102 and the sixth output pin 125 on the Riser card 1012 is missed. The third preset signal is a divided-by-four signal output by the sixth output pin 125 on the Riser card 1012.

[0119] Figure 7 A structural schematic diagram of a server provided by an embodiment of the present application is shown in FIG. 1. The server provided by the embodiment of the present application includes: Figure 7

[0120] ​The mainboard 102, the backboard 1011 and the Riser card 1012, the mainboard 102 includes the CPLD 132, the first output pin 133, the second output pin 134 and the third output pin 135, the backboard 1011 includes the first double D flip-flop 111, the first crystal oscillator 112, the first output pin 113, the second output pin 114 and the third output pin 115, and the Riser card 1012 includes the second double D flip-flop 121, the second crystal oscillator 122, the fourth output pin 123, the fifth output pin 124 and the sixth output pin 125. The first output pin 113 of the backboard 1011 is connected with the first cable 201, the second output pin 114 of the backboard 1011 is connected with the second cable 202, and the third output pin 115 of the backboard 1011 is connected with the third cable 203. The fourth output pin 123 of the Riser card 1012 is connected with the fourth cable 211, the fifth output pin 125 of the Riser card 1012 is connected with the fifth cable 212, and the sixth output pin 125 of the Riser card 1012 is connected with the sixth cable 213.

[0121] The first crystal oscillator 112 in the backboard 1011 generates a base frequency signal and transmits the base frequency signal to the first output pin 113 and the first double D flip-flop 111. The first output pin 113 transmits the base frequency signal to the CPLD 132 on the mainboard 102 through the first cable 201. The CPLD 132 on the mainboard 102 can determine whether the first cable 201 between the mainboard 102 and the backboard 1011 is correctly connected according to the base frequency signal received through the first cable 201.

[0122] When the first output pin 133 on the mainboard 102 receives a signal, the CPLD 132 on the mainboard 102 compares the signal received by the first output pin 133 with a first preset signal. If they are consistent, it is determined that the first cable 201 between the first output pin 133 on the mainboard 102 and the first output pin 113 on the backboard 1011 is correctly connected. If they are not consistent, it is determined that the first cable 201 between the first output pin 133 on the mainboard 102 and the first output pin 113 on the backboard 1011 is incorrectly connected. When the first crystal oscillator 112 generates a base frequency signal and the first output pin 133 on the mainboard 102 does not receive a signal, the CPLD 132 on the mainboard 102 determines that the first cable 201 between the first output pin 133 on the mainboard 102 and the first output pin 113 on the backboard 1011 is missed. The first preset signal is the base frequency signal output by the first output pin 113 on the backboard 1011.

[0123] When the second output pin 134 on the mainboard 102 receives a signal, the CPLD 132 on the mainboard 102 compares the signal received by the second output pin 134 with a second preset signal, and if they are consistent, it is determined that the second cable 202 between the second output pin 134 on the mainboard 102 and the second output pin 114 on the backboard 1011 is correctly connected, and if they are inconsistent, it is determined that the second cable 202 between the second output pin 134 on the mainboard 102 and the second output pin 114 on the backboard 1011 is incorrectly connected. When the first crystal oscillator 112 generates a base frequency signal, and the second output pin 134 on the mainboard 102 does not receive a signal, the CPLD 132 on the mainboard 102 determines that the second cable 202 between the second output pin 134 on the mainboard 102 and the second output pin 114 on the backboard 1011 is missing. The second preset signal is a divided-by-two signal output by the second output pin 114 on the backboard 1011.

[0124] When the third output pin 135 on the mainboard 102 receives a signal, the CPLD 132 on the mainboard 102 compares the signal received by the third output pin 135 with a third preset signal, and if they are consistent, it is determined that the third cable 203 between the third output pin 135 on the mainboard 102 and the third output pin 115 on the backboard 1011 is correctly connected, and if they are inconsistent, it is determined that the third cable 203 between the third output pin 135 on the mainboard 102 and the third output pin 115 on the backboard 1011 is incorrectly connected. When the first crystal oscillator 112 generates a base frequency signal, and the third output pin 135 on the mainboard 102 does not receive a signal, the CPLD 132 on the mainboard 102 determines that the third cable 203 between the third output pin 135 on the mainboard 102 and the third output pin 115 on the backboard 1011 is missing. The third preset signal is a divided-by-four signal output by the third output pin 115 on the backboard 1011.

[0125] The second crystal oscillator 122 in the Riser card 1012 generates a base frequency signal and transmits it to the fourth output pin 123 and the second double D flip-flop 121. The fourth output pin 123 transmits the base frequency signal to the CPLD 132 on the mainboard 102 through the fourth cable 211. The CPLD 132 on the mainboard 102 can determine whether the fourth cable between the mainboard 102 and the Riser card 1012 is correctly connected according to the base frequency signal received through the fourth cable.

[0126] When the first output pin 133 on the mainboard 102 receives a signal, the CPLD 132 on the mainboard 102 compares the signal received by the first output pin 133 with a first preset signal, and if they are consistent, it is determined that the fourth cable 211 between the first output pin 133 on the mainboard 102 and the fourth output pin 123 on the Riser card 1012 is correctly connected, and if they are not consistent, it is determined that the fourth cable 211 between the first output pin 133 on the mainboard 102 and the fourth output pin 123 on the Riser card 1012 is incorrectly connected. When the second crystal oscillator 122 generates a base frequency signal and the first output pin 133 on the mainboard 102 does not receive a signal, the CPLD 132 on the mainboard 102 determines that the fourth cable 211 between the first output pin 133 on the mainboard 102 and the fourth output pin 123 on the Riser card 1012 is missing. The first preset signal is the base frequency signal output by the fourth output pin 123 on the Riser card 1012.

[0127] When the second output pin 134 on the mainboard 102 receives a signal, the CPLD 132 on the mainboard 102 compares the signal received by the second output pin 134 with a second preset signal, and if they are consistent, it is determined that the fifth cable 212 between the second output pin 134 on the mainboard 102 and the fifth output pin 124 on the Riser card 1012 is correctly connected, and if they are not consistent, it is determined that the fifth cable 212 between the second output pin 134 on the mainboard 102 and the fifth output pin 124 on the Riser card 1012 is incorrectly connected. When the second crystal oscillator 122 generates a base frequency signal and the second output pin 134 on the mainboard 102 does not receive a signal, the CPLD 132 on the mainboard 102 determines that the fifth cable 212 between the second output pin 134 on the mainboard 102 and the fifth output pin 124 on the Riser card 1012 is missing. The second preset signal is the halved frequency signal output by the fifth output pin 124 on the Riser card 1012.

[0128] When the third output pin 135 on the mainboard 102 receives a signal, the CPLD 132 on the mainboard 102 compares the signal received by the third output pin 135 with a third preset signal, if consistent, it is determined that the sixth cable 213 between the third output pin 135 on the mainboard 102 and the sixth output pin 125 on the Riser card 1012 is correctly connected, if not consistent, it is determined that the sixth cable 213 between the third output pin 135 on the mainboard 102 and the sixth output pin 125 on the Riser card 1012 is incorrectly connected. When the second crystal oscillator 122 generates a base frequency signal and the third output pin 135 on the mainboard 102 does not receive a signal, the CPLD 132 on the mainboard 102 determines that the sixth cable 213 between the third output pin 135 on the mainboard 102 and the sixth output pin 125 on the Riser card 1012 is missing. The third preset signal is a quarter frequency signal output by the sixth output pin 125 on the Riser card 1012.

[0129] The server described above can further include a BMC 103 (baseboard management controller), and when the CPLD 132 on the mainboard determines that the cables between the baseboard 1011 or the Riser card 1012 and the mainboard 102 are incorrectly connected or missing, the CPLD 132 reports the incorrectly connected or missing information to the BMC 103, and the BMC 103 can alarm the user on the management page.

[0130] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be understood in a broad sense, for example, it can be fixedly connected, or indirectly connected through an intermediate medium, or the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0131] In the present application or the device or element implied by the present application must have a specific orientation, and therefore cannot be understood as a limitation of the present application. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0132] The terms "first", "second", etc. (if any) in the description and claims of this application and above drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that data thus used can be interchanged, where appropriate, so that the embodiments of the application described herein can be carried out in other than the order shown or described herein. Furthermore, the terms "comprising" and "including" and any variations thereof are intended to cover a non-exclusive inclusion, for example, a process, method, system, product or apparatus that comprises a list of steps or units can not necessarily be limited to those steps or units that are clearly listed, but can include other not clearly listed steps or units that are a part of the process, method, product or apparatus.

[0133] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit it; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A backsheet characterized by, The application relates to a frequency divider, which comprises: a first crystal oscillator, at least one D flip-flop and at least two output pins; the first crystal oscillator is connected with one D flip-flop and one output pin, and the at least one D flip-flop is connected with the remaining output pins, and each of the output pins is connected with a cable; the first crystal oscillator is used for generating a base frequency signal and transmitting the base frequency signal to the one D flip-flop and the one output pin, and the at least one D flip-flop is used for generating a frequency-divided signal according to the base frequency signal and transmitting the frequency-divided signal to the remaining output pins; the one output pin is used for transmitting the base frequency signal to a mainboard, and the remaining output pins are used for transmitting the frequency-divided signal to the mainboard, and the mainboard is used for judging whether the cables between the mainboard and the backboard are correctly connected according to the base frequency signal and / or the frequency-divided signal.

2. The backsheet of claim 1, wherein the at least two output pins comprise a first output pin, a second output pin and a third output pin; the first crystal oscillator is connected with the first output pin, and the at least one D flip-flop is connected with the second output pin and the third output pin, the first output pin is connected with a first cable, the second output pin is connected with a second cable, and the third output pin is connected with a third cable; the first crystal oscillator is used for transmitting the base frequency signal to the first output pin, and the at least one D flip-flop is used for generating a two-frequency-divided signal and a four-frequency-divided signal according to the base frequency signal, transmitting the two-frequency-divided signal to the second output pin and transmitting the four-frequency-divided signal to the third output pin; the first output pin transmits the base frequency signal to the mainboard through the first cable, the second output pin transmits the two-frequency-divided signal to the mainboard through the second cable, and the third output pin transmits the four-frequency-divided signal to the mainboard through the third cable; the mainboard is used for judging whether the first cable between the mainboard and the backboard is correctly connected according to the base frequency signal, judging whether the second cable between the mainboard and the backboard is correctly connected according to the two-frequency-divided signal, and judging whether the third cable between the mainboard and the backboard is correctly connected according to the four-frequency-divided signal.

3. The backsheet of claim 2, wherein the at least one D flip-flop comprises a first flip-flop and a second flip-flop; the first flip-flop comprises a first clock pin, a first trigger pin, a first non-inverted output pin and a first inverted output pin, and the second flip-flop comprises a second clock pin, a second trigger pin, a second non-inverted output pin and a second inverted output pin; the first inverted output pin is connected with the first trigger pin, the first non-inverted output pin is connected with the second clock pin, and the second inverted output pin is connected with the second trigger pin; the first clock pin receives the base frequency signal; the first non-inverted output pin outputs a two-frequency-divided signal of the base frequency signal to the second clock pin and the second output pin; the second non-inverted output pin outputs a four-frequency-divided signal of the base frequency signal to the third output pin.

4. A Riser card, characterized in that, The application further relates to a frequency divider, which comprises: a second crystal oscillator, at least one D flip-flop and at least two output pins; the second crystal oscillator is connected with one D flip-flop and one output pin, and the at least one D flip-flop is connected with the remaining output pins, and each of the output pins is connected with a cable; the second crystal oscillator is used for generating a base frequency signal and transmitting the base frequency signal to the one D flip-flop and the one output pin, and the at least one D flip-flop is used for generating a frequency-divided signal according to the base frequency signal and transmitting the frequency-divided signal to the remaining output pins; the one output pin is used for transmitting the base frequency signal to a mainboard, and the remaining output pins are used for transmitting the frequency-divided signal to the mainboard, and the mainboard is used for judging whether the cables between the mainboard and the backboard are correctly connected according to the base frequency signal and / or the frequency-divided signal. The second crystal oscillator is connected with a D flip-flop and an output pin, the at least one D flip-flop is connected with the remaining output pins, and each of the output pins is connected with a cable; The second crystal oscillator is used to generate a base frequency signal and transmit the base frequency signal to the D flip-flop and the output pin, and the at least one D flip-flop is used to generate a frequency division signal according to the base frequency signal and transmit the frequency division signal to the remaining output pins; The output pin is used to transmit the base frequency signal to the mainboard, the remaining output pins are used to transmit the frequency division signal to the mainboard, and the mainboard is used to determine whether the cable between the mainboard and the Riser card is correctly connected according to the base frequency signal and / or the frequency division signal.

5. The Riser card of claim 4, wherein, The at least two output pins include a fourth output pin, a fifth output pin and a sixth output pin; The second crystal oscillator is connected with the fourth output pin, the at least one D flip-flop is connected with the fifth output pin and the sixth output pin, the fourth output pin is connected with a fourth cable, the fifth output pin is connected with a fifth cable, and the sixth output pin is connected with a sixth cable; The second crystal oscillator is used to transmit the base frequency signal to the fourth output pin, and the at least one D flip-flop is used to generate a two-frequency division signal and a four-frequency division signal according to the base frequency signal, transmit the two-frequency division signal to the fifth output pin, and transmit the four-frequency division signal to the sixth output pin; The fourth output pin is used to transmit the base frequency signal to the mainboard through the fourth cable, the fifth output pin is used to transmit the two-frequency division signal to the mainboard through the fifth cable, and the sixth output pin is used to transmit the four-frequency division signal to the mainboard through the sixth cable; The mainboard is used to determine whether the fourth cable between the mainboard and the Riser card is correctly connected according to the base frequency signal, determine whether the fifth cable between the mainboard and the Riser card is correctly connected according to the two-frequency division signal, and determine whether the sixth cable between the mainboard and the Riser card is correctly connected according to the four-frequency division signal.

6. A server, characterized by It comprises: at least one of a backboard and a Riser card, and a mainboard; The backboard and the Riser card comprise: a crystal oscillator, at least one D flip-flop and at least two output pins; The crystal oscillator is connected with a D flip-flop and an output pin, the at least one D flip-flop is connected with the remaining output pins, and each of the output pins is connected with a cable; The crystal oscillator is used to generate a base frequency signal and transmit the base frequency signal to the D flip-flop and the output pin, and the at least one D flip-flop is used to generate a frequency division signal according to the base frequency signal and transmit the frequency division signal to the remaining output pins; The output pin is used to transmit the base frequency signal to the mainboard, the remaining output pins are used to transmit the frequency division signal to the mainboard, and the mainboard is used to determine whether the cable between the backboard and / or the Riser card is correctly connected according to the base frequency signal and / or the frequency division signal.

7. The server of claim 6, wherein, The backboard comprises: a first crystal oscillator, a first output pin, a second output pin and a third output pin; the first crystal oscillator is connected with the first output pin, the at least one D flip-flop is connected with the second output pin and the third output pin, the first output pin is connected with a first cable, the second output pin is connected with a second cable, and the third output pin is connected with a third cable; the first crystal oscillator is used to transmit the base frequency signal to the first output pin, the at least one D flip-flop is used to generate a half frequency signal and a quarter frequency signal according to the base frequency signal, and transmit the half frequency signal to the second output pin and the quarter frequency signal to the third output pin; the first output pin transmits the base frequency signal to the mainboard through the first cable, the second output pin transmits the half frequency signal to the mainboard through the second cable, and the third output pin transmits the quarter frequency signal to the mainboard through the third cable; the mainboard is used to determine whether the first cable between the mainboard and the backboard is correctly connected according to the base frequency signal, whether the second cable between the mainboard and the backboard is correctly connected according to the half frequency signal, and whether the third cable between the mainboard and the backboard is correctly connected according to the quarter frequency signal.

8. The server of claim 6, wherein, The Riser card comprises: a second crystal oscillator, a fourth output pin, a fifth output pin and a sixth output pin; the second crystal oscillator is connected with the fourth output pin, the at least one D flip-flop is connected with the fifth output pin and the sixth output pin, the fourth output pin is connected with a fourth cable, the fifth output pin is connected with a fifth cable, and the sixth output pin is connected with a sixth cable; the second crystal oscillator is used to transmit the base frequency signal to the fourth output pin, the at least one D flip-flop is used to generate a half frequency signal and a quarter frequency signal according to the base frequency signal, and transmit the half frequency signal to the fifth output pin and the quarter frequency signal to the sixth output pin; the fourth output pin transmits the base frequency signal to the mainboard through the fourth cable, the fifth output pin transmits the half frequency signal to the mainboard through the fifth cable, and the sixth output pin transmits the quarter frequency signal to the mainboard through the sixth cable; the mainboard is used to determine whether the fourth cable between the mainboard and the Riser card is correctly connected according to the base frequency signal, whether the fifth cable between the mainboard and the Riser card is correctly connected according to the half frequency signal, and whether the sixth cable between the mainboard and the Riser card is correctly connected according to the quarter frequency signal.

9. The server of any of claims 6-8, wherein, The mainboard comprises a complex programmable logic device, which is used to determine whether the cables between the backboard and / or the Riser card are correctly connected according to the base frequency signal and / or the frequency division signal.

10. The server of any of claims 6-8, wherein, The server further comprises: A substrate management controller connected with the mainboard, used to display the misconnection or missed connection information when receiving the misconnection or missed connection information occurred in the mainboard.

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