Design Method of Doorbell Engine for PCIE-to-RAPIDIO Bridge

Abstract

The present invention relates to the field of integrated circuit technology, and particularly to a design method for a doorbell engine of a PCIE-to-RAPIDIO bridge. The PCIE-to-RAPIDIO bridge system mainly includes: a PCIE core, a RAPIDIO core, and a doorbell engine module dell_engine; the doorbell engine module dell_engine is used to process the conversion of PCIE-to-RAPIDIO bridge doorbell information; the doorbell information is divided into the Inbound doorbell signal and the Outbound doorbell signal of the RAPIDIO core, that is, the IB Doorbell mode and the OB Doorbell mode; an engine module is used as a link for data conversion between PCIE and RAPIDIO to effectively realize the conversion between the Inbound and Outbound doorbell information of the PCIE-to-RAPIDIO bridge, thereby realizing the transmission of doorbell signals.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and particularly to a design method for a doorbell engine of a PCIE-to-RAPIDIO bridge. Background Art

[0002] With the continuous development of integrated circuit technology, the clock frequency has been continuously increasing, and the requirement for the data transmission rate has also been further improved. The interconnection architectures of traditional buses such as PCI and CPCI can no longer meet the requirement of the highest rate in terms of transmission rate, so serial bus protocols for high-speed transmission such as RAPIDIO and PCIE have gradually replaced the traditional architectures and have certain advantages in the market.

[0003] RAPIDIO is an interconnection architecture proposed for the development of embedded systems, which is a high-reliability, high-performance, packet-switching-based interconnection architecture and an open interconnection technology standard. PCI-Express is a high-speed serial computing expansion bus standard, which has characteristics such as point-to-point high-speed interconnection, flexible expansion, space-saving serial connection, excellent RAS characteristics, and low power consumption. As a CPU peripheral bus interface, it is widely used in computer systems.

[0004] Currently, RAPIDIO is often used as the interface standard for embedded systems, while PCIE is mostly used for data exchange between most computer systems and peripheral devices. Therefore, the PCIE-to-RAPIDIO bridge is particularly important as a link between RAPIDIO and PCIE. The PCIE-to-RAPIDIO bridge can improve the interface capabilities between a computer and multi-node, multi-type hardware subsystems, and increase the data exchange capabilities within the computer system.

[0005] The PCIE protocol packet format mainly includes forms such as MWr and MRd, and the RAPIDIO protocol packet format mainly includes forms such as NREAD / NWRITE, NWRITE_R, SWRITE, and DOORBELL. Among them, the DOORBELL data packet, as doorbell information, is a short notification message used for message notification between the master device and the slave device. Therefore, for the DOORBELL data packet of the PCIE-to-RAPIDIO bridge, a special doorbell engine needs to be designed to implement the conversion function of the DOORBELL information between the PCIE-to-RAPIDIO bridges. Summary of the Invention

[0006] Aiming at the deficiencies of the prior art, the present invention provides a design method for the doorbell engine of a PCIE-to-RAPIDIO bridge. For different types of doorbell information of Inbound and Outbound, an engine module is used as the link for data conversion between PCIE and RAPIDIO to effectively realize the conversion between Inbound and Outbound doorbell information of the PCIE-to-RAPIDIO bridge, thereby realizing the transmission of doorbell signals.

[0007] The present invention is realized through the following technical solutions:

[0008] A design method for the doorbell engine of a PCIE-to-RAPIDIO bridge. The PCIE-to-RAPIDIO bridge system mainly includes: a PCIE core, a RAPIDIO core, and a doorbell engine module dell_engine; the doorbell engine module dell_engine is used to process the conversion of doorbell information of the PCIE-to-RAPIDIO bridge.

[0009] When the doorbell information is the Inbound doorbell signal of the RAPIDIO core, that is, in the IB Doorbell mode; the doorbell engine module dell_engine processes the doorbell information of the PCIE-to-RAPIDIO bridge and converts the Inbound doorbell signal of RAPIDIO into an MWr data packet of the PCIE core.

[0010] When the doorbell information is the Outbound doorbell signal of the RAPIDIO core, that is, in the OB Doorbell mode; an MWr / MRd data packet of the PCIE core is sent, and through protocol conversion, the converted doorbell information is output to the internal controller of the RAPIDIO core through the doorbell engine module dell_engine, and then the doorbell engine inside the RAPIDIO core is used to realize the conversion function of the Outbound doorbell signal of RAPIDIO.

[0011] Preferably, for the Inbound doorbell signal of the RAPIDIO core, when the RAPIDIO core receives the Inbound doorbell information, the RAPIDIO core stores the doorbell ID and related information fields in an internal FIFO, and the doorbell information stored in this FIFO can be obtained through the control status register.

[0012] Preferably, when processing the Inbound doorbell signal part in the doorbell engine module dell_engine module, the dell_engine module is divided into a dbell_apb module and a dbell_axi module. The main function of the dbell_apb module is to process the APB interface with the RAPIDIO core domain and receive the doorbell information generated by the RAPIDIO core. The main function of the dbell_axi module is to receive the RAPIDIO core doorbell information received by the dbell_apb module, receive the memory space setting for storing the doorbell generated by the external custom configuration module, and convert the doorbell information into AXI protocol output according to the received data and memory configuration, and finally form the MWr data packet of the PCIE core.

[0013] Preferably, the process of the doorbell engine module dell_engine module processing the Inbound doorbell signal is as follows: when the number of doorbells in the doorbell information register stored in the RAPIDIO core obtained by the dbell_axi module is greater than zero, a doorbell request is triggered. The doorbell request signal is transmitted to the dbell_apb module. At this time, the doorbell information is read from the RAPIDIO core through the APB interface. Subsequently, the doorbell information received by the dbell_apb module is output to the dbell_axi module to generate the doorbell information of the AXI protocol. According to the address configuration space, the doorbell information read from the RAPIDIO core is stored in the PCIE core, where the memory space for storing the doorbell information is a customizable circular queue.

[0014] Preferably, for the Outbound doorbell signal of the RAPIDIO core, the master device can be implemented by configuring the dedicated control status register of the RAPIDIO core.

[0015] Preferably, the process of the doorbell engine module dell_engine module processing the Outbound doorbell information of the RAPIDIO core is as follows: the control status register for generating the Outbound doorbell signal is configured by the master device by sending the MWr / MRd data packet of the PCIE core; first, the MWr / MRd data packet of the PCIE core is sent. Through the PCIE core, the control status register configuration data is converted into AXI protocol data, and then output as APB protocol data through the AXI to APB protocol conversion module, and finally output to the dbell_apb module inside the dell_engine. The dbell_apb module controls and forwards the configuration data to the internal controller of the RAPIDIO core, thereby realizing the configuration of the internal control status register of the RAPIDIO core and realizing the conversion function of the RAPIDIO Outbound doorbell information.

[0016] The present invention has the following beneficial effects:

[0017] 1) For the RAPIDIO Inbound doorbell information, a dedicated doorbell engine serves as a link to effectively handle the information conversion between RAPI0.0.DIO and the PCIE bridge.

[0018] 2) For the RAPIDIO Outbound doorbell information, by sending PCIE data packets, after protocol conversion, the control status register of the RAPIDIO core is configured, and the internal controller of the RAPIDIO core is driven to send doorbell information, which can simply and effectively complete the Outbound doorbell engine. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0020] Figure 1 It is the structural block diagram of the Inbound doorbell information of the present invention.

[0021] Figure 2 It is the flowchart of the internal IB DB of the dell_engine module of the present invention.

[0022] Figure 3 It is the implementation block diagram related to the IB DB of the dell_engine module of the present invention.

[0023] Figure 4 It is the flowchart of the internal OB DB of the dell_engine module of the present invention.

[0024] Figure 5 It is the implementation block diagram related to the OB DB of the dell_engine module of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0026] Please refer to Figures 1 - 5, the present invention provides a design method for the doorbell engine of the PCIE-to-RAPIDIO bridge. The PCIE-to-RAPIDIO bridge system mainly includes: a PCIE core, a RAPIDIO core, and a doorbell engine module dell_engine; the doorbell engine module dell_engine is used to process the conversion of the PCIE-to-RAPIDIO bridge doorbell information;

[0027] When the doorbell information is the Inbound (abbreviation: IB) doorbell signal of the RAPIDIO core, that is, in the IB Doorbell mode; the doorbell engine module dell_engine processes the doorbell information of the PCIE-to-RAPIDIO bridge, and converts the Inbound doorbell signal of RAPIDIO into an MWr data packet of the PCIE core;

[0028] When the doorbell information is the Outbound (abbreviation: OB) doorbell signal of the RAPIDIO core, that is, in the OB Doorbell (abbreviation: OB DB) mode; send the MWr / MRd data packet of the PCIE core, through protocol conversion, output the converted doorbell information to the internal controller of the RAPIDIO core through the doorbell engine module dell_engine, and then use the doorbell engine inside the RAPIDIO core to implement the conversion function of the Outbound doorbell signal of RAPIDIO.

[0029] When in the IB Doorbell mode: In the IB Doorbell (abbreviation: IBDB) mode, when the RAPIDIO core receives the doorbell information, the RAPIDIO core will store the doorbell ID and related information fields in an internal FIFO. The doorbell information stored in this FIFO can be obtained through the RAPIDIO IB doorbell status control and the RAPIDIO IB doorbell message register. The content of the RAPIDIO IB doorbell status control and the RAPIDIO IB doorbell message register is shown in Tables 1-2 below.

[0030] Table 1 is the RAPIDIO IB doorbell control status register:

[0031]

[0032] Table 2 is the RAPIDIO IB doorbell information register:

[0033]

[0034] After the RAPIDIO core receives the doorbell information, it needs to convert the doorbell information into a PCIE MWr packet for output. For this situation, the present invention designs a dedicated dell_engine module to implement the conversion of doorbell information between the RAPIDIO core and the PCIE core, converting the doorbell information of the APB protocol of the RAPIDIO core into the AXI protocol doorbell information, and converting it into a PCIE core MWr packet through routing.

[0035] The part of the dell_engine module that processes Inbound doorbell information is divided into the dbell_apb module and the dbell_axi module. The main function of the dbell_apb module is to process the APB interface with the RAPIDIO core domain and receive the doorbell information generated by the RAPIDIO core. The main function of the dbell_axi module is to receive the RAPIDIO core doorbell information received by the dbell_apb module, receive the memory space setting for storing the doorbell generated by the external custom configuration module, and convert the doorbell information into an AXI protocol output according to the received data and memory configuration, and finally form a PCIE core MWr data packet.

[0036] As Figure 2 shown, the process of the dell_engine module processing Inbound doorbell information is as follows: When the number of doorbells in the doorbell information register stored in the RAPIDIO core obtained by the dbell_axi module is greater than zero, a doorbell request is triggered. The doorbell request signal is transmitted to the dbell_apb module. At this time, the doorbell information is read from the RAPIDIO core through the APB interface. Subsequently, the doorbell information received by the dbell_apb module is output to the dbell_axi module to generate the doorbell information of the AXI protocol. According to the address configuration space, the doorbell information read from the RAPIDIO core is stored in the PCIE core, where the memory space for storing the doorbell information is a customizable circular queue.

[0037] When in the OB Doorbell mode: For the OB Doorbell mode, the present invention uses the doorbell engine in the RAPIDIO core internal controller to implement the Outbound Doorbell conversion. The implementation method is that the host device configures the control status register dedicated to generating OB doorbell messages, where the control status register includes the RAPIDIO OB doorbell control status register and the RAPIDIO OB doorbell message register. The contents of the two registers are shown in Tables 3 to 4. These registers contain content such as the doorbell information field and the destination ID, and can support multiple parallel OB DB messages. By configuring the above registers, the OB Doorbell information of the RAPIDIO core is sent to the RAPIDIO core domain to implement the OB Doorbell conversion function.

[0038] Table 3 is the RAPIDIO OB doorbell control status register:

[0039]

[0040] Table 4 is the RAPIDIO OB doorbell information register:

[0041]

[0042] In order to configure the control status register of the internal controller of the RAPIDIO core, the design of this situation in the present invention is also implemented in the dell_engine module. The OB doorbell information output by the PCIE core is sent to the internal controller of the RAPIDIO core through the dell_engine module, and finally the doorbell conversion function is implemented inside the RAPIDIO core controller.

[0043] As Figure 4 shown, the process of the PCIE-to-RAPIDIO bridge handling RAPIDIO Outbound doorbell information is as follows: The control status register for OB doorbell message generation is configured by the master device by sending MWr / MRd data packets of the PCIE core. First, the MWr / MRd data packets of the PCIE core are sent. Through the PCIE core, the configuration data of the control status register is converted into data in the AXI protocol, and then output as APB protocol data through the AXI-to-APB protocol conversion module, and finally output to the dbell_apb module inside the dell_engine. The dbell_apb module controls and forwards the configuration data to the RAPIDIO controller, thereby realizing the configuration of the internal control status register of the RAPIDIO and realizing the conversion function of the RAPIDIO Outbound doorbell information.

[0044] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. Design method of doorbell engine for PCIE to RAPIDIO bridge, characterized in that, The PCIE-to-RAPIDIO bridge system mainly includes: a PCIE core, a RAPIDIO core, and a doorbell engine module dell_engine; the doorbell engine module dell_engine is used to process the conversion of PCIE-to-RAPIDIO bridge doorbell information; When the doorbell information is the Inbound doorbell signal of the RAPIDIO core, that is, in the IB Doorbell mode; the doorbell engine module dell_engine processes the doorbell information of the PCIE-to-RAPIDIO bridge, and converts the Inbound doorbell signal of RAPIDIO into an MWr data packet of the PCIE core; When the doorbell information is the Outbound doorbell signal of the RAPIDIO core, that is, in the OB Doorbell mode; send the MWr / MRd data packet of the PCIE core, through protocol conversion, output the converted doorbell information to the internal controller of the RAPIDIO core through the doorbell engine module dell_engine, and then use the doorbell engine inside the RAPIDIO core to implement the Outbound doorbell signal conversion function of RAPIDIO; When processing the part of the Inbound doorbell signal in the doorbell engine module dell_engine, the dell_engine module is divided into a dbell_apb module and a dbell_axi module. The main function of the dbell_apb module is to process the APB interface with the RAPIDIO core domain and receive the doorbell information generated by the RAPIDIO core. The main function of the dbell_axi module is to receive the RAPIDIO core doorbell information received by the dbell_apb module, receive the memory space setting for storing doorbells generated by an external custom configuration module, and convert the doorbell information into an AXI protocol output according to the received data and memory configuration, and finally form an MWr data packet of the PCIE core.

2. The doorbell engine design method of the PCIE to RAPIDIO bridge according to claim 1, wherein For the Inbound doorbell signal of the RAPIDIO core, when the RAPIDIO core receives the Inbound doorbell information, the RAPIDIO core will store the doorbell ID and related information fields in an internal FIFO, and the doorbell information stored in this FIFO can be obtained through the control status register.

3. The doorbell engine design method of the PCIE-to-RAPIDIO bridge according to claim 1, characterized in that, The process of the doorbell engine module dell_engine processing the Inbound doorbell signal is as follows: when the number of doorbells in the doorbell information register stored in the RAPIDIO core obtained by the dbell_axi module is greater than zero, a doorbell request is triggered, and the doorbell request signal is transmitted to the dbell_apb module. At this time, the doorbell information is read from the RAPIDIO core through the APB interface, and then the doorbell information received by the dbell_apb module is output to the dbell_axi module to generate doorbell information in the AXI protocol. According to the address configuration space, the doorbell information read from the RAPIDIO core is stored in the PCIE core, and the memory space for storing doorbell information is a customizable circular queue.

4. The doorbell engine design method of the PCIE to RAPIDIO bridge according to claim 1, characterized in that, For the Outbound doorbell signal of the RAPIDIO core, the master device can be achieved by configuring the dedicated control status register of the RAPIDIO core.

5. The doorbell engine design method of the PCIE to RAPIDIO bridge according to claim 4, characterized in that, The process of the doorbell engine module dell_engine module handling the Outbound doorbell information of the RAPIDIO core is as follows: The control status register for Outbound doorbell signal generation is configured by the master device by sending MWr / MRd data packets of the PCIE core; First, send the MWr / MRd data packets of the PCIE core. Through the PCIE core, the control status register configuration data is converted into data in the AXI protocol, and then output as APB protocol data through the AXI to APB protocol conversion module, and finally output to the dbell_apb module inside dell_engine. The dbell_apb module controls and forwards the configuration data to the internal controller of the RAPIDIO core, thereby realizing the configuration of the internal control status register of the RAPIDIO core and realizing the conversion function of the RAPIDIO Outbound doorbell information.

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