Anti-splitting device and method with embedded passive radio frequency noise suppressor

Abstract

The present application relates to a crackstop device and method having embedded passive radio frequency noise suppressors, and discloses a radio frequency integrated circuit (RFIC) chip including an integrated circuit (IC) region and a crackstop device laterally surrounding the IC region. The crackstop device includes a metal barrier (or, a concentric metal barrier) electrically isolated from the IC region. One or more noise suppressors, particularly one or more passive filters (e.g., low pass filters, high pass filters, band pass filters, and / or band stop filters) are integrated into the structure of the metal barrier to suppress the propagation of noise signals within a particular RF range through the crackstop device. The particular radio frequency range can be a customer specified operating parameter. By embedding the customized noise suppressors into the crackstop device, local signal interference specific to the customer specified operating parameter can be minimized while also avoiding or at least minimizing the risk of moisture ingress into the IC region. A method of forming the chip is also disclosed.

Description

Technical Field

[0001] This invention relates to crackstop devices, and more particularly to embodiments of radio frequency integrated circuit (RFIC) chips having crackstop devices, said crackstop devices having one or more embedded noise suppressors, and embodiments of methods for forming such RFIC chips. Background Technology

[0002] The fabrication of integrated circuit (IC) chips involves creating multiple ICs with identical designs on a semiconductor wafer and laterally surrounding the ICs with a crack-resistant device (also known as a sealing ring). The wafer is then diced (i.e., shredded) into individual chips. The individual IC chips are then directly packaged or mounted onto a laminate or printed circuit board (PCB). Traditionally, the crack-resistant device is a metal barrier (also known as a metal wall) consisting of stacked through-hole strips and conductors. This metal barrier protects the IC from damage (e.g., cracks) and prevents moisture from entering the IC during chip dicing and chip packaging / mounting. Unfortunately, on radio frequency (RF) IC chips, including millimeter-wave IC chips, the metal barrier can propagate RF noise signals. Summary of the Invention

[0003] In light of the foregoing, this document discloses embodiments of chips, particularly radio frequency integrated circuit (RFIC) chips with crack-resistant devices having one or more embedded noise suppressors (also referred to herein as noise dampeners). Specifically, the RFIC chip may include an integrated circuit (IC) region and crack-resistant devices laterally surrounding the IC region. The crack-resistant devices may include metal barriers (or concentric metal barriers) physically separated from the IC region. One or more noise suppressors, particularly one or more passive filters (e.g., low-pass filters, high-pass filters, band-pass filters, and / or band-stop filters), may be integrated into the structure of the metal barrier and (if applicable) between the structures of the metal barrier to suppress the propagation of noise signals within a specific RF range through the crack-resistant devices. The specific RF range may be, for example, customer-specified operating parameters. By embedding customized noise suppressors into the crack-resistant devices, local signal interference specific to customer-specified operating parameters can be minimized, while also avoiding or at least minimizing the risk of moisture entering the IC region. Embodiments of methods for forming such RFIC chips are also disclosed herein.

[0004] More specifically, embodiments of a radio frequency integrated circuit (RFIC) chip with a crack-resistant device are disclosed herein, the crack-resistant device having one or more embedded noise suppressors (also referred to herein as noise cancellers). Each embodiment of the RFIC chip may include a substrate, an integrated circuit (IC) region on a central portion of the substrate, and a crack-resistant device on an edge portion of the substrate. In some embodiments of the RFIC chip, the crack-resistant device may include a single metal barrier laterally surrounding and physically separated from the IC region. Furthermore, the metal barrier may include at least one integrated passive filter (e.g., a low-pass filter, a high-pass filter, a band-pass filter, and / or a band-stop filter) comprising at least one electromagnetic device (e.g., a resistor, an inductor, a capacitor, and / or a stub). In these embodiments of the RFIC chip, the electromagnetic device may be embedded within the metal barrier. In other embodiments of the RFIC chip, the crack-resistant device may include multiple metal barriers. These metal barriers may include a first metal barrier laterally surrounding and physically separated from the IC region and a second metal barrier laterally surrounding the first metal barrier. The metal barrier may also include at least one integrated passive filter (e.g., a low-pass filter, a high-pass filter, a band-pass filter, and / or a band-stop filter) comprising at least one electromagnetic device (e.g., a resistor, an inductor, a capacitor, and / or a stub). In these embodiments of the RFIC chip, the electromagnetic device may be embedded in the first metal barrier, embedded in the second metal barrier, embedded in a combination of the first and second metal barriers, and / or embedded in the space between the first and second metal barriers and electrically connected to the first and second metal barriers.

[0005] In each embodiment of the disclosed RFIC chip, the IC region may include multiple devices, including RF devices and optionally other types of devices. These devices may include at least a first device at a first location and a second device at a second location within the IC region. The first device may be an RF device configured to operate within a specific RF range. The second device may be another RF device or some other type of device. In any case, each passive filter may be configured to suppress the propagation of RF noise signals within a specific RF range. Thus, when a radio frequency signal within a specific RF range is emitted by the first device (e.g., by an aggressor device) and coupled to an adjacent metal barrier of the anti-crack device, the passive filter suppresses the transmission of RF signal noise through the anti-crack device (i.e., through the metal barrier) to the second device (e.g., to the victim device) to prevent interference with the operation of the second device.

[0006] An embodiment of a method for designing and manufacturing a radio frequency integrated circuit (RFIC) chip with a crack-resistant device having one or more embedded noise suppressors (also referred to herein as noise cancellers) is also disclosed herein. More specifically, the method embodiment may include accessing the design of the RFIC chip. This RFIC chip design may include a substrate having a central portion and edge portions laterally surrounding the central portion, and an integrated circuit (IC) region located on the central portion. The RFIC design may include multiple devices located in the IC region, including RF devices and optionally other types of devices. These devices may include at least a first device at a first location and a second device at a second location in the IC region. The first device may be an RF device and the second device may be another RF device or some other type of device.

[0007] The method embodiments may further include establishing a specific radio frequency (RF) range for the operation of the RFIC chip and thereby for the operation of the first device. The design of the RFIC chip can then be updated to include a crack-resistant device having at least one metal barrier. The metal barrier may be located on an edge portion of the substrate, laterally surrounding and physically separated from the IC region. Furthermore, the metal barrier may include at least one integrated passive filter (e.g., a low-pass filter, a high-pass filter, a band-pass filter, and / or a band-stop filter) comprising at least one electromagnetic device (e.g., a resistor, an inductor, a capacitor, and / or a stub). Each passive filter may be configured to suppress the propagation of RF noise signals within the specific RF range. The RFIC chip can then be manufactured according to the updated design. By updating the design to include such a crack-resistant device, the method ensures that when RF signals within the specific RF range are emitted by the first device (e.g., by an interfering device) and coupled to the adjacent metal barrier of the crack-resistant device, the passive filters suppress RF signal noise from propagating through the crack-resistant device (i.e., through the metal barrier) to the second device (e.g., to the victim device) to prevent interference with the operation of the second device. Attached Figure Description

[0008] The invention will be better understood from the following detailed description with reference to the accompanying drawings, which are not necessarily drawn to scale and in which:

[0009] Figure 1A This is an overall layout diagram of a radio frequency integrated circuit (RFIC) chip with a continuous crack prevention device; Figure 1B and Figure 1C They are Figure 1A Different cross-sectional views of the RFIC chip; and Figure 1D and Figure 1E They are Figure 1A An exemplary layout diagram of the metal wire pattern and metal via strip pattern within the crack prevention device of the RFIC chip;

[0010] Figure 2A This is the overall layout diagram of an RFIC chip with a discontinuous crack prevention device; Figure 2B and Figure 2C They are Figure 2A Different cross-sectional views of an RFIC chip;

[0011] Figures 3A-3C This is a layout diagram showing different disclosed embodiments of an RFIC chip with a crack prevention device having an embedded passive noise suppressor;

[0012] Figures 4A-4D This is a circuit diagram showing an exemplary low-pass filter that can be embedded in a crack prevention device;

[0013] Figures 5A-5D This is a circuit diagram showing an exemplary high-pass filter that can be embedded in a crack prevention device;

[0014] Figures 6A-6C This is a circuit diagram showing an exemplary bandpass filter that can be embedded in a crack prevention device;

[0015] Figures 7A-7D This is a circuit diagram showing an exemplary band-stop filter that can be embedded in a crack prevention device;

[0016] Figure 8A This is a layout diagram of an exemplary RFIC chip, for example. Figure 3A As shown, each embedded noise suppressor in the anti-crack device is specifically a low-pass filter, for example... Figure 4A As shown; Figure 8B and Figure 8C They are Figure 8A Different cross-sectional views of the RFIC chip; and Figure 8D and Figure 8E They are Figure 8A An exemplary layout diagram of the metal wire pattern and metal via strip pattern within the crack prevention device of the RFIC chip;

[0017] Figure 9A This is a layout diagram of an exemplary RFIC chip, for example. Figure 3B As shown, each embedded noise suppressor is specifically a bandpass filter, for example... Figure 6A As shown; Figures 9B-9D They are Figure 9A Different cross-sectional views of the RFIC chip; and Figure 9E and Figure 9F They are Figure 9A An exemplary layout diagram of the metal wire pattern and metal via strip pattern within the crack prevention device of the RFIC chip;

[0018] Figure 10AThis is a layout diagram of an exemplary RFIC chip, for example. Figure 3C As shown, each embedded noise suppressor is specifically a band-stop filter, for example... Figure 7D As shown; Figures 10B-10D They are Figure 10A Different cross-sectional views of the RFIC chip; and Figure 10E and Figure 10F They are Figure 10A An exemplary layout diagram of the metal wire pattern and metal via strip pattern within the crack prevention device of the RFIC chip;

[0019] Figure 11 This is a flowchart illustrating an embodiment of a method for designing and manufacturing an RFIC chip with a crack-resistant device having one or more embedded noise suppressors; and

[0020] Figure 12 It is a schematic diagram illustrating a representative hardware environment (i.e., a computer system) used to implement the disclosed design system, method, and computer program product. Detailed Implementation

[0021] As described above, integrated circuit (IC) chip manufacturing involves fabricating multiple ICs with the same design on a semiconductor wafer and laterally surrounding the ICs with a crack-resistant device (also known as a sealing ring). The wafer is then diced (i.e., shredded) into individual chips. The individual IC chips are then directly packaged or mounted onto a printed circuit board (PCB).

[0022] Figure 1A and Figures 1B-1C These are layout diagrams and different cross-sectional views of an exemplary chip 100. The chip 100 includes a substrate 101, an integrated circuit (IC) region 110 on a central portion 102 of the substrate 101, and a crack-resistant device 120 on an edge portion 103 of the substrate 101 laterally surrounding the IC region 110. The crack-resistant device 120 includes a metal barrier 125. The metal barrier 125 includes an optional middle of line (MOL) metal contact strip pattern 121 that extends vertically from the substrate 101 through a dielectric material 126 to the lowest back end of the line (BEOL) metal level (i.e., to the M...). o (layer), and on the metal contact strip pattern 121, including the stacking of alternating layers of metal via strip pattern 123 and metal wire pattern 122, the metal via strip pattern 123 and metal wire pattern 122 being located within the interlayer dielectric (ILD) layer 135 of the BEOL metal layer from the lowest BEOL metal layer to the highest BEOL metal layer (i.e., from M). o Hierarchy to M x (hierarchy).

[0023] Each metal pattern (i.e., optional metal contact strip pattern 121, metal through-hole strip pattern 123, and metal line pattern 122) at each level of the metal barrier 125 is continuous, such that it completely surrounds (i.e., completely laterally surrounds) the IC region 110. Furthermore, within the metal barrier 125, the metal patterns are vertically aligned and in contact with each other, such that the metal barrier 125 itself is a continuous metal barrier without any vertical or horizontal gaps. Figure 1D An exemplary layout of a metal wire pattern 122 is shown, which includes metal wires connected to create a rectangular metal structure having linear sides that completely surround the IC region 110. Figure 1E The layout of the metal via strip pattern 123 is shown, comprising metal via strips patterned and connected to create a rectangular metal structure with chain-like sides completely surrounding the IC region 110. An optional metal contact strip pattern 121 may have substantially the same layout as the metal via strip pattern or a different layout. It should be noted that although there is a break in the metal contact strip pattern 121 and the metal via strip pattern 123 in cross-section ZZ, Figure 1C The gray shaded area 124 in the ZZ section is included to indicate that there is metallic material before and after the section ZZ, such that the metal barrier 125 is continuous (i.e., without gaps).

[0024] Such a crack-resistant device 120 not only prevents damage during chip dicing and chip packaging / mounting, but also inhibits moisture from entering the IC region 110. Unfortunately, on radio frequency (RF) IC chips, including millimeter-wave IC chips, the continuous metal barrier 125 of the crack-resistant device 120 can propagate RF noise signals between devices, for example, from the first device 111, particularly an RF device (also referred to herein as an aggressor device), to the second device 112, particularly another RF device or non-RF device (also referred to herein as a victim device), thereby interrupting or interfering with the operation of the second device 112.

[0025] Figure 2A and Figures 2B-2CThese are layout diagrams and different cross-sectional views of an exemplary chip 200. Like chip 100, this chip 200 includes a substrate 201, an integrated circuit (IC) region 210 having RF devices (e.g., 211-212) on a central portion 202 of the substrate 201, and a crack-resistant device 220 on an edge portion 203 of the substrate 201 laterally surrounding the IC region 210. This crack-resistant device 220 includes a metal barrier 225. The metal barrier 225 includes an optional intermediate process (MOL) metal contact strip pattern 221 that extends vertically from the substrate 201 through a dielectric material 226 to the lowest back-to-end process (BEOL) metal level (i.e., to the M... o (Level), and on the metal contact strip pattern 221, including the stacking of alternating layers of metal via strip pattern 223 and metal wire pattern 222, the metal via strip pattern 223 and metal wire pattern 222 within the interlayer dielectric (ILD) layer 235 of the BEOL metal level from the lowest BEOL metal level to the highest BEOL metal level (i.e., from M). o Hierarchy to M x (hierarchy).

[0026] Each metal pattern at each level of the metal barrier 225 (i.e., the optional metal contact strip pattern 221, metal through-hole strip pattern 223, and metal line pattern 222) can be configured in substantially the same manner as the metal patterns in the metal barrier 125. However, instead of the metal patterns being continuous, each metal pattern may include one or more dielectric-filled gaps, such that there are dielectric-filled gaps 230 that extend the entire height of the metal barrier 225 of the crack prevention device 220. Therefore, the metal barrier 225 is decomposed into discrete metal walls (i.e., not continuous). It should be noted that, except at the gaps 230, Figure 2C The gray shaded area 224 in section ZZ is included to illustrate the presence of metallic material in the metal via strips and metal contact strip patterns before and after section ZZ. In any case, the dielectric fill gaps 230 physically block the propagation of RF noise signals. However, at advanced technology nodes, the ILD material layer 235 within the dielectric fill gaps 230 is typically a structurally porous low-k or ultra-low-k ILD material layer. Therefore, while these dielectric fill gaps 230 prevent the propagation of RF noise signals, they facilitate the entry of moisture into the IC region 210.

[0027] In light of the foregoing, this document discloses embodiments of chips, particularly radio frequency integrated circuit (RFIC) chips with crack-resistant devices having one or more embedded noise suppressors (also referred to herein as noise cancellers). Specifically, the RFIC chip may include an integrated circuit (IC) region and crack-resistant devices laterally surrounding the IC region. The crack-resistant devices may include a metal barrier (or, a concentric metal barrier) physically separated from the IC region. One or more noise suppressors, particularly one or more passive filters (e.g., low-pass filters, high-pass filters, band-pass filters, and / or band-stop filters), may be integrated into the structure of the metal barrier and (if applicable) between the structures of the metal barrier to suppress the propagation of noise signals within a specific RF range through the crack-resistant devices. The specific RF range may be, for example, customer-specified operating parameters. By embedding customized noise suppressors into the crack-resistant devices, local signal interference specific to customer-specified operating parameters can be minimized, while also avoiding or at least minimizing the risk of moisture entering the IC region. Embodiments of methods for forming such RFIC chips are also disclosed herein.

[0028] More specifically, refer to the information disclosed in this article. Figures 3A-3C These are embodiments of radio frequency integrated circuit (RFIC) chips 300A-300C. RFIC chips 300A-300C may include a substrate 301. Substrate 301 may be a semiconductor substrate (e.g., a silicon substrate). Alternatively, substrate 301 may be a semiconductor layer of a semiconductor-on-insulator structure (e.g., a silicon layer of a silicon-on-insulator (SOI) structure). In any case, substrate 301 may have a central portion 302 and an edge portion 303.

[0029] RFIC chips 300A-300C may include an integrated circuit (IC) region 310 located on a central portion 302 of a substrate 301. The IC region 310 may include an RFIC.

[0030] For the purposes of this disclosure, an RFIC is an IC that includes RF devices and / or circuitry configured to operate at frequencies within the radio spectrum and optionally includes other non-RF devices. The radio spectrum includes RF signals with frequencies ranging from 3 Hz to 3 THz. RFIC applications include, but are not limited to, wireless communication applications (e.g., mobile phones, Wi-Fi devices, Bluetooth devices, satellite transceivers, etc.), radar system applications, military applications, imaging applications, etc. Fourth-generation (4G) RFIC applications operate at 6 GHz or below. Fifth-generation (5G) RFIC applications under development are designed to operate in ultra-wideband (UWB), which includes the same sub-6 GHz band previously covered by 4G applications and the lower portion of the millimeter-wave band (mmWave band) (e.g., 24 GHz to 100 GHz). Those skilled in the art will recognize that the millimeter-wave band is a sub-band within the radio spectrum and includes RF signals with extremely high frequencies ranging from 24 GHz to 300 GHz. The wavelength range of RF signals in this millimeter-wave band is from 1 millimeter at 300 GHz to 10 millimeters at 30 GHz (hence the name).

[0031] In any case, the specific RF frequency range used for the RFIC in IC region 310 can be, for example, a customer-specified operating parameter. For illustrative purposes, only the first device 311 and the second device 312 are shown in the figure. The first device 311 can be an RF device, such as an RF transistor, and is referred to herein as an interfering device. The second device 312 can be another RF device (e.g., another RF transistor) or some other non-RF device and is referred to herein as a victim device. It should be understood that, typically, IC region 310 of RFIC chips 300A-300C will include more than two devices. Such devices can include, but are not limited to, RF front-end devices (e.g., receivers and / or transmitters and / or transceivers), devices for signal processing, etc.

[0032] The RFIC chip 300A-300C may also include a crack prevention device 320 located on the edge portion 303 of the substrate 301. In all embodiments, the crack prevention device 320 may include a metal barrier (e.g., see...). Figure 3A A single metal barrier 325), or multiple concentric metal barriers laterally surrounding the IC region 310 (e.g., see...). Figures 3B-3CThe first metal barrier 325.1 and the second metal barrier 325.2 are located within the IC region 310. Metal barriers 325 or 325.1-325.2 can be physically separated from the IC region 310. Furthermore, the space between the IC region 310 and the adjacent metal barriers 325 or 325.1 can be filled with dielectric material and no conductive interconnect structures (e.g., metal wires, metal vias, metal contact strips, etc.) can electrically connect metal barriers 325 or 325.2-325.2 to the IC region 310, or more specifically, to any device or local interconnect within the IC region 310. In other words, the metal barriers can be electrically isolated from the IC region 310.

[0033] Furthermore, one or more passive noise suppressors (also referred to herein as noise dampers), particularly one or more passive filters 390, can be integrated into the structure of the metal barrier. Each passive filter 390 may include at least one electromagnetic device (e.g., a resistor, inductor, capacitor, or stub) and can be configured to suppress the propagation of RF noise signals within a specific RF range through the anti-crack device 320 at different locations on the RFIC chips 300A-300C. By embedding the passive noise suppressor into the anti-crack device 320, local signal interference between devices (e.g., between interfering device 311 and victim device 312) can be minimized, while also avoiding or at least minimizing the risk of moisture entering the IC area.

[0034] Specifically, as described above, each passive filter 390 may include one or more electromagnetic devices 3911-391. n Electromagnetic devices 3911-391 n This may include, for example, resistors, inductors, capacitors, and / or short wires. Electromagnetic devices 3911-391 n Electrical connections (e.g., series and / or parallel) may be made between the interfering device and the victim devices 311-312 to suppress the propagation of noise signals from the interfering device 311 to the victim device 312 within a specific RF range. This specific RF range may be, for example, a customer RF range used for the operation of RF devices within IC region 310.

[0035] The passive filter 390 can be, for example, a passive low-pass filter, a passive high-pass filter, a passive band-pass filter, and / or a passive band-stop filter. A “low-pass filter” is a passive filter configured to allow only signals below a specific frequency (e.g., below the minimum frequency of a specific RF range) to propagate. A “high-pass filter” is a passive filter configured to allow only signals above a specific frequency (e.g., above the maximum frequency of a specific RF range) to propagate. A “band-pass filter” is a passive filter configured to allow only signals within a specific frequency band to propagate (e.g., a band below the minimum frequency of a specific RF range or a band above the maximum frequency of a specific RF range). A “band-stop filter” (also referred to herein as a “notch filter”) is a filter configured to allow only a specific frequency band to propagate (e.g., corresponding to a specific RF range or a band wider than that specific RF range). Therefore, any passive filter 390 of the above types can be configured such that RF noise signals within at least a specific RF range are suppressed from propagating from the interfering device to the victim device.

[0036] Figures 4A-4D This is a circuit diagram illustrating an exemplary low-pass filter that can be embedded in the anti-crack device 320 of RFIC chips 300A, 300B, or 300C along the signal path between the interfering device and the victim device.

[0037] Figures 5A-5D This is a circuit diagram illustrating an exemplary high-pass filter that can be embedded in the anti-crack device 320 of RFIC chips 300A, 300B, or 300C along the signal path between the interfering device and the victim device.

[0038] Figures 6A-6C This is a circuit diagram illustrating an exemplary bandpass filter that can be embedded in the anti-crack device 320 of RFIC chips 300A, 300B, or 300C along the signal path between the interfering device and the victim device.

[0039] Figures 7A-7D This is a circuit diagram illustrating an exemplary band-stop filter (i.e., a notch filter) that can be embedded in the anti-crack device 320 of an RFIC chip 300A, 300B, or 300C along the signal path between the interfering device and the victim device.

[0040] As described above, stubs can also be used to form passive filters. For the purposes of this disclosure, a stub (also referred to as a resonant stub) is a slender metallic feature connected only at one end. Although not shown in the figures, it should be understood that different combinations of stubs (i.e., number, size, shape, position, etc.) can be added to the structure of a metallic barrier to create one or more electromagnetic devices, such as resistors, inductors, and / or capacitors, thereby creating passive filters.

[0041] For example, as described above and in Figures 4A-7D The passive filters 390 described in the text can be combined with... Figure 3A The crack prevention device 320 for the RFIC chip 300A Figure 3B RFIC chip 300B or Figure 3C In the RFIC chip 300C, RF noise signals are suppressed from propagating from the interfering device 311 to the victim device 312 through the anti-crack device 320, thereby avoiding interference with the operation of the victim device 312. It should be understood that... Figures 4A-7D The passive filter shown is not intended to be limiting. Various other passive filters (including other low-pass filters, other high-pass filters, other bandpass filters, and other band-stop filters) that incorporate electromagnetic devices (e.g., resistors, inductors, capacitors, and / or stubs) are well known in the art. Alternatively, such a passive filter may be incorporated into… Figure 3A The crack prevention device 320 for the RFIC chip 300A Figure 3B RFIC chip 300B or Figure 3C In the RFIC chip 300C, RF noise signals are suppressed from propagating from the interference device 311 to the victim device 312 through the anti-crack device 320, thereby avoiding interference with the operation of the victim device 312.

[0042] Figures 8A-8E An exemplary embodiment of the RFIC chip 300A is shown in more detail, wherein the anti-crack device 320 includes a single metal barrier 325 and one or more passive filters. Each passive filter may include one or more electromagnetic devices embedded within a structure of the metal barrier 325. The passive filter may be, for example, according to... Figure 4A The circuit diagram shows the configuration of a 390A low-pass filter.

[0043] More specifically, Figure 8A and Figures 8B-8C These are layout diagrams and different cross-sectional views of an exemplary RFIC chip 300A. This RFIC chip 300A may include a semiconductor substrate 301 and an IC region 310 on a central portion 302 of the semiconductor substrate 301. The IC region 310 may include, but is not limited to, a first device 311 (e.g., an RF device, such as an RF transistor, also referred to herein as an interfering device) and a second device 312 (e.g., another RF device or some other non-RF device, also referred to herein as a victim device). The RFIC chip 300A may further include a crack-resistant device 320 on an edge portion of the semiconductor substrate 301. The crack-resistant device 320 may include a single metal barrier 325 that laterally surrounds the IC region 310 and is physically separated from the IC region 310.

[0044] This single metal barrier 325 may include an optional intermediate process (MOL) metal contact strip pattern 321 that extends vertically from the substrate 301 through the dielectric material 326 to the lowest back-to-end process (BEOL) metal level (i.e., to M). o (layer), and on the metal contact strip pattern 321, including the stacking of alternating layers of metal via strip pattern 323 and metal wire pattern 322, the metal via strip pattern 323 and metal wire pattern 322 being located within the interlayer dielectric (ILD) layer 335 of the BEOL metal layer from the lowest BEOL metal layer to the highest BEOL metal layer (i.e., from M). o Hierarchy to M x (hierarchy).

[0045] Each metal pattern (i.e., optional metal contact strip pattern 321, metal through-hole strip pattern 323, and metal line pattern 322) at each level of the metal barrier 325 can be continuous, such that it completely surrounds (i.e., completely laterally surrounds) the IC region 310. Furthermore, the metal patterns at different levels can be vertically aligned and in contact with each other, such that the metal barrier 325 itself is a continuous metal barrier without any vertical or horizontal gaps or interruptions.

[0046] Figure 8D An exemplary layout of metal wire pattern 322 is shown, which includes metal wires patterned and connected to create a metal shape that completely surrounds IC region 310. For example, the metal wires within each metal wire pattern may include substantially linear lines and these lines may form the sides of a metal rectangle surrounding IC region 310. Figure 8E The layout of a metal via strip pattern 323 is shown, comprising metal via strips patterned and connected to create metal shapes (e.g., metal rectangles) substantially identical to those in a metal wire pattern. For illustrative purposes, the metal via strips within each metal via strip pattern are shown as patterned as substantially linear metal chains that form the edges of a metal rectangle surrounding an IC region. Figures 8D-8E Provided for illustrative purposes only and not intended to be limiting. Alternatively, the metal shape at each level surrounding the IC region can be different (e.g., circular, elliptical, etc.) and / or the pattern of the metal via strips forming the edges of the metal shapes in the metal via strip pattern can vary. For example, linear metal chains can have more complex shapes. Optional metal contact strip pattern 321 can have a layout substantially the same as or different from the metal via strip pattern.

[0047] In addition to the aforementioned features of the metal pattern, each metal pattern at each level of the metal barrier 325 of the anti-crack device 320 of the RFIC chip 300A may include at least one segment, which is specifically patterned into the shape of an electromagnetic device for a passive filter, such as... Figures 8D-8EAs shown. For example, for each low-pass filter 390A, each metal pattern at each level of the metal barrier 325 may include a segment specifically patterned in the shape of an inductor 3911. From level to level, these segments patterned in the shape of an electromagnetic device may be substantially identical and vertically aligned, such that the resulting electromagnetic device extends the entire height of the metal barrier 325. For example, as Figure 8C As shown, for the low-pass filter 390A, from layer to layer, these segments patterned into the shape of an inductor can be substantially the same and vertically aligned, such that the resulting inductor 3911 is embedded in the metal barrier 325 and extends the entire height of the metal barrier 325.

[0048] Furthermore, these segments, patterned into the shape of electromagnetic devices, can be strategically positioned along the metal barrier 325 between the potential coupling regions 313-314 and the interfering and victim devices 311-312. For example, in this case, the inductor 3911 of each low-pass filter 390A can be positioned between the first coupling region 313 (i.e., the coupling region between the anti-crack device 320 and the first device 311 at a first location near the periphery within the IC region 310) and the second coupling region 314 (e.g., the coupling region between the anti-crack device 320 and the second device 312 at a second location near the periphery within the IC region 310). Such a low-pass filter 390A can be employed to ensure that when any RF noise signal above a certain frequency (e.g., above the minimum frequency of a specific RF range in which the RFIC chip operates) is emitted by the first device 311 and coupled to the metal barrier 325 at the first coupling region 313, the RF noise is suppressed from propagating through the metal barrier 325 to the second coupling region 314, thereby preventing interference with the operation of the second device 312.

[0049] It should be noted that although there are interruptions in the metal contact strip pattern 321 and the metal through-hole strip pattern 323 in cross-section ZZ, Figure 8C The gray shaded area 324 in the ZZ section is included to illustrate the presence of metallic material before and after the ZZ section, wherein the individual metallic barriers 325 are continuous (i.e., without gaps) and even span segments specifically patterned into the shape of an electromagnetic device. Therefore, in Figures 8A-8EIn the exemplary RFIC chip 300A shown, a single metal barrier 325 can suppress moisture from entering the IC region 310. However, it should be understood that having a single metal barrier 325 limits the types of passive filters that can be incorporated therein. For example, a passive filter containing electromagnetic devices connected in parallel may be difficult to integrate into a single metal barrier. Furthermore, a passive filter with capacitors may be difficult to integrate into a single metal barrier without creating an interruption in the capacitor dielectric between the two capacitor plates, which could allow moisture to enter the IC region 310.

[0050] In any case, as described above, in the RFIC chip 300A, a single metal barrier 325 can be physically separated from the IC region 310. This single metal barrier 325 can be further electrically isolated from the IC region 310. For example, the RFIC chip 300A may not have any interconnection between the single metal barrier 325 and devices or other features within the IC region 310. Additionally, to ensure that the single metal barrier 325 is not electrically connected to the IC region 310 through the substrate 301, the metal barrier 325 may fall on some form of isolation region within the edge portion 303 of the substrate 301. The isolation region 381 may be, for example, a doped well region, or alternatively, a moat region (i.e., a region protected during well implantation) having a different conductivity type and / or level than the adjacent semiconductor material 383 between the isolation region 381 and the IC region 310. For example, the semiconductor substrate 301 may have a first type of conductivity (e.g., a P-substrate) at a relatively low conductivity level, the isolation region 381 may be a doped well region (e.g., an N+ well region) with a second type of conductivity at a relatively high conductivity level, and the adjacent semiconductor material 383 between the isolation region 381 and the IC region 310 may be another doped well region with a first type of conductivity (e.g., a P-well region) having a higher conductivity level than the substrate. Alternatively, the isolation region 381 may be a conventional shallow trench isolation (STI) region (i.e., a trench extending into the substrate 301 and filled with one or more layers of isolation material).

[0051] Figures 9A-9F An exemplary embodiment of the RFIC chip 300B is shown in more detail, wherein the anti-crack device 320 includes a plurality of concentric metal barriers (e.g., a first metal barrier 325.1, also referred to herein as an inner metal barrier, and a second metal barrier 325.2, also referred herein as an outer metal barrier) and one or more passive filters, the one or more passive filters including one or more electromagnetic devices embedded only within the first metal barrier 325.1. The passive filter may be, for example, according to... Figure 6A The circuit diagram shows the configuration of the 390B bandpass filter.

[0052] More specifically, Figure 9A and Figures 9B-9D These are layout diagrams and different cross-sectional views of an exemplary RFIC chip 300B. This RFIC chip 300B may include a semiconductor substrate 301 and an IC region 310 on a central portion 302 of the semiconductor substrate 301. The IC region 310 may include, but is not limited to, a first device 311 (e.g., an RF device, such as an RF transistor, also referred to herein as an interfering device) and a second device 312 (e.g., another RF device or some other non-RF device, also referred to herein as a victim device).

[0053] The RFIC chip 300B may also include a crack prevention device 320 on the edge portion of the semiconductor substrate 301. The crack prevention device 320 may include a plurality of concentric metal barriers. The concentric metal barriers may include a first metal barrier 325.1 (i.e., an inner metal barrier) that laterally surrounds and is physically separated from the IC region and the IC region, and a second metal barrier 325.2 (i.e., an outer metal barrier) that laterally surrounds and is physically separated from the first metal barrier 325.1.

[0054] Each metal barrier 325.1 and 325.2 may include an optional intermediate process (MOL) metal contact strip pattern 321 that extends vertically from the substrate 301 through the dielectric material 326 to the lowest back-to-end process (BEOL) metal level (i.e., to M). o (layer), and on the metal contact strip pattern 321, including the stacking of alternating layers of metal via strip pattern 323 and metal wire pattern 322, the metal via strip pattern 323 and metal wire pattern 322 within the interlayer dielectric (ILD) layer 335 of the BEOL metal layer from the lowest BEOL metal layer to the highest BEOL metal layer (i.e., from M). o Hierarchy to M x (hierarchy).

[0055] Typically, each metal pattern (i.e., the optional metal contact strip pattern 321, metal through-hole strip pattern 323, and metal wire pattern 322) at each level of the first metal barrier 325.1 surrounds (i.e., laterally surrounds) the IC region 310. However, within the first metal barrier 325.1, the metal patterns may or may not be completely continuous (due to the incorporation of electromagnetic devices, as discussed in more detail below). Each metal pattern (i.e., the optional metal contact strip pattern 321, metal through-hole strip pattern 323, and metal wire pattern 322) at each level of the second metal barrier 325.2 is continuous, so that it completely surrounds (i.e., completely laterally surrounds) the first metal barrier 325.1.

[0056] Figure 9EAn exemplary layout of metal line patterns 322 for the first and second metal barriers 325.1 and 325.2 at any given level is shown. These metal line patterns include metal lines that are patterned and connected to create a first metal shape surrounding the IC region 310 and a second metal shape surrounding the first metal shape. For example, the metal lines within each metal line pattern may include substantially linear lines forming the sides of a first metal rectangle surrounding the IC region 310 and the sides of a second metal rectangle surrounding the first metal rectangle. Figure 9F An exemplary layout of metal via strip patterns 323 for the first and second metal barriers 325.1 and 325.2 at any given level is shown. These metal via strip patterns include metal via strips that are patterned and connected to create metal via shapes substantially identical to those in the metal wire pattern. For illustrative purposes, the metal via strips within each metal via strip pattern are shown as patterned as substantially linear metal chains that form the sides of a first metal rectangle surrounding the IC region and the sides of a second metal rectangle surrounding the first metal rectangle. Figures 9E-9F Provided for illustrative purposes only and not intended to be limiting. Alternatively, the metal shape at each level around the IC region can be different (e.g., circular, elliptical, etc.) and / or the pattern of the metal via strip (particularly) forming the edges of the metal shape in the metal via strip pattern can vary. For example, a linear metal chain can have a more complex shape. Optional metal contact strip pattern 321 can have a layout substantially the same as or different from the metal via strip pattern.

[0057] In addition to the features of the aforementioned metallic patterns, such as Figures 9E-9F As shown, each metal pattern at each level of the first metal barrier 325.1 in the anti-crack device 320 of the RFIC chip 300B may include at least one segment, which is specifically patterned into the shape of an electromagnetic device for at least one passive filter. For example, for each bandpass filter 390B, each metal pattern at each level of the first metal barrier 325.1 may include a segment, which is specifically patterned into the shape of a multi-finger capacitor plate of an inductor 3911 and a capacitor 3912. From level to level, these segments patterned into the shape of electromagnetic devices may be substantially identical and vertically aligned, such that the resulting electromagnetic device is embedded in the first metal barrier 325.1 and further extends the entire height of the first metal barrier 325.1. For example, as Figure 9C As shown, for bandpass filter 390B, from layer to layer, these segments patterned into the shape of multi-finger capacitor plates of inductors and capacitors can be substantially identical and vertically aligned, such that the resulting inductors 3911 and capacitors 3912 are embedded in the first metal barrier 325.1, extending the entire height of the first metal barrier 325.1, and connected in series.

[0058] It should be noted that, depending on the configuration of the passive filter, including the type of electromagnetic device and the connections between those devices, integrating the electromagnetic device into the first metal barrier 325.1 may result in the formation of a dielectric-filled gap that could allow moisture to enter the IC region 310. For example, in the bandpass filter 390B shown above and in the figures, the capacitor 3912 connected in series with the inductor 3911 comprises multi-finger capacitor plates separated by capacitor dielectrics. The capacitor dielectrics are an effective interruption in the first metal barrier 325.1, providing a potential path through which moisture can reach the IC region. However, the second metal barrier 325.2, as described above, is continuous and completely surrounds (i.e., completely laterally surrounds) the first metal barrier 325.1, providing additional protection against moisture entering the IC region 310.

[0059] In any case, the electromagnetic devices for the passive filter can be strategically positioned along the first metal barrier 325.1 between the potential coupling regions 313-314 and the interfering and victim devices 311-312. For example, in this case, the inductor 3911 and capacitor 3912 of each bandpass filter 390B are positioned between the first coupling region 313 (i.e., the coupling region between the anti-crack device 320 and the first device 311 at a first location near the periphery within the IC region 310) and the second coupling region 314 (e.g., the coupling region between the anti-crack device 320 and the second device 312 at a second location near the periphery within the IC region 310). Therefore, each bandpass filter 390B can be used to ensure that when any RF noise signal outside a certain frequency band (excluding the specific RF range in which the RFIC chip operates) is emitted by the first device 311 and coupled to the first metal barrier 325.1 at the first coupling region 313, the RF noise is suppressed from being transmitted through the first metal barrier 325.1 to the second coupling region 314, thereby avoiding interference with the operation of the second device 312.

[0060] Although interruptions occur in the metal contact strip pattern 321 and the metal through-hole strip pattern 323 in cross sections ZZ and YY, Figure 9C The cross-section ZZ and Figure 9D The gray shaded area 324 in the cross section YY is included to illustrate that there is metallic material before and after these cross sections, the first metal barrier 325.1 is interrupted only at the capacitor dielectric of the capacitor 3912, while the second metal barrier 325.2 is continuous.

[0061] As described above, in the RFIC chip 300B, a first metal barrier 325.1 laterally surrounds the IC region 310 and is physically separated from the IC region 310, while a second metal barrier 325.2 laterally surrounds the first metal barrier 325.1 and is physically separated from the first metal barrier 325.1. Furthermore, the first metal barrier 325.1 and the second metal barrier 325.2 may be electrically isolated from the IC region 310 and from each other. For example, the RFIC chip 300B may not have any interconnections between the first metal barrier 325.1 and devices or other features within the IC region 310, or between the first metal barrier 325.1 and the second metal barrier 325.2. Additionally, to avoid unnecessary connections between the first metal barrier, the second metal barrier, and / or the IC region 310 via the substrate 301, the metal barriers 325.1 and 325.2 may fall on some form of isolation region within the edge portion 303 of the substrate 301. For example, isolation regions 381-382 may be in the substrate 301 and aligned below the first and second metal barriers 325.1-325.2, respectively. These isolation regions 382 may be doped well regions. Isolation region 381 may be a doped well region, or alternatively, a trench region (i.e., a region protected during well implantation). In either case, isolation region 381 may have a different conductivity type than isolation region 382, ​​and may further have a different conductivity type and / or a different conductivity level than the adjacent semiconductor material 383 between isolation region 381 and IC region 310. For example, semiconductor substrate 301 may have a first type of conductivity (e.g., P-substrate) at a relatively low conductivity level, and isolation region 382 may be a doped well region (e.g., N+ well region) with a second type of conductivity at a relatively high conductivity level. In some embodiments, isolation region 381 may be a doped well region (e.g., P+ well region) with a higher level of first type conductivity, and the adjacent semiconductor material 383 between isolation region 381 and IC region 310 may have a second type of conductivity. In other embodiments, isolation region 381 may be a trench region having a first type of conductivity at substantially the same level as the substrate (e.g., a P-trench region), while the adjacent semiconductor material 383 between isolation region 381 and IC region 310 may be another doped well region (e.g., a P-well) having a first type of conductivity with a higher conductivity level than the substrate 301. Alternatively, the first and second metal barriers 325.1 and 325.2 may lie on conventional shallow trench isolation (STI) regions (i.e., trenches extending into the substrate 301 and filled with one or more layers of isolation material).

[0062] Figures 10A-10FAn exemplary embodiment of the RFIC chip 300C is shown in more detail, wherein the anti-crack device 320 includes a plurality of concentric metal barriers (e.g., a first metal barrier 325.1, also referred to herein as an inner metal barrier, and a second metal barrier 325.2, also referred herein as an outer metal barrier) and one or more passive filters having electromagnetic devices embedded in the space between the first metal barrier, the second metal barrier, the two metal barriers, and / or the space between the metal barriers. The passive filter may be, for example, according to... Figure 7D The circuit diagram shows the configuration of the band-stop filter 390C.

[0063] More specifically, Figure 10A and Figures 10B-10D These are layout diagrams and different cross-sectional views of an exemplary RFIC chip 300C. This RFIC chip 300C may include a semiconductor substrate 301 and an IC region 310 on a central portion 302 of the semiconductor substrate 301. The IC region 310 may include, but is not limited to, a first device 311 (e.g., an RF device, such as an RF transistor, also referred to herein as an interfering device) and a second device 312 (e.g., another RF device or some other non-RF device, also referred to herein as a victim device).

[0064] The RFIC chip 300C may also include a crack prevention device 320 on the edge portion of the semiconductor substrate 301. The crack prevention device 320 may include a plurality of concentric metal barriers. The concentric metal barriers may include a first metal barrier 325.1 (i.e., an inner metal barrier) that is laterally surrounded and physically separated from the IC region and a second metal barrier 325.2 (i.e., an outer metal barrier) that is laterally surrounded by the first metal barrier 325.1.

[0065] Each metal barrier 325.1 and 325.2 may include an optional intermediate process (MOL) metal contact strip pattern 321 that extends vertically from the substrate 301 through the dielectric material 326 to the lowest back-to-end process (BEOL) metal level (i.e., to M). o (layer), and on the metal contact strip pattern 321, including the stacking of alternating layers of metal via strip pattern 323 and metal wire pattern 322, the metal via strip pattern 323 and metal wire pattern 322 within the interlayer dielectric (ILD) layer 335 of the BEOL metal layer from the lowest BEOL metal layer to the highest BEOL metal layer (i.e., from M). o Hierarchy to M x (hierarchy).

[0066] Typically, each metal pattern (i.e., optional metal contact strip pattern 321, metal through-hole strip pattern 323, and metal wire pattern 322) at each level of the first metal barrier 325.1 surrounds (i.e., laterally surrounds) the IC region 310. However, within the first metal barrier 325.1, the metal patterns may or may not be completely continuous (due to the incorporation of electromagnetic devices, as discussed in more detail below). Each metal pattern (i.e., optional metal contact strip pattern 321, metal through-hole strip pattern 323, and metal wire pattern 322) at each level of the second metal barrier 325.2 is continuous, so that it completely surrounds (i.e., completely laterally surrounds) the first metal barrier 325.1.

[0067] Figure 10E An exemplary layout of metal line patterns 322 for the first and second metal barriers 325.1 and 325.2 at any given level is shown. These metal line patterns include metal lines that are patterned and connected to create a first metal shape surrounding the IC region 310 and a second metal shape surrounding the first metal shape. For example, the metal lines within each metal line pattern may include substantially linear lines forming the sides of a first metal rectangle surrounding the IC region 310 and the sides of a second metal rectangle surrounding the first metal rectangle. Figure 10F An exemplary layout of metal via strip patterns 323 for the first and second metal barriers 325.1 and 325.2 at any given level is shown. These metal via strip patterns comprise metal via strips that are patterned and connected to create metal via shapes substantially identical to those in the metal wire pattern. For illustrative purposes, the metal via strips within each metal via strip pattern are shown as patterned as substantially linear metal chains that form the sides of a first metal rectangle surrounding the IC region and the sides of a second metal rectangle surrounding the first metal rectangle. Figures 10E-10F Provided for illustrative purposes only and not intended to be limiting. Alternatively, the metal shape at each level around the IC region can be different (e.g., circular, elliptical, etc.) and / or the pattern of the metal via strip (particularly) forming the edges of the metal shape in the metal via strip pattern can vary. For example, a linear metal chain can have a more complex shape. Optional metal contact strip pattern 321 can have a layout substantially the same as or different from the metal via strip pattern.

[0068] In addition to the features of the metal pattern described above, the metal pattern may include segments within a first metal barrier, within a second metal barrier, within a combination of the first and second metal barriers, and / or within the space between metal barriers for at least one passive filter. For example, for the band-stop filter 390C, each metal pattern at each level of the first metal barrier 325.1 in the anti-crack device 320 of the RFIC chip 300C may include segments specifically patterned in the shape of multi-finger capacitor plates of a first inductor and a first capacitor. From level to level, these segments patterned in the shape of multi-finger capacitor plates of the first inductor and the first capacitor may be substantially identical and vertically aligned such that the resulting first inductor 3911 and first capacitor 3912 are embedded in the first metal barrier 325.1, extending the entire height of the first metal barrier 325.1, and connected in series, as shown below. Figure 10C As shown. Furthermore, for the band-stop filter 390C, each metal pattern at each level of the first and second metal barriers 325.1-325.2 may include segments specifically patterned into the shape of multi-finger capacitor plates of a second capacitor. From level to level, these segments patterned into the shape of multi-finger capacitor plates of the second capacitor may be substantially identical and vertically aligned, such that the resulting second capacitor 3914 has capacitor plates embedded in the metal barriers 325.1-325.2, facing each other, and extending the entire height of the metal barriers 325.1-325.2. Furthermore, for the band-stop filter 390C, the metal pattern at one or more levels may include segments specifically patterned into the shape of a second inductor 3913 having end terminals respectively connected to the first and second metal barriers, such that the second inductor 3913 and the second capacitor 3914 are connected in parallel. It should be noted that the inductor does not need to extend the entire height of the metal barriers as long as the end terminals of the second inductor are connected to the metal barriers.

[0069] In this embodiment, interconnection 395 and / or interruption 396 in the metal barrier may be required to create the desired passive circuitry (e.g., to properly connect the parallel-connected second inductor and second capacitor to the series-connected first inductor and first capacitor).

[0070] It should be noted that, depending on the configuration of the passive filter, including the type of electromagnetic device and the connections between those devices, integrating the electromagnetic device into the metal barrier 325 may result in the formation of a dielectric-filled gap that could allow moisture to enter the IC region 310. Care should be taken during the design process to ensure that no such gap is formed in the second metal barrier 325.2, ensuring that the second metal barrier 325.2 completely surrounds (i.e., completely laterally surrounds) the first metal barrier 325.1 and provides additional protection against moisture entering the IC region 310.

[0071] In any case, the electromagnetic device for the passive filter may be strategically placed along and / or between the first and second metal barriers 325.1-325, so as to be located between the potential coupling regions 313-314 and the interfering and victim devices 311-312. For example, in this case, the electromagnetic devices 3911-3914 of the band-stop filter 390C are placed between the first coupling region 313 (i.e., the coupling region between the anti-crack device 320 and the first device 311 at a first location near the periphery within the IC region 310) and the second coupling region 314 (e.g., the coupling region between the anti-crack device 320 and the second device 312 at a second location near the periphery within the IC region 310). Therefore, each band-stop filter 390C can be used to ensure that when any RF noise signal in a certain frequency band (including the specific RF range in which the RFIC chip operates) is emitted by the first device 311 and coupled to the first metal barrier 325.1 at the first coupling region 313, the RF noise is suppressed from being transmitted through the first metal barrier 325.1 to the second coupling region 314, thereby avoiding interference with the operation of the second device 312.

[0072] As shown in the figures of the previously described embodiment, although interruptions occur in the metal contact strip pattern 321 and the metal through-hole strip pattern 323 in cross sections ZZ and YY, Figure 10C The cross-section ZZ and Figure 10D The gray shaded area 324 in the cross section YY is included to illustrate that there is metallic material before and after these cross sections. The first metal barrier 325.1 is interrupted only at the capacitor dielectric of the first capacitor 3912 and at any necessary interruption 396, and the second metal barrier 325.2 is continuous.

[0073] As described above, in the RFIC chip 300C, a first metal barrier 325.1 laterally surrounds the IC region 310 and is physically separated from the IC region 310, and a second metal barrier 325.2 laterally surrounds the first metal barrier 325.1. Although the first and second metal barriers 325.1-325.2 can be electrically connected to each other to create specific passive circuits (e.g., band-stop circuits), they are electrically isolated from the IC region 310. That is, the RFIC chip 300C may not have any interconnections between the first and / or second metal barriers 325.1-325.2 and devices or other features within the IC region 310. Furthermore, to avoid unwanted connections between the first metal barrier, the second metal barrier, and / or the IC region 310 via the substrate 301, the metal barriers 325.1 and 325.2 may fall on some form of isolation region within the edge portion 303 of the substrate 301. For example, isolation regions 381-382 may be aligned within the substrate 301 and below the first and second metal barriers 325.1-325.2, respectively. These isolation regions 382 may be doped well regions. Isolation region 381 may be a doped well region, or alternatively, a trench region (i.e., a region protected during well implantation). In either case, isolation region 381 may have a different type of conductivity than isolation region 382, ​​and may further have a different type of conductivity and / or a different level of conductivity than the adjacent semiconductor material 383 between isolation region 381 and IC region 310. For example, semiconductor substrate 301 may have a first type of conductivity (e.g., P-substrate) at a relatively low level of conductivity and isolation region 382 may be a doped well region (e.g., N+ well region) with a second type of conductivity at a relatively high level of conductivity. In some embodiments, isolation region 381 may be a doped well region (e.g., P+ well region) with a higher level of first type of conductivity and the adjacent semiconductor material 383 between isolation region 381 and IC region 310 may have a second type of conductivity. In other embodiments, isolation region 381 may be a trench region having a first type of conductivity at substantially the same level as the substrate (e.g., a P-trench region), while the adjacent semiconductor material 383 between isolation region 381 and IC region 310 may be another doped well region (e.g., a P-well) having a first type of conductivity with a higher conductivity level than the substrate 301. Alternatively, the first and second metal barriers 325.1 and 325.2 may lie on conventional shallow trench isolation (STI) regions (i.e., trenches extending into the substrate 301 and filled with one or more layers of isolation material).

[0074] refer to Figure 11 The flowchart also discloses an embodiment of a method for designing and manufacturing a radio frequency integrated circuit (RFIC) chip with a crack prevention device having one or more embedded noise suppressors (also referred to herein as noise dampeners).

[0075] More specifically, method embodiments may include developing a design for an RFIC chip (see process step 1102). An RFIC is an IC whose devices and circuitry are configured to operate at frequencies within the radio spectrum. The radio spectrum includes radio frequency signals with a frequency range of 3 Hz to 3 THz. RFIC applications include, but are not limited to, wireless communication applications (e.g., mobile phones, Wi-Fi devices, Bluetooth devices, satellite transceivers, etc.), radar system applications, military applications, imaging applications, etc. Fourth-generation (4G) RFIC applications operate at 6 GHz or below. Fifth-generation (5G) RFIC applications under development are designed to operate in ultra-wideband (UWB), which includes the same sub-6 GHz band previously covered by 4G applications and the lower portion of the millimeter-wave band (mmWave band) (e.g., 24 GHz to 100 GHz). Those skilled in the art will recognize that the millimeter-wave band is a sub-band within the radio spectrum and includes RF signals with extremely high frequencies ranging from 24 GHz to 300 GHz. The wavelength range of RF signals in this millimeter-wave band is from 1 millimeter at 300 GHz to 10 millimeters at 30 GHz (hence the name).

[0076] The method embodiment may also include establishing a specific radio frequency (RF) range for the operation of the RFIC chip (see process step 1104). The specific RF range can be established according to a specific application and further according to operating parameters specified by the customer.

[0077] Method embodiments may also include performing RF noise modeling based on the design (see process step 1106). For example, the design of an RFIC chip may include a layout of devices to be formed with the IC region of the RFIC chip. RF noise modeling may include modeling the potential noise coupling between the anti-crack device surrounding the IC region and any RF devices located near the periphery within the IC region. Such RF noise modeling may include identifying any interfering-victim device pairs. That is, RF noise modeling may indicate when coupling occurs between the anti-crack device and an RF signal that is within a specific RF range and emitted by a first device, and in particular, the RF device (also referred to herein as an interfering device) will interfere with the operation of a second device (e.g., another RF device or some non-RF device, also referred to herein as a victim device) because the RF signal will propagate along the anti-crack device and couple with the second device. Various techniques for performing RF noise modeling are well known in the art, and therefore, details of these techniques have been omitted from the specification to allow the reader to focus on the prominent aspects of the disclosed methods.

[0078] Method embodiments may also include updating the design of the RFIC chip to include a crack prevention device with one or more embedded noise suppressors (see process step 1108). Updating the design of the RFIC chip in process step 1108 may include selecting a basic crack prevention device configuration from several possible configurations, such as: a crack prevention device including a single metal barrier in RFIC chip 300A, the single metal barrier having at least one passive filter having one or more electromagnetic devices integrated therein; a crack prevention device including multiple concentric metal barriers in RFIC chip 300B, the multiple concentric metal barriers having at least one passive filter having one or more electromagnetic devices integrated only in the first metal barrier; or a crack prevention device including multiple concentric metal barriers in RFIC chip 300C, the multiple concentric metal barriers having at least one passive filter having one or more electromagnetic devices integrated in the space between the first metal barrier, the second metal barrier, both the first metal barrier and the second metal barrier, and / or the space between the first metal barrier and the second metal barrier.

[0079] Updating the RFIC chip design in process step 1108 can further include selecting a specific filter circuit structure for each specific passive filter to be included in the anti-crack device. That is, as discussed above regarding structural embodiments, the passive filter may include one or more electromagnetic devices (e.g., resistors, inductors, capacitors, and / or stubs) connected along a single path between the interfering device and the victim device (e.g., in series and / or in parallel), such that the passive filter functions as a low-pass filter (e.g., see [link to relevant documentation]). Figures 4A-4D The circuit diagrams show different exemplary low-pass filters and high-pass filters (e.g., see...). Figures 5A-5D Different exemplary high-pass filters shown in the circuit diagram), band-pass filters (e.g., see...) Figures 6A-6C The different exemplary bandpass filters shown), or bandstop filters (for example, see...) Figures 7A-7D (The different exemplary band-stop filters shown above). Figures 4A-7D Any passive filter shown or any other suitable passive filter may be included in the crack prevention device.

[0080] Once a specific passive filter is selected, it can be customized to suppress the propagation of RF noise signals within a specific RF range. That is, given a specific RF range, a passive filter calculator can be used to determine the required specifications of the electromagnetic components of the specific passive filter (e.g., inductance of inductors, resistance of resistors, capacitance of capacitors, etc., if applicable) to achieve the desired result. In the case of a low-pass filter, the desired result may include the propagation of only those RF signals below a specific frequency, which is below the minimum frequency of the specific RF range, thereby suppressing the propagation of RF noise signals within that specific RF range. In the case of a high-pass filter, the desired result may include the propagation of only those RF signals above a specific frequency, which is above the maximum frequency of the specific RF range, thereby suppressing the propagation of RF noise signals within that specific RF range. In the case of a band-pass filter, the desired result may include the propagation of only those RF signals within a specific frequency band outside the specific RF range, thereby suppressing the propagation of RF noise signals within that specific RF range. Finally, in the case of a band-stop filter, the desired result may include the propagation of only those RF signals outside a specific frequency band that includes the specific RF range, thereby suppressing the propagation of RF noise signals within that specific RF range.

[0081] Filter calculators, including low-pass filter calculators, high-pass filter calculators, band-pass filter calculators, and band-stop filter calculators, are well known in the art. Therefore, details of such calculators are omitted in this specification to allow the reader to focus on the prominent aspects of the disclosed embodiments. However, it should be understood that the calculations used to determine the specifications of an electromagnetic device will vary depending on the specific passive filter circuit selected.

[0082] For example, in the anti-crack device 320 of the RFIC chip 300B, and in... Figure 6A The exemplary bandpass filter shown in the circuit diagram is for a given minimum frequency (also known as the cutoff frequency) of a specific radio frequency range. L The required inductance (L) of the inductor and the required capacitance (C) of the capacitor can be determined using the following equations:

[0083]

[0084] The anti-crack device 320 used in the RFIC chip 300C is employed and Figure 7D The exemplary bandstop filter shown in the circuit diagram is for a given minimum frequency (also known as the low cutoff frequency) of a specific RF range. L Furthermore, it specifies the maximum frequency of a particular radio frequency range (also known as the high cutoff frequency (f)). HThe required inductances (L1 and L2) for the first and second inductors can be determined using the following equations, and the required capacitances (C1 and C2) for the first and second capacitors can be further determined:

[0085]

[0086] as well as

[0087]

[0088] Next, given the circuit configuration of a particular passive filter, the previously determined specifications of the electromagnetic device of that particular passive filter, the design rules for the technology node under discussion (including, but not limited to, the critical dimensions specified for different BEOL metal layers), the selected basic anti-crack device configuration (e.g., an anti-crack device with a single metal barrier; an anti-crack device with multiple concentric metal barriers, wherein the electromagnetic device of each passive filter will be integrated only into the inner metal barrier; or an anti-crack device with multiple concentric metal barriers, wherein the electromagnetic device of each passive filter will be integrated into and / or between each metal barrier), and given the location of the interfering and victim devices under discussion within the IC region, an anti-crack device can be designed such that the electromagnetic device of the particular passive filter is integrated therein, meets the required specifications, and is electrically connected in such a way (e.g., in parallel and / or in series) to create the particular passive filter along the potential signal path between the interfering and victim devices.

[0089] The RFIC chip can then be manufactured according to the updated design (see process step 1110). For example, multiple IC regions can be fabricated on the semiconductor wafer according to the updated design, each region being laterally surrounded by a crack-resistant device. The semiconductor wafer can then be diced (i.e., shredded) into individual RFIC chips. Given the updated design, each manufactured RFIC chip can have a structure corresponding to RFIC chip structure 300A (see detailed description above). Figure 3A and Figures 8A-8E This corresponds to the structure of the RFIC chip structure 300B (see the detailed description above). Figure 3B and Figures 9A-9F ), or the structure corresponding to the RFIC chip structure 300C (see the detailed description above). Figure 3C and Figures 10A-10FIn other words, the manufactured RFIC chip 300A, 300B, or 300C may include: a substrate 301; an integrated circuit (IC) region 310 on the central portion 302 of the substrate 301; and a crack-resistant device 320 having a metal barrier (e.g., 325 in RFIC chip 300A or 325.1-325-2 in RFIC chip 300B or 300C) on the edge portion 303 of the substrate 301 that laterally surrounds and electrically isolates the IC region 310, and a passive filter 390 embedded in the metal barrier. In the manufactured RFIC chip, each passive filter 390 ensures that when an RF signal within a specific RF range is emitted by a first device 311 (e.g., an RF device, also referred to herein as an interfering device, located at a first position near the periphery within the IC region 310) and coupled to the anti-crack device 320, the transmission of the RF signal through the anti-crack device 320 to a second device 312 (e.g., another RF device or non-RF device, also referred herein as a victim device, located at a second position near the periphery within the IC region 310) is suppressed to prevent interference with the second device 312.

[0090] The individual RFIC chip can then be directly packaged or mounted onto a printed circuit board (PCB).

[0091] The methods described above are used to manufacture integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), bare chips, or packaged forms. In the latter case, the chip is mounted in a single-chip package (e.g., a plastic carrier with leads attached to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier with surface interconnects or buried interconnects, or both). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product, such as a motherboard, or (b) a final product. The final product can be any product that includes the integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0092] The present invention can be implemented in a design system, method, and / or computer program product. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to execute the present invention.

[0093] Computer-readable storage media can be tangible devices that can hold and store instructions for use by an instruction execution device. Computer-readable storage media can be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable optical disc read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanical encoding devices such as punched cards or raised structures in recesses into which instructions are recorded, and any suitable combination of the foregoing. The computer-readable storage media used herein should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through optical fibers), or electrical signals transmitted through wires.

[0094] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device or via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network) to an external computer or external storage device. The network may include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the corresponding computing / processing device.

[0095] Computer-readable program instructions used to perform the operations of this invention may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and traditional procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, a field-programmable gate array (FPGA), or a programmable logic array (PLA) may execute the computer-readable program instructions to personalize the electronic circuitry in order to perform the configuration of this invention by utilizing the state information of the computer-readable program instructions.

[0096] The invention is described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0097] These computer-readable program instructions can be provided to the processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or the processor of the other programmable data processing apparatus, create tools for implementing the functions / actions specified in the flowchart and / or block diagram blocks or blocks. These computer-readable program instructions can also be stored in a computer-readable storage medium that can instruct a computer, programmable data processing apparatus, and / or other means to operate in a particular manner, such that the computer-readable storage medium containing the instructions includes an article of manufacture comprising instructions that implement the functions / actions specified in the flowchart and / or block diagram blocks or blocks.

[0098] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer-implemented process, such that the instructions executed on the computer, other programmable apparatus or other device perform the functions / actions specified in flowchart and / or block diagram blocks or blocks.

[0099] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a portion of a module, segment, or instruction, comprising one or more executable instructions for implementing a specified logical function. In some alternative embodiments, the functions marked in the blocks may occur in a non-consecutive order. For example, depending on the functions involved, two consecutively shown blocks may actually be executed substantially simultaneously, or sometimes these blocks may be executed in reverse order. It will also be noted that each block illustrated in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or implements a combination of dedicated hardware and computer instructions.

[0100] A representative hardware environment (i.e., a computer system) used to implement the disclosed design system, method, and computer program product. Figure 12 The diagram illustrates a hardware configuration of an information processing / computer system according to an embodiment herein. The system includes at least one processor or central processing unit (CPU) 10. The CPU 10 is interconnected via a system bus 12 to various devices, such as random access memory (RAM) 14, read-only memory (ROM) 16, and input / output (I / O) adapters 18. I / O adapters 18 may be connected to peripheral devices, such as disk units 11 and tape drives 13, or other system-readable program storage devices. The system can read inventive instructions from the program storage device and perform the methods of the embodiments herein according to those instructions. The system also includes a user interface adapter 19, which connects a keyboard 15, a mouse 17, a speaker 24, a microphone 22, and / or other user interface devices such as a touchscreen device (not shown) to the bus 12 to collect user input. Additionally, a communication adapter 20 connects the bus 12 to a data processing network 25, and a display adapter 21 connects the bus 12 to a display device 23, which, for example, may be an output device such as a monitor, printer, or transmitter.

[0101] It should be understood that the terminology used herein is for the purpose of describing the disclosed structures and methods and is not restrictive. For example, as used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. Furthermore, as used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Additionally, as used herein, terms such as “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” “upper,” “lower,” “below,” “below,” “above,” “parallel,” “orthogonal,” etc., are intended to describe relative positions in orientation and illustration (unless otherwise stated), and terms such as “contact,” “direct contact,” “adjacent,” “directly adjacent,” “closely adjacent,” etc., are intended to indicate that at least one element is physically in contact with another element (without other elements separating the elements). The term "lateral" is used herein to describe the relative position of elements, and more specifically, to indicate that when these elements are oriented and illustrated in a drawing, an element is positioned to the side of another element rather than above or below it. For example, an element laterally adjacent to another element will be next to the other element, an element laterally close to another element will be directly next to the other element, and an element laterally surrounding another element will be adjacent to and adjoin the outer wall of that other element. All the means or steps plus functional elements, their corresponding structures, materials, actions, and equivalents in the following claims are intended to include any structure, material, or action that performs a function in combination with other claimed elements specifically claimed.

[0102] The description of various embodiments of the present invention is presented for illustrative purposes and is not intended to be exhaustive or limiting to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements to technologies found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A structure for a radio frequency integrated circuit chip, comprising: The substrate includes a central portion and an edge portion; The integrated circuit region is located on this central portion; as well as Multiple metal barriers, located on this edge portion, include: A first metal barrier laterally surrounds the integrated circuit region and is physically separated from the integrated circuit region; A second metal barrier, laterally surrounding the first metal barrier; and A passive filter includes at least one electromagnetic device, wherein the passive filter is embedded in any one of the following: the first metal barrier, the second metal barrier, both the first and second metal barriers, or the space between the first and second metal barriers; and wherein the passive filter suppresses the propagation of radio frequency noise signals through the plurality of metal barriers at different locations within the integrated circuit region. The first metal barrier is located on a first well region in the substrate, and the second metal barrier is located on a second well region in the substrate and has a different conductivity type than the first well region.

2. The structure according to claim 1, in, The integrated circuit region includes radio frequency devices configured to operate in the radio frequency range. The passive filter suppresses radio frequency noise signal propagation within the radio frequency range, and Specifically, when a radio frequency signal within the radio frequency range is emitted by a first device of the radio frequency device at a first location within the integrated circuit area and coupled to the first metal barrier, the passive filter suppresses the transmission of the radio frequency signal through either the first metal barrier or the second metal barrier to prevent interference with the operation of the second device of the radio frequency device at a second location within the integrated circuit area.

3. The structure according to claim 1, in, The substrate includes a semiconductor substrate, which includes: a first well region having a first type of conductivity; and a second well region physically separated from the first well region and having a second type of conductivity. The region of the substrate between the first well region and the second well region has a first type of conductivity with a lower conductivity level than the first well region. The first metal barrier is located on the substrate in the region between the first well region and the second well region, and The second metal barrier is located on the second well region.

4. The structure according to claim 1, wherein, The passive filter is any one of a low-pass filter, a high-pass filter, a band-pass filter, and a band-stop filter.

5. The structure according to claim 1, wherein, The at least one electromagnetic device includes any one of a resistor, a capacitor, an inductor, and a short wire.

6. The structure according to claim 1, wherein, The second metal barrier is electrically isolated from the first metal barrier, and the at least one electromagnetic device is integrated into the first metal barrier.

7. The structure according to claim 1, wherein, At least the second metal barrier is a continuous metal barrier.

8. The structure according to claim 7, in, The at least one electromagnetic device includes an inductor, and The inductor is embedded in any one of the first metal barrier, the second metal barrier, and the space between the first metal barrier and the second metal barrier.

9. The structure according to claim 7, in, The at least one electromagnetic device includes a capacitor, the capacitor comprising: a first capacitor plate; a second capacitor plate; and a capacitor dielectric between the first capacitor plate and the second capacitor plate. The first capacitor plate and the second capacitor plate are respectively embedded in the first metal barrier and in any one of the adjacent sections of the first metal barrier and the second metal barrier.

10. A method for forming the structure of a radio frequency integrated circuit chip, the method comprising: An integrated circuit region, including radio frequency devices, is formed on the substrate; as well as At least one metal barrier is formed on the substrate. The at least one metal barrier includes a first metal barrier laterally surrounding and physically separated from the integrated circuit region, a second metal barrier laterally surrounding the first metal barrier, and at least one passive filter. The at least one passive filter includes at least one electromagnetic device. The at least one passive filter can be embedded in the first metal barrier, embedded in the second metal barrier, embedded in both the first and second metal barriers, or embedded in the space between the first and second metal barriers. Furthermore, the at least one passive filter suppresses the propagation of radio frequency noise signals through the at least one metal barrier at different locations within the integrated circuit region. The first metal barrier is located on a first well region in the substrate, and the second metal barrier is located on a second well region in the substrate and has a different conductivity type than the first well region.

11. The method of claim 10, further comprising: Access to a chip design includes: a substrate having a central portion and edge portions laterally surrounding the central portion; and an integrated circuit region having the radio frequency device located on the central portion; Establish the radio frequency range for the operation of this radio frequency device; The design was updated to include the at least one metal barrier and the at least one passive filter integrated into the at least one metal barrier at the edge portion, such that the at least one passive filter is configured to suppress the propagation of radio frequency noise signals within the radio frequency range through the at least one metal barrier; and The chip is manufactured according to the updated design, wherein the manufacturing of the chip includes the formation of the integrated circuit region and the formation of the at least one metal barrier.

12. The method according to claim 10, in, The at least one passive filter is any one of a low-pass filter, a high-pass filter, a band-pass filter, and a band-stop filter, and The at least one electromagnetic device includes any one of a resistor, a capacitor, an inductor, and a short wire.

13. The method according to claim 10, in, At least the second metal barrier consists of a continuous metal barrier.

Images