RISC-V-based ai computing heterogeneous system

Abstract

The application belongs to the field of integrated circuits, and particularly relates to an AI computing heterogeneous system based on RISC-V. The system mainly comprises: a processor based on a RISC-V instruction set with multiple peripheral interfaces, which is used for sending a custom extension instruction; a NICE (Nuclei Instruction Co-unit Extension) coprocessor module used for executing the custom extension instruction; a register table module used for temporarily storing parameters; an SRAM controller module used for external SRAM control; and a PE (Processing Elements) array calculation module containing an arbitration module and a PE calculation unit, which is used for realizing neural network hardware acceleration calculation. The RISC-V processor transmits the custom extension instruction to the NICE core coprocessor through the NICE bus, controls and schedules the PE array to complete efficient calculation according to the configuration parameters, greatly reduces the access to the storage space, and reduces power consumption. Meanwhile, the system can change the configuration parameters to reconstruct the PE array, and improves the versatility and flexibility.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of integrated circuits, and particularly relates to an AI computing heterogeneous system based on RISC-V. BACKGROUND

[0002] The proposal of AI (Artificial Intelligence) is to simulate human brain thinking and solve problems through machines. In the past three decades, AI has developed rapidly and has received great attention and been widely applied in many fields such as speech recognition, intelligent robots and the like. AI computing, as the core of AI research, imitates biological intelligence to solve complex problems through inspiration from nature.

[0003] As an important research content of AI computing, neural networks are gradually developing towards more complex topological connections and more diverse network structures. The performance difference between different types of networks in different applications is also increasing. Therefore, AI computing requires stronger computing power and more flexible computing architecture to adapt to more application scenarios and perform more complex calculations. However, due to the problems of memory wall and power wall, the current general-purpose computing based on von Neumann architecture is difficult to meet the demand of high-performance AI computing. Moreover, in AI computing, parameters often need to be accessed frequently, and the power consumption of data access is much higher than that of computing. Therefore, reducing the power consumption of large-scale data access is also a big problem in AI computing.

[0004] In order to solve the above problems, there is an urgent need for a reconfigurable AI computing system in the field of artificial intelligence. A reconfigurable AI computing system can be compatible with different types of networks and can realize the trade-off between performance and power consumption according to the characteristics of different networks. During the calculation process, the system can realize higher hardware resource utilization and improve the calculation efficiency by reconfiguring the hardware connection.

[0005] RISC-V is an open-source instruction set architecture based on RISC (Reduced Instruction Set Computer). Because the traditional architectures such as x86 and ARM have relatively high complexity and high development and use costs, researchers have proposed a simplified open-source instruction set architecture RISC-V. Compared with x86 and ARM, RISC-V is more concise, and the instruction set is more regular and simple. The RISC-V-based CPU (Central Processing Unit) has a small kernel area and low power consumption. It supports modular design and has scalability, and also supports extended instructions, and users can customize the required instruction set according to the requirements. In addition, due to the open-source nature of RISC-V, anyone who has the ability and ideas can participate in its development, and the design and use costs are low. The heterogeneous system combined with RISC-V is very flexible and has configurability, and developers can almost design microprocessors for any field by combining or expanding multiple instruction sets.

[0006] Nowadays, artificial intelligence is developing rapidly, and the computing power demand of AI computing is growing exponentially, constantly challenging the limit of computing power. The AI computing hardware platform needs a more efficient control architecture. Although the RISC-V-based CPU does not have specific instructions for controlling AI computing, it has strong expandability, so people can design specific instructions for controlling AI computing based on the expandability of RISC-V, achieve efficient control of AI computing, and improve the efficiency of AI computing. SUMMARY

[0007] The traditional AI computing system architecture needs a large number of parallel ports, and the data transmission is complex, and it cannot flexibly schedule the computing units to complete efficient computing, resulting in high power consumption. However, the RISC-V-based CPU has the characteristics of strong expandability and low power consumption, and it can be combined with other processors to realize a heterogeneous system, flexibly configure an AI computing network, and reconfigure hardware connections. Therefore, based on RISC-V, the present application designs a NICE (Nuclei Instruction Co-unit Extension) core co-processor according to the NICE bus protocol, combines with a PE (Processing Elements) array, and proposes a heterogeneous AI computing system architecture to solve the problems of diverse network structure, frequent access to storage space, and high power consumption encountered in AI computing.

[0008] The present application proposes an AI computing heterogeneous system architecture based on RISC-V, which includes the following modules:

[0009] The processor based on the RISC-V instruction set is defined as a RISC-V processor, which is used to send custom extended instructions and has multiple peripheral interfaces.

[0010] NICE core coprocessor, used for executing custom extension instructions, comprising an instruction decoding module, an instruction execution module, and a top-level control module;

[0011] a register table, used for temporarily storing various configuration parameters transmitted by the RISC-V processor through custom extension instructions;

[0012] a first SRAM controller, used for controlling a first external SRAM;

[0013] a second SRAM controller, used for controlling a second external SRAM;

[0014] a PE array calculation module, used for implementing neural network hardware acceleration calculation, comprising an arbitration module and a PE calculation unit;

[0015] The RISC-V processor is connected with the NICE core coprocessor through a NICE bus interface, the RISC-V processor receives configuration parameters generated by a host computer based on AI calculation content, the configuration parameters are downloaded to the RISC-V processor in the form of custom extension instructions, and the RISC-V processor transmits the parameters to the NICE core coprocessor through the NICE bus interface.

[0016] The NICE core coprocessor is connected with the first SRAM controller, the register table, and the PE array calculation module, the NICE core coprocessor processes the received custom extension instructions through the instruction decoding module to convert them into enabling signals of corresponding functions, the instruction execution module is used for receiving the enabling signals and executing instruction functions, and the top-level control module is used for controlling parameter scheduling of the PE array calculation module; the custom extension instructions include writing SRAM, reading SRAM, initializing network configuration, initializing calculation configuration, and starting network calculation.

[0017] The register table is connected with the PE array calculation module and the RISC-V processor, the register table receives and buffers configuration parameters and input data of the PE array, the configuration parameters include PE array network configuration parameters, weights, and arbitration module configuration parameters, the register table also receives final calculation results obtained by the PE array calculation module, and returns the final calculation results to the host computer through the RISC-V processor.

[0018] The first SRAM controller is connected with the first external SRAM and the NICE core coprocessor, and controls the first external SRAM to read and write configuration parameters.

[0019] The second SRAM controller is connected with the second external SRAM and the PE array calculation module, and controls the second external SRAM to read and write calculation parameters.

[0020] Further, the data processing flow of the RISC-V-based AI computing heterogeneous system comprises:

[0021] Step 1, determining AI computing content, using a script file to generate corresponding configuration parameters according to a data set on a host computer, the configuration parameters including network configuration parameters, weights, arbitration module configuration parameters and input activation parameters;

[0022] Step 2, customizing an extended instruction at a software layer and downloading it to RISC-V to realize code function reconstruction; the host computer transmits the configuration parameters to the RISC-V processor through a serial port, and the RISC-V processor transmits the parameters to the NICE core coprocessor through the NICE bus as a bridge;

[0023] Step 3, the NICE core coprocessor receives the write SRAM instruction sent by the RISC-V processor, completes instruction decoding through a selector, executes the write SRAM instruction in an instruction execution module, uses a first SRAM controller to write the configuration parameters into a first external SRAM; in AI computing, the write SRAM instruction needs to be repeatedly executed until all parameters are written into the first external SRAM;

[0024] Step 4, the NICE core coprocessor receives the initialization network configuration instruction from the RISC-V processor to configure the PE computing unit module; specifically, under the control of a top-level control module in the NICE core coprocessor, the network configuration parameters in the first external SRAM are read through the first SRAM controller and transmitted to a register table, and the PE units participating in the calculation are enabled according to the network configuration parameters;

[0025] Step 5, the NICE core coprocessor receives the initialization computing configuration instruction from the RISC-V processor to read the weights and arbitration module parameters from the first external SRAM and transmit them to the register table, and the arbitration module parameters configure the communication network architecture of the PE array;

[0026] Step 6, the NICE core coprocessor receives the start network computing instruction from the RISC-V processor to read the input activation parameters from the first external SRAM and transmit them to the register table, the top-level control module in the NICE core coprocessor sends a parameter taking signal to the PE array computing module, the PE array computing module takes out the input activation parameters from the register table for network computing, writes the computing parameters into a second external SRAM, and finally saves the final result through the register table and transmits it back to the host computer.

[0027] The advantages of the present application mainly include:

[0028] 1. The AI computing system architecture of the present application has flexible reconfiguration: the code function reconfiguration of RISC-V is programmed and downloaded in the software layer, the register parameters of the AI computing architecture are flexibly configured, the communication network of the PE array is reconfigured, and a more efficient AI computing communication scheme is formed. Finally, the access to the storage space is reduced, the power consumption is reduced, and the computing efficiency is improved.

[0029] 2. The present application designs a NICE core coprocessor specially used for controlling AI computing: according to the NICE bus protocol provided by RISC-V, an adaptive NICE core coprocessor is designed for expanding RISC-V instructions and controlling AI computing, and a high-efficiency AI computing control architecture is formed.

[0030] 3. The present application allows system-level expansion: the system architecture allows the expansion of multiple systems, and the interconnection, cooperation and expansion of multiple systems are realized by configuring RISC-V programs.

[0031] 4. The present application adopts a software and hardware cooperative mode: different instructions are sent by the host computer to execute different functions, which has high flexibility. At the same time, it can return part of the calculation results to the host computer for function testing. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 It is a traditional AI computing system framework diagram;

[0033] Figure 2 It is a system framework diagram of an AI computing heterogeneous system based on RISC-V proposed by the present application;

[0034] Figure 3 It is a specific structure diagram of a NICE core module of an AI computing heterogeneous system based on RISC-V proposed by the present application;

[0035] Figure 4 It is a pseudo instruction usage format and a 32-bit R type NICE core extension instruction format diagram of an AI computing heterogeneous system based on RISC-V proposed by the present application;

[0036] Figure 5 It is a NICE core extension instruction interface timing diagram of an AI computing heterogeneous system based on RISC-V proposed by the present application;

[0037] Figure 6 It is a schematic diagram of instruction data flow transmission of an AI computing heterogeneous system based on RISC-V proposed by the present application;

[0038] Figure 7 It is a RISC-V expandable peripheral diagram of an AI computing heterogeneous system based on RISC-V proposed by the present application;

[0039] Figure 8 The present application proposes a system-level topology of an AI computing heterogeneous system based on RISC-V. DETAILED DESCRIPTION

[0040] The present application will be described in detail below in combination with the accompanying drawings and examples.

[0041] Figure 1 A traditional AI computing system framework is shown in FIG. 1. The traditional architecture designed for AI computing needs to control each PE computing unit of the PE array to interact with external systems such as FPGA (Field Programmable Gate Array) during computation. The PE computing unit obtains computing input data through the FPGA, and the result of the computation needs to be transmitted back to the FPGA. Such a data transmission mode uses a large number of parallel ports, resulting in a large resource overhead. At the same time, it cannot be completed independently and always needs to send control signals through the FPGA to drive the entire computing process. Since the PE array structure for AI computing does not have reconfigurability and cannot be flexibly configured, it cannot achieve flexible access to storage space, resulting in resource waste. At the same time, the system architecture lacks modules that can realize interaction and collaboration among multiple systems, so it is difficult to realize system-level expansion.

[0042] The main embodiment of the present application uses RISC-V in combination with a self-developed NICE core coprocessor to control AI computing using a heterogeneous system and configure parameters to reconfigure the neural network structure. It meets the needs of AI computing for multiple network computing, reduced power consumption, and reduced hardware resource waste.

[0043] EMBODIMENT

[0044] This example is implemented on a Zynq XC7Z035 FPGA of Xilinx Company, and a pulse neural network is used to realize electrocardiogram signal recognition. The implementation method of the present application is described in detail.

[0045] The AI computing heterogeneous system framework based on RISC-V proposed by the present application is shown in FIG. 2. Figure 2The system mainly consists of RISC-V and NICE cores connected by NICE bus, register table, SRAM controller controlling two external SRAMs, and PE array for AI calculation. The host computer 1 downloads programs to the RISC-V processor 2. The NICE core 3 is a coprocessor that cooperates with the RISC-V processor 2 to perform instruction extension and can efficiently control the PE array 4. The PE array consists of an arbitration module 5 and multiple computing units PE and has the characteristics of flexible reconfiguration. The SRAM controllers 6 and 7 control the external SRAMs. The SRAM_1 peripheral 8 is responsible for configuration parameter storage, and the SRAM_2 peripheral 9 is responsible for calculation parameter storage. The register table 10 is responsible for caching configuration parameters and input data.

[0046] The starting input of this embodiment is the electrocardiogram signal data set collected by the electrocardiogram sensor. Since the format of the collected data set does not match the calculation method of the PE array, the data needs to be preprocessed by software on the PC to process the data set format into dual-channel input data. The entire calculation process of the electrocardiogram signal data set is as follows: the first channel inputs 640 data, and the 640*512*64 structure of the two-layer pulse neural network is calculated in the PE array to obtain 64 output data. The second channel inputs 16 data, which are combined with the output of the first pulse neural network to obtain 80 input data. Then, the 80*96*4 structure of the two-layer pulse neural network is calculated in the PE array to finally obtain the 4-class electrocardiogram signal recognition output result, and the inference of the electrocardiogram signal data set is completed.

[0047] Since different data sets require different calculation architectures for AI calculation, most neural network hardware accelerators have fixed structures and cannot flexibly reconfigure the computing units. Therefore, the present application uses a RISC-V processor with a NICE bus to control the computing units and independently designs a NICE core coprocessor 3 dedicated to controlling AI calculation. The NICE bus connects the RISC-V and NICE core coprocessor, enabling the system to flexibly reconfigure the AI calculation unit according to the extended instructions. The overall structure of the designed NICE core module is as follows: Figure 3As shown in the figure, the instruction decoding module 11 and the instruction execution module 12 complete the analysis and execution of the extended instructions designed by the application in the software layer, and the top-level control module 13 is responsible for scheduling the related parameters of AI calculation. The instruction decoding module 11 is composed of a MUX selector, receives the 7-bit instr package data transmitted by the RISC-V processor 2, selects the specified function preset in the NICE core 3 according to the instr package content, and transmits the enable signal of the specified function to the instruction execution module 12. The interface signals of the NICE coprocessor mainly include the request req channel and the feedback rsp channel. The instruction execution module 12 transmits data under the control of the request handshake signals req_valid and req_ready and the feedback handshake signals rsp_valid and rsp_ready, and processes the data transmitted from the RISC-V processor 2 under the control of the enable signal of the specified function. The RISC-V processor 2 first sends the req_valid signal, which represents sending an instruction request, and the instruction execution module 12 of the NICE core 3 returns req_ready, which represents receiving an instruction request. After completing the handshake, the NICE core 3 receives the source operand rs1 and rs2 data. Then the instruction execution module 12 of the NICE core 3 sends the rsp_valid signal, which represents sending a feedback request, and the RISC-V processor 2 returns rsp_ready, which represents receiving a feedback request. Finally, the NICE core 3 returns the rdat data to the RISC-V processor 2 when the rsp channel signal handshake is successful, thereby completing the complete data transmission from the RISC-V processor 2 to the NICE core 3 controlled by the extended instruction.

[0048] The application needs to use the NICE core coprocessor to control AI calculation, and the data amount of AI calculation is large, so the design adopts a 512KB*16 size external SRAM for parameter storage, which can be further expanded according to the needs. At the same time, due to the reconfigurable characteristics of the application, it is necessary to have the ability to flexibly control the top-level control module and the PE calculation array. Therefore, the SRAM for parameter storage is divided into a network configuration parameter part, a calculation configuration parameter part and an electrocardio signal input data part. According to this embodiment, the application designs 5 extended instructions of writing SRAM, reading SRAM, initializing network configuration, initializing calculation configuration and starting network calculation to realize efficient control of the system. The NICE core extended instruction needs to use the pseudo instruction.insn to construct 5 extended instructions according to the NICE bus protocol through software on the host computer, and design the instruction decoding and instruction execution modules of the 5 instructions. The usage format of the pseudo instruction.insn according to the R-type instruction coding is as shown in the figure. Figure 4 (1), wherein.insn is used to inform the compiler of the instruction form, and r represents that the instruction type is R type, and the other parts correspond to Figure 4Parts of the 32-bit NICE instruction encoding format of (2). The NICE core coprocessor instruction decoding module decodes instructions according to the R-type NICE instruction format of RISC-V. The NICE core extension instruction designed in the present application is as shown in Figure 4 The 32-bit R-type NICE instruction format of (2) is shown. The 32-bit encoding is composed of six parts, including an extra encoding space, source register 1, source register 2, destination register, enable bits for controlling three registers, and operation code. The extra encoding space func7 has 7 bits, which corresponds to the data of the instr packet sent by RISC-V, represents the preset function serial number, and can extend up to 128 instructions at most. Source register 1 and source register 2 are data sent by RISC-V, and destination register is data returned to RISC-V. Among them, x0 represents the use of x0 integer register, which is reserved for constant 0, indicating hardware zero. "%0", "%1", etc. represent the operands of the instruction, or called placeholders. In the embedded assembly, variables are associated with placeholders "%0", "%1", etc. according to the order of appearance. The {xd, xs1, xs2} bit is the enable signal of the three registers, which is used to control whether the register rs1, rs2 and the target register rd need to be read. If the value of the xs1 bit is 1, it indicates that the instruction needs to read the operand 1 in the rs1 register, and rs2 is the same. If the value of the xd bit is 1, it indicates that the instruction needs to write back the result to the target register specified by xd. The operation code opcode segment corresponds to which custom predefined instruction group space is used, and there are 4 custom predefined instruction groups, each of which has its own operation code, and can extend up to 512 instructions at most. For example Figure 4As shown, the custom-3 instruction set is used for the extended instructions of the present application, and the opcode 0x7b is assigned to this instruction set. Other custom instruction sets can be used by changing the opcode. The write SRAM instruction uses source register 1 (rs1) and source register 2 (rs2), so the value of {xd, xs1, xs2} of func3 is {011}. The data of the sent instr packet is "1", and the default function 1 is selected to execute the write SRAM, the address is received from source register 1 (rs1), and the data is received from source register 2 (rs2). The NICE core controls the SRAM controller to write data to the SRAM at the specified address. The read SRAM instruction uses source register 1 (rs1) and destination register (rd), so the value of {xd, xs1, xs2} of func3 is {110}. The data of the sent instr packet is "2", and the default function 2 is selected to execute the read SRAM, the address is received from source register 1, and the data at the specified address of the SRAM is read by the NICE core to control the SRAM controller, and the read result is returned from the destination register. The three instructions of initializing network configuration, initializing computing configuration, and starting network computing only use source register 1 (rs1), so the value of {xd, xs1, xs2} of func3 is {010}. The data of the sent instr packet is "3, 4, 5", and the default functions 3, 4, 5 are executed. The timing diagram of the interface of the NICE core extended instruction used by the present application is shown in Figure 5 As shown, the read SRAM instruction is only for debugging.

[0049] In order to realize flexible configuration of parameters, the application transmits parameters from the host computer 1 to the RISC-V processor 2 through the serial port. The RISC-V processor 2 sends a write SRAM instruction, which is parsed by the NICE core 3 instruction decoding, and the instruction execution receives data, which is written into the SRAM_1 peripheral 8 under the control of the SRAM_1 controller 6. Then the RISC-V processor 2 sends an initialization network configuration instruction to control the SRAM_1 controller 6 to read the network configuration parameters from the SRAM_1 peripheral 8 and transmit them to the top-level control 13 module and then configure them to the register table. Next, the RISC-V processor 2 sends an initialization calculation configuration instruction to read the weight and arbitration module configuration parameters from the SRAM_1 peripheral 8, transmit them to the top-level control 13 module and cache them to the register table 10. Finally, the RISC-V processor 2 sends a start network calculation instruction to read the input activation parameters from the SRAM_1 peripheral 8, transmit them to the top-level control 13 module and configure them to the register table 10. The RISC-V processor 2 sends a parameter taking signal to the PE array 4 for AI calculation, and reads the parameters from the register table 10. The PE array starts the electrocardiogram recognition network according to the configuration, and starts the electrocardiogram signal recognition calculation to finally obtain the inference result. In the electrocardiogram signal recognition, two two-layer pulse neural networks use four PE units according to the configuration. In the PE unit, the system reads the input activation and weight in sequence to calculate the neuron. After each neuron calculation is completed, the top-level control module 13 controls the SRAM_2 controller 7 to write the calculation result parameters of the current neuron into the SRAM_2 peripheral 9. Between the PE units, after one layer of neural network uses one PE unit to complete the calculation, the top-level control module 13 controls the next layer of neural network to read the calculation result of the previous layer of neural network as input and uses the second PE unit to perform calculation. After the first pulse neural network is calculated, the top-level control module 13 merges the output result and the second channel data as input and transmits them to the second pulse neural network to continue using two PE units to complete the two-layer pulse neural network calculation. During this period, the PE unit uses the arbitration module 5 to realize data interaction according to the arbitration parameters. The obtained electrocardiogram recognition calculation result is stored in the register table 10 under the control of the top-level control module 13, and is transmitted to the host computer 1 through the RISC-V processor 2. The above data flow of the application is shown in the instruction data flow transmission diagram. Figure 6 The read SRAM operation not mentioned above is only used for debugging.

[0050] The application scenarios of chips at this stage are more complex, and most chips cannot expand new functions after tape-out, which is difficult to meet the demand. The RISC-V-based processor can solve this problem. As an independent and complete CPU, it integrates various peripheral functions, and its expandable peripherals such as Figure 7The hardware part of the RISC-V processor includes peripherals such as I2C, GPIO, PWM, UART, etc., and the peripherals are controlled by using the external device bus module 14, different peripheral configurations can be flexibly selected, and different types of AI computing or additional functions can be easily realized. Therefore, the application can call a specified function to write a corresponding program on the host computer 1, so that the specified peripherals can realize various functions. In addition, when loading the host computer program, the host computer 1 can send a selection signal according to the needs, and use the BOOT selection to store the code in the FLASH or RAM. The default RAM mode has the advantages of fast execution speed, and the disadvantage is that the program disappears when power is off, and needs to be downloaded repeatedly every time the power is turned on. The advantage of using the FLASH mode is that the written program can be saved and run offline, which can meet the application needs.

[0051] In addition, the AI computing scale is increasing, and future systems also pay more attention to compatibility and large-scale data processing, and the use of RISC-V processors can complete system-level expansion. Therefore, the application proposes a system-level expansion architecture combined with RISC-V as shown in the figure. Figure 8 Since the application combines RISC-V with AI computing, multiple systems can interact with the RISC-V processor and the off-chip bus 15, realize interconnection, cooperation and expansion through the off-chip bus 15, and realize system-level expansion. Each system needs independent SRAM to perform functions, and more systems can improve computing power, configure large-scale neural networks, and process large-scale data to meet the needs of different users. At the same time, multiple systems can improve the expansion capability and enhance the overall flexibility.

Claims

1. A heterogeneous AI computing system based on RISC-V, characterized in that, include: A processor based on the RISC-V instruction set is defined as a RISC-V processor, used to send custom extended instructions and has a variety of peripheral interfaces; The NICE core coprocessor is used to execute custom extended instructions and includes an instruction decoding module, an instruction execution module, and a top-level control module. The register table is used to temporarily store various configuration parameters transmitted by the RISC-V processor through custom extended instructions; A first SRAM controller is used to control a first external SRAM; The second SRAM controller is used to control the second external SRAM; The PE array computing module is used to implement hardware-accelerated computing for neural networks, and includes an arbitration module and PE computing units. The RISC-V processor is connected to the NICE core coprocessor via the NICE bus interface. The RISC-V processor receives configuration parameters generated by the host computer based on AI computing content. These configuration parameters are downloaded to the RISC-V processor in the form of custom extended instructions. The RISC-V processor then transmits the parameters to the NICE core coprocessor via the NICE bus interface. The NICE core coprocessor is connected to the first SRAM controller, register table, and PE array computing module. The NICE core coprocessor processes the received custom extended instructions through the instruction decoding module and converts them into enable signals for the corresponding functions. The instruction execution module is used to receive the enable signals and execute the instruction functions. The top-level control module is used to control the parameter scheduling of the PE array computing module. The custom extended instructions include writing to SRAM, reading from SRAM, initializing network configuration, initializing computing configuration, and starting network computing. The register table is connected to the PE array computing module and the RISC-V processor respectively. The register table receives and caches the configuration parameters and input data of the PE array. The configuration parameters include PE array network configuration parameters, weights, and arbitration module configuration parameters. The register table also receives the final calculation results obtained by the PE array computing module and transmits them back to the host computer via the RISC-V processor; The first SRAM controller is connected to the first external SRAM and the NICE core coprocessor respectively. The first SRAM controller controls the first external SRAM to read and write configuration parameters. The second SRAM controller is connected to the second external SRAM and the PE array computing module respectively, and the second SRAM controller controls the second external SRAM to read and write computing parameters.

2. The RISC-V-based heterogeneous AI computing system according to claim 1, characterized in that, The data processing flow of the AI ​​computing heterogeneous system is as follows: Step 1: Determine the AI ​​computation content. Use a script file on the host computer to generate the corresponding configuration parameters based on the dataset. The configuration parameters include network configuration parameters, weights, arbitration module configuration parameters, and input activation parameters. Step 2: Define custom extension instructions in the software layer and download them to RISC-V to refactor the code functionality; the host computer transmits configuration parameters to the RISC-V processor via serial port, and the RISC-V processor uses the NICE bus as a bridge to pass the parameters to the NICE core coprocessor. Step 3: The NICE core coprocessor receives the write SRAM instruction sent by the RISC-V processor, completes the instruction decoding through the selector, executes the write SRAM instruction in the instruction execution module, and uses the first SRAM controller to write the configuration parameters into the first external SRAM. In AI calculation, the write SRAM instruction needs to be executed repeatedly until all parameters are written into the external first external SRAM. Step 4: The NICE core coprocessor receives the initialization network configuration instruction from the RISC-V processor and configures the PE computing unit module. Specifically, under the control of the top-level control module in the NICE core coprocessor, the network configuration parameters in the first external SRAM are read through the first SRAM controller and transmitted to the register table. The PE units participating in the calculation are enabled according to the network configuration parameters. Step 5: The NICE core coprocessor receives the initialization calculation configuration instruction from the RISC-V processor, reads the weights and arbitration module parameters from the first external SRAM, and transmits them to the register table. The arbitration module parameters configure the communication network architecture of the PE array. Step 6: The NICE core coprocessor receives the network computation start instruction from the RISC-V processor, reads the input activation parameters from the first external SRAM, and transmits them to the register table. The top-level control module in the NICE core coprocessor sends a parameter fetching signal to the PE array computation module. The PE array computation module retrieves the input activation parameters from the register table, performs network computation, writes the computation parameters into the second external SRAM, and finally saves the final result through the register table and transmits it back to the host computer.

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