Silicon carbide igbt device with vertical floating and resistive field plate termination and method of fabrication

Abstract

The application provides a vertical floating and resistive field plate terminal silicon carbide IGBT device and a preparation method, a vertical groove type metal-insulator-semiconductor (MIS) structure is introduced in a cell terminal area, a multi-region junction terminal expansion / multi-floating field limiting ring / half-insulating polysilicon SIPOS resistance field plate technology is combined, and a high-efficiency super-high-voltage silicon carbide IGBT device terminal is realized: in a blocking state, the resistance field plate performs lateral voltage division, the groove type MIS structure keeps the same potential with the half-insulating polysilicon connected with the resistance field plate, the device front Ptop multi-region junction terminal expansion and Pshield multi-floating field limiting ring structure are combined to modulate the body and surface electric field, the terminal area is continuously and fully depleted, the main junction electric field concentration is relieved, and the area occupied by the terminal area is reduced. Under the premise of ensuring the high-efficiency terminal of the groove type silicon carbide IGBT device, the high breakdown voltage and the reliability of the oxide layer are maintained.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor technology, specifically a silicon carbide IGBT device with vertical floating and resistive field plate termination. Background Technology

[0002] Flexible DC transmission is a key supporting technology for building smart power transmission networks, and its converter devices and switching devices are playing an increasingly prominent role. Currently, fully controlled devices, represented by silicon (Si) IGBTs, are gradually approaching the physical limits achievable by silicon materials in terms of voltage blocking capability. This results in existing converter devices based on Si switching devices being not only bulky but also having high energy losses. Silicon carbide (SiC), as one of the representatives of third-generation wide-bandgap semiconductor materials, possesses characteristics such as a large bandgap, high critical avalanche breakdown field strength, high thermal conductivity, and strong radiation resistance, making it a promising candidate for high-voltage, high-power systems. Silicon carbide insulated-gate bipolar transistor (IGBT) devices exhibit low conduction losses, high blocking voltage, fast switching speed, good high-temperature performance, and strong radiation resistance. If silicon carbide IGBT devices can be used in ultra-high voltage flexible DC transmission systems, the withstand voltage of a single IGBT can be increased to 4-5 times the current level. This will significantly reduce the number of devices connected in series and auxiliary equipment, improve the flexibility of the device, and achieve the goal of making all converter devices of flexible DC transmission lightweight, compact, low-loss, and highly reliable.

[0003] One of the key design considerations for 10,000-volt ultra-high voltage SiC IGBTs is the implementation of high-efficiency and high-reliability junction termination technology. When transplanting widely used termination technologies in Si IGBT devices, such as junction extension, floating field limiting rings, and field plates, to ultra-high voltage SiC IGBTs, the area occupied by the termination region will increase dramatically in order to withstand the ultra-high voltage and alleviate the electric field of the main junction and surface. Consequently, the current carrying capacity of ultra-high voltage SiC IGBT devices will decrease significantly, electrical characteristics will degrade, and their advantages in smart transmission networks will be weakened. Summary of the Invention

[0004] To address the aforementioned issues, this invention proposes a vertically-type floating and resistive field-plate-terminated silicon carbide IGBT device and its fabrication method. By introducing a vertical trench-type metal-insulator-semiconductor (MIS) structure into the cell termination region, combined with multi-junction termination extension / multi-floating field-limiting ring / semi-insulating polysilicon SIPOS resistive field-plate technology, a high-efficiency ultra-high voltage silicon carbide IGBT device termination is achieved. In the blocking state, the resistive field-plate performs lateral voltage division, and the trench-type MIS structure maintains equipotential with the connected semi-insulating polysilicon. Combined with the Ptop multi-junction termination extension and Pshield multi-floating field-limiting ring structure on the front side of the device, the bulk and surface electric fields are modulated, achieving self-continuous total depletion in the termination region, alleviating the main junction and surface electric fields, and reducing the area occupied by the termination region. This invention maintains high breakdown voltage and oxide layer reliability while ensuring high-efficiency termination of the trench-type silicon carbide IGBT device.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A silicon carbide IGBT device with vertical floating and resistive field plate termination includes a collector metal 9, a P+ collector region 10 above the collector metal 9, an N-type field blocking layer 8 above the P+ collector region 10, and an N-drift region 7 above the N-type field blocking layer 8. The upper left side of the interior of the N-drift region 7 is an active region, within which a gate groove is provided. A silicon gate 5 and a gate dielectric 51 filling the gate groove are provided within the gate groove. Below the gate groove is a P+ shielding layer 6, and to the upper left of the gate groove is a P-type base region 3. To the upper left of the P-type base region 3 is a P+ ohmic contact region 2, and to the upper right of the first P-type base region 3 is an N+ source region 4. The N+ source region 4 and the P+ ohmic contact region 2 are electrically connected to the ohmic contact metal 1 above them. To the right of the gate groove is a transition region P-type base region 3, and to the upper right of the transition region P-type base region 3 is the P+ ohmic contact region 2. To the right of the P-type base region 3 in the transition region is the device's terminal region. Multiple separate vertical metal-insulator-semiconductor (MIS) trench structures are provided within the terminal region. Each MIS trench contains heavily doped polysilicon or metal 41 with a doping concentration higher than 1e19, and an insulating dielectric 31 filling the trench. The spacing between the trenches gradually increases from left to right. A P-type junction terminal extension region 21 is located above adjacent MIS trench regions. Above the terminal region is a passivation layer 11, and above the passivation layer 11 is a semi-insulating polysilicon 12. The semi-insulating polysilicon 12 is connected to the vertical metal-insulator-semiconductor (MIS) trench structure below it through selective etching of the passivation layer 11. The semi-insulating polysilicon 12 is also connected to the ohmic contact metal 1 on the left and right sides. Above and to the right of the terminal region is an N+ source region 4, which is electrically connected to the ohmic contact metal 1 above it.

[0007] As a preferred embodiment, the gate dielectric 51 is SiO2, and the insulating dielectric 31 is SiO2 or a low-K dielectric.

[0008] As a preferred embodiment, the P+ ohmic contact region 2, N+ source region 4, P-type base region 3, P+ shielding layer 6, and P-type junction terminal extension region 21 are all formed by multiple ion implantations.

[0009] As a preferred embodiment, the materials of the P+ ohmic contact region 2, N+ source region 4, P-type base region 3, P+ shielding layer 6, P-type junction terminal extension region 21, N- drift region 7, N-type field blocking layer 8, and P+ collector region 10 of the device are all silicon carbide.

[0010] To achieve the above-mentioned objectives, the present invention also provides a second type of silicon carbide IGBT device with vertical floating and resistive field plate termination, which differs from the first type in that the vertical metal-insulator-semiconductor (MIS) trench structure in the termination region is strip-shaped.

[0011] To achieve the above-mentioned objectives, this invention also provides a third type of vertically floating silicon carbide IGBT device with resistive field plate termination, comprising a collector metal 9, a P+ collector region 10 above the collector metal 9, an N-type field blocking layer 8 above the P+ collector region 10, and an N-drift region 7 above the N-type field blocking layer 8; the upper left side of the interior of the N-drift region 7 is an active region, a gate groove is provided in the active region, a silicon gate 5 and a gate dielectric 51 filling the gate groove are provided in the gate groove, a P+ shielding layer 6 is below the gate groove, and a P-type base region 3 is located to the upper left of the gate groove; a P+ ohmic contact region 2 is located to the upper left of the P-type base region 3, and an N+ source region 4 is located to the upper right of the P-type base region 3; the N+ source region 4 and the P+ ohmic contact region... 2 is electrically connected to the ohmic contact metal 1 above it; to the right of the gate groove is the transition region P-type base region 3, and to the upper right of the transition region P-type base region 3 is the P+ ohmic contact region 2; to the right of the transition region P-type base region 3 is the device termination region, and multiple separate vertical metal-insulator-semiconductor (MIS) trench structures are provided in the termination region. The MIS trenches are provided with heavily doped polycrystalline silicon or metal 41 with a doping concentration higher than 1e19, and insulating dielectric 31 filling the MIS trenches. The spacing between each trench gradually increases from left to right. A P-type junction termination extension region 21 is provided above the adjacent MIS trench regions; above the termination region is the passivation layer 11, and to the upper right of the termination region is the N+ source region 4, which is electrically connected to the ohmic contact metal 1 above it.

[0012] To achieve the above-mentioned objectives, this invention also provides a fourth type of vertically floating silicon carbide IGBT device with resistive field plate termination, comprising a collector metal 9, a P+ collector region 10 above the collector metal 9, an N-type field blocking layer 8 above the P+ collector region 10, and an N-drift region 7 above the N-type field blocking layer 8; the upper left side of the interior of the N-drift region 7 is an active region, a gate groove is provided in the active region, a silicon gate 5 is provided in the gate groove, a gate dielectric 51 filling the gate groove is provided, a P+ shielding layer 6 is below the gate groove, and a P-type base region 3 is located to the upper left of the gate groove; a P+ ohmic contact region 2 is located to the upper left of the P-type base region 3, and an N+ source region 4 is located to the upper right of the P-type base region 3; the N+ source region 4 and the P+ ohmic contact region 2 are connected to... The ohmic contact metal 1 above it is electrically connected; to the right of the gate groove is the transition region P-type base region 3, and to the upper right of the transition region P-type base region 3 is the P+ ohmic contact region 2; to the right of the transition region P-type base region 3 is the device termination region, and the termination region is provided with multiple separate and strip-shaped vertical metal-insulator-semiconductor (MIS) trench structures. The MIS trenches are provided with heavily doped polycrystalline silicon or metal 41 with a doping concentration higher than 1e19, and insulating dielectric 31 filling the MIS trenches. The spacing between each trench gradually increases from left to right. A P-type junction termination extension region 21 is provided above the adjacent MIS trench regions. Above the termination region is a passivation layer 11. To the upper right of the termination region is the N+ source region 4, and the N+ source region 4 is electrically connected to the ohmic contact metal 1 above it.

[0013] To achieve the above-mentioned objectives, this invention also provides a method for fabricating a silicon carbide IGBT device with vertical floating and resistive field plate terminals, comprising the following steps:

[0014] Step 1: Clean the epitaxial wafer, and implant aluminum ions onto the N-epitaxial layer to form a P-type base region and a P-type junction terminal extension region;

[0015] Step 2: Nitrogen ions are injected into the polycrystalline silicon as an implantation barrier layer to form an N+ source region;

[0016] Step 3: Using polysilicon as an implantation barrier layer, aluminum ions are implanted to form a P+ ohmic contact region;

[0017] Step 4: Etching to form MIS structure trenches and gate trenches;

[0018] Step 5: Aluminum ions are implanted to form a P+ shielding layer, dry oxygen oxidation is used to generate a gate oxide layer, and then polysilicon is deposited by annealing in a nitrogen atmosphere to pattern the polysilicon.

[0019] Step 6: Deposit a passivation layer and semi-insulating polycrystalline silicon material in the terminal area;

[0020] Step 7: Deposit and etch metal to form electrodes;

[0021] This invention achieves high-efficiency, ultra-high voltage silicon carbide (IGBT) device termination by introducing a vertical trench-type metal-insulator-semiconductor (MIS) structure into the cell termination region, combined with multi-junction termination extension / multi-floating field-limiting ring / semi-insulating polysilicon SIPOS resistive field plate technology. In the blocking state, the resistive field plate performs lateral voltage division, and the trench-type MIS structure maintains equipotential with the connected semi-insulating polysilicon. Combined with the Ptop multi-junction termination extension and Pshield multi-floating field-limiting ring structure on the front side of the device, the bulk and surface electric fields are modulated, achieving self-continuous total depletion in the termination region, alleviating the electric field of the main junction and surface, and reducing the area occupied by the termination region. This invention maintains high breakdown voltage and oxide layer reliability while ensuring high-efficiency termination of the trench-type silicon carbide IGBT device. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a traditional trench-type silicon carbide IGBT structure with multiple floating field limiting rings;

[0023] Figure 2 This is a schematic diagram of the structure of a silicon carbide IGBT device with a vertical floating and resistive field plate terminal according to Embodiment 1 of the present invention.

[0024] Figure 3 This is a schematic diagram of the cleaning epitaxial wafer of Embodiment 5 of the present invention, showing the formation of a P-type base region and a P-type junction terminal extension region by implanting aluminum ions on the N-epitaxial layer.

[0025] Figure 4 This is a schematic diagram of the formation of an N+ source region by implanting nitrogen ions using polycrystalline silicon as an implantation barrier layer in Embodiment 5 of the present invention;

[0026] Figure 5 This is a schematic diagram of the formation of a P+ ohmic contact region by implanting aluminum ions using polycrystalline silicon as an implantation barrier layer in Embodiment 5 of the present invention;

[0027] Figure 6 This is a schematic diagram of etching to form MIS structure trenches and gate trenches in Embodiment 5 of the present invention;

[0028] Figure 7 This is a schematic diagram of the process in Embodiment 5 of the present invention, in which aluminum ions are implanted to form a P+ shielding layer, dry oxygen oxidation is used to generate a gate oxide layer, and then polysilicon is deposited by annealing in a nitrogen atmosphere.

[0029] Figure 8 This is a schematic diagram of the passivation layer and semi-insulating polycrystalline silicon material deposited in the terminal region of Embodiment 5 of the present invention;

[0030] Figure 9 This is a schematic diagram of the deposition and etching of metal to form an electrode according to Embodiment 5 of the present invention;

[0031] Figure 10This is a schematic diagram of the structure of a silicon carbide IGBT device with a vertical floating and resistive field plate terminal according to Embodiment 2 of the present invention.

[0032] Figure 11 This is a schematic diagram of the structure of the silicon carbide IGBT device with vertical floating and resistive field plate terminal according to Embodiment 3 of the present invention.

[0033] Figure 12 This is a schematic diagram of the structure of the silicon carbide IGBT device with vertical floating and resistive field plate terminal according to Embodiment 4 of the present invention.

[0034] 1 is the ohmic contact metal, 2 is the P+ ohmic contact region, 3 is the P-type base region, 4 is the N+ source region, 5 is the polysilicon gate, 51 is the gate dielectric, 6 is the P+ shielding layer, 7 is the N- drift region, 8 is the N-type field blocking layer, 9 is the collector metal, 10 is the P+ collector region, 11 is the passivation layer, 12 is the semi-insulating polysilicon, 21 is the P-type junction termination extension region, 31 is the insulating dielectric, and 41 is the heavily doped polysilicon or metal. Detailed Implementation

[0035] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0036] Example 1

[0037] like Figure 2As shown, a silicon carbide IGBT device with vertical floating and resistive field plate termination includes a collector metal 9, a P+ collector region 10 above the collector metal 9, an N-type field blocking layer 8 above the P+ collector region 10, and an N-drift region 7 above the N-type field blocking layer 8. The upper left side of the interior of the N-drift region 7 is an active region, within which a gate groove is provided. A silicon gate 5 and a gate dielectric 51 filling the gate groove are provided within the gate groove. Below the gate groove is a P+ shielding layer 6, and to the upper left of the gate groove is a P-type base region 3. To the upper left of the P-type base region 3 is a P+ ohmic contact region 2, and to the upper right of the first P-type base region 3 is an N+ source region 4. The N+ source region 4 and the P+ ohmic contact region 2 are electrically connected to the ohmic contact metal 1 above them. To the right of the gate groove is a transition region P-type base region 3, and to the upper right of the transition region P-type base region 3 is a P+ ohmic contact region 2. To the right of the P-type base region 3 in the transition region is the device's terminal region. Multiple separate vertical metal-insulator-semiconductor (MIS) trench structures are provided within the terminal region. Each MIS trench contains heavily doped polysilicon or metal 41 with a doping concentration higher than 1e19, and an insulating dielectric 31 filling the MIS trench. The spacing between the trenches gradually increases from left to right. A P-type junction terminal extension region 21 is located above adjacent MIS trench regions. Above the terminal region is a passivation layer 11, and above the passivation layer 11 is a semi-insulating polysilicon 12. The semi-insulating polysilicon 12 is connected to the vertical metal-insulator-semiconductor (MIS) trench structure below it through selective etching of the passivation layer 11. The semi-insulating polysilicon 12 is connected to the ohmic contact metal 1 on the left and right sides. Above and to the right of the terminal region is an N+ source region 4, which is electrically connected to the ohmic contact metal 1 above it.

[0038] As a preferred embodiment, the gate dielectric 51 is SiO2, and the insulating dielectric 31 is SiO2 or a low-K dielectric.

[0039] As a preferred embodiment, the P+ ohmic contact region 2, N+ source region 4, P-type base region 3, P+ shielding layer 6, and P-type junction terminal extension region 21 are all formed by multiple ion implantations.

[0040] As a preferred embodiment, the materials of the P+ ohmic contact region 2, N+ source region 4, P-type base region 3, P+ shielding layer 6, P-type junction terminal extension region 21, N- drift region 7, N-type field blocking layer 8, and P+ collector region 10 of the device are all silicon carbide.

[0041] This example achieves high-efficiency ultra-high voltage silicon carbide IGBT device termination by introducing a vertical trench metal-insulator-semiconductor (MIS) structure in the cell termination region, combined with multi-junction termination extension / multi-floating field limiting ring / semi-insulating polysilicon SIPOS resistive field plate technology. In the blocking state, the resistive field plate performs lateral voltage division, and the trench-type MIS structure maintains equipotential with the connected semi-insulating polysilicon. Combined with the Ptop multi-junction termination extension and Pshield multi-floating field limiting ring structure on the front side of the device, the bulk and surface electric fields are modulated, achieving self-continuous total depletion in the termination region, alleviating the electric field of the main junction and surface, and reducing the area occupied by the termination region. This invention maintains high breakdown voltage and oxide layer reliability while ensuring high-efficiency termination of the trench-type silicon carbide IGBT device.

[0042] Example 2

[0043] like Figure 10 As shown, this embodiment is obtained by replacing the separated MIS trench structure with a strip-shaped MIS trench structure in Embodiment 1.

[0044] Example 3

[0045] This embodiment is obtained by removing the semi-insulating polycrystalline silicon SIPOS material from the device in Embodiment 1 and using only the passivation layer.

[0046] like Figure 11 As shown, a vertically floating silicon carbide IGBT device with resistive field plate termination includes a collector metal 9, a P+ collector region 10 above the collector metal 9, an N-type field blocking layer 8 above the P+ collector region 10, and an N-drift region 7 above the N-type field blocking layer 8. The upper left side of the interior of the N-drift region 7 is an active region, within which a gate groove is provided. A silicon gate 5 and a gate dielectric 51 filling the gate groove are provided within the gate groove. Below the gate groove is a P+ shielding layer 6, and to the upper left of the gate groove is a P-type base region 3. To the upper left of the P-type base region 3 is a P+ ohmic contact region 2, and to the upper right of the P-type base region 3 is an N+ source region 4. The N+ source region 4 and the P+ ohmic contact region 2 are connected to the ohmic contact region above them. The contact metal 1 is electrically connected; to the right of the gate groove is the transition region P-type base region 3, and to the upper right of the transition region P-type base region 3 is the P+ ohmic contact region 2; to the right of the transition region P-type base region 3 is the device termination region, which has multiple separate vertical metal-insulator-semiconductor (MIS) trench structures. The MIS trenches contain heavily doped polysilicon or metal 41 with a doping concentration higher than 1e19, and insulating dielectric 31 filling the MIS trenches. The spacing between the trenches gradually increases from left to right. A P-type junction termination extension region 21 is provided above the adjacent MIS trench regions; above the termination region is the passivation layer 11, and to the upper right of the termination region is the N+ source region 4, which is electrically connected to the ohmic contact metal 1 above it.

[0047] Example 4

[0048] This embodiment is obtained by removing the semi-insulating polycrystalline silicon SIPOS material from the device in Embodiment 2 and using only the passivation layer.

[0049] like Figure 12 As shown, a vertically floating silicon carbide IGBT device with resistive field plate termination includes a collector metal 9, a P+ collector region 10 above the collector metal 9, an N-type field blocking layer 8 above the P+ collector region 10, and an N-drift region 7 above the N-type field blocking layer 8. The upper left side of the interior of the N-drift region 7 is an active region, within which a gate groove is provided. A silicon gate 5 and a gate dielectric 51 filling the gate groove are provided within the gate groove. Below the gate groove is a P+ shielding layer 6, and to the upper left of the gate groove is a P-type base region 3. To the upper left of the P-type base region 3 is a P+ ohmic contact region 2, and to the upper right of the P-type base region 3 is an N+ source region 4. The N+ source region 4 and the P+ ohmic contact region 2 are in ohmic contact with their respective upper counterparts. Metal 1 is electrically connected; to the right of the gate groove is the transition region P-type base region 3, and to the upper right of the transition region P-type base region 3 is the P+ ohmic contact region 2; to the right of the transition region P-type base region 3 is the device termination region, which has multiple separate and strip-shaped vertical metal-insulator-semiconductor (MIS) trench structures. The MIS trenches contain heavily doped polysilicon or metal 41 with a doping concentration higher than 1e19, and insulating dielectric 31 filling the MIS trenches. The spacing between the trenches gradually increases from left to right. A P-type junction termination extension region 21 is provided above the adjacent MIS trench regions; above the termination region is the passivation layer 11, and to the upper right of the termination region is the N+ source region 4, which is electrically connected to the ohmic contact metal 1 above it.

[0050] Example 5

[0051] like Figures 3-9 As shown, this example provides a method for fabricating a silicon carbide IGBT device with vertical floating and resistive field plate terminations, including the following steps:

[0052] Step 1: Clean the epitaxial wafer, implant aluminum ions onto the N-epitaxial layer to form a P-type base region and a P-type junction termination extension region; (e.g.) Figure 3 As shown;

[0053] Step 2: Nitrogen ions are implanted using polysilicon as an implantation barrier layer to form an N+ source region; for example... Figure 4 As shown;

[0054] Step 3: Using polycrystalline silicon as an implantation barrier layer, aluminum ions are implanted to form a P+ ohmic contact region; such as... Figure 5 As shown;

[0055] Step 4: Etching to form MIS structure trenches and gate trenches; such as Figure 6 As shown;

[0056] Step 5: Aluminum ions are implanted to form a P+ shielding layer, dry oxidation is performed to generate a gate oxide layer, followed by annealing and deposition of polysilicon under a nitrogen atmosphere, and the polysilicon is patterned; for example... Figure 7 As shown;

[0057] Step 6: Deposit a passivation layer and semi-insulating polycrystalline silicon material in the terminal area; such as... Figure 8 As shown;

[0058] Step 7: Deposit and etch metal to form electrodes; such as Figure 9 As shown;

[0059] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A silicon carbide IGBT device with vertical floating and resistive field plate termination, characterized in that: It includes a collector metal (9), a P+ collector region (10) above the collector metal (9), an N-type field blocking layer (8) above the P+ collector region (10), and an N-drift region (7) above the N-type field blocking layer (8); the upper left side of the interior of the N-drift region (7) is an active region, a gate groove is provided in the active region, a silicon gate (5) is provided in the gate groove, a gate dielectric (51) filling the gate groove is provided, and a P+ shielding layer is below the gate groove. 6) The upper left of the gate recess is a P-type base region (3); the upper left of the P-type base region (3) is a P+ ohmic contact region (2), the upper right of the P-type base region (3) is an N+ source region (4), the N+ source region (4) and the P+ ohmic contact region (2) are electrically connected to the ohmic contact metal (1) above them; the right side of the gate recess is a transition region P-type base region (3), the upper right of the transition region P-type base region (3) is a P+ ohmic contact region (2); the transition region P-type base region To the right of area (3) is the terminal area of ​​the device. Multiple separate vertical metal-insulator-semiconductor (MIS) trench structures are provided in the terminal area. The MIS trenches are provided with heavily doped polysilicon or metal (41) with a doping concentration higher than 1e19 and insulating dielectric (31) filling the MIS trenches. The spacing between each trench gradually increases from left to right. A P-type junction terminal extension area (21) is provided above the adjacent MIS trench areas. Above the terminal area is a passivation layer (11). Above the passivation layer (11) is a semi-insulating polysilicon (12). The semi-insulating polysilicon (12) is connected to the vertical metal-insulator-semiconductor (MIS) trench structure below it by selectively etching the passivation layer (11). The semi-insulating polysilicon (12) is connected to the ohmic contact metal (1) on the left and right. The upper right of the terminal area is an N+ source area (4). The N+ source area (4) is electrically connected to the ohmic contact metal (1) above it.

2. The silicon carbide IGBT device with vertical floating and resistive field plate termination according to claim 1, characterized in that: The gate dielectric (51) is SiO2, and the insulating dielectric (31) is SiO2 or a low-K dielectric.

3. The silicon carbide IGBT device with vertical floating and resistive field plate termination according to claim 1, characterized in that: The P+ ohmic contact region (2), N+ source region (4), P-type base region (3), P+ shielding layer (6), and P-type junction terminal extension region (21) are all formed by multiple ion implantations.

4. The silicon carbide IGBT device with vertical floating and resistive field plate termination according to claim 1, characterized in that: The materials of the P+ ohmic contact region (2), N+ source region (4), P-type base region (3), P+ shielding layer (6), P-type junction terminal extension region (21), N- drift region (7), N-type field blocking layer (8), and P+ collector region (10) are all silicon carbide.

5. The silicon carbide IGBT device with vertical floating and resistive field plate termination according to claim 1, characterized in that: The vertical metal-insulator-semiconductor (MIS) trench structure in the terminal area is strip-shaped.

6. A silicon carbide IGBT device with vertical floating and resistive field plate termination, characterized in that: The system includes a collector metal (9), a P+ collector region (10) above the collector metal (9), an N-type field blocking layer (8) above the P+ collector region (10), and an N-drift region (7) above the N-type field blocking layer (8). The upper left side of the N-drift region (7) is an active region, within which a gate groove is provided. The gate groove contains a silicon gate (5) and a gate dielectric (51) filling the gate groove. Below the gate groove is a P+ shielding layer (6), and to the upper left of the gate groove is a P-type base region (3). To the upper left of the P-type base region (3) is a P+ ohmic contact region (2), and to the upper right of the P-type base region (3) is an N+ source region (4). The N+ source region (4) and the P+ ohmic contact region (2) are electrically connected to the ohmic contact metal (1) above them. Connection; To the right of the gate groove is the transition region P-type base region (3), and to the upper right of the transition region P-type base region (3) is the P+ ohmic contact region (2); To the right of the transition region P-type base region (3) is the device terminal region, and the terminal region is provided with multiple separate vertical metal-insulator-semiconductor (MIS) trench structures. The MIS trenches are provided with heavily doped polysilicon or metal (41) with a doping concentration higher than 1e19, and insulating dielectric (31) filling the MIS trenches. The spacing between each trench gradually increases from left to right. A P-type junction terminal extension region (21) is provided above the adjacent MIS trench regions; Above the terminal region is a passivation layer (11), and to the upper right of the terminal region is an N+ source region (4). The N+ source region (4) is electrically connected to the ohmic contact metal (1) above it.

7. A silicon carbide IGBT device with vertical floating and resistive field plate termination, characterized in that: The system includes a collector metal (9), a P+ collector region (10) above the collector metal (9), an N-type field blocking layer (8) above the P+ collector region (10), and an N-drift region (7) above the N-type field blocking layer (8). The upper left side of the interior of the N-drift region (7) is an active region, and a gate groove is provided in the active region. A silicon gate (5) and a gate dielectric (51) filling the gate groove are provided in the gate groove. A P+ shielding layer (6) is below the gate groove, and a P-type base region (3) is located to the upper left of the gate groove. A P+ ohmic contact region (2) is located to the upper left of the P-type base region (3), and an N+ source region (4) is located to the upper right of the P-type base region (3). The N+ source region (4) and the P+ ohmic contact region (2) are electrically connected to the ohmic contact metal (1) above them. To the right of the gate groove is the transition region P-type base region (3), and to the upper right of the transition region P-type base region (3) is the P+ ohmic contact region (3); to the right of the transition region P-type base region (3) is the device terminal region, and the terminal region is provided with multiple separate and strip-shaped vertical metal-insulator-semiconductor (MIS) trench structures. The MIS trenches are provided with heavily doped polysilicon or metal (41) with a doping concentration higher than 1e19, and insulating dielectric (31) filling the MIS trenches. The spacing between each trench gradually increases from left to right. A P-type junction terminal extension region (21) is provided above the adjacent MIS trench regions; above the terminal region is a passivation layer (11), and to the upper right of the terminal region is an N+ source region (4). The N+ source region (4) is electrically connected to the ohmic contact metal (1) above it.

8. The method for fabricating a silicon carbide IGBT device with vertical floating and resistive field plate terminals according to any one of claims 1 to 7, characterized in that, Includes the following steps: Step 1: Clean the epitaxial wafer, and implant aluminum ions onto the N-epitaxial layer to form a P-type base region and a P-type junction terminal extension region; Step 2: Nitrogen ions are injected into the polycrystalline silicon as an implantation barrier layer to form an N+ source region; Step 3: Using polysilicon as an implantation barrier layer, aluminum ions are implanted to form a P+ ohmic contact region; Step 4: Etching to form MIS structure trenches and gate trenches; Step 5: Aluminum ions are implanted to form a P+ shielding layer, dry oxygen oxidation is used to generate a gate oxide layer, and then polysilicon is deposited by annealing in a nitrogen atmosphere to pattern the polysilicon. Step 6: Deposit a passivation layer and semi-insulating polycrystalline silicon material in the terminal area; Step 7: Deposit and etch metal to form electrodes.

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