Memory and method of manufacturing the same, memory system

Abstract

Embodiments of the present disclosure disclose a memory, a manufacturing method thereof, and a memory system. The memory has a first region and a second region, and includes a first semiconductor structure and a second semiconductor structure which are bonded. The first semiconductor structure includes: a first electrode structure located in the second region and including a first conductive line extending in a first direction and a plurality of second conductive lines extending in a second direction; wherein a level at which the second conductive lines are located is the same as a level at which word lines of the first semiconductor structure are located or a level at which bit lines of the first semiconductor structure are located, and the level at which the second conductive lines are located is different from a level at which the first conductive line is located; the first direction and the second direction intersect; a second electrode structure located in the second region and including a third conductive line extending in the first direction and a plurality of fourth conductive lines extending in the second direction; wherein the fourth conductive lines are located between two adjacent second conductive lines; and a dielectric structure located between the first electrode structure and the second electrode structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the field of integrated circuits, and in particular, to a memory and a manufacturing method thereof, and a memory system. BACKGROUND

[0002] The memory includes an array of memory cells and a peripheral circuit, and active devices and passive devices (e.g., capacitors) are usually arranged in the peripheral circuit. As the integration of the memory is improved, more capacitors or capacitors with larger capacitance values need to be arranged to meet the circuit requirements.

[0003] However, arranging more capacitors or capacitors with larger capacitance values requires a larger area, which makes the size of the formed memory larger and is not conducive to the improvement of the integration of the memory. SUMMARY

[0004] According to a first aspect of embodiments of the present disclosure, a memory is provided, the memory having a first region and a second region, the memory comprising a first semiconductor structure and a second semiconductor structure bonded together; the first semiconductor structure comprises:

[0005] an array of memory cells located in the first region and connected to the second semiconductor structure;

[0006] a first electrode structure located in the second region, comprising: a first conductive line extending in a first direction and a plurality of second conductive lines extending in a second direction; wherein the second conductive lines are located in a same level as word lines of the first semiconductor structure or bit lines of the first semiconductor structure, and the second conductive lines are located in a different level from the first conductive line; the first direction and the second direction intersect;

[0007] a second electrode structure located in the second region, comprising: a third conductive line extending in the first direction and a plurality of fourth conductive lines extending in the second direction; wherein the fourth conductive lines are located in the same level as the second conductive lines, and the third conductive line is located in the same level as the first conductive line; the fourth conductive lines are located between two adjacent second conductive lines; one end of the second conductive line away from the third conductive line is connected to the first conductive line; one end of the fourth conductive line away from the first conductive line is connected to the third conductive line;

[0008] a dielectric structure located between the first electrode structure and the second electrode structure.

[0009] According to a second aspect of embodiments of the present disclosure, a manufacturing method of a memory is provided, the memory having a first region and a second region, the manufacturing method comprising:

[0010] forming a memory cell array;

[0011] forming a first electrode structure; wherein the first electrode structure comprises a first conductive line extending along a first direction and a plurality of second conductive lines extending along a second direction; wherein the second conductive lines are located at a same level as word lines or bit lines, and the second conductive lines are located at a different level than the first conductive line; the first direction and the second direction intersect;

[0012] forming a second electrode structure; wherein the second electrode structure comprises a third conductive line extending along the first direction and a plurality of fourth conductive lines extending along the second direction; wherein the fourth conductive lines are located at a same level as the second conductive lines, and the third conductive line is located at a same level as the first conductive line; the fourth conductive lines are located between two adjacent second conductive lines; the second conductive lines are connected to the first conductive line at an end opposite to the third conductive line; the fourth conductive lines are connected to the third conductive line at an end opposite to the first conductive line;

[0013] forming a dielectric structure; wherein the dielectric structure is located between the first electrode structure and the second electrode structure;

[0014] bonding the memory cell array and a second semiconductor structure; wherein the memory cell array is located in the first region and connected to the second semiconductor structure; the first electrode structure and the second electrode structure are located in the second region.

[0015] According to a third aspect of the embodiments of the present disclosure, a memory system is provided, comprising:

[0016] The memory in any of the above embodiments is configured to store data.

[0017] A memory controller coupled to the memory is configured to control the memory.

[0018] In the embodiments of the present disclosure, by setting the first electrode structure to include the first conductive line and the plurality of second conductive lines, the second electrode structure to include the third conductive line and the plurality of fourth conductive lines, and the dielectric structure to be located between the first electrode structure and the second electrode structure, the first electrode structure, the dielectric structure, and the second electrode structure can form a capacitor with a large capacitance, which is conducive to better meeting the circuit requirements. Moreover, the second conductive line is located in the same level as the word line or the bit line, and the fourth conductive line is located in the same level as the second conductive line, so that the second conductive line and the fourth conductive line can be completed in the same manufacturing process as the word line or the bit line in the memory, which can reduce the probability of short circuit between the second conductive line and the fourth conductive line, control the difference in capacitance, and thus meet the requirements of the circuit with high precision requirements on the capacitance difference.

[0019] In addition, the first electrode structure, the dielectric structure, and the second electrode structure in the first semiconductor structure are all located in the second region, so that the non-array region in the first semiconductor structure can be fully utilized without occupying the space of the second semiconductor structure, which can reduce the size of the second semiconductor structure while meeting the circuit requirements, and is conducive to improving the integration of the memory.

[0020] Further, the first semiconductor structure and the second semiconductor structure are bonded, which can reduce the planar size of the memory and is conducive to further improving the integration of the memory. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 is a layout schematic diagram of a memory according to an embodiment of the present disclosure;

[0022] Figures 2a to 2c is a structure schematic diagram of a memory according to an embodiment of the present disclosure;

[0023] Figure 3a and Figure 3b is another structure schematic diagram of a memory according to an embodiment of the present disclosure;

[0024] Figure 4 is a flowchart of a manufacturing method of a memory according to an embodiment of the present disclosure;

[0025] Figure 5a and Figure 5b is a manufacturing process schematic diagram of a memory according to an embodiment of the present disclosure Figure One ;

[0026] Figure 6a and Figure 6b is a manufacturing process schematic diagram of a memory according to an embodiment of the present disclosure

[0027] Figure 7a and Figure 7bis a schematic diagram of a manufacturing process of a memory according to an embodiment of the present disclosure;

[0028] Figure 8a and Figure 8b is a schematic diagram of a manufacturing process of a memory according to an embodiment of the present disclosure Figure Four ;

[0029] Figure 9a and Figure 9b is a schematic diagram of a manufacturing process of a memory according to an embodiment of the present disclosure Figure One ;

[0030] Figure 10 is a schematic diagram of a manufacturing process of a memory according to an embodiment of the present disclosure;

[0031] Figure 11a and Figure 11b is a schematic diagram of a manufacturing process of a memory according to an embodiment of the present disclosure;

[0032] Figure 12a and Figure 12b is a schematic diagram of a manufacturing process of a memory according to an embodiment of the present disclosure Figure Four . DETAILED DESCRIPTION

[0033] The technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation described herein. On the contrary, these implementations are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0034] The present disclosure will be described in more detail in the following paragraphs with reference to the accompanying drawings. The advantages and features of the present disclosure will be more apparent from the following description and claims. It should be noted that the accompanying drawings are very simplified and use non-precise proportions, only to facilitate, clarify the purpose of assisting the description of the embodiments of the present disclosure.

[0035] It can be understood that the meaning of "on", "above" and "over" of the present disclosure should be interpreted in the broadest way, so that "on" not only means the meaning of "on" with no intervening features or layers between them (i.e. directly on something), but also includes the meaning of "on" with intervening features or layers between them.

[0036] In the embodiments of the present disclosure, the terms "first", "second", "third" and the like are used to distinguish similar objects, and do not necessarily mean a specific order or sequence.

[0037] In embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend over the entirety of an underlying or overlying structure, or can have an extent that is less than the underlying or overlying structure. Further, a layer can be a region of a continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be located between a top surface and a bottom surface of a continuous structure, or the layer can be between any horizontal pair of planes at the top surface and the bottom surface of the continuous structure. A layer can extend horizontally, vertically, and / or along an inclined surface. A layer can include a plurality of sub-layers.

[0038] It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0039] Dynamic random access memory (DRAM) includes an array of memory cells and a peripheral circuit on the same substrate, and a large number of capacitors need to be arranged in the peripheral circuit to realize functions such as decoupling of input / output signals and charge pump.

[0040] The capacitors in the peripheral circuit include metal-oxide-metal (MOM) capacitors and metal-oxide-semiconductor (MOS) capacitors, and the like, and the fabrication of the capacitors is usually completed in the fabrication process of the back-end metal interconnection layer.

[0041] However, the above-mentioned capacitors and the metal wiring of the capacitors all need to occupy a large area, so that the size of the formed memory is large, which is not conducive to the improvement of the integration of the memory. Moreover, in the case that the size of the memory remains basically unchanged, a large number of peripheral circuit capacitors will occupy more space of the array of memory cells, resulting in a decrease in the space that can be occupied by the array of memory cells, that is, a decrease in the utilization rate of the memory.

[0042] In addition, the capacitor density in the array of memory cells of the DRAM memory is very large, but due to the influence of defects, the difference of the capacitors in the array of memory cells is large, which is not suitable for use in circuits with high precision requirements on capacitor difference.

[0043] Therefore, embodiments of the present disclosure provide a memory and a manufacturing method thereof, and a memory system.

[0044] Figure 1 is a layout schematic diagram of a memory 300 according to an embodiment of the present disclosure. Referring to Figure 1As shown, the memory 300 includes a first region 300a, a second region 300b, and a third region 300c, the third region 300c surrounding the first region 300a and the second region 300b. The first region 300a can be a region in which an array of memory cells is disposed in the memory, the second region 300b includes a region in which a redundant region between the array of memory cells in the memory and a peripheral circuit disposed in the memory, and the third region 300c can be a region in which a sealing structure is disposed in the memory.

[0045] Figures 2a to 2c is a structural schematic diagram of a memory 300 according to an embodiment of the present disclosure, wherein, Figure 2a is a sectional view of the memory 300 along the dashed line AA' in Figure 1 is a sectional view of the memory 300 along the dashed line AA' in Figure 2b is a sectional view of the memory 300 along the dashed line AA' in Figure 2a is a top view of the memory 300 in the xy plane along the dashed line BB' in Figure 2c is a top view of the memory 300 in the xy plane along the dashed line BB' in Figure 2a is an enlarged view of a partial region of the memory 300 at the dashed line box S in Figures 2a to 2c As shown, the memory 300 includes a first semiconductor structure 100 and a second semiconductor structure 200 that are bonded; the first semiconductor structure 100 includes:

[0046] an array of memory cells, located in the first region 300a as shown, and connected to the second semiconductor structure 200; Figure 1 a first electrode structure 110, located in the second region 300b as shown, including: a first conductive line 111 extending in a first direction, and a plurality of second conductive lines 112 extending in a second direction; wherein the level at which the second conductive lines 112 are located is the same as the level at which the word lines of the first semiconductor structure 100 are located or the level at which the bit lines of the first semiconductor structure 100 are located, and the level at which the second conductive lines 112 are located is different from the level at which the first conductive lines 111 are located; the first direction and the second direction intersect;

[0047] Figure 1 a second electrode structure 120, located in the second region 300b as shown, including: a third conductive line 121 extending in the first direction, and a plurality of fourth conductive lines 122 extending in the second direction; wherein the level at which the fourth conductive lines 122 are located is the same as the level at which the second conductive lines 112 are located, and the level at which the third conductive lines 121 are located is the same as the level at which the first conductive lines 111 are located; the fourth conductive lines 122 are located between two adjacent second conductive lines 112; the end of the second conductive line 112 that is relatively far from the third conductive line 121 is connected to the first conductive line 111; the end of the fourth conductive line 122 that is relatively far from the first conductive line 111 is connected to the third conductive line 121;

[0048] a second electrode structure 120, located in the second region 300b as shown, including: a third conductive line 121 extending in the first direction, and a plurality of fourth conductive lines 122 extending in the second direction; wherein the level at which the fourth conductive lines 122 are located is the same as the level at which the second conductive lines 112 are located, and the level at which the third conductive lines 121 are located is the same as the level at which the first conductive lines 111 are located; the fourth conductive lines 122 are located between two adjacent second conductive lines 112; the end of the second conductive line 112 that is relatively far from the third conductive line 121 is connected to the first conductive line 111; the end of the fourth conductive line 122 that is relatively far from the first conductive line 111 is connected to the third conductive line 121; Figure 1

[0049] ​​A dielectric structure is between the first electrode structure 110 and the second electrode structure 120.

[0050] The first semiconductor structure 100 and the second semiconductor structure 200 can be wafers, and can also be cut wafers, for example, dies. The bonded first semiconductor structure 100 and the second semiconductor structure 200 include: a bonded wafer and wafer, a bonded wafer and die, or a bonded die and die, etc.

[0051] The memory cell array can be a dynamic random memory cell array, including a plurality of memory cells, the memory cell including a transistor and an energy storage element coupled to the transistor, the energy storage element being a capacitor for storing electric charge. The memory cell array can also be a phase change memory cell array, including a plurality of memory cells, the memory cell including a transistor and an energy storage element coupled to the transistor, the energy storage element implementing information storage based on the difference in resistivity between crystalline and amorphous phases of a phase change material (e.g., a chalcogenide compound). The memory cell array can also be a ferroelectric random memory cell array, including a plurality of memory cells, the memory cell including a transistor and an energy storage element coupled to the transistor, the energy storage element implementing information storage based on the switching between two polarization states of a ferroelectric material under the action of an external electric field.

[0052] Referring to 2b, the first electrode structure 110 includes a first conductive line 111 extending along the x direction and a plurality of second conductive lines 112 arranged side by side along the x direction, each second conductive line 112 extending along the y direction. The second electrode structure 120 includes a third conductive line 121 extending along the x direction and a plurality of fourth conductive lines 122 arranged side by side along the x direction, each fourth conductive line 122 extending along the y direction.

[0053] It should be noted that the same level used in the present disclosure means that the two film layers have the same distance from the top surface of the first semiconductor structure or the bottom surface of the first semiconductor structure, and the different level means that the two film layers have different distances from the top surface of the first semiconductor structure or the bottom surface of the first semiconductor structure.

[0054] For example, the second conductive line at the same level as the word line can mean that the second conductive line and the word line have the same distance from the top surface (or bottom surface) of the first semiconductor structure. The second conductive line at the same level as the bit line can mean that the second conductive line and the bit line have the same distance from the top surface (or bottom surface) of the first semiconductor structure. The second conductive line at a different level from the first conductive line can mean that the second conductive line and the first conductive line have different distances from the top surface (or bottom surface) of the first semiconductor structure.

[0055] In the present example, the first direction can be represented by an x direction, the second direction can be represented by a y direction, and a z direction is perpendicular to the plane in which the x direction and the y direction lie. The x direction and the y direction intersect, and the included angle between the x direction and the y direction includes an acute angle, a right angle, or an obtuse angle. In other embodiments, the first direction can be represented by a y direction, and the second direction can be represented by an x direction, which will be described in detail below.

[0056] Still referring to Figure 2b As shown, the second conductive lines 112 and the fourth conductive lines 122 are located at the same level, and the fourth conductive lines 122 are located between two adjacent second conductive lines 112. The second conductive lines 112 are electrically insulated from the third conductive lines 121 at one end close to the third conductive lines 121, and the fourth conductive lines 122 are electrically insulated from the first conductive lines 111 at one end close to the first conductive lines 111.

[0057] In some embodiments, the length of the first conductive lines 111 in the x direction is the same as the length of the third conductive lines 121 in the x direction. In other embodiments, the length of the first conductive lines 111 in the x direction is different from the length of the third conductive lines 121 in the x direction.

[0058] In some embodiments, the length of the second conductive lines 112 in the y direction is the same as the length of the fourth conductive lines 122 in the y direction. In other embodiments, the length of the second conductive lines 112 in the y direction is different from the length of the fourth conductive lines 122 in the y direction.

[0059] The dielectric structure is located between the first electrode structure 110 and the second electrode structure 120, including: the dielectric structure is located between the first conductive lines 111 and the third conductive lines 121, between the first conductive lines 111 and the fourth conductive lines 122, between the second conductive lines 112 and the third conductive lines 121, and between the second conductive lines 112 and the fourth conductive lines 122.

[0060] The material of the first conductive lines 111, the second conductive lines 112, the third conductive lines 121, and the fourth conductive lines 122 includes a conductive material, for example, tungsten, tantalum, titanium, nickel, platinum, tungsten nitride, tantalum nitride, or titanium nitride, etc. The materials of any two of the first conductive lines 111, the second conductive lines 112, the third conductive lines 121, and the fourth conductive lines 122 can be the same or different.

[0061] The material of the dielectric structure includes a dielectric material, for example, silicon oxide, aluminum oxide, or hafnium oxide, etc.

[0062] It should be noted that the first electrode structure, the dielectric structure and the second electrode structure can constitute a capacitor. In actual applications, one or more capacitors can be arranged in the second region according to design requirements, and the present disclosure does not limit this. For example, the capacitors can be arranged in a redundant region between the memory cell array and / or a region in which a peripheral circuit is arranged in the memory.

[0063] In the embodiments of the present disclosure, by arranging that the first electrode structure includes the first conductive line and the plurality of second conductive lines, the second electrode structure includes the third conductive line and the plurality of fourth conductive lines, and the dielectric structure is located between the first electrode structure and the second electrode structure, the first electrode structure, the dielectric structure and the second electrode structure can constitute a capacitor with a large capacitance value, which is conducive to better meeting the circuit requirements. Moreover, the level at which the second conductive line is located is the same as the level at which the word line is located or the level at which the bit line is located, and the level at which the fourth conductive line is located is the same as the level at which the second conductive line is located. The second conductive line and the fourth conductive line can be completed in the same manufacturing process as the word line or the bit line in the memory, which can reduce the probability of short circuit between the second conductive line and the fourth conductive line, control the difference of the capacitor, and thus meet the requirements of the circuit with high precision requirements on the capacitor difference.

[0064] In addition, the first electrode structure, the dielectric structure and the second electrode structure in the first semiconductor structure are all located in the second region, which can make full use of the non-array region in the first semiconductor structure without occupying the space of the second semiconductor structure. In this way, the size of the second semiconductor structure can be reduced while meeting the circuit requirements, which is conducive to improving the integration of the memory.

[0065] Further, the first semiconductor structure and the second semiconductor structure are arranged in a bonded manner, which can reduce the planar size of the memory and is conducive to further improving the integration of the memory.

[0066] In some embodiments, the memory cell array includes: a transistor, a gate of the transistor being connected with a word line; wherein, when the level at which the second conductive line is located is the same as the level at which the word line is located, the second direction is parallel to the direction in which the word line extends; the material of the word line, the material of the second conductive line and the material of the fourth conductive line are the same.

[0067] The memory includes a word line and a bit line, the word line being connected with a gate of a transistor, and the bit line being connected with a source or a drain of the transistor. A voltage is applied to the word line to control the conduction or turn-off of the transistor. The bit line is used to perform a read or write operation on an energy storage element when the transistor is turned on.

[0068] The word line is located in at least one level, and the bit line is located in at least one level. Figure 1 As shown in the first region 300a, the word line, the second conductive line 112 and the fourth conductive line 122 are all located in the same level and extend along the y direction. The bit line is located in at least one level. Figure 1The first region 300a shown in the figure, the bit line, the first conductive line 111 and the third conductive line 121 all extend along the x direction, and the bit line can be located in the same level as the first conductive line 111 and the third conductive line 121 or can be located in different levels. That is, in the present example, the second direction is parallel to the direction in which the word line extends, and the first direction is parallel to the direction in which the bit line extends.

[0069] In some embodiments, the second conductive line 112 and the fourth conductive line 122 are a single film layer, for example, the second conductive line 112 and the fourth conductive line 122 are tungsten metal. In other embodiments, the second conductive line 112 and the fourth conductive line 122 are a composite film layer, for example, referring to Figure 2a or Figure 2b As shown, the second conductive line 112 includes a first metal layer 1121 and a first adhesive layer 1122, and the fourth conductive line 122 includes a second metal layer 1221 and a second adhesive layer 1222. In a specific embodiment, the word line, the second conductive line 112 and the fourth conductive line 122 are a composite film layer of tungsten nitride-tungsten metal.

[0070] In the embodiments of the present disclosure, by setting the second conductive line, the fourth conductive line and the word line to be located in the same level, the second direction being parallel to the direction in which the word line extends, and the material of the word line, the material of the second conductive line and the material of the fourth conductive line being the same, the second conductive line, the fourth conductive line and the word line can be completed in the same manufacturing process, which can reduce the manufacturing process of the memory and save the manufacturing cost.

[0071] Further, since the second conductive line, the fourth conductive line and the word line are completed in the same manufacturing process, the probability of short circuit between the second conductive line and the fourth conductive line can be reduced, and the difference in capacitance can be controlled, thereby meeting the demand of the circuit with high precision requirement on the difference in capacitance.

[0072] In some embodiments, the spacing between adjacent second conductive lines and fourth conductive lines is the same as the spacing between adjacent word lines. It should be noted that the spacing between the two electrode plates of the capacitor manufactured in the back-end-of-line process is usually greater than the spacing between the word lines, so that the capacitor occupies a larger area and has a lower density. In the embodiments of the present disclosure, by setting the spacing between adjacent second conductive lines and fourth conductive lines to be the same as the spacing between adjacent word lines, the spacing between the second conductive line and the fourth conductive line is smaller, which can reduce the occupied area of the capacitor and is beneficial to increasing the density of the capacitor.

[0073] In some embodiments, as shown in FIG. 2c, the dielectric structure includes: a first sub-dielectric structure 131 including: a first dielectric layer 1311 between one of the two adjacent second conductive lines (e.g., the second conductive line 112a) and the fourth conductive line 122; and a second sub-dielectric structure 132 including: two second dielectric layers 1321 and a semiconductor layer 1322; wherein one of the two second dielectric layers is between the other of the two adjacent second conductive lines (e.g., the second conductive line 112b) and the semiconductor layer 1322, and the other of the two second dielectric layers 1321 is between the semiconductor layer and the fourth conductive line 122.

[0074] As shown in FIG. 2c, the first sub-dielectric structure 131 further includes an air gap 1312 in the first dielectric layer 1311, i.e. Figure 2c The first sub-dielectric structure 131 in FIG. 2c is a hollow structure. In other embodiments, the first sub-dielectric structure 131 can be a solid structure.

[0075] The material of the first dielectric layer 1311 includes: silicon oxide, silicon nitride, or silicon oxynitride, etc. In this example, the first dielectric layer 1311 is silicon oxide. The material of the second dielectric layer 1321 includes: silicon oxide, silicon nitride, or silicon oxynitride, etc. In this example, the second dielectric layer 1321 is silicon oxide. The material of the semiconductor layer 1322 includes: silicon, germanium, or silicon carbide, etc. In this example, the semiconductor layer 1322 is silicon.

[0076] It can be understood that, in this example, the first sub-dielectric structure between one of the two adjacent second conductive lines and the fourth conductive line is different from the second sub-dielectric structure between the other of the two adjacent second conductive lines and the fourth conductive line. In other embodiments, the first sub-dielectric structure between one of the two adjacent second conductive lines and the fourth conductive line can be the same as the second sub-dielectric structure between the other of the two adjacent second conductive lines and the fourth conductive line, which is not limited in the present disclosure.

[0077] In the embodiments of the present disclosure, by arranging the first sub-dielectric structure between one of the two adjacent second conductive lines and the fourth conductive line and the second sub-dielectric structure between the other of the two adjacent second conductive lines and the fourth conductive line, since the second sub-dielectric structure includes the semiconductor layer, the dielectric constant of the whole dielectric structure can be increased, which is beneficial to increase the capacitance value of the capacitor, so as to better meet the circuit requirements.

[0078] Figure 3a and Figure 3b FIG. 3c is another structural schematic diagram of a memory 300 according to the embodiments of the present disclosure, wherein, Figure 3a FIG. 3c shows the structure along the direction of the arrow in FIG. 3c. Figure 1A cross-sectional view of the memory 300 along the middle dashed line A1A1’ is shown in FIG. 3A. Figure 3b A top view of the memory 300 along the middle dashed line B1B1’ is shown in FIG. 3B. Figure 3a A top view of the memory 300 along the middle dashed line B1B1’ is shown in FIG. 3B. Figure 3a A top view of the memory 300 along the middle dashed line B1B1’ is shown in FIG. 3B. Figure 3b As shown in FIG. 3A, the source or drain of the transistor is connected to the bit line; wherein the second direction is parallel to the direction in which the bit line extends; the material of the bit line, the material of the second conductive line and the material of the fourth conductive line are the same.

[0079] The bit line is located at least in the first region 300a shown in FIG. 3A, and the bit line, the second conductive line 112 and the fourth conductive line 122 are located in the same level and extend along the x direction. The word line is located at least in the first region 300a shown in FIG. 3A, and the word line, the first conductive line 111 and the third conductive line 121 extend along the y direction, and the word line is located in a different level from the first conductive line 111 and the third conductive line 121. That is, in the present example, the second direction is parallel to the direction in which the bit line extends, and the first direction is parallel to the direction in which the word line extends. In a specific embodiment, the bit line, the second conductive line 112 and the fourth conductive line 122 are tungsten. Figure 1 Figure 1 The bit line is located at least in the first region 300a shown in FIG. 3A, and the bit line, the second conductive line 112 and the fourth conductive line 122 are located in the same level and extend along the x direction. The word line is located at least in the first region 300a shown in FIG. 3A, and the word line, the first conductive line 111 and the third conductive line 121 extend along the y direction, and the word line is located in a different level from the first conductive line 111 and the third conductive line 121. That is, in the present example, the second direction is parallel to the direction in which the bit line extends, and the first direction is parallel to the direction in which the word line extends. In a specific embodiment, the bit line, the second conductive line 112 and the fourth conductive line 122 are tungsten.

[0080] In the present example, the first direction can be represented by the y direction, the second direction can be represented by the x direction, and the z direction is perpendicular to the plane in which the x direction and the y direction lie. The x direction and the y direction intersect, and the included angle between the x direction and the y direction includes an acute angle, a right angle or an obtuse angle.

[0081] In the embodiments of the present disclosure, by arranging the second conductive line, the fourth conductive line and the bit line in the same level, the second direction being parallel to the direction in which the bit line extends, and the material of the bit line, the material of the second conductive line and the material of the fourth conductive line being the same, the second conductive line, the fourth conductive line and the bit line can be completed in the same manufacturing process, which can reduce the manufacturing process of the memory and save the manufacturing cost.

[0082] Further, since the second conductive line, the fourth conductive line and the bit line are completed in the same manufacturing process, the probability of short circuit between the second conductive line and the fourth conductive line can be reduced, and the difference in capacitance can be controlled, thereby meeting the demand of the circuit with high precision requirement on the difference in capacitance.

[0083] ​In some embodiments, the spacing between adjacent second and fourth conductive lines is the same as the spacing between adjacent bit lines. It should be noted that the spacing between the two electrode plates of a capacitor fabricated in later processes is typically greater than the spacing between bit lines, resulting in a larger capacitor area and lower density. In this embodiment, by setting the spacing between adjacent second and fourth conductive lines to be the same as the spacing between adjacent bit lines, the spacing between the second and fourth conductive lines is smaller, which reduces the capacitor's area and facilitates an increase in capacitor density.

[0084] In some embodiments, refer to Figure 2b or Figure 3b As shown, the first electrode structure 110 further includes: a first contact plug 113, located between the first conductive line 111 and the second conductive line 112; wherein, one end of the first contact plug 113 is connected to the first conductive line 111, and the other end of the first contact plug 113 is connected to the second conductive line 112; the second electrode structure 120 further includes: a second contact plug 123, located between the third conductive line 121 and the fourth conductive line 122; wherein, one end of the second contact plug 123 is connected to the third conductive line 121, and the other end of the second contact plug 123 is connected to the fourth conductive line 122.

[0085] It is understood that in this embodiment, the first contact plug 113 is located at the level between the first conductive line 111 and the second conductive line 112, and is used to connect the first conductive line 111 and the second conductive line 112. The second conductive line 112, the first contact plug 113, and the first conductive line 111 constitute one electrode plate of the capacitor. The second contact plug 123 is located at the level between the third conductive line 121 and the fourth conductive line 122, and is used to connect the third conductive line 121 and the fourth conductive line 122. The fourth conductive line 122, the second contact plug 123, and the third conductive line 121 constitute the other electrode plate of the capacitor. Here, the level where the first contact plug 113 is located is the same as the level where the second contact plug 123 is located.

[0086] In other embodiments, the first conductive line 111 can contact the second conductive line 112, that is, no contact plug needs to be provided between the first conductive line 111 and the second conductive line 112, and the first conductive line 111 and the second conductive line 112 constitute one electrode plate of the capacitor; the third conductive line 121 can contact the fourth conductive line 122, that is, no contact plug needs to be provided between the third conductive line 121 and the fourth conductive line 122, and the third conductive line 121 and the fourth conductive line 122 constitute the other electrode plate of the capacitor.

[0087] The material of the first contact plug 113 and the second contact plug 123 includes a conductive material, for example, tungsten, tantalum, titanium, nickel, platinum, aluminum, copper, tungsten nitride, tantalum nitride, or titanium nitride, etc. The material of the first contact plug 113 and the second contact plug 123 can be the same or different.

[0088] In the embodiments of the present disclosure, by arranging the first contact plug, the probability of short circuit between the first conductive line and the fourth conductive line can be reduced, by arranging the second contact plug, the probability of short circuit between the third conductive line and the second conductive line can be reduced, and thus the probability of short circuit between the first electrode structure and the second electrode structure can be reduced, and the reliability of the memory can be improved.

[0089] In some embodiments, the first semiconductor structure further includes an isolation structure located in the second region and between the first electrode structure and the memory cell array and between the second electrode structure and the memory cell array. The material of the isolation structure includes an insulating material, for example, silicon oxide or silicon nitride, etc. By arranging the isolation structure between the first electrode structure and the memory cell array and between the second electrode structure and the memory cell array, the coupling between the capacitor and the memory cell array can be reduced.

[0090] In some embodiments, the isolation structure is arranged around the first electrode structure, the second electrode structure, and the dielectric structure. It can be understood that in the present embodiment, the isolation structure is an isolation ring, which can better isolate the capacitor and the memory cell array, and further reduce the coupling between the capacitor and the memory cell array. In other embodiments, the isolation structure can also be an isolation wall.

[0091] In some embodiments, the second semiconductor structure 200 includes a peripheral circuit; the first electrode structure 110 and the second electrode structure 120 are respectively connected with the peripheral circuit; the peripheral circuit is configured to supply power to the first electrode structure 110 and the second electrode structure 120, so that the potential of the first electrode structure 110 and the potential of the second electrode structure 120 are different.

[0092] Referring to Figure 2a or Figure 3a As shown, the peripheral circuit includes a transistor 202, and the source, channel and drain of the transistor 202 are located in the substrate 201. The second semiconductor structure 200 further includes a shallow trench isolation 203, an insulating layer 204 and an interconnection structure 205, the shallow trench isolation 203 is located between two adjacent transistors 202, the insulating layer 204 covers the substrate 201 and the peripheral circuit, and the interconnection structure 205 is located in the insulating layer 204. The peripheral circuit is electrically connected with the first electrode structure 110 (for example, the first conductive line) through a part of the interconnection structure, and is electrically connected with the second electrode structure 120 (for example, the third conductive line) through another part of the interconnection structure.

[0093] In some embodiments, referring to Figure 2a or Figure 3a As shown, the memory 300 further includes a bonding structure 151 in the bonding layer 150, and the first electrode structure 110 or the second electrode structure 120 can be electrically connected to the interconnection structure 205 through the bonding structure 151. Further, an electrically conductive structure 141 is arranged between the first electrode structure 110 or the second electrode structure 120 and the bonding structure 151, as shown in Figure 2a The materials of the electrically conductive structure 141, the bonding structure 151, and the interconnection structure 205 include electrically conductive materials, such as tungsten, tantalum, titanium, nickel, platinum, aluminum, copper, tungsten nitride, tantalum nitride, or titanium nitride, etc.

[0094] It should be noted that Figure 2a or Figure 3a One bonding structure 151 shown in or

[0095] In some embodiments, referring to Figure 2b or Figure 3b As shown, the first electrode structure 110 (for example, the first electrically conductive wire 111) is connected to a first node A in the peripheral circuit, and the second electrode structure 120 (for example, the third electrically conductive wire 121) is connected to a second node B in the peripheral circuit, and the potential of the first node A and the potential of the second node B are different, for example, the first node A is grounded, and the second node B is at a positive potential; or, the second node B is grounded, and the first node A is at a positive potential.

[0096] In the embodiments of the present disclosure, by arranging the peripheral circuit in the second semiconductor structure and arranging the memory cell array in the first semiconductor structure, the peripheral circuit and the memory cell array can be connected by bonding, thereby reducing the planar size of the memory, and arranging the first electrode structure, the dielectric structure, and the second electrode structure in the non-array region of the first semiconductor structure without occupying the space of the second semiconductor structure, which can reduce the size of the second semiconductor structure while meeting the circuit requirements, and is conducive to improving the integration of the memory.

[0097] In some embodiments, referring to Figure 2a or Figure 3a As shown, the memory 300 further includes an interconnection channel 142 through which the peripheral circuit is led out to a pad. The material of the interconnection channel 142 includes an electrically conductive material, such as tungsten, tantalum, titanium, nickel, platinum, aluminum, copper, tungsten nitride, tantalum nitride, or titanium nitride, etc.

[0098] In some embodiments, the memory 300 comprises a three-dimensional memory.

[0099] In some embodiments, the three-dimensional memory comprises a dynamic random access memory, a phase change memory, a ferroelectric memory, or the like.

[0100] Figure 4 is a flowchart of a manufacturing method of a memory having a first region and a second region according to an embodiment of the present disclosure, referring to Figure 4 , the manufacturing method comprises at least the following steps:

[0101] S100: forming a memory cell array;

[0102] S200: forming a first electrode structure; wherein the first electrode structure comprises a first conductive line extending along a first direction and a plurality of second conductive lines extending along a second direction; wherein the second conductive lines are located at a same level as the word lines or the bit lines, and the second conductive lines are located at a different level from the first conductive lines; the first direction and the second direction intersect;

[0103] S300: forming a second electrode structure; wherein the second electrode structure comprises a third conductive line extending along the first direction and a plurality of fourth conductive lines extending along the second direction; wherein the fourth conductive lines are located at the same level as the second conductive lines, and the third conductive line is located at the same level as the first conductive line; the fourth conductive lines are located between two adjacent second conductive lines; the second conductive line, at an end opposite to the third conductive line, is connected to the first conductive line; the fourth conductive line, at an end opposite to the first conductive line, is connected to the third conductive line;

[0104] S400: forming a dielectric structure; wherein the dielectric structure is located between the first electrode structure and the second electrode structure;

[0105] S500: bonding the memory cell array and the second semiconductor structure; wherein the memory cell array is located in the first region and is electrically connected to the second semiconductor structure; the first electrode structure and the second electrode structure are located in the second region.

[0106] Exemplarily, in step S100, the memory cell array can be formed by thin film deposition, photolithography, etching, or the like, and the memory cell array is located in the first region 300a as shown in Figure 1 .

[0107] Exemplarily, in steps S200, S300 and S400, the first electrode structure, the second electrode structure and the dielectric structure can be formed by thin film deposition, photolithography, etching, or the like, as shown in Figure 2b or Figure 3bThe first electrode structure 110, the second electrode structure 120 and the dielectric structure 130 shown are located in Figure 1 The second region 300b shown is in the second region 300a.

[0108] Exemplarily, in step S500, a flip chip bonding process can be adopted to form the memory 300 as shown. Figure 2a or Figure 3a The memory 300 shown is electrically connected between the memory cell array and the second semiconductor structure 200 through the bonding structure 151 at the bonding interface.

[0109] In some embodiments, the step S100 includes forming a transistor, and the manufacturing method further includes forming a word line connected with a gate of the transistor; wherein the second direction is parallel to a direction in which the word line extends when the second conductive line is located in the same level as the word line; the step S200 includes forming the second conductive line when the word line is formed; the step S300 includes forming the fourth conductive line when the word line is formed; and the material of the word line, the material of the second conductive line and the material of the fourth conductive line are the same.

[0110] For example, a transistor of the memory cell array and a word line connected with a gate of the transistor can be formed in the first region of the memory, and the word line is used to control the transistor to be turned on or turned off. When the word line is formed, the second conductive line and the fourth conductive line can be formed in the second region of the memory, the second conductive line constitutes part of the first electrode structure, the fourth conductive line constitutes part of the second electrode structure, and the word line, the second conductive line and the fourth conductive line are located in the same level and extend along the y direction.

[0111] In the embodiments of the present disclosure, by setting that the second conductive line, the fourth conductive line and the word line are located in the same level, the second direction is parallel to a direction in which the word line extends, and the material of the word line, the material of the second conductive line and the material of the fourth conductive line are the same, the second conductive line, the fourth conductive line and the word line can be completed in the same manufacturing process, which can reduce the manufacturing process of the memory and save the manufacturing cost.

[0112] In some embodiments, the dielectric structure includes a first sub-dielectric structure and a second sub-dielectric structure; the dielectric structure is formed by: forming the first sub-dielectric structure between one of the two adjacent second conductive lines and the fourth conductive line; wherein the first sub-dielectric structure includes a first dielectric layer; and forming the second sub-dielectric structure between the other of the two adjacent second conductive lines and the fourth conductive line; wherein the second sub-dielectric structure includes two second dielectric layers and a semiconductor layer; one of the two second dielectric layers is located between the other of the two adjacent second conductive lines and the semiconductor layer, and the other of the two second dielectric layers is located between the semiconductor layer and the fourth conductive line.

[0113] Figures 5a to 8b This is a schematic diagram illustrating a method for manufacturing a memory according to an embodiment of this disclosure. The following will be combined with... Figure 4 , Figures 5a to 8b Further details will be provided regarding this disclosure.

[0114] First, a substrate is provided, the material of which includes semiconductor materials, such as silicon, germanium, or silicon carbide. In this example, the substrate is a silicon substrate.

[0115] Next, the substrate is etched to form a plurality of first trenches in a first region and a plurality of second trenches in a second region, the first trenches and the second trenches extending along a second direction; after etching, the substrate in the first region includes a first body portion and a plurality of first protrusions protruding from the first body portion, and the substrate in the second region includes a second body portion and a plurality of second protrusions protruding from the second body portion. Here, the first trenches and the second trenches can be formed simultaneously or sequentially, and this disclosure does not impose any limitation.

[0116] Figure 5a A top view of the second region after etching is shown. Figure 5b It shows along Figure 5a The cross-sectional view with the dashed line in the middle, refer to Figure 5a and Figure 5b As shown, the substrate 401 is etched downward along the z-direction to form a second trench 402. The bottom of the second trench 402 is located inside the substrate 401, and the second trench 402 is located between two adjacent second protrusions.

[0117] Then, a gate dielectric layer covering at least a portion of the first protrusion is formed; a second dielectric material layer covering at least a portion of the second protrusion is formed. For example, at least a portion of the first protrusion is oxidized to form the gate dielectric layer; at least a portion of the second protrusion is oxidized to form the second dielectric material layer. In this example, the gate dielectric layer and the second dielectric material layer may be oxidized simultaneously; in other examples, the gate dielectric layer and the second dielectric material layer may be formed separately, for example, using a thin-film deposition process.

[0118] Figure 6a A top view of the second region after oxidation is shown. Figure 6b It shows along Figure 6a The cross-sectional view with the dashed line in the middle, refer to Figure 6a and Figure 6b As shown, the oxidized portion forms a second dielectric material layer 404, which covers the top and part of the sidewalls of the second protrusion.

[0119] In some embodiments, before forming the gate dielectric layer, the fabrication method further comprises: forming a barrier material layer covering the first trench sidewall and bottom, and etching back to remove part of the barrier material layer to form a barrier layer at the bottom of the first trench. In an example, the barrier layer can be a single film layer, such as a silicon oxide layer or a silicon nitride layer. In another example, the barrier layer can be a composite film layer, such as the barrier layer comprising a first barrier sub-layer and a second barrier sub-layer. The barrier layer is used to electrically isolate the source or drain of the transistor from the gate, thereby reducing the leakage current of the transistor.

[0120] In actual applications, the barrier material layer covers the sidewall and bottom of the second trench at the same time, and when the barrier layer is formed at the bottom of the first trench, the barrier layer 403 is formed at the bottom of the second trench, as shown in Figure 6b The barrier layer 403 comprises a first barrier sub-layer 4031 and a second barrier sub-layer 4032, the first barrier sub-layer 4031 can be a silicon nitride layer, and the second barrier sub-layer 4032 can be a silicon oxide layer.

[0121] Next, a metal material layer covering the gate dielectric material layer is formed, and the first dielectric layer is filled into the first trench formed with the metal material layer; a metal material layer covering the second dielectric material layer is formed, and the first dielectric layer is filled into the second trench formed with the metal material layer. The metal material layer can be tungsten, and the first dielectric layer can be a silicon oxide layer.

[0122] In some embodiments, before forming the metal material layer covering the gate dielectric material layer, an adhesion material layer covering the gate dielectric material layer is formed; and before forming the metal material layer covering the second dielectric material layer, an adhesion material layer covering the second dielectric material layer is formed. The adhesion material layer can be tungsten nitride.

[0123] In actual applications, the adhesion material layer covering the gate dielectric material layer and the second dielectric material layer can be formed at the same time, the metal material layer covering the adhesion material layer is formed, and after the metal material layer is formed, the first dielectric layer is filled into the first trench and the second trench at the same time.

[0124] Figure 7a A top view of the second region after the first dielectric layer is filled is shown, Figure 7b A sectional view along the dotted line in Figure 7a is shown, and Figure 7a and Figure 7b As shown in FIGS. 4B and 4C, the second dielectric material layer 404, the adhesion material layer 405, the metal material layer 406, and the first dielectric layer 407 are sequentially arranged along the edge of the second trench 402 towards the center of the second trench 402, and the second dielectric material layer 404, the adhesion material layer 405, and the metal material layer 406 are annular.

[0125] Next, the gate dielectric material layer and the metal material layer located in the first trench are etched to form the gate dielectric layer and the gate layer (i.e., word line) of the transistor in the first trench; the second dielectric material layer and the metal material layer located in the second trench are etched to form two second dielectric layers, a second conductive line and a fourth conductive line in the second trench.

[0126] In practical applications, the gate dielectric material layer and metal material layer located in the first trench and the second dielectric material layer and metal material layer located in the second trench can be etched simultaneously. In this way, the second conductive line, the fourth conductive line and the word line can be completed in the same manufacturing process, which can reduce the number of manufacturing steps of the memory and save manufacturing costs.

[0127] Figure 8a A top view of the second region after etching the second dielectric material layer, adhesive material layer, and metal material layer is shown. Figure 8b It shows along Figure 8a A cross-sectional view with dashed lines, for example, may show the second dielectric material layer, adhesive material layer, and metal material layer etched downwards to form two opposing through-holes 408, such as... Figure 8a As shown, two through holes 408 divide the annular second dielectric material layer into two second dielectric layers, and two through holes 408 divide the annular adhesive material layer and metal material layer into a second conductive line 112 and a fourth conductive line 122. The second conductive line 112 includes a first metal layer 1121 and a first adhesive layer 1122, and the fourth conductive line 122 includes a second metal layer 1221 and a second adhesive layer 1222.

[0128] It should be noted that in this example, the two ends of the annular second dielectric material layer, adhesive material layer, and metal material layer opposite each other along the y-direction are not completely removed, and the second dielectric layer, the second conductive line, and the fourth conductive line are in a "J" shape. In other embodiments, by adjusting the size and / or position of the through-hole 408, the second dielectric layer, the second conductive line, and the fourth conductive line can be in an "L" shape or a straight line.

[0129] It is understood that the second and fourth conductive lines located in the same second trench are electrically isolated by a first sub-dielectric structure (i.e., a first dielectric layer), and the second and fourth conductive lines located in different second trenches are electrically isolated by a second sub-dielectric structure (i.e., two second dielectric layers and a second protrusion (i.e., a semiconductor layer) located between the two second dielectric layers). That is, the first sub-dielectric structure includes: a first dielectric layer located between one of the two adjacent second conductive lines and the fourth conductive line; the second sub-dielectric structure includes: two second dielectric layers and a semiconductor layer; one of the two second dielectric layers is located between the other of the two adjacent second conductive lines and the semiconductor layer, and the other of the two second dielectric layers is located between the semiconductor layer and the fourth conductive line.

[0130] In some embodiments, refer to Figure 8a and Figure 8b As shown, step S200 includes: forming a first contact plug 113; wherein the first contact plug 113 is located between the first conductive line 111 and the second conductive line 112; wherein one end of the first contact plug 113 is connected to the first conductive line 111, and the other end of the first contact plug 113 is connected to the second conductive line 112; step S300 includes: forming a second contact plug 123; wherein the second contact plug 123 is located between the third conductive line 121 and the fourth conductive line 122; wherein one end of the second contact plug 123 is connected to the third conductive line 121, and the other end of the second contact plug 123 is connected to the fourth conductive line 122.

[0131] In practical applications, when forming the word line contact plug connected to the word line, a first contact plug and a second contact plug can be formed. When forming the conductive line connected to the word line contact plug, a first conductive line and a third conductive line can be formed. The word line contact plug and the conductive line electrically connected to the word line contact plug are located in a first region, while the first contact plug, the second contact plug, the first conductive line, and the third conductive line are located in a second region.

[0132] In some embodiments, refer to Figure 8b As shown, the above fabrication method further includes forming a third sub-dielectric structure 409 in the second protrusion, wherein the third sub-dielectric structure 409 may be a silicon oxide layer. In a specific example, the third sub-dielectric structure 409 includes voids.

[0133] It should be noted that, in Figures 5a to 8b In the example shown, the second direction is parallel to the extension direction of the word line, and the first direction is parallel to the extension direction of the bit line.

[0134] In some embodiments, the above-described fabrication method further includes: forming a bit line connected to the source or drain of the transistor; wherein, when the layer where the second conductive line is located is the same as the layer where the bit line is located, the second direction is parallel to the direction in which the bit line extends; the above-described step S200 includes: forming a second conductive line when forming the bit line; the above-described step S300 includes: forming a fourth conductive line when forming the bit line; wherein, the material of the bit line, the material of the second conductive line, and the material of the fourth conductive line are the same.

[0135] For example, when forming transistors for a memory cell array in the first region, forming transistors for a memory cell array in the second region is as follows: Figure 9a and 9b The dummy transistor post 410 shown is, for example, Figure 9a A top view of the dummy transistor pillar 410 is shown. Figure 9b It shows along Figure 9a The cross-sectional view with the dashed line in the middle, refer to Figure 9a and Figure 9b As shown, multiple dummy transistor pillars 410 are arranged side by side along a first direction, and the dummy transistor pillars 410 extend along the x-direction.

[0136] For example, after forming the memory cell array, a first semiconductor structure having the memory cell array and dummy transistors formed is bonded to the substrate 500, such as... Figure 10 As shown, before bonding, an insulating layer covering the memory cell array and the dummy transistor pillars 410 can be formed, and the insulating layer can be planarized.

[0137] Exemplarily, the substrate is inverted so that the back side of the substrate faces upwards. The back side of the substrate is thinned to expose the end of the transistor and the dummy transistor pillar that is furthest from the insulating layer. The transistor is then doped to form the source or drain of the transistor. It should be noted that in practical applications, the thickness of the thinned substrate can be reasonably set according to the device requirements. For example, in some embodiments, after thinning the back side of the substrate, the end of the dummy transistor pillar that is furthest from the insulating layer may not be exposed.

[0138] For example, a bit line is formed that is connected to the source or drain of the transistor. The bit line extends along a second direction. When forming the bit line, a second conductive line and a fourth conductive line extending along the second direction are formed. Figure 11a A top view of the second region after the formation of the second and fourth conductive lines is shown. Figure 11b It shows along Figure 11a The cross-sectional view with the dashed line in the middle, refer to Figure 11a and Figure 11b As shown, the second conductive line 112 and the fourth conductive line 122 are alternately arranged along the y direction, and both the second conductive line 112 and the fourth conductive line 122 extend along the x direction.

[0139] In actual application, the insulating material layer covering the back surface of the substrate, the transistor and the dummy transistor column can be formed, and the bit line, the second conductive line and the fourth conductive line extending along the second direction can be formed in the insulating material layer through etching and thin film deposition process. In this way, the second conductive line, the fourth conductive line and the bit line can be completed in the same manufacturing process, so that the manufacturing process of the memory can be reduced, and the manufacturing cost can be saved.

[0140] In some embodiments, the step S200 includes: forming a first contact plug; wherein the first contact plug is located between the first conductive line and the second conductive line; wherein one end of the first contact plug is connected with the first conductive line, and the other end of the first contact plug is connected with the second conductive line; and the step S300 includes: forming a second contact plug; wherein the second contact plug is located between the third conductive line and the fourth conductive line; wherein one end of the second contact plug is connected with the third conductive line, and the other end of the second contact plug is connected with the fourth conductive line.

[0141] In actual application, the first contact plug and the second contact plug 123 can be formed when the bit line contact plug connected with the bit line is formed (as shown in Figure 12b The bit line contact plug and the conductive line electrically connected with the bit line contact plug are located in the first region, and the first contact plug, the second contact plug 123, the first conductive line 111 and the third conductive line 121 are located in the second region.

[0142] It should be noted that, in the example shown in Figures 9a to 12b The second direction is parallel to the extension direction of the bit line, and the first direction is parallel to the extension direction of the word line.

[0143] In some embodiments, the manufacturing method further includes:

[0144] forming an isolation structure; wherein the isolation structure is located in the second region, and is located between the first electrode structure and the memory cell array and between the second electrode structure and the memory cell array.

[0145] For example, the isolation trench penetrating through the dielectric structure is formed, the isolation trench is located between the first electrode structure and the memory cell array and between the second electrode structure and the memory cell array, the isolation material is filled into the isolation trench, and the isolation structure is formed. By forming the isolation structure between the first electrode structure and the memory cell array and between the second electrode structure and the memory cell array, the coupling between the capacitor and the memory cell array can be reduced.

[0146] In some embodiments, the second semiconductor structure includes a peripheral circuit; the step S500 includes: bonding the memory cell array and the peripheral circuit; and the manufacturing method further includes:

[0147] bonding the first electrode structure and the peripheral circuitry; wherein the first electrode structure is connected to the peripheral circuitry;

[0148] bonding the second electrode structure and the peripheral circuitry; wherein the second electrode structure is connected to the peripheral circuitry.

[0149] Exemplarily, the first electrode structure is connected to a first node in the peripheral circuitry through the first bonding structure, and the second electrode structure is connected to a second node in the peripheral circuitry through the second bonding structure, the first node and the second node have different electric potentials, for example, the first node is grounded and the second node has a positive electric potential, or the second node is grounded and the first node has a positive electric potential.

[0150] The embodiments of the present disclosure further provide a memory system, comprising:

[0151] The memory 300 in any of the above embodiments is configured to store data.

[0152] The memory controller is coupled to the memory 300 and is configured to control the memory 300.

[0153] The memory system can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality device, an augmented reality device, or any other suitable electronic device with a memory.

[0154] The memory controller can control the logical operation of the memory 300, that is, the memory 300 can perform one or more logical operations, such as a programming operation or a reading operation, under the control of the memory. The memory controller can send command signals, address signals, and data signals to the memory 300 through the input / output interface. The memory controller and the memory 300 can be integrated in a semiconductor device such as a solid state drive (SSD), and can also be integrated in a semiconductor device such as a memory card.

[0155] In some embodiments, the memory system further comprises:

[0156] The host is coupled to the memory controller and is configured to send or receive data.

[0157] The host can be a processor (for example, a central processing unit or a system on chip (for example, an application processor)) of an electronic device. The host can be configured to send data to the memory. Alternatively, the host can be configured to receive data from the memory.

[0158] The above merely provides the specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A memory, comprising: The memory has a first region and a second region, and includes a first semiconductor structure and a second semiconductor structure which are bonded together; The first semiconductor structure includes: a memory cell array located in the first region and connected with the second semiconductor structure; a first electrode structure located in the second region and including: a first conductive line extending in a first direction and a plurality of second conductive lines extending in a second direction; wherein a level at which the second conductive lines are located is the same as a level at which word lines of the first semiconductor structure are located or a level at which bit lines of the first semiconductor structure are located, and the level at which the second conductive lines are located is different from a level at which the first conductive line is located; the first direction and the second direction intersect; a second electrode structure located in the second region and including: a third conductive line extending in the first direction and a plurality of fourth conductive lines extending in the second direction; wherein a level at which the fourth conductive lines are located is the same as a level at which the second conductive lines are located, and a level at which the third conductive line is located is the same as a level at which the first conductive line is located; the fourth conductive lines are located between two adjacent second conductive lines; the second conductive lines are connected with the first conductive line at an end opposite to the third conductive line; and the fourth conductive lines are connected with the third conductive line at an end opposite to the first conductive line; a dielectric structure located between the first electrode structure and the second electrode structure.

2. The memory of claim 1, wherein, The memory cell array includes: a transistor whose gate is connected with the word line; wherein when the level at which the second conductive lines are located is the same as the level at which the word lines are located, the second direction is parallel to a direction in which the word lines extend; and a material of the word lines, a material of the second conductive lines and a material of the fourth conductive lines are the same.

3. The memory of claim 2, wherein, A spacing between adjacent second conductive lines and fourth conductive lines is the same as a spacing between adjacent word lines.

4. The memory of claim 2, wherein, The dielectric structure includes: a first sub-dielectric structure including: a first dielectric layer located between one of two adjacent second conductive lines and the fourth conductive line; a second sub-dielectric structure including: two second dielectric layers and a semiconductor layer; wherein one of the two second dielectric layers is located between the other of the two adjacent second conductive lines and the semiconductor layer, and the other of the two second dielectric layers is located between the semiconductor layer and the fourth conductive line.

5. The memory of claim 1, wherein, The memory cell array includes: a transistor whose source or drain is connected with the bit line; wherein when the level at which the second conductive lines are located is the same as the level at which the bit lines are located, the second direction is parallel to a direction in which the bit lines extend; and a material of the bit lines, a material of the second conductive lines and a material of the fourth conductive lines are the same.

6. The memory of claim 5, wherein, A spacing between adjacent second conductive lines and fourth conductive lines is the same as a spacing between adjacent bit lines.

7. The memory of claim 1, wherein, The first electrode structure further includes: A first contact plug is located between the first conductive line and the second conductive line; one end of the first contact plug is connected with the first conductive line, and the other end of the first contact plug is connected with the second conductive line. The second electrode structure further comprises: A second contact plug is located between the third conductive line and the fourth conductive line; one end of the second contact plug is connected with the third conductive line, and the other end of the second contact plug is connected with the fourth conductive line.

8. The memory of claim 1, wherein, The first semiconductor structure further comprises: an isolation structure located in the second region and located between the first electrode structure and the memory cell array and between the second electrode structure and the memory cell array.

9. The memory of claim 8, wherein, The isolation structure is arranged around the first electrode structure, the second electrode structure and the dielectric structure.

10. The memory of claim 1, wherein, The second semiconductor structure comprises a peripheral circuit; wherein the first electrode structure and the second electrode structure are respectively connected with the peripheral circuit.

11. The memory of claim 1, wherein, The memory comprises a dynamic random access memory.

12. A method of fabricating a memory, comprising: The memory has a first region and a second region, and the manufacturing method comprises: forming a memory cell array; forming a first electrode structure; wherein the first electrode structure comprises a first conductive line extending in a first direction and a plurality of second conductive lines extending in a second direction; wherein the level at which the second conductive lines are located is the same as the level at which word lines are located or the level at which bit lines are located, and the level at which the second conductive lines are located is different from the level at which the first conductive lines are located; the first direction and the second direction intersect; forming a second electrode structure; wherein the second electrode structure comprises a third conductive line extending in the first direction and a plurality of fourth conductive lines extending in the second direction; wherein the level at which the fourth conductive lines are located is the same as the level at which the second conductive lines are located, and the level at which the third conductive lines are located is the same as the level at which the first conductive lines are located; the fourth conductive lines are located between two adjacent second conductive lines; the second conductive lines are connected with the first conductive lines at an end relatively far away from the third conductive lines; and the fourth conductive lines are connected with the third conductive lines at an end relatively far away from the first conductive lines; forming a dielectric structure; wherein the dielectric structure is located between the first electrode structure and the second electrode structure; bonding the memory cell array and a second semiconductor structure; wherein the memory cell array is located in the first region and connected with the second semiconductor structure; the first electrode structure and the second electrode structure are located in the second region.

13. The method of manufacturing according to claim 12, wherein, The forming of the memory cell array comprises: forming a transistor; The manufacturing method further comprises: forming the word line connected with the gate of the transistor; wherein when the level at which the second conductive lines are located is the same as the level at which the word lines are located, the second direction is parallel to the direction in which the word lines extend; The forming of the first electrode structure comprises: forming the second conductive lines when the word lines are formed; The forming of the second electrode structure comprises: The fourth conductive line is formed when the word line is formed; wherein the material of the word line, the material of the second conductive line and the material of the fourth conductive line are the same.

14. The method of manufacturing according to claim 13, wherein, The dielectric structure comprises: a first sub-dielectric structure and a second sub-dielectric structure; The forming of the dielectric structure comprises: The first sub-dielectric structure is formed between one of the two adjacent second conductive lines and the fourth conductive line; wherein the first sub-dielectric structure comprises a first dielectric layer; The second sub-dielectric structure is formed between the other of the two adjacent second conductive lines and the fourth conductive line; wherein the second sub-dielectric structure comprises two second dielectric layers and a semiconductor layer; one of the two second dielectric layers is located between the other of the two adjacent second conductive lines and the semiconductor layer, and the other of the two second dielectric layers is located between the semiconductor layer and the fourth conductive line.

15. The method of manufacturing of claim 12, wherein, The forming of the memory cell array comprises: forming a transistor; The manufacturing method further comprises: The bit line is formed in connection with the source or the drain of the transistor; wherein when the level at which the second conductive line is located is the same as the level at which the bit line is located, the second direction is parallel to the direction in which the bit line extends; The forming of the first electrode structure comprises: The second conductive line is formed when the bit line is formed; The forming of the second electrode structure comprises: The fourth conductive line is formed when the bit line is formed; wherein the material of the bit line, the material of the second conductive line and the material of the fourth conductive line are the same.

16. The method of manufacturing of claim 12, wherein, The forming of the first electrode structure comprises: A first contact plug is formed; wherein the first contact plug is located between the first conductive line and the second conductive line; wherein one end of the first contact plug is connected with the first conductive line, and the other end of the first contact plug is connected with the second conductive line; The forming of the second electrode structure comprises: A second contact plug is formed; wherein the second contact plug is located between the third conductive line and the fourth conductive line; wherein one end of the second contact plug is connected with the third conductive line, and the other end of the second contact plug is connected with the fourth conductive line.

17. The method of manufacturing of claim 12, wherein, The manufacturing method further comprises: An isolation structure is formed; wherein the isolation structure is located in the second region, and is located between the first electrode structure and the memory cell array and between the second electrode structure and the memory cell array.

18. The method of manufacturing of claim 12, wherein, The second semiconductor structure comprises a peripheral circuit; The bonding of the memory cell array and the second semiconductor structure comprises: bonding the memory cell array and the peripheral circuit; The manufacturing method further comprises: The first electrode structure is bonded with the peripheral circuit; wherein the first electrode structure is connected with the peripheral circuit; The second electrode structure is bonded with the peripheral circuit; wherein the second electrode structure is connected with the peripheral circuit.

19. A memory system, comprising: It comprises: The memory as claimed in any one of claims 1 to 11 is configured to store data; A memory controller is coupled to the memory and configured to control the memory.

20. The memory system of claim 19, wherein, The memory system also includes: a host coupled to the memory controller configured to send or receive the data.

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