Satellite position synchronization determination method, receiver and computer readable storage medium

Abstract

Embodiments of the present application relate to the field of navigation positioning, and disclose a satellite bit synchronization determination method, a receiver and a computer readable storage medium. The method comprises: acquiring a binary data stream broadcast by a satellite; intercepting N-bit data in the binary data stream through a sliding window with a length of N; obtaining an integral result corresponding to the N-bit data in the sliding window when the sliding window slides to a position; the integral result comprises a first integral result and a second integral result, the first integral result is obtained by integrating the result of multiplying the N-bit data and first pattern data corresponding to the satellite bit by bit, and the second integral result is obtained by integrating the result of multiplying the N-bit data and second pattern data corresponding to the satellite bit by bit; and determining whether bit synchronization is successful according to the integral result, so that bit synchronization can be accurately realized, thereby improving the accuracy of GNSS positioning.

Description

Technical Field

[0001] This invention relates to the field of navigation and positioning, and in particular to a method for determining satellite position synchronization, a receiver, and a computer-readable storage medium. Background Technology

[0002] With the development of mobile technology, the positioning function of Global Navigation Satellite System (GNSS) has become widespread in applications such as mobile phones, smart wearables, smart logistics, shared bicycles, and locators, becoming an essential function in market products.

[0003] Bit synchronization, also known as bit synchronization, is the process by which a receiver determines the position of a received satellite signal within the data bits of the satellite's broadcast message, thereby identifying the start edge position of the received satellite signal message bits. Bit synchronization is one of the key steps in satellite positioning. If a bit synchronization error occurs, the time in the satellite signal observations will deviate by milliseconds. In GNSS positioning, a 1ms error can lead to a positioning deviation of 300km. Therefore, accurate bit synchronization is crucial for GNSS positioning. Summary of the Invention

[0004] The purpose of this invention is to provide a method for determining satellite bit synchronization, a receiver, and a computer-readable storage medium, so as to accurately achieve bit synchronization and thereby improve the accuracy of GNSS positioning.

[0005] To address the aforementioned technical problems, embodiments of the present invention provide a method for determining satellite bit synchronization, applied to a receiver, comprising: acquiring a binary data stream broadcast by a satellite; extracting N bits of data from the binary data stream through a sliding window of length N; acquiring an integration result corresponding to the N bits of data within the sliding window at each position; wherein the integration result includes a first integration result and a second integration result, the first integration result being the result obtained by integrating the N bits of data with a first mode data corresponding to the satellite bitwise, the first mode data being N bits of binary data, and the first N / 2 bits being the same as the last N / 2 bits; the second integration result being the result obtained by integrating the N bits of data with a second mode data corresponding to the satellite bitwise, the second mode data being N bits of binary data, and the first N / 2 bits being the opposite of the last N / 2 bits; and determining whether bit synchronization is successful based on the integration result.

[0006] An embodiment of the present invention also provides a receiver, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the satellite bit synchronization determination method described above.

[0007] Embodiments of the present invention also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the above-described method for determining satellite bit synchronization.

[0008] In this embodiment of the invention, a binary data stream broadcast by a satellite is acquired, and a sliding window of length N slides through the binary data stream. At each position the window slides to, the integration result corresponding to the N bits of data within the window is acquired. The integration result includes a first integration result and a second integration result. The first integration result is the result obtained by integrating the N bits of data with the first mode data corresponding to the satellite, where the first mode data is N bits of binary data, and the first N / 2 bits are the same as the last N / 2 bits. The second integration result is the result obtained by integrating the N bits of data with the second mode data corresponding to the satellite, where the second mode data is N bits of binary data, and the first N / 2 bits are opposites of the last N / 2 bits. Based on the integration results, it is determined whether bit synchronization is successful. This embodiment of the invention performs double integration on the N bits of data within the sliding window, employing a sliding window double integration method. This overcomes the influence of noise, ensuring accurate and rapid bit synchronization under strong signal conditions, thereby improving the accuracy of GNSS positioning.

[0009] Furthermore, determining whether bit synchronization is successful based on the integration result includes: for each integration result obtained, determining whether the currently obtained integration result is a valid peak value among all obtained integration results; wherein, the absolute value of the valid peak value is greater than a preset threshold, and when the integration result is a first integration result, the valid peak value is the peak value among all obtained first integration results, and when the integration result is a second integration result, the valid peak value is the peak value among all obtained second integration results; recording the first occurrence number of the valid peak value; and determining that bit synchronization is successful when the first occurrence number is greater than a first preset occurrence number.

[0010] Furthermore, the step of determining whether each acquired integration result is a valid peak value among all acquired integration results includes: storing each acquired integration result in an array; wherein the array includes a first array and a second array, the first array being used to store the first integration result, and the second array being used to store the second integration result; determining whether the first integration result currently stored in the first array is a valid peak value within the first array, or determining whether the second integration result currently stored in the second array is a valid peak value within the second array. Using two arrays allows for the orderly storage of the results of integrating N bits of data within the sliding window with the data from the two modes bit-by-bit, facilitating accurate identification of valid peak values ​​during the sliding window process, thereby facilitating the subsequent determination of whether bit synchronization was successful.

[0011] In addition, each integration result has a corresponding number in the array, which represents the order in which the integration results are stored in the array; after confirming successful bit synchronization, the method further includes: determining the number corresponding to the maximum integration result, and taking the modulo N / 2 of the number corresponding to the maximum integration result to obtain an integer k; using k as the data bit edge deviation. This invention provides a method for determining data bit edge deviation, which accurately determines whether bit synchronization is successful while facilitating the acquisition of the data bit edge deviation.

[0012] In addition, during the sliding process of the sliding window, the method further includes: recording the second number of times the sliding window slides; if the second number is greater than or equal to the second preset number and the bit synchronization has not yet been determined to be successful, then the bit synchronization is determined to be unsuccessful; if the second number is less than the second preset number and the bit synchronization has not yet been determined to be successful, then the sliding window is controlled to slide backward one position.

[0013] In addition, after the determination of bit synchronization failure, the method further includes: resetting the N-bit data in the sliding window, the second number of sliding window slides, the array and the first number of slides, and restarting the determination process of satellite bit synchronization until bit synchronization is successful or the signal is lost, to prevent bit synchronization from failing to be completed effectively for too long.

[0014] Furthermore, N = 20n, where n is an integer greater than or equal to 2. A larger n results in greater improvement in the reliability of weak signal bit synchronization and higher bit synchronization sensitivity. Attached Figure Description

[0015] One or more embodiments are illustrated by way of example with reference to the accompanying drawings, and these illustrative descriptions do not constitute a limitation on the embodiments.

[0016] Figure 1This is a flowchart of a method for determining satellite position synchronization in an embodiment of the present invention;

[0017] Figure 2 This is a flowchart illustrating the implementation of step 102 in this embodiment of the invention;

[0018] Figure 3 This is a flowchart illustrating the implementation of step 103 in this embodiment of the invention;

[0019] Figure 4 This is another flowchart of the satellite position synchronization determination method in the embodiments of the present invention;

[0020] Figure 5 This is a schematic diagram of 220 Stream units in a coordinate system under an ideal, noise-free condition in an embodiment of the present invention;

[0021] Figure 6 This is a schematic diagram of the result of integrating the 40-bit data in the sliding window with P0 and P1 under ideal conditions in an embodiment of the present invention.

[0022] Figure 7 This is a schematic diagram of the peak coordinates in the integral result of multiplying 40 bits of data in the sliding window with P0 and P1 bit by bit in an ideal case according to an embodiment of the present invention.

[0023] Figure 8 This is a schematic diagram showing some abnormal jumps in the Stream unit in the embodiment of the present invention;

[0024] Figure 9 This is a schematic diagram of 220 Stream units in the coordinate system under noise interference conditions in an embodiment of the present invention;

[0025] Figure 10 This is a schematic diagram of the result of integrating the 40-bit data in the sliding window with P0 and P1 respectively under noise interference in an embodiment of the present invention.

[0026] Figure 11 This is a schematic diagram of the peak coordinates in the result of integrating the 40-bit data in the sliding window with P0 and P1 respectively under noise interference in an embodiment of the present invention.

[0027] Figure 12 This is a schematic diagram of the result of integrating 60 bits of data in the sliding window with P0 and P1 bitwise under noise interference in an embodiment of the present invention.

[0028] Figure 13 This is a schematic diagram of the peak coordinates in the result of integrating the 60-bit data in the sliding window with P0 and P1 respectively under noise interference in an embodiment of the present invention.

[0029] Figure 14 This is a schematic diagram illustrating the increased noise interference in an embodiment of the present invention, resulting in more abnormal transitions in the 220 Stream units output by the carrier ring.

[0030] Figure 15 This is a schematic diagram of 220 Stream units in the coordinate system under increased noise interference in an embodiment of the present invention;

[0031] Figure 16 This is a schematic diagram of the result of integrating the 40-bit data in the sliding window with P0 and P1 under increased noise interference in an embodiment of the present invention.

[0032] Figure 17 This is a schematic diagram of the result of bitwise multiplication and integration using a 60-bit pattern and 60 bits of data within a sliding window under conditions of increased noise interference in an embodiment of the present invention.

[0033] Figure 18 This is a schematic diagram of the receiver in an embodiment of the present invention. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details are presented in the various embodiments of the present invention to facilitate a better understanding of this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments. The division of the various embodiments below is for ease of description and should not constitute any limitation on the specific implementation of the present invention. The various embodiments can be combined with and referenced by each other without contradiction.

[0035] Bit synchronization, also known as bit synchronization, is used by the receiver to determine the position of a received satellite signal within the data bits of the satellite's broadcast message, thereby determining the starting edge position of the received satellite signal's data bits. When the receiver begins tracking a satellite signal, the carrier loop outputs a binary data stream unit (recorded as 1 and -1) with a code rate of 1 kHz. Since the data bit rate of GPS L1C / A and BeiDou D1 signals is 50 Hz, one data bit contains 20 stream units. Under ideal noise-free conditions, the 20 stream units within one data bit remain unchanged (all 1s or all -1s). When the data bit changes, the stream units will transition at the bit boundaries. Bit synchronization is used to find the correct position of the data bit boundaries within the stream.

[0036] Bit synchronization is a crucial step in satellite positioning, serving the following purposes: accurately acquiring the 1-20ms portion of the satellite signal transmission time, laying the foundation for pseudorange observation extraction; demodulating navigation message data bits to obtain the satellite's transmitted navigation message; after frame synchronization, combining phase and bit synchronization information to assemble a complete satellite signal observation measurement for PVT calculation; and enabling longer coherent integration, providing lower noise and higher sensitivity for the tracking loop. A bit synchronization error can cause millisecond-level time deviations in satellite signal observations. In GNSS positioning, a 1ms error can lead to a 300km positioning deviation; therefore, accurate bit synchronization is essential for GNSS positioning.

[0037] Ideally, a transition between two adjacent 1-millisecond-wide Stream units indicates the discovery of a message bit edge. However, due to ubiquitous noise, in most real-world scenarios, the download loop cannot correctly demodulate all Stream unit levels. This can lead to one or more abnormal transitions within the 20ms corresponding to a message bit. If bit edges are determined solely from Stream unit level transitions, it can result in bit synchronization errors, especially under weak GNSS signal conditions, where multiple abnormal random transitions in the Stream unit level are possible. Therefore, bit synchronization algorithms must overcome the influence of noise.

[0038] The embodiments of this invention relate to a method for determining satellite position synchronization, which can be applied to the determination of position synchronization for various satellites, such as BeiDou satellites and GPS satellites. This embodiment employs a sliding window dual-integration method, which can overcome the influence of noise, ensuring accurate and rapid position synchronization under strong signal conditions, while also significantly improving the reliability of position synchronization under weak signal conditions and increasing the sensitivity of position synchronization.

[0039] The flowchart of the satellite position synchronization determination method in this embodiment is as follows: Figure 1 As shown, it includes:

[0040] Step 101: Obtain the binary data stream broadcast by the satellite.

[0041] Step 102: Use a sliding window of length N to slide in the binary data stream. Every time the sliding window slides to a position, obtain the integral result corresponding to the N bits of data in the sliding window.

[0042] Step 103: Determine whether bit synchronization was successful based on the integration result.

[0043] The following is a detailed explanation of the implementation details of the satellite position synchronization determination method in this embodiment. The following content is only for the convenience of understanding and is not necessary for implementing this solution.

[0044] In step 101, the receiver can acquire the binary data stream broadcast by the satellite from the carrier ring. The binary data stream output by the carrier ring can be denoted as Stream, with a code rate of 1 kHz. The basic unit of Stream can be denoted as Streamunit, with 1 bit unit lasting 1 ms and a value of -1 or 1.

[0045] In some implementations, the binary data stream broadcast by the satellite can be the binary data stream broadcast by the BeiDou satellite. Under normal circumstances, the binary data stream can be represented as: { 1, 1, 1, 1, 1,-1, 1, 1,-1,-1,-1, 1,-1,1,-1, 1, 1,-1,-1,-1, 1}.

[0046] In some implementations, the binary data stream broadcast by the satellite can be a binary data stream broadcast by a GPS satellite, which can normally be represented as: {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}.

[0047] In step 102, the integration result includes a first integration result and a second integration result. The first integration result is obtained by integrating N-bit data and the first mode data corresponding to the satellite, where the first mode data is N-bit binary data and the first N / 2 bits are the same as the last N / 2 bits. The second integration result is obtained by integrating N-bit data and the second mode data corresponding to the satellite, where the second mode data is N-bit binary data and the first N / 2 bits are opposites of the last N / 2 bits. The first and second mode data are used to detect BIT edge transitions.

[0048] In this embodiment, the length of the sliding window, the length of the first mode data, and the length of the second mode data are all the same. In this embodiment, the length can be understood as the number of bits in binary data. N can be determined based on the duration t of one message bit, for example, N = tn, where n is an even number greater than or equal to 2. For example, when t = 20ms, N can be 40, i.e., N = 2 × 20. However, in specific implementations, N can also be greater than 40; this embodiment does not specifically limit this.

[0049] In some implementations, the binary data stream broadcast by the satellite is a 20ms binary data stream broadcast by the BeiDou satellite. This 20ms binary data stream consists of the following 20 bits: {1, 1, 1, 1, 1, -1, 1, 1, -1, -1, 1, -1, 1, -1, -1, -1, -1, 1}. N = 20 × 2 = 40. Under the above conditions, the first mode data (P0) and the second mode data (P1) can be represented as follows:

[0050] P0={1,1,1,1,1,-1,1,1,-1,-1,1,-1,1,-1,1,1,-1,-1,-1,1,1,1,1,1,1,-1,1,1,-1,-1,1,-1,1,-1,1,1,-1,-1,-1,1}

[0051] P1={1,1,1,1,1,-1,1,1,-1,-1,1,-1,1,-1,1,1,-1,-1,-1,1,-1,-1,-1,-1,-1,1,-1,-1,1,1,-1,1,-1,1,-1,-1,1,1,1,-1}.

[0052] In some implementations, the binary data stream broadcast by the satellite is a 20ms binary data stream broadcast by Global Positioning System (GPS) satellites. This 20ms binary data stream consists of the following 20 bits: {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}. N = 20 × 2 = 40. Under the above conditions, the first mode data, represented by P0, and the second mode data, represented by P1, can be expressed as follows:

[0053] P0={ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}

[0054] P1={1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1}.

[0055] As can be seen from the above implementation, the first 20 and last 20 bits of P0 are the same, that is, the 21st bit of P0 is the same as the 1st bit, the 22nd bit of P0 is the same as the 2nd bit, the 23rd bit of P0 is the same as the 3rd bit, and the 40th bit of P0 is the same as the 20th bit. In other words, the i-th bit of P0 is the same as the (i+N / 2)-th bit, where 1 ≤ i ≤ N / 2. The first 20 and last 20 bits of P1 are opposites of each other, that is, the 21st bit of P1 is the opposite of the 1st bit, the 22nd bit of P1 is the opposite of the 2nd bit, the 23rd bit of P1 is the opposite of the 3rd bit, and the 40th bit of P1 is the opposite of the 20th bit. In other words, the i-th bit of P1 is the opposite of the (i+N / 2)-th bit, or the (i+N / 2)-th bit of P1 is obtained by inverting the i-th bit, where 1 ≤ i ≤ N / 2. Taking t=20 and N=40 as an example, P0 and P1 can be determined based on the 20ms binary data stream broadcast by the satellite. For example, the first 20 bits of P0 and P1 are the same as the content of the 20ms binary data stream broadcast by the satellite.

[0056] In some implementations, step 102 can be implemented as follows: Figure 2 As shown, it includes:

[0057] Step 1021: Each time the sliding window is slid to a position, obtain N bits of data within the sliding window.

[0058] Step 1022: Multiply the N-bit data in the sliding window with the first mode data P0 corresponding to the satellite bit by bit and then integrate to obtain the first integral result.

[0059] Step 1023: Multiply the N-bit data in the sliding window with the second mode data P1 corresponding to the satellite bit by bit and then integrate to obtain the second integral result.

[0060] The above integration after multiplying by each digit can be understood as: multiplying by each digit and then adding them together. To facilitate understanding of this process, a specific example is given below:

[0061] Suppose the binary data stream (Stream) obtained from the carrier ring broadcast by the satellite is:

[0062] D={ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,

[0063] 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,

[0064] -1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1}

[0065] D consists of 40 ones and 20 ones. The sliding window length N (taking 40 as an example) is the same as the length of the pattern (including P0 and P1). After using the sliding window to extract the data from 1 to 40 in D, the 40 bits of data within the sliding window are as follows:

[0066] WD={1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,

[0067] 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}

[0068] When both P0 and P1 are patterns corresponding to GPS satellites, P0 and P1 can be represented as follows:

[0069] P0={ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}

[0070] P1={1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1}

[0071] The first integral result obtained by multiplying the 40-bit data WD and P0 bit by bit and then integrating is 40, and the second integral result obtained by multiplying WD and P1 bit by bit is 0.

[0072] Moving the sliding window one position forward yields the current 40 bits of data within the window, which is the truncation of bits 2 to 41 from D as follows:

[0073] WD={1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,

[0074] 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1-1}

[0075] The first integral result obtained by multiplying the 40 bits of data in the current sliding window with P0 bit by bit is 38. The second integral result obtained by multiplying the 40 bits of data in the current sliding window with P1 bit by bit is 2.

[0076] Similarly, as the carrier ring collects more Stream data, the sliding window moves backward continuously, and the number of first and second integral results obtained by multiplying the N bits of data captured by the sliding window with P0 and P1 will increase.

[0077] In step 103, the success of bit synchronization is determined based on the integration results. The integration results include the first integration result and the second integration result described above.

[0078] In this embodiment, when a message bit transition occurs, if P0 or P1 is perfectly aligned with the transition position, the integration result will become the maximum peak value (ideally, this maximum peak value is 40 when the length of P0 and P1 is 40). As the sliding window moves towards the direction of the bit transition, the number of misalignments usually decreases gradually at first, and the integration result increases accordingly. When there is a perfect match, i.e., P0 or P1 is exactly the same as the 40 bits of data within the sliding window, the integration result becomes the maximum, forming a peak value. Subsequently, as the sliding window moves away from the bit transition position, the number of misalignments gradually increases, and the integration result decreases accordingly. The maximum peak value found at this point contains bit synchronization information. Therefore, in this embodiment, the maximum peak value can be determined from the acquired integration results (i.e., the first integration results and the second integration results). The maximum value of the integration result can also be called the maximum integration result. The maximum integration result is used to determine whether bit synchronization is successful.

[0079] In some implementations, the method of implementing step 103 can be found in [reference needed]. Figure 3 ,include:

[0080] Step 1031: For each integral result obtained, determine whether the currently obtained integral result is a valid peak value among all the obtained integral results. If yes, proceed to step 1032; otherwise, continue executing step 1031.

[0081] Step 1032: Record the first number of valid peak occurrences.

[0082] Step 1033: When the first count is greater than the first preset number of times, the bit synchronization is confirmed to be successful.

[0083] In step 1031, if the absolute value of the effective peak value is greater than a preset threshold, the effective peak value is the peak value among all the acquired first integration results when the integration result is a first integration result, and the effective peak value is the peak value among all the acquired second integration results when the integration result is a second integration result. In this embodiment, each time the sliding window slides one position, two integration calculations are performed to obtain two integration results, namely the first integration result and the second integration result mentioned above. During the sliding window process, several first integration results and several second integration results are calculated. If the currently acquired first integration result is the peak value among all the acquired first integration results, and the absolute value of the peak value is greater than the preset threshold, then the currently acquired first integration result is a effective peak value. If the currently acquired second integration result is the peak value among all the acquired second integration results, and the absolute value of the peak value is greater than the preset threshold, then the currently acquired second integration result is a effective peak value. If the currently acquired first integration result is not the peak value among all the acquired first integration results, and the currently acquired second integration result is not the peak value among all the acquired second integration results, then step 1031 is continued to be executed to judge the newly acquired integration result.

[0084] The preset threshold can be set according to actual needs, and its specific value can be referenced to the signal strength setting.

[0085] In the specific implementation, it can be first determined whether the currently acquired first integral result is the peak value among all the previously acquired first integral results. If so, it is then determined whether the absolute value of the peak value is greater than a preset threshold. If so, the currently acquired first integral result is determined to be a valid peak value. For the currently acquired second integral result, a similar judgment is made as for the first integral result to finally determine whether the currently acquired second integral result is a valid peak value. If yes, step 1032 is executed; otherwise, step 1031 is executed to judge the newly acquired integral result.

[0086] In step 1032, the first occurrence of a valid peak value is recorded. That is, each time a valid peak value is determined in step 1031, it is recorded once. For example, if a valid peak value appears once in each of the first integral results, it is recorded once; if a valid peak value appears once in each of the second integral results, it is recorded again.

[0087] In some implementations, an array BitPos can be pre-set to store the first count, and the value in the array BitPos is incremented by 1 each time a valid peak occurs.

[0088] In step 1033, when the first count is greater than the first preset number, it is determined that bit synchronization is successful. The first preset number can be set according to actual needs, and this embodiment does not impose a specific limitation on it.

[0089] In some implementations, step 1031 can be implemented as follows: for each integration result obtained, the integration result is stored in an array; wherein the array includes a first array and a second array, the first array is used to store the first integration result, and the second array is used to store the second integration result; it is determined whether the first integration result currently stored in the first array is a valid peak value in the first array, or it is determined whether the second integration result currently stored in the second array is a valid peak value in the second array.

[0090] For example, let's denote the first array as S0 and the second array as S1. After a sliding window extracts the Stream data collected from the carrier ring, the first integral result obtained by multiplying it bitwise with P0 and then integrating is stored in array S0. After a sliding window extracts the Stream data collected from the carrier ring, the second integral result obtained by multiplying it bitwise with P1 and then integrating is stored in array S1. As the carrier ring continues to provide Stream data for sliding window multiplication and integration, the integration results in S0 and S1 gradually accumulate, meaning the number of integration results in S0 and S1 gradually increases.

[0091] Referring to the specific example of integrating by bitwise multiplication above, the first integral result obtained by integrating the 40-bit data WD and P0 within the sliding window is 40, and the second integral result obtained by integrating the 40-bit data WD and P1 is 0. These two values ​​are stored in arrays S0 and S1 respectively, resulting in S0={40} and S1={0}. After the sliding window moves one position to the right, the first integral result obtained by integrating the 40-bit data WD and P0 within the sliding window is 38, and the second integral result obtained by integrating the 40-bit data WD and P1 is 2. These two values ​​are stored in arrays S0 and S1 respectively, resulting in S0={40, 38} and S1={0, 2}. As the sliding window moves, each time it moves one position to the right, a value is added to arrays S0 and S1. Each time a first integral result is stored in array S0, a check is performed to determine whether the first integral result stored in S0 is a valid peak value within S0. Each time a second integral result is stored in array S1, a check is performed to determine whether the second integral result currently stored in S1 is a valid peak value within S1.

[0092] In the specific implementation, recording the first occurrence of a valid peak can be understood as: recording the sum of the number of times a valid peak occurs in S0 and the number of times a valid peak occurs in S1.

[0093] In some implementations, each integration result is assigned a number in an array, which indicates the order in which the integration results are stored in the array. When the first number is greater than a first preset number, the method for determining satellite bit synchronization further includes: determining the number corresponding to the effective peak value, and taking the modulo N / 2 of the number corresponding to the effective peak value to obtain an integer k; using k as the data bit edge deviation. For example, S1={0,2}, assuming 2 is the current effective peak value in S1, the number corresponding to the value 0 in S1 is 1, and the number corresponding to the value 2 is 2, assuming N=40, then the number k can be obtained by taking the modulo 20 of the number 2 corresponding to the effective peak value.

[0094] In some embodiments, during the sliding window process, the method further includes: recording a second number of sliding window movements; if the second number is greater than or equal to a second preset number and the bit synchronization has not yet been determined to be successful, then the bit synchronization is determined to have failed; if the second number is less than the second preset number and the bit synchronization has not yet been determined to be successful, then the sliding window is controlled to slide backward one position. The second preset number can be set according to actual needs, and this embodiment does not specifically limit it.

[0095] In some implementations, after determining that bit synchronization has failed, the process further includes: resetting the N-bit data within the sliding window, the second number of sliding window moves, the array, and the first number, and restarting the satellite bit synchronization determination process until bit synchronization is successful or the signal is lost. Resetting the N-bit data within the sliding window can be understood as: moving the sliding window and re-capturing N bits of data. Resetting the second number of sliding window moves can be understood as clearing the second number to 0, i.e., restarting the calculation of the number of sliding window moves. Resetting the array can be understood as: clearing the array. Resetting the first number can be understood as clearing the first number to 0, i.e., restarting the process of accumulating the maximum integral result greater than a preset threshold; signal loss refers to satellite signal loss.

[0096] In this embodiment, to prevent the inability to effectively complete bit synchronization for an excessively long period of time, a preset threshold number of sliding window attempts, namely a second preset number of attempts, WN, is established. When the number of sliding window attempts (the second number) is less than or equal to WN, the bit synchronization process continues. If bit synchronization is still not completed when the number of sliding window attempts is greater than or equal to WN, the bit synchronization is considered to have failed, and D, wcnt, S0, S1, and BitPos are reset. Bit synchronization restarts, and this process is repeated until bit synchronization is successful or the signal is lost.

[0097] In some implementations, for ease of description, the following terms are defined:

[0098] Stream: The binary data stream output by the carrier ring, with a bit rate of 1 kHz.

[0099] Stream unit: The basic unit of a Stream. One unit lasts for 1ms and has a value of -1 or 1.

[0100] BIT: Navigation message data bit, with a code rate of 50Hz. One message BIT lasts for 20ms and consists of 20-bit stream units.

[0101] Window: A sliding window that extracts a pre-defined number of units from a Stream for subsequent operations. Each time the window slides, it moves one Stream unit backward.

[0102] Pattern: The pattern definition for detecting bit edges, multiplied by the integral of the stream data captured by the sliding window.

[0103] BitPos: An array of 20 elements that counts potential bit synchronization position information.

[0104] S0 / S1: Save the result of the integral of the Stream captured by the sliding window and the Pattern, which is used to find the peak value, i.e. the maximum integral result.

[0105] Peak value: The value of an element in S0 and S1, where the value of the element is greater than or equal to the values ​​of the elements before and after it.

[0106] SN: Predetermined threshold for effective peak value (the specific value is related to signal strength).

[0107] Valid peak value: The peak value of S0 or S1 that is greater than or equal to SN.

[0108] BN: A predetermined threshold for the number of times the bit synchronization position occurs. When BitPos[k] is greater than or equal to BN, k is the bit synchronization result.

[0109] WN: A predetermined threshold for the number of sliding window operations, used to reset the bit synchronization algorithm when it is detected that bit synchronization cannot be effectively completed for an extended period of time.

[0110] Based on the definitions of the above terms, a flowchart for the method of determining satellite position synchronization can be found in [reference needed]. Figure 4 ,include:

[0111] Step 401: Obtain Stream data from the carrier ring.

[0112] Step 402: Determine whether the number of times the sliding window has slid, wcnt, is less than the sliding window threshold, WN; if yes, proceed to step 403; otherwise, proceed to step 409. Here, the number of times the sliding window has slid, wcnt, has the same meaning as the second number mentioned above, and WN has the same meaning as the second preset number mentioned above.

[0113] Step 403: Increment the sliding window count wcnt, and extract the data WD within the sliding window from the Stream based on the sliding window.

[0114] Step 404: Multiply WD bitwise with P0 and P1 respectively, integrate the results and save them into arrays S0 and S1.

[0115] Step 405: Determine whether there is a new peak value in S0 and S1 that is greater than or equal to SN; if so, proceed to step 406; otherwise, proceed to step 401. This step can also be understood as determining whether there is a new valid peak value in S0 and S1, where SN is the aforementioned preset threshold.

[0116] Step 406: Divide the index corresponding to the peak value by 20 to obtain the integer k, and increment the BitPos[k] counter value by 1. Here, BitPos[k] can be understood as the array used to store the first count mentioned above. 20 represents the duration of one message bit; if the duration of one message bit is not 20, 20 can be any other value. The index corresponding to the peak value can be understood as the number of the peak value in the array mentioned above.

[0117] Step 407: Determine whether BitPos[k] is greater than or equal to BN; if yes, proceed to step 408, otherwise proceed to step 401.

[0118] Step 408: Bit synchronization successful, k is determined to be the message bit edge offset.

[0119] Step 409: Reset D, wcnt, S0, S1, BitPos.

[0120] To facilitate understanding of this implementation method, specific examples are provided below:

[0121] In some implementations, the ideal noise-free situation is equivalent to the actual strong signal situation. WN=180, SN=20, BN=4, P0 and P1 lengths are 40, the sliding window length is 40, and the carrier ring output is as follows: 220 Stream units. According to the Stream unit data and bit synchronization rules, position 19 is the bit synchronization position. The starting position of the message BIT is the position 19 after the position index modulo 20 in the Stream, that is, the 19th, 39th, 59th...219th, etc.

[0122] D={1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 ,1,1,1,1,1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1, -1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1 -1,-1,-1,-1,-1,-1,-1,-1,-1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,1,1,1,1,1 ,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,-1,-1}

[0123] A schematic diagram of the 220 Stream units in the coordinate system under ideal noise-free conditions can be found in [reference needed]. Figure 5 After extracting the Stream data using a sliding window and multiplying it bitwise by P0 and P1, the result is integrated and stored in S0 and S1, as shown below. Figure 6 As shown, Figure 6 This is a schematic diagram illustrating the result of integrating the 40-bit data within the sliding window with P0 and P1 bitwise under ideal conditions. From Figure 6 As can be seen, under ideal conditions, the graph is relatively regular, and all peaks that satisfy the condition that the absolute value is greater than or equal to SN(20) are valid peaks, and the coordinates are labeled as follows: Figure 7 , Figure 7 This is a schematic diagram of the peak coordinates in the integral of the result after multiplying 40 bits of data within the sliding window by P0 and P1 bit by bit under ideal conditions. Figure 7In the diagram, the black boxes represent the valid peak points and their coordinates. The valid peak points appear at (19,40), (39,-40), (59,40), (79,-40), (99,-40), (119,40), (139,-40), (159,40), and (179,-40). After modulo 20 on their corresponding index coordinates (i.e., the subscripts corresponding to the peak points), they all equal 19. BitPos

[19] is accumulated to 9, which is greater than or equal to the bit synchronization threshold BN(4). Therefore, it can be determined that position 19 in the Stream is the starting position of the message BIT. In fact, when the 4th valid peak point (79,-40) is obtained, BitPos

[19] is accumulated to 4. At this time, BitPos

[19] >=BN, and it can be determined that the bit synchronization is successful. There is no need to perform subsequent sliding window integration processing.

[0124] In some implementations, noise interference is added to the theoretical data, equivalent to a medium or weak signal situation in reality. While keeping WN, SN, BN, P0 / P1, and the sliding window length unchanged, position 19 in the 220 stream units of the carrier loop output remains the true bit synchronization position. Due to the noise interference, some abnormal transitions occur in the stream unit. (Refer to...) Figure 8 , Figure 8 The underlined positions indicate the locations where abnormal transitions occur. A diagram of these 220 Stream units can be found in [reference needed]. Figure 9 , Figure 9 This is a schematic diagram of 220 Stream units in the coordinate system under noise interference. After truncating the Stream data with a sliding window and multiplying it bitwise by P0 and P1, the result is integrated and stored in S0 and S1, as shown below. Figure 10 As shown, Figure 10 This is a schematic diagram showing the result of integrating the 40-bit data within the sliding window with P0 and P1 bit by bit under noise interference. From... Figure 10 As can be seen, the graph is quite messy under noisy conditions. All peaks that satisfy the condition that the absolute value is greater than or equal to SN(20) are valid peaks, and the coordinates are labeled as follows. Figure 11 , Figure 11 This is a schematic diagram of the peak coordinates in the result of integrating the 40-bit data in the sliding window with P0 and P1 bit by bit under noise interference. Figure 11In the diagram, the black boxes represent the valid peak points and their coordinates. The valid peak points appear at (19,22), (39,-26), (59,26), (72,-20), (79,-22), (92,-20), (99,-20), (119,24), (139,-20), (159,24), and (179,-32). After modulo 20 on their corresponding index coordinates, BitPos

[19] is accumulated to 9, BitPos

[12] is accumulated to 2, and BitPos

[19] is greater than or equal to BN(4). Therefore, it can be determined that position 19 in the Stream is the starting position of the message BIT. In fact, when the 5th valid peak point (79,-22) is obtained, BitPos

[19] is accumulated to 4. At this time, BitPos

[19] >=BN, and it can be determined that the bit synchronization is successful. No further sliding window integration processing is needed.

[0125] In some implementations, for weak signals, the Pattern can be increased from 40 bits to 60 bits or two more bits (multiples of 20), and the sliding window length can also be increased to 60 or a corresponding length, without changing the algorithm processing flow. In this case, using the Pattern to detect the flipping of three consecutive data bits is equivalent to increasing the relevant integration time, which can further improve the success rate of lower-level synchronization for weak signals. For example, P0 and P1 can be represented as follows:

[0126] P0={ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}

[0127] P1={ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1, -1,-1,-1,-1,-1,-1,-1,-1,-1,-1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}

[0128] Using the Stream from the noise interference example above, keeping BN (==4) constant, set WN=160, SN=30, P0 / P1 length to 60, and sliding window length to 60. Extract the Stream data through the sliding window, multiply it by P0 and P1, integrate the result, and store it in S0 and S1. Figure 12 As shown, Figure 12 This diagram illustrates the result of integrating the 60-bit data within the sliding window with P0 and P1 bitwise, under noise interference. From... Figure 12 As can be seen, some peak values ​​have increased significantly. All peak values ​​that satisfy the condition that the absolute value is greater than or equal to SN (==30) are considered valid peak values, and their coordinates are indicated as follows: Figure 13 . Figure 13 This is a schematic diagram of the peak coordinates in the result of integrating the 60-bit data in the sliding window with P0 and P1 bit by bit under noise interference. Figure 13 In the diagram, the black boxes represent the valid peak points and their coordinates. The valid peak points appear at (19,36), (39,-38), (99,-34), (119,30), (139,-38), and (159,38). After modulo 20 on their corresponding index coordinates, BitPos

[19] is accumulated to 6. The previously incorrect position 12 is filtered out, and the statistically obtained bit synchronization position is more accurate. BitPos

[19] is greater than or equal to BN (==4), so it can be determined that position 19 in the Stream is the starting position of the message BIT. In fact, when the 4th valid peak point (119,30) is obtained, BitPos

[19] is accumulated to 4. At this time, BitPos

[19] >=BN, so it can be determined that the bit synchronization is successful and no further sliding window integration processing is needed.

[0129] As can be seen from the above examples, under the same noise interference, increasing the length of the pattern and the sliding window can improve the accuracy of bit synchronization.

[0130] In some implementations, further increasing noise interference is equivalent to further weakening the signal. The impact of the increased pattern and sliding window on sensitivity is observed. Based on the original noisy data, with 19 still representing the true bit synchronization position, increasing noise interference results in more abnormal transitions in the 220 stream units output by the carrier loop. (Refer to...) Figure 14 , Figure 14 Compared to Figure 8 The location of the added abnormal transition is Figure 14 The bolded and underlined area is shown in the diagram. For a schematic representation of the 220 Stream units in the coordinate system under increased noise interference, please refer to [reference needed]. Figure 15 The Stream data is extracted through a sliding window of length 40, multiplied bitwise by P0 and P1, and then integrated. The result is stored in S0 and S1, as shown below. Figure 16 As shown, Figure 16 A schematic diagram illustrating the result of integrating the 40-bit data within the sliding window with P0 and P1 bitwise under conditions of increased noise interference. From... Figure 16 As can be seen, there are multiple valid peak values ​​that satisfy the condition of being greater than or equal to the threshold SN (==20), such as Figure 16In addition to the points in the Chinese box that have a value of 19 after modulo 20, there are also many valid peak points scattered in other locations. These valid peak points can interfere with the bit synchronization judgment and even cause misjudgment.

[0131] The result of performing a bitwise multiplication integration using a 60-bit pattern and 60 bits of data within a sliding window is as follows: Figure 17 As shown: when the threshold SN is increased to 30, a large number of invalid peaks are filtered out, and the positions of the valid peaks are all 19 after modulo 20, thus avoiding or reducing the possibility of misjudgment.

[0132] Therefore, increasing the pattern and sliding window length can effectively improve the sensitivity of the bit synchronization process, but at the cost of requiring more time to collect longer stream units and waiting for a scenario with three consecutive bit transitions, which will increase the bit synchronization time.

[0133] As can be seen from the above analysis, the embodiments of the present invention can quickly and accurately complete bit synchronization under strong and medium signals, and improve the accuracy and sensitivity of bit synchronization under weak signals by increasing the pattern length and sliding window length.

[0134] As can be seen from the above examples, the bit synchronization determination method in the embodiments of the present invention can quickly and accurately complete bit synchronization under strong and medium signal conditions. Under weak signal conditions, the accuracy and sensitivity of bit synchronization can be improved by increasing the pattern length and sliding window length, thereby shortening the first positioning time, improving positioning reliability, and enhancing user experience.

[0135] It should be noted that the examples described above in this embodiment are merely illustrative for ease of understanding and do not constitute a limitation on the technical solution of the present invention.

[0136] The steps of the various methods described above are only for clarity. In practice, they can be combined into one step or some steps can be split into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this patent. Adding insignificant modifications or introducing insignificant designs to the algorithm or process, but without changing the core design of the algorithm and process, are also within the scope of protection of this patent.

[0137] Embodiments of the present invention relate to a receiver, such as... Figure 18 As shown, it includes at least one processor 501; and a memory 502 communicatively connected to at least one processor 501; wherein the memory 502 stores instructions executable by at least one processor 501, the instructions being executed by at least one processor 501 to enable at least one processor 501 to perform the satellite bit synchronization determination method in the above embodiment.

[0138] The memory 502 and processor 501 are connected via a bus, which can include any number of interconnecting buses and bridges. The bus connects various circuits of one or more processors 501 and memory 502 together. The bus can also connect various other circuits, such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further herein. A bus interface provides an interface between the bus and the transceiver. The transceiver can be a single element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by processor 501 is transmitted over a wireless medium via an antenna, which further receives data and transmits it to processor 501.

[0139] Processor 501 is responsible for managing the bus and general processing, and can also provide various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory 502 can be used to store data used by processor 501 during operation.

[0140] This invention relates to a computer-readable storage medium storing a computer program. When executed by a processor, the computer program implements the above-described method embodiments.

[0141] That is, those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. This program is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0142] Those skilled in the art will understand that the above embodiments are specific examples of implementing the present invention, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the present invention.

Claims

1. A method of determining the position of a satellite, characterized in that The method is applied to a receiver, and comprises the following steps: acquiring a binary data stream broadcast by a satellite; sliding a sliding window with a length of N in the binary data stream, and acquiring an integral result corresponding to N-bit data in the sliding window every time the sliding window slides to a position; wherein the integral result comprises a first integral result and a second integral result, the first integral result is an integral result obtained by multiplying the N-bit data by first pattern data corresponding to the satellite bit by bit, the first pattern data is binary data with N bits, and the first N / 2 bits are the same as the last N / 2 bits; the second integral result is an integral result obtained by multiplying the N-bit data by second pattern data corresponding to the satellite bit by bit, the second pattern data is binary data with N bits, and the first N / 2 bits are the opposite of the last N / 2 bits; determining whether bit synchronization is successful according to the integral result; the step of determining whether bit synchronization is successful according to the integral result comprises the following steps: judging whether the integral result currently acquired is an effective peak value in the integral results acquired every time the integral result is acquired; wherein the absolute value of the effective peak value is greater than or equal to a preset threshold, in the case that the integral result is the first integral result, the effective peak value is a peak value in the first integral results acquired, and in the case that the integral result is the second integral result, the effective peak value is a peak value in the second integral results acquired; recording a first number of times when the effective peak value appears; the recording of the first number of times when the effective peak value appears is recording the sum of the number of times when the effective peak value appears in the first integral result and the number of times when the effective peak value appears in the second integral result; determining that bit synchronization is successful when the first number of times is greater than a first preset number of times.

2. The method of claim 1, wherein, the step of judging whether the integral result currently acquired is an effective peak value in the integral results acquired every time the integral result is acquired comprises the following steps: storing the integral result in an array every time the integral result is acquired; wherein the array comprises a first array and a second array, the first array is used for storing the first integral result, and the second array is used for storing the second integral result; judging whether the first integral result currently stored in the first array is an effective peak value in the first array, or judging whether the second integral result currently stored in the second array is an effective peak value in the second array.

3. The method of claim 2, wherein the satellite position is determined by: each integral result has a number corresponding to the integral result in the array, and the number is used for representing the order in which the integral result is stored in the array; when the first number of times is greater than the first preset number of times, the method further comprises the following steps: determining the number corresponding to the effective peak value, and obtaining an integer k after the number corresponding to the effective peak value is taken modulo N / 2; taking the k as a data bit edge deviation.

4. The method according to any one of claims 1 to 3, characterized in that, in the process of sliding the sliding window, the method further comprises the following steps: recording a second number of times when the sliding window slides; determining that bit synchronization fails when the second number of times is greater than or equal to a second preset number of times and bit synchronization has not been determined to be successful; controlling the sliding window to slide backward by one bit when the second number of times is less than the second preset number of times and bit synchronization has not been determined to be successful.

5. The method of claim 4, wherein, After the determination of the bit synchronization fails, further comprising: resetting the N-bit data in the sliding window, the second number of times of sliding of the sliding window, the array and the first number of times, and restarting the determination process of the satellite bit synchronization until the bit synchronization succeeds or the signal is lost.

6. The method of claim 1 to 2, characterized in that, The N = tn, wherein n is an even number greater than or equal to 2, and t is the duration of one bit of the navigation message.

7. The method of claim 1, wherein, In the case that the satellite is a GPS satellite, the first pattern data P0 and the second pattern data P1 are as follows respectively: P0={ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1} P1={1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1} In the case that the satellite is a Beidou satellite, the first pattern data P0 and the second pattern data P1 are as follows respectively: P0={1,1,1,1,1,-1,1,1,-1,-1,1,-1,1,-1,1,1,-1,-1,-1,1,1,1,1,1,1,-1,1,1,-1,-1,1,-1,1,-1,1,1,-1,-1,-1,1} P1={1,1,1,1,1,-1,1,1,-1,-1,1,-1,1,-1,1,1,-1,-1,-1,1,-1,-1,-1,-1,-1,1,-1,-1,1,1,-1,1,-1,1,-1,-1,1,1,1, -1}。 8. A receiver, characterized by comprising: at least one processor; and a memory in communication with the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method for determining bit synchronization of a satellite according to any one of claims 1 to 7.

9. A computer readable storage medium storing a computer program, characterized in that, The computer program is executed by the processor to implement the method for determining bit synchronization of a satellite according to any one of claims 1 to 7.

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