A server and an axi interconnect device and method thereof

Abstract

The application discloses a server and an AXI interconnection device and method thereof, applied to the technical field of device interconnection, and comprises a decoder configured to receive and parse a sideband signal transmitted by a first device; an internal router connected with the first device and at least two second devices through an AXI bus, configured to determine an operation object of the first device according to a parsing result, receive operation content transmitted by the first device and send the operation content to the operation object for execution, and feed back feedback information to the first device; and an arbitrator connected with the first device and at least two third devices through the AXI bus, configured to send, in an arbitration manner, operation content transmitted by any one of the third devices to the first device for execution, and feed back feedback information of the first device to the third device. The application can realize AXI interconnection, has a simple structure, and can avoid the problems of large chip area occupation, resource and space waste.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of device interconnection technology, in particular to a server and an AXI interconnection device and method thereof. BACKGROUND

[0002] At present, the on-chip bus of SoC (System on Chip) is still in the development stage, and is not as mature as the bus of microcomputer. At present, there is no unified standard, so various manufacturers and organizations have introduced their own standards in order to occupy a place in the future on-chip bus standard of SoC. ARM Company introduced its own bus: AMBA (Advanced Microcontroller Bus Architecture) in 1995. It is independent of the processor and manufacturing technology, and enhances the reusability of peripherals and system macro cells in various applications, and is very suitable for the requirements of modern large-scale integrated circuit design automation.

[0003] A new bus: AXI (Advanced Extensible Interface) is added in AMBA 3.0. It is an on-chip bus oriented to high performance, high bandwidth and low delay. Its address / control and data phases are separated, it supports unaligned data transmission, and only the first address is needed in burst transmission. In addition, it uses a separate read / write data channel design, supports significant transmission access and out-of-order access. It can be seen that AXI is a new high-performance protocol in AMBA. AXI technology enriches the existing AMBA standard content, and can meet the needs of super high performance and complex SoC design

[0004] From the above, it can be seen that the AXI protocol is strictly a point-to-point master-slave interface protocol. When multiple peripherals need to interact with each other, we need to add an AXI Interconnect module, that is, an AXI interconnection matrix. Please refer to Figure 1 , which is a schematic diagram of AXI Interconnect interconnection. The function of AXI Interconnect is to provide a switching mechanism for connecting one or more AXI master devices to one or more AXI slave devices. This function is similar to the switching matrix in a switch. Some AXI Interconnect IP cores currently available can support up to 16 master devices and 16 slave devices. The IP core can be configured, that is, several masters and several slaves can be selected according to the specific use, and if more interfaces are needed, several IP cores can be added.

[0005] The AXI Interconnect is in the form of an IP core at present, and its internal structure is not open to the outside, so that the technology adopted in the internal structure cannot be known. Moreover, the AXI Interconnect in the form of an IP core is too complex in function, when we only use the basic function, the whole IP core needs to be added, which leads to the chip area being too large, the power consumption being high, and some functions of the IP core not being used, resulting in the waste of resources and space.

[0006] In summary, how to effectively realize the AXI interconnection of the device and avoid the chip area being too large, the waste of resources and space is a technical problem to be solved by the technical personnel in the field at present. SUMMARY

[0007] The purpose of the present application is to provide a server and an AXI interconnection device and method thereof, so as to effectively realize the AXI interconnection of the device and avoid the chip area being too large, the waste of resources and space.

[0008] To solve the above technical problems, the present application provides the following technical solutions:

[0009] An AXI interconnection device comprises:

[0010] A decoder connected with a first device and an internal router, used for receiving a sideband signal sent by the first device and sending a parsing result to the internal router;

[0011] The internal router connected with the first device and at least two second devices through an AXI bus, used for determining the operation object of the first device from each of the second devices according to the received parsing result, receiving operation content sent by the first device and sending to the operation object, so that the operation object executes the received operation content, and the feedback information of the operation object is fed back to the first device;

[0012] An arbitrator connected with the first device and at least two third devices through an AXI bus, used for sending the received operation content sent by any one of the third devices to the first device in an arbitration manner, so that the first device executes the received operation content, and the feedback information of the first device is fed back to the third device.

[0013] Preferably, the second device connected with the internal router through the AXI bus comprises an MCTP device, and the MCTP device simultaneously serves as a third device and is connected with the arbitrator.

[0014] Preferably, the third device connected to the arbiter through the AXI bus comprises an ARM device, and a read data channel of the AXI bus between the ARM device and the arbiter is directly connected to a read data channel of the AXI bus between the first device and the arbiter; a read address channel of the AXI bus between the ARM device and the arbiter is directly connected to a read address channel of the AXI bus between the first device and the arbiter.

[0015] Preferably, the second device connected to the internal router through the AXI bus further comprises a VGA device, a first BMC, and a second BMC redundant to the first BMC.

[0016] Preferably, the decoder is further configured to:

[0017] After receiving the sideband signal sent by the first device, store the sideband signal;

[0018] When receiving the retransmission instruction sent by the internal router, re-analyze the sideband signal and send the analysis result to the internal router.

[0019] Preferably, the arbiter is configured to send, in an arbitration manner, any one of the operation contents sent by the third devices to the first device, so that the first device executes the received operation content, comprising:

[0020] When the arbiter receives write requests sent by only one third device at the same time, the arbiter receives the operation content sent by the third device and sends the operation content to the first device, so that the first device executes the received operation content.

[0021] When the arbiter receives write requests sent by at least two third devices at the same time, the arbiter receives the operation content sent by the third device with the highest priority and sends the operation content to the first device, so that the first device executes the received operation content.

[0022] Preferably, the internal router receives the operation content sent by the first device and sends the operation content to the operation object, so that the operation object executes the received operation content, comprising:

[0023] When the first device performs a write operation, the internal router receives the operation content in the order of write address before write data, and sends the received operation content to the operation object in the order of write address before write data, so that the operation object executes the received operation content.

[0024] Preferably, when the first device performs a write operation, the internal router receives operation content in the order of write address before write data, and sends the received operation content to the operation object in the order of write address before write data, so that the operation object executes the received operation content, including:

[0025] When the first device performs a write operation, the internal router controls the write address ready signal of the AXI bus between the first device to be low after receiving the write address, and controls the write data ready signal of the AXI bus between the first device to switch from low to high;

[0026] The internal router sends the received write data to the operation object to make the operation object execute the received operation content after determining that the write address is completely sent to the operation object after receiving the write data;

[0027] After receiving the feedback information sent by the operation object indicating write completion, the write address ready signal of the AXI bus between the first device is controlled to be high.

[0028] An AXI interconnection method, comprising:

[0029] The decoder connected with the first device and the internal router receives the sideband signal sent by the first device and sends the analysis result to the internal router;

[0030] The internal router connected with the first device and at least two second devices through the AXI bus determines the operation object of the first device from each of the second devices according to the received analysis result;

[0031] The internal router receives the operation content sent by the first device and sends it to the operation object, so that the operation object executes the received operation content, and feeds back the feedback information of the operation object to the first device;

[0032] The arbitrator connected with the first device and at least two third devices through the AXI bus sends the received operation content of any one of the third devices to the first device through arbitration, so that the first device executes the received operation content, and feeds back the feedback information of the first device to the third device.

[0033] A server comprising the AXI interconnection device as described above.

[0034] With the technical solution provided by the embodiment of the application, the decoder connected with the first device and the internal router is arranged to receive the sideband signal sent by the first device and send the analysis result to the internal router. Therefore, the internal router can determine the operation object of the first device from the second devices according to the received analysis result, and the internal router can receive the operation content sent by the first device through the AXI bus and send the operation content to the operation object so that the operation object executes the received operation content, and the feedback information of the operation object is fed back to the first device. It can be seen that the decoder and the internal router of the application realize the read and write of the first device to any one of the second devices, that is, the decoder and the internal router of the application realize the AXI connection between the first device as the master device and the second devices.

[0035] The arbitrator is connected with the first device and at least two third devices through the AXI bus, and can send the received operation content sent by any one of the third devices to the first device through arbitration, so that the first device executes the received operation content, and the feedback information of the first device is fed back to the third device. It can be seen that the arbitrator of the application realizes the read and write of any third device to the first device, that is, the arbitrator of the application realizes the AXI connection between the first device as the slave device and the third devices.

[0036] The application scheme does not need to use the AXI Interconnect in the form of the IP core of the traditional scheme, but only needs to pass through the decoder, the internal router and the arbitrator to realize the AXI connection between the first device as the master device and the second devices, and the AXI connection between the first device as the slave device and the third devices. The structure of the decoder, the internal router and the arbitrator is simple and has high reliability, and can avoid the problems of large chip area, waste of resources and space. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only some embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0038] Figure 1 It is a structural schematic diagram of an AXI interconnection device in the application;

[0039] Figure 2 It is a structural schematic diagram of an AXI interconnection device in a specific embodiment of the application;

[0040] Figure 3 An implementation flowchart of an AXI interconnection method in the present application. DETAILED DESCRIPTION

[0041] The core of the present application is to provide an AXI interconnection device, which is simple in structure and can avoid the problems of large chip area occupation, resource and space waste.

[0042] In order to enable personnel in the art to better understand the present application, the present application will be further described in detail below in combination with the drawings and specific embodiments. Obviously, the described embodiments are only some of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0043] Please refer to Figure 1 , Figure 1 An AXI interconnection device in the present application, which can include:

[0044] A decoder 10 connected with the first device and the internal router 20, used for receiving the sideband signal sent by the first device and sending the analysis result to the internal router 20;

[0045] An internal router 20 connected with the first device and at least two second devices through the AXI bus, used for determining the operation object of the first device this time from each second device according to the received analysis result, receiving the operation content sent by the first device and sending it to the operation object, so that the operation object executes the received operation content, and feeds back the feedback information of the operation object to the first device;

[0046] An arbitrator 30 connected with the first device and at least two third devices through the AXI bus, used for sending the operation content received from any one of the third devices to the first device in an arbitration manner, so that the first device executes the received operation content, and feeds back the feedback information of the first device to the third device.

[0047] Specifically, in the scheme of the present application, the decoder 10 is connected with the first device, and by receiving and analyzing the sideband signal sent by the first device, the data transmission direction this time can be determined, that is, the sideband signal carries the direction information of data transmission, according to which it can be determined which second device the first device needs to operate this time. After obtaining the analysis result by analyzing the sideband signal, the decoder 10 needs to send the analysis result to the internal router 20.

[0048] Of course, in one embodiment, the decoder 10 can be configured to resend the parsing result to the internal router 20, in consideration of the fact that, for example, the communication is interfered, the internal router 20 finds that the parsing result is incorrect after receiving the parsing result, and the like. That is, in one embodiment of the present application, the decoder 10 can also be configured to:

[0049] After receiving the sideband signal sent by the first device, the sideband signal is stored;

[0050] When the retransmission instruction sent by the internal router 20 is received, the sideband signal is parsed again and the parsing result is sent to the internal router 20.

[0051] In this embodiment, in order to resend the parsing result, after receiving the sideband signal sent by the first device, the sideband signal is not only parsed, but also stored. When the retransmission instruction sent by the internal router 20 is received, it indicates that the previously transmitted parsing result has a problem, for example, the internal router 20 receives an incomplete or incorrect parsing result, and sends a retransmission instruction to the decoder 10, so that the decoder 10 can use the stored sideband signal to parse the sideband signal again and send the parsing result to the internal router 20.

[0052] It should be noted that in this embodiment, the storage is not the parsing result, but the sideband signal. This is because the error may be caused by the parsing process, so by storing the sideband signal and re-parsing, such situations can be handled, which is beneficial to further guarantee the reliability of the scheme. In addition, it can be understood that in actual application, a deletion mechanism can be set, for example, the stored sideband signal is periodically deleted to avoid the situation that the storage space is exhausted. Of course, other types of deletion mechanisms can also be set in other occasions, which does not affect the implementation of the present application.

[0053] In addition, the specific communication protocol used by the decoder 10 to connect with the first device can be various, as long as the transmission of the sideband signal can be effectively realized.

[0054] The internal router 20 of the present application is connected with the first device and at least two second devices through an AXI bus, that is, whether the communication between the internal router 20 and the first device or the communication between the internal router 20 and any one of the second devices conforms to the AXI protocol rule.

[0055] Since the internal router 20 can determine the operation object of the first device from the respective second devices according to the received resolution result, i.e., determine which second device needs to be read / written by the first device this time, after receiving the operation content sent by the first device based on the AXI protocol, the operation content can be sent to the operation object based on the AXI protocol, so that the operation object executes the received operation content, and finally, the feedback information of the operation object can be fed back to the first device based on the AXI protocol. It can be understood that based on the AXI protocol, when the read operation is performed, the feedback information of the operation object is the specific read data content, and when the write operation is performed, the feedback information of the operation object is sent through the write response channel in the AXI bus.

[0056] In one specific embodiment of the present application, the internal router 20 receives the operation content sent by the first device and sends it to the operation object, so that the operation object executes the received operation content, which specifically includes:

[0057] When the first device performs the write operation, the internal router 20 receives the operation content in the order of write address first and write data, and sends the received operation content to the operation object in the order of write address first and write data, so that the operation object executes the received operation content.

[0058] The AXI protocol stipulates that the write data can be earlier than the write address or later than the write address, and in this embodiment, the implementation of the write data later than the write address, i.e., the order of address first and data, is selected for the functional design of the internal router 20, which is relatively simple and convenient to implement and has high reliability.

[0059] Further, in one specific embodiment of the present application, when the first device performs the write operation, the internal router 20 receives the operation content in the order of write address first and write data, and sends the received operation content to the operation object in the order of write address first and write data, so that the operation object executes the received operation content, which specifically includes:

[0060] When the first device performs the write operation, the internal router 20 controls the write address ready signal of the AXI bus between the first device to be low after the write address is received, and controls the write data ready signal of the AXI bus between the first device to be switched from low to high;

[0061] After the internal router 20 receives the write data, when it is determined that the write address is completely sent to the operation object, the received write data is sent to the operation object to make the operation object execute the received operation content;

[0062] After receiving the feedback information sent by the operation object and indicating the write completion, the control controls the write address ready signal of the AXI bus between the control and the first device to be high.

[0063] Specifically, the process of the write operation on the first device is described in detail in this embodiment, and the purpose of address preceding data is effectively achieved.

[0064] In the address receiving stage, the internal router 20 can determine the operation object of the first device in this time through the received analysis result, so as to Figure 2 For example, the operation object of the first device in this time is determined as the VGA (Video Graphics Array) device.

[0065] In the process of receiving the write address, the write data ready signal of the AXI bus between the internal router 20 and the first device is kept low, so that the receiving of the write address is performed first. When the receiving of the write address is completed, the write data ready signal of the AXI bus between the internal router 20 and the first device is switched from low to high, so as to allow the receiving of the write data.

[0066] In addition, after the receiving of the write address is completed, the internal router 20 controls the write address ready signal of the AXI bus between the internal router 20 and the first device to be low, so as to temporarily prohibit the first device from issuing a new write address.

[0067] After the receiving of the write data is completed, there are different cases. For example, the operation object determined in this time is the VGA device, that is, the received write address may have been transmitted to the VGA device, may not have been transmitted to the VGA device, or a part of the write address is currently transmitted. In order to ensure that the write address precedes the write data, the internal router 20 needs to determine whether the write address is completely transmitted to the operation object after the receiving of the write data is completed. Only when it is determined that the write address is completely transmitted to the operation object, the internal router 20 will transmit the received write data to the operation object.

[0068] There are many ways to determine whether the write address is completely transmitted to the operation object. Generally, the last signal can be used to determine. If the last data of the write address is transmitted to the VGA device, the last signal of the AXI bus between the internal router 20 and the VGA device is high, indicating that the write address is completely transmitted to the operation object.

[0069] The write data ready signal of the AXI bus between the internal router 20 and the VGA device can be set to low before the write address is completely sent, and the write data ready signal of the AXI bus between the internal router 20 and the VGA device can be set to high after it is determined that the write address has been completely sent, to allow the sending of write data.

[0070] After the operation object receives the operation content, in this example, the VGA device receives the write address and the write data, the data write operation can be performed, and after the execution is completed, the feedback information indicating the write completion sent by the internal router 20 to the first device, the internal router 20 will further feed back the feedback information to the first device, and at the same time, the internal router 20 can pull up the write address ready signal of the AXI bus between the internal router 20 and the first device to allow the first device to transmit the next write address.

[0071] In the above embodiment, the process of the write operation of the first device is specifically described, and the purpose of the write address preceding the write data is effectively achieved.

[0072] The AXI bus includes 5 channels: read address (read address channel), write address (write address channel), read data (read data channel), write data (write data channel), and write response (write response channel), so that the read operation and the write operation are independent and do not affect each other, that is, the read operation can be performed at the same time when the write operation is performed.

[0073] The first device performs the read operation, similar to the process of the write operation, but there is no separate response channel, because the data read by the first device can be regarded as the feedback of the second device. And the read data must be after the read address, because only after the read address is sent, the read data feedback by the operation object can be received, so there is no need to specially consider the sequence of the read data and the read address.

[0074] In a specific embodiment of the present application, the arbitrator 30 is configured to send any one of the operation contents sent by the third device to the first device in an arbitration manner, so that the first device executes the received operation content, and can specifically include:

[0075] When the arbitrator 30 receives only one write request sent by the third device at the same time, the operation content sent by the third device is received and sent to the first device, so that the first device executes the received operation content;

[0076] At the same time, when the arbitrator 30 receives at least two write requests from third devices, it sends the operation content sent by the third device with the highest priority to the first device so that the first device can execute the received operation content.

[0077] Arbitrator 30 needs to determine which third device is currently accessing the first device through arbitration. A commonly used arbitration method is to arbitrate based on the order of triggering time and in combination with priority.

[0078] That is, if the arbitrator 30 receives only one write request from a third device at any given time, it can receive the operation content sent by the third device and send it to the first device so that the first device can execute the received operation content.

[0079] At the same time, if the arbitrator 30 receives write requests from at least two third devices, it needs to select the third device according to priority.

[0080] by Figure 2 In this implementation, the arbitrator 30 receives write requests from both an MCTP (Multi-Channel Transmission Platform) device and an ARM (Advanced RISC Machines) device simultaneously. Initially, the write address ready signals of both the MCTP device and the ARM device are low. When the write address valid signals of both devices are high in the IDLE state, it indicates that write requests from both the MCTP device and the ARM device have been received simultaneously.

[0081] For example, in practical implementation, if the ARM device is prioritized over the MCTP device, then requests from the ARM device will be processed first, meaning the MCTP device's write address ready signal will remain low. For the ARM device's write address ready signal, it will be pulled high in the next clock cycle when its write address valid signal is high. When both the ARM device's write address valid and write address ready signals are high, its write address ready signal will be pulled low. For the ARM device's write data valid signal, it will be pulled high only after both the write address valid and write address ready signals are high, meaning the write data is generated after the write address. The subsequent operations are consistent with the internal routing module's operation described earlier, i.e., the incoming information can be saved and sent. The MCTP device needs to wait until the ARM device completes its write operation, and after the ARM device completes its write operation, the arbitrator 30 can then re-arbitrate.

[0082] It should be noted that, Figure 2 In the embodiment, only two third devices are provided, and thus only the priority division between the MCTP device and the ARM device is performed. In other embodiments, more third devices can be provided, which are all connected to the first device through the arbiter 30, and this does not affect the implementation of the present application.

[0083] Similarly, when the read requests of at least two third devices are received at the same time, the priority arbitration can also be performed to select the third device with the highest priority to perform the read operation.

[0084] In a specific embodiment of the present application, the second device connected to the internal router 20 through the AXI bus includes the MCTP device, and the MCTP device is also connected to the arbiter 30 as a third device.

[0085] From the above description, it can be seen that the second device communicates with the first device as a slave device, and the third device communicates with the first device as a master device. This embodiment considers that some types of devices may need to read / write data to / from the first device, and the first device may also need to read / write data to / from the device. Therefore, the present application supports that one device simultaneously serves as a second device and a third device.

[0086] For example, in this embodiment, the MCTP device is connected to the internal router 20 as a second device through the AXI bus, and is connected to the arbiter 30 as a third device through the AXI bus. The present application supports that one device simultaneously serves as a second device and a third device. Figure 2 This embodiment is adopted in the MCTP device.

[0087] In addition, in other embodiments, for devices with the same requirement, the connection of the MCTP device in the above embodiment can also be adopted. Figure 2

[0088] Further, in a specific embodiment of the present application, the third device connected to the arbiter 30 through the AXI bus includes the ARM device, and the read data channel of the AXI bus between the ARM device and the arbiter 30 is directly connected to the read data channel of the AXI bus between the first device and the arbiter 30; the read address channel of the AXI bus between the ARM device and the arbiter 30 is directly connected to the read address channel of the AXI bus between the first device and the arbiter 30.

[0089] ​The implementation considers that the third device requiring read / write operation on the first device is less, usually only the MCTP device and the ARM device, and the MCTP device usually only has the requirement of write operation and does not need to read the data of the first device, and therefore the implementation directly connects the read data channel of the AXI bus between the ARM device and the arbiter 30 to the read data channel of the AXI bus between the first device and the arbiter 30, and correspondingly, directly connects the read address channel of the AXI bus between the ARM device and the arbiter 30 to the read address channel of the AXI bus between the first device and the arbiter 30.

[0090] That is, the read address and read data of the AXI bus of the ARM device do not need to be arbitrated with other third devices, and can be directly connected to the read address and read data of the AXI bus of the first device.

[0091] The specific type of the second device of the application can also be various, for example, in a specific implementation of the application, the second device connected by the internal router 20 through the AXI bus further includes a VGA device, a first BMC, and a second BMC redundant to the first BMC.

[0092] Figure 2 The BMC device in the above-mentioned means is the BMC device including the first BMC and the second BMC redundant to the first BMC, and through the redundant setting of the BMC, the reliability of the BMC device can be guaranteed. Of course, in other specific occasions, other specific types of second devices can also be set.

[0093] In addition, the specific type of the first device of the application can also be set and selected according to actual needs, for example, specifically a PCIe device.

[0094] By applying the technical solution provided in this embodiment of the invention, a decoder 10 connected to the first device and the internal router 20 is configured to receive sideband signals sent by the first device and send the parsing results to the internal router 20. Therefore, the internal router 20 can determine the target of the first device's current operation from among the various second devices based on the received parsing results. Furthermore, the internal router 20 can receive the operation content sent by the first device via the AXI bus and send it to the target, thereby enabling the target to execute the received operation content and feed back the target's feedback information to the first device. It can be seen that, through the decoder 10 and the internal router 20 of this application, the first device can read and write to any one of the second devices; that is, through the decoder 10 and the internal router 20 of this application, an AXI connection between the first device as the master device and the second devices is achieved.

[0095] Arbitrator 30 is connected to the first device and at least two third devices via an AXI bus. It can arbitrate to send any operation content received from any third device to the first device, causing the first device to execute the received operation content and sending feedback information back to the third devices. It can be seen that arbitrator 30 of this application enables any third device to read and write to the first device; that is, arbitrator 30 of this application enables AXI connections between the first device and each third device when the first device acts as a slave device.

[0096] This application does not require the traditional IP core-based AXI Interconnect solution. Instead, it achieves AXI connections between the first device (as the master) and each of the second devices, and between the first device (as the slave) and each of the third devices, all through the decoder 10, internal router 20, and arbitrator 30. Furthermore, the decoder 10, internal router 20, and arbitrator 30 have a simple structure, high reliability, and avoid excessive chip area usage, thus preventing wasted resources and space.

[0097] Corresponding to the above embodiments of the AXI interconnection device, this invention also provides an AXI interconnection method, which can be referred to in conjunction with the above.

[0098] See also Figure 3 The following is a flowchart illustrating the implementation of an AXI interconnection method according to the present invention, which may include the following steps:

[0099] Step S301: The decoder connected to the first device and the internal router receives the sideband signal sent by the first device and sends the parsing result to the internal router;

[0100] Step S302: The internal router connected with the first device and the at least two second devices through the AXI bus determines the operation object of the first device from the respective second devices according to the received analysis result;

[0101] Step S303: The internal router receives the operation content sent by the first device and sends it to the operation object, so that the operation object executes the received operation content, and feeds back the feedback information of the operation object to the first device;

[0102] Step S304: The arbitrator connected with the first device and the at least two third devices through the AXI bus sends the received operation content sent by any one of the third devices to the first device through arbitration, so that the first device executes the received operation content, and feeds back the feedback information of the first device to the third device.

[0103] In one specific embodiment of the present application, it further comprises:

[0104] The decoder stores the sideband signal after receiving the sideband signal sent by the first device;

[0105] When receiving the retransmission instruction sent by the internal router, the sideband signal is reanalyzed and the analysis result is sent to the internal router.

[0106] In one specific embodiment of the present application, the arbitrator sends the received operation content sent by any one of the third devices to the first device through arbitration, so that the first device executes the received operation content, comprising:

[0107] When the arbitrator receives the write request sent by only one third device at the same time, the operation content sent by the third device is received and sent to the first device, so that the first device executes the received operation content;

[0108] When the arbitrator receives the write request sent by at least two third devices at the same time, the operation content sent by the third device with the highest priority is received and sent to the first device, so that the first device executes the received operation content.

[0109] In one specific embodiment of the present application, the internal router receives the operation content sent by the first device and sends it to the operation object, so that the operation object executes the received operation content, comprising:

[0110] When the first device performs a write operation, the internal router receives the operation content in the order of write address before write data, and sends the received operation content to the operation object in the order of write address before write data, so that the operation object executes the received operation content.

[0111] In one embodiment of the present application, when the first device performs a write operation, the internal router receives operation content in the order of write address before write data, and sends the received operation content to the operation object in the order of write address before write data, so that the operation object executes the received operation content, including:

[0112] When the first device performs a write operation, the internal router controls the write address ready signal of the AXI bus between the internal router and the first device to be low after receiving the write address, and controls the write data ready signal of the AXI bus between the internal router and the first device to switch from low to high;

[0113] After receiving the write data, the internal router sends the received write data to the operation object to make the operation object execute the received operation content when it is determined that the write address is completely sent to the operation object;

[0114] After receiving the feedback information indicating write completion sent by the operation object, the internal router controls the write address ready signal of the AXI bus between the internal router and the first device to be high.

[0115] Corresponding to the above embodiments of the AXI interconnection device and method, the embodiments of the present application also provide a server, which can include the AXI interconnection device in any of the above embodiments, and will not be repeated here.

[0116] It should also be noted that in this document, relational terms such as first and second and the like can only be used to distinguish one entity or action from another entity or action, without necessarily requiring or implying any such actual relationship or order between or among the entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, so that a process, method, article, or apparatus that comprises a list of elements does not include only those elements, but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element.

[0117] Those skilled in the art will further realize that the mere conception of the examples described herein is sufficient to enable practitioners to practice the examples as changed or modified for specific applications, and that various other modifications or changes in form and detail can be made by those skilled in the art without departing from the spirit and scope of the application. Accordingly, the drawings and descriptions are to be regarded as illustrative in nature and not as restrictive.

[0118] The principles and implementations of the present application have been described in specific examples. The above description is only used to help understand the technical solutions of the present application and the core ideas thereof. It should be pointed out that, for those skilled in the art, without departing from the principles of the present application, some improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the present application.

Claims

1. An AXI interconnect device, characterized by, The application relates to a system for connecting a first device with at least two second devices, comprising: a decoder connected with the first device and an internal router, for receiving a sideband signal sent by the first device and sending a parsing result to the internal router; the internal router connected with the first device and at least two second devices through AXI bus, for determining an operation object of the first device from each of the second devices according to the received parsing result, receiving operation content sent by the first device and sending the operation content to the operation object, so that the operation object executes the received operation content and feeds back information of the operation object to the first device; an arbitrator connected with the first device and at least two third devices through AXI bus, for sending, in an arbitration mode, operation content sent by any one of the third devices to the first device, so that the first device executes the received operation content and feeds back information of the first device to the third device.

2. The AXI interconnect device of claim 1, wherein, The second device connected with the internal router through AXI bus comprises an MCTP device, and the MCTP device simultaneously serves as a third device and is connected with the arbitrator.

3. The AXI interconnect device of claim 2, wherein, The third device connected with the arbitrator through AXI bus comprises an ARM device, and a read data channel of the AXI bus between the ARM device and the arbitrator is directly connected with a read data channel of the AXI bus between the first device and the arbitrator; a read address channel of the AXI bus between the ARM device and the arbitrator is directly connected with a read address channel of the AXI bus between the first device and the arbitrator.

4. The AXI interconnect device of claim 2, wherein, The second device connected with the internal router through AXI bus further comprises a VGA device, a first BMC and a second BMC which is redundant to the first BMC.

5. The AXI interconnect device of claim 1, wherein, The decoder is further used for: storing the sideband signal after receiving the sideband signal sent by the first device; re-parsing the sideband signal and sending a parsing result to the internal router when receiving a retransmission instruction sent by the internal router.

6. The AXI interconnect device of claim 1, wherein, The arbitrator is used for sending, in an arbitration mode, operation content sent by any one of the third devices to the first device, so that the first device executes the received operation content, and comprises: when the arbitrator receives write requests sent by only one third device at the same time, the arbitrator receives operation content sent by the third device and sends the operation content to the first device, so that the first device executes the received operation content; when the arbitrator receives write requests sent by at least two third devices at the same time, the arbitrator receives operation content sent by the third device with the highest priority and sends the operation content to the first device, so that the first device executes the received operation content.

7. The AXI interconnect device of any of claims 1 to 6, wherein, The internal router receives operation content sent by the first device and sends the operation content to the operation object, so that the operation object executes the received operation content, and comprises: When the first device performs a write operation, the internal router receives operation content in the order of write address before write data, and sends the received operation content to the operation object in the order of write address before write data, so that the operation object executes the received operation content.

8. The AXI interconnect device of claim 7, wherein, When the first device performs a write operation, the internal router receives operation content in the order of write address before write data, and sends the received operation content to the operation object in the order of write address before write data, so that the operation object executes the received operation content, comprising: When the first device performs a write operation, the internal router controls the write address ready signal of the AXI bus between the first device to be low after receiving the write address, and controls the write data ready signal of the AXI bus between the first device to be switched from low to high; The internal router sends the received write data to the operation object to make the operation object execute the received operation content after receiving the write data and determining that the write address is completely sent to the operation object; After receiving the feedback information sent by the operation object indicating write completion, the write address ready signal of the AXI bus between the first device is controlled to be high.

9. An AXI interconnect method, comprising: Comprising: The decoder connected with the first device and the internal router receives the sideband signal sent by the first device and sends the analysis result to the internal router; The internal router connected with the first device and at least two second devices through the AXI bus determines the operation object of the first device this time from each of the second devices according to the received analysis result; The internal router receives the operation content sent by the first device and sends it to the operation object, so that the operation object executes the received operation content, and feeds back the feedback information of the operation object to the first device; The arbiter connected with the first device and at least two third devices through the AXI bus sends the received operation content of any one of the third devices to the first device in an arbitrated manner, so that the first device executes the received operation content, and feeds back the feedback information of the first device to the third device.

10. A server, characterized by The AXI interconnection device comprises the AXI interconnection device according to any one of claims 1 to 8.

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