Circuitry and methods for detecting word line leakage and process defects in an NVM array

Abstract

Embodiments of this disclosure relate to circuits and methods for detecting word line leakage and process defects in an NVM array. An integrated circuit die includes memory sectors, each memory sector comprising a memory array. The die includes a voltage regulator having a first transistor driven by an output voltage to generate a gate voltage based on a difference between a constant current and a leakage current. A selection circuit selectively couples the gate voltage to a selected one of a plurality of memory sectors. A leakage detector circuit drives a second transistor with the output voltage to generate a replication voltage based on a difference between a variable current and a copy of a constant current, increases the variable current in response to the replication voltage being greater than the gate voltage, and activates a leakage detection signal indicating excessive leakage within the memory array in response to the replication voltage being less than the gate voltage.

Description

[0001] Related applications

[0002] This application claims priority to provisional application U.S. Patent No. 63 / 218,621, filed July 6, 2021, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to the field of non-volatile memory, and more particularly to circuitry and techniques for determining the presence of process defects (such as excessive row decoder leakage, word line leakage, and bit line leakage) in non-volatile memory arrays. This disclosure provides on-chip test circuitry that can be used during the sorting stage of manufactured electronic wafers. Background Technology

[0004] Non-volatile memory (NVM) is used in many electronic devices in the modern world. NVM is formed on a dedicated die or together with other components (e.g., system-on-a-chip) on the die.

[0005] like Figure 1 As shown, during manufacturing, multiple dies 11 containing NVM arrays are formed on wafer 10. Each sample die 11 includes i sectors Sector[0], ..., Sector[i], each sector containing an array 19 of memory cells C arranged in rows and columns. Each array 19 has a size of m×n, where m is the number of columns and n is the number of rows. Memory cells C in each row are controlled by word lines from word lines WL[0], ..., WL[n], and memory cells C in each column can be read from or written via bit line / complementary bit line pairs BL[0], ..., BL[m]. A row decoder and level shifter circuit 15 receives the row address pre-decoded from the address and decodes the bits of the row address. A column decoder circuit 17 receives the column address pre-decoded from the address and decodes the bits of the column address.

[0006] In read mode, the Sector[0], ..., Sector[i] to be selected for read / write can be determined based on the address and selected by actuation of the associated switches S0, ..., Si. Switch Sw is closed to connect read regulator 12 to the selected sector. The column address used by column decoder 17 is used to select multiple bit lines BL[0], ..., BL[m] via column multiplexer 18, and the row address is used by row decoder 15 to select and actuate one of the word lines WL[0], ..., WL[n] by activating one of the word lines WL[0], ..., WL[n] via the corresponding word line driver D0, ..., Dn. The word line drivers D0, ..., Dn are powered by read voltage Vread.

[0007] During manufacturing, it is desirable to know whether the NVM array on a given die contains a process error, as indicated by excessive leakage current in the row decoder, excessive leakage current in the word lines, or excessive leakage current in the bit lines. This is typically performed by opening switch Sw to supply the read voltage Vread to the word line drivers D0, ..., Dn, closing the test enable switch S_EN_test, and forcing an external read voltage onto pad 13 connected to the selected sector Sector[0], ..., Sector[i] for use by its row decoder 15. Whether die 11 has experienced a process error can be determined by monitoring the current drawn from the external voltage source (not explicitly shown) supplying the external voltage and comparing that current to the expected current.

[0008] While this technique works, it consumes excessive on-chip area because it requires additional pads to apply the external read voltage. Furthermore, the use of an external read voltage necessitates external testing equipment, making the testing of large quantities of this die 11 slow and cumbersome.

[0009] Therefore, it is necessary to further develop methods to determine whether the NVM array on the die is subject to process errors. Summary of the Invention

[0010] This document discloses an integrated circuit die comprising multiple memory sectors, each memory sector including a memory array. The integrated circuit die has a voltage regulator including a first transistor driven by an output voltage to generate a gate voltage based on the difference between a constant current and a leakage current. A selection circuit is configured to selectively couple the gate voltage to a selected one of the multiple memory sectors. A leakage detector circuit is configured to: drive a second transistor with the output voltage to generate a replication voltage based on the difference between a variable current and a copy of a constant current; increase the variable current in response to the replication voltage being greater than the gate voltage; and activate a leakage detection signal in response to the replication voltage being less than the gate voltage, the leakage detection signal indicating excessive leakage within the memory array of the selected memory sector.

[0011] To detect excessive leakage current within the row decoder of a selected memory sector, the leakage current detector circuit can be configured to: a) deselect all word lines within the memory array of the selected memory sector; b) set a variable current with an amplitude within a zero threshold; c) increase the variable current by a given amount in response to a replication voltage greater than the gate voltage, and wait for a given period of time; d) if increasing the variable current by the given amount causes the replication voltage to become less than the gate voltage, activate the leakage current detection signal to indicate excessive leakage current within the row decoder of the selected memory sector; and e) if increasing the variable current by the given amount does not cause the replication voltage to become less than the gate voltage, return to c).

[0012] To detect excessive leakage in a selected word line within a memory sector, the leakage detector circuit can also be configured to: f) select a word line within the selected memory array sector while keeping the remaining word lines unselected; g) wait for a given time period; h) disable the leakage detection signal if the selection of the word line causes the gate voltage to become less than the replication voltage, thereby indicating excessive leakage in the selected word line of the selected memory sector; and i) enable the leakage detection signal if the selection of the word line does not cause the gate voltage to become less than the replication voltage, thereby indicating that there is no excessive leakage in the selected word line.

[0013] To detect excessive leakage in a bit line of a selected memory sector, the leakage detector circuit can be configured to: a) deselect all word lines in the memory array of the selected memory sector and select one bit line in the memory array; b) set a variable current with an amplitude within a zero threshold; c) increase the variable current by a given amount in response to a replication voltage greater than the gate voltage and wait for a given period of time; d) if increasing the variable current by the given amount causes the replication voltage to become less than the gate voltage, activate the leakage detection signal, thus indicating excessive leakage in the bit line; and e) if increasing the variable current by the given amount does not cause the replication voltage to become less than the gate voltage, return to c). Attached Figure Description

[0014] Figure 1 It is a schematic representation of a prior art wafer on which multiple integrated circuit dies are formed, wherein each integrated circuit die has a built-in test circuit that can be used to perform leakage current testing.

[0015] Figure 2 This is a schematic block diagram of a first embodiment of an integrated circuit die having built-in test circuitry that can be used to perform line decoder leakage detection and word line leakage detection, as disclosed herein.

[0016] Figure 3A This shows the operation. Figure 2The flowchart shows the steps of using an integrated circuit die to perform leakage detection in a line decoder.

[0017] Figure 3B This shows the operation. Figure 2 The flowchart shows the steps for using an integrated circuit die to perform word line leakage detection.

[0018] Figure 4 This is a schematic block diagram of a second embodiment of an integrated circuit die having built-in test circuitry that can be used to perform line decoder leakage detection and word line leakage detection, as disclosed herein.

[0019] Figure 5 This is a schematic block diagram of a third embodiment of an integrated circuit die having built-in test circuitry that can be used to perform line decoder leakage detection and word line leakage detection, as disclosed herein.

[0020] Figure 6 This is a schematic block diagram of a fourth embodiment of an integrated circuit die having built-in test circuitry that can be used to perform line decoder leakage detection and word line leakage detection, as disclosed herein.

[0021] Figure 7 This is a schematic block diagram of a first embodiment of an integrated circuit die having a built-in test circuit that can be used to perform bit line leakage detection, as disclosed herein.

[0022] Figure 8 This shows the operation. Figure 7 The flowchart shows the steps of using an integrated circuit die to perform bit line leakage detection.

[0023] Figure 9 This is a schematic block diagram of a second embodiment of an integrated circuit die having a built-in test circuit that can be used to perform bit line leakage detection, as disclosed herein.

[0024] Figure 10 This is a schematic block diagram of a third embodiment of an integrated circuit die having a built-in test circuit that can be used to perform bit line detection, as disclosed herein.

[0025] Figure 11 This is a schematic block diagram of a fourth embodiment of an integrated circuit die having a built-in test circuit that can be used to perform bit line detection, as disclosed herein.

[0026] Figure 12 It is shown Figure 2 The graph shows the integrated circuit die in operation when performing leakage current detection in the line decoder.

[0027] Figure 13 It is shown Figure 2 The graph shows the integrated circuit die in operation when performing leakage current detection in the line decoder. Detailed Implementation

[0028] The following disclosure enables those skilled in the art to make and use the subject matter disclosed herein. The general principles described herein can be applied to embodiments and applications other than those detailed above, without departing from the spirit and scope of this disclosure. This disclosure is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed or suggested herein.

[0029] Now for reference Figure 2 Described is a non-volatile memory circuit 20 comprising a voltage regulator 12' and a leakage detector arrangement 23, which cooperate to measure line decoder leakage and word line leakage (such as that caused by a resistive short circuit) within a memory array (not shown for ease of viewing) of sectors[0], ..., Sector[i]. This non-volatile memory circuit 20 is contained within an integrated circuit die and can be used during the manufacture of a wafer containing multiple such integrated circuit dies in the electrical wafer sorting stage to determine which integrated circuit die (e.g., chip) will be discarded, and / or to perform binning of different integrated circuit dies on the wafer.

[0030] Sectors [0], ..., Sector [i] are selectively connected via corresponding switches S0, ..., Si to receive the gate voltage Vgate. This gate voltage Vgate is used by the row decoder and word line driver of sector [0], ..., Sector [i]. Specifically, the gate voltage Vgate can be used to generate the word line voltage for the read / write cycles of sector [0], ..., Sector [i].

[0031] Voltage regulator 12' generates a gate voltage Vgate. Voltage regulator 12' includes a power MOS transistor, such as a PMOS transistor MP1, whose source is connected to the power supply voltage Vdd, whose drain is connected to the first terminal of a resistor R with adjustable resistance, and whose gate is connected to be driven by the output of amplifier 21 (which is voltage Pgate). The non-inverting terminal of amplifier 21 is connected to receive a bandgap (reference) voltage Vbg, and its inverting terminal is connected to receive a feedback voltage Fbk generated at the second terminal of the resistor R with adjustable resistance.

[0032] Current I2 is drawn from the second terminal of a resistor R with adjustable resistance through a current mirror device 22. The current mirror device 22 includes a constant current source 26 connected between the power supply voltage Vdd and the drain of n-channel transistor MN1, generating a constant current I1. The source of n-channel transistor MN1 is grounded, and its gate is connected to its drain. n-channel transistor MN1 and n-channel transistor MN2 are in the current mirror device, therefore the gates of n-channel transistors MN1 and MN2 are interconnected. The drain of n-channel transistor MN2 is connected to the second terminal of a resistor R with adjustable resistance to sink current I2 (I2 being a copy or multiple of I1) from the second terminal of the resistor R with adjustable resistance. Its source is grounded, and as previously described, its gate is connected to the gate of n-channel transistor MN1 (and therefore also to the drain of n-channel transistor MN1).

[0033] The leakage current detector arrangement 23 includes a PMOS transistor MP2, a copy of PMOS transistor MP1. The source of PMOS transistor MP2 is connected to the supply voltage Vdd, its drain is connected to node N, and its gate is connected to the output of amplifier 21 to receive voltage Pgate. An adjustable current source 27 is connected between node N and the test enable switch S_EN_test. The test enable switch S_EN_test selectively connects the adjustable current source 27 to ground, thereby selectively enabling the adjustable current source 27 to draw a desired current from node N. The adjustable current source 27 receives the current configuration bit from the finite state machine (FSM) 25.

[0034] n-channel transistor MN3 is in a current mirror configuration with n-channel transistors MN1 and MN2. The drain of n-channel transistor MN3 is connected to node N, its source is connected to ground, and its gate is connected to the gates of n-channel transistors MN1 and MN2 (and the drain of n-channel transistor MN1). The non-inverting terminal of amplifier 24 (arranged as a comparator) is connected to receive the gate voltage Vgate, its inverting terminal is connected to node N, and its output is connected to provide the leakage flag WL_Leak to FSM25.

[0035] Now refer to another source Figure 3A Flowchart 50 and Figures 10 to 11The graph is used to describe the operation of the non-volatile memory circuit 20 in the test mode of performing line decoder leakage detection. To start line decoder leakage detection, the control bit EN_TEST (block 51) is set to enable the leakage detector arrangement 23, which involves closing the S_EN_test switch. At this time, the sector to be tested is selected from Sector[0], ..., Sector[i] by closing the switch associated with the sector to be tested from the switches S0, ..., Si (block 52), but no word lines are selected in the selected sector (e.g., no word line driver enables its output in the selected sector).

[0036] Then, FSM 25 sets the configuration bit so that the current Ivar generated by the variable current generator 27 has zero amplitude (block 53). Note that the gate voltage Vgate is generated by R The stable voltage defined by I2+Vbg is independent of the leakage current Ileak flowing into the selected sector. On the other hand, the voltage Pgate used to bias the gate of PMOS transistor MP2 depends on the leakage current Ileak flowing into the selected sector. As the leakage current Ileak increases, the voltage Pgate decreases to provide more overdrive voltage to PMOS transistor MP1, allowing MP1 to provide the necessary current to maintain its drain voltage at Vgate; as the leakage current Ileak decreases, the voltage Pgate increases to provide less overdrive voltage to PMOS transistor MP1, thereby reducing the current pulled out by MP1 and maintaining the drain voltage of MP1 at Vgate.

[0037] Keeping this in mind, note that the replication voltage Vgate_copy is generated at node N. Specifically, the voltage Pgate used to bias the gate of PMOS transistor MP2 causes PMOS transistor MP2 to pull a current to node N equal to the current pulled to the drain of PMOS transistor MP1. The total current drawn from node N will be equal to the sum of currents I2 and Ileak. As a result, as explained, while Vgate will remain constant, Vgate_copy will depend inversely on the sum of I3 and Ivar—the larger the magnitude of Ivar, the smaller the voltage Vgate_copy will be.

[0038] Since the magnitude of current Ivar (block 53) is zero at this time, this means that no current is subtracted from I3, and the difference between the drain current of PMOS transistor MP2 and current I3 (which is a copy of current I1 and therefore less than the total current pulled from MP1) will charge node N to Vgate_copy.

[0039] As a result, at this point, Vgate_copy is greater than Vgate. Since amplifier 24 is configured as a comparator, the Vgate_copy at its inverting terminal is greater than the Vgate at its non-inverting terminal, meaning its output is not active—WL_Leak is logic low. These conditions can... Figures 10 to 11 It was observed at the time marked as time T1.

[0040] In response to WL_Leak being logic low, FSM 25 increments the configuration bit by a given amount, thereby increasing the current Ivar to a non-zero magnitude (block 54), and waits for a time period T (block 55). As Ivar increases, the value of Vgate_copy decreases, as explained above. This can be achieved by... Figures 12 to 13 The time intervals marked as T2 and T3 are observed, where Vgate_copy decreases due to the increase of Ivar. For the time interval T, this can be a fixed time interval set to provide adequate functionality in the worst-case scenario; however, additionally or alternatively, the duration of time interval T can be set by FSM 25.

[0041] If, when time period T expires, Vgate_copy is still greater than Vgate (block 56), this means WL_Leak remains logically low. This situation can... Figure 13 The time marked as time T3 is observed. In response to WL_Leak remaining logic low when time period T expires, FSM 25 increments the configuration bit again by the given amount (block 57), thereby increasing the current Ivar, and waits again for time period T (back to block 55). If this increase in Ivar is sufficient to make Vgate_copy equal to or less than Vgate, then amplifier 24 activates the signal WL_Leak, which then (at block 56) indicates that the current configuration bit will be stored by FSM 25. This situation can be... Figure 12 The time marked as T3 in Figure 13 At time T4, it was observed that the magnitude of Vgate_copy had dropped below Vgate, and therefore WL_Leak had taken effect.

[0042] When WL_Leak first takes effect, these configuration bits enable the determination of leakage current from the row decoder. For example, if these configuration bits are greater than the set value, it means that the leakage current through the row decoder is greater than expected, and it can be inferred that the chip has suffered a process defect and should be discarded or packaged accordingly.

[0043] Therefore, it should be understood that FSM 25 will continuously increment the configuration bit, wait for a time period T, and read WL_Leak (e.g., repeating steps 57, 55, and 56) until WL_Leak becomes active. In some applications, WL_Leak may never become active, meaning that the variable current source 27 cannot generate a current equal to the leakage current from the word line decoder—in this case, it is also assumed that the chip is subject to a process error once FSM 25 increments the configuration bit to the level it is programmed to reach (or once FSM increments the configuration bit above a certain threshold).

[0044] The above operations can be performed on each sector Sector[0], ..., Sector[i] to test all chips on the wafer.

[0045] Now refer to another source Figure 3B Flowchart 60 describes the operation of the non-volatile memory circuit 20 in the test mode for performing word line leakage detection. To begin word line leakage detection, the control bit EN_TEST is set (block 61), enabling the leakage detector arrangement 23 by closing the S_EN_test switch. At this time, the sector to be tested is selected from Sector[0], ..., Sector[i] by closing the switch associated with the sector to be tested from switches S0, ..., Si (block 62). Then, the variable current source 27 is programmed by the FSM 25 using the configuration bits determined during the row decoder leakage detection (block 63). After this, the desired word line to be tested is activated, while other word lines are deactivated (block 64), and a waiting period T is performed (block 65). If WL_Leak takes effect when time period T expires (meaning the magnitude of Ivar is sufficient to make Vgate_copy equal to or less than Vgate), this indicates that the select line is not short-circuited by a resistor (block 66). If the select line is short-circuited, the current configuration bit will cause variable current source 27 to generate an Ivar with an magnitude insufficient to make Vgate_copy equal to or less than Vgate. Therefore, if WL_Leak does not take effect when time period T expires, it can be inferred that word line leakage has occurred, the chip has suffered a process error, and therefore the chip can be discarded.

[0046] On the other hand, if WL_Leak takes effect when time period T expires, it can be assumed that the selected word line is correct, the selected word line is deselected, and the next word line is selected for testing (block 67). Then, FSM 25 waits for time period T again (block 65), FSM 25 reads WL_Leak again (block 66), and FSM 25 evaluates whether the currently selected word line is subject to word line leakage based on whether WL_Leak is effective. This process is repeated (blocks 66, 67, and 65) until all word lines in the selected sector have been evaluated. Similarly, this test can be performed on each word line of each sector Sector[0], ..., Sector[i] to test all chips on the wafer.

[0047] In the embodiment of the non-volatile memory circuit 20 shown, amplifier 24 (configured as a comparator) in conjunction with FSM 25 is used to compare Vgate_copy with Vgate. However, in some cases, it may be desirable to use a digital comparison of Vgate_copy with Vgate instead of an analog comparison performed by the non-volatile memory circuit 20.

[0048] Such an embodiment is in Figure 4 The current mirror device 22 and regulator 12' remain unchanged compared to the non-volatile memory circuit 20. The difference here is that instead of using a comparator to compare Vgate and Vgate_copy, the comparison is performed digitally by the analog-to-digital converter (ADC) 35. That is, the ADC 35 has inputs connected to receive Vgate and Vgate_copy. The ADC 35 digitizes these voltages, compares them with each other, and generates WL_Leak as a unit (bit) digital signal indicating whether Vgate_copy is less than or equal to Vgate. WL_Leak is provided to the N-bit register 36, which generates configuration bits for the variable current source 27 based on WL_Leak.

[0049] Therefore, the difference between non-volatile memory circuit 20' and non-volatile memory circuit 20 is that non-volatile memory circuit 20' uses ADC 35 to compare Vgate and Vgate_copy instead of a comparator, and uses N-bit register 36 to generate configuration bits instead of a state machine. Apart from this, the actual operation of non-volatile memory circuit 20' in performing line decoder leakage tests and word line leakage tests remains the same as described above.

[0050] Now refer to another source Figure 3AFlowchart 50 describes the operation of the non-volatile memory circuit 20' in the test mode for performing line decoder leakage detection. To begin line decoder leakage detection, the control bit EN_TEST (block 51) is set to enable the leakage detector arrangement 23, which involves closing the S_EN_test switch. At this time, the sector to be tested is selected from Sector[0], ..., Sector[i] by closing the switch associated with the sector to be tested from switches S0,..., Si (block 52), but no word lines are selected in the selected sector (e.g., no word line driver enables its output in the selected sector).

[0051] Initially, when the line decoder leakage detection begins, the configuration bits stored in the N-bit register 36 are zero, and these configuration bits are output as the variable current source 27, causing the current Ivar to have a zero amplitude (block 53).

[0052] As explained earlier, Vgate is created by R I2+Vbg defines the stable voltage and is independent of the leakage current Ileak flowing into the selected sector. On the other hand, Vgate_copy is a function of the voltage Pgate (which itself depends on the leakage current Ileak flowing into the selected sector), I3 (a copy of I1), and Ivar used to bias the gate of the PMOS transistor MP2.

[0053] Since Ivar is 0, Vgate_copy is greater than Vgate. As a result, ADC 35 generates WL_Leak as a logic low.

[0054] In response to WL_Leak being logic low, N-bit register 36 increments the configuration bit by a given amount, thereby increasing the current Ivar to a non-zero magnitude (block 54), and waits for a time period T (block 55). As Ivar increases, the value of Vgate_copy decreases (because Ivar is subtracted from I3 at node N). When time period T expires, if Vgate_copy is still greater than Vgate (block 56), this means WL_Leak remains logic low. In response to WL_Leak remaining logic low when time period T expires, N-bit register 36 again increments the configuration bit by a given amount (block 57), thereby increasing the current Ivar, and waits for another time period T (back to block 55).

[0055] If this increase in Ivar is sufficient to make Vgate_copy equal to or less than Vgate, then ADC 35 activates the signal WL_Leak, which (at block 56) indicates that the current configuration bits will be stored in N-bit register 36. These configuration bits, when WL_Leak first activates, allow the determination of leakage current from the line decoder. For example, if these configuration bits are greater than the set value, this means that leakage through the line decoder is greater than expected, and it can be inferred that the chip has suffered a process defect and should be discarded or boxed accordingly.

[0056] Therefore, N-bit register 36 will continuously increment the configuration bit, wait for a time period T, and read WL_Leak (e.g., repeat steps 57, 55, and 56) until WL_Leak becomes active. In some applications, WL_Leak may never become active, meaning that variable current source 27 cannot generate a current equal to the leakage current from the word line decoder—in this case, once N-bit register 36 increments the configuration bit to the level it is programmed to reach, and WL_Leak has not yet become active, it is also assumed that the chip is subject to a process error. The above operation can be performed on each sector Sector[0], ...,Sector[i] to test all chips on the wafer.

[0057] Now refer to another source Figure 3B Flowchart 60 describes the operation of the non-volatile memory circuit 20' in the test mode for performing word line leakage detection. To begin word line leakage detection, the control bit EN_TEST is set (block 61) to enable the leakage detector arrangement 23, which involves closing the S_EN_test switch. At this time, the sector to be tested is selected from Sector[0], ..., Sector[i] by closing the switch associated with the sector to be tested from switches S0, ..., Si (block 62). Then, the variable current source 27 is programmed by the N-bit register 36 using the configuration bits determined during the line decoder leakage detection (block 63).

[0058] Afterward, the desired word line to be tested becomes active, while other word lines are deactivated (block 64), and a waiting period T is initiated (block 65). If WL_Leak becomes active when time period T expires, this means that the select line has not experienced a resistor short circuit (block 66) – if the select line were short-circuited, the current configuration bit would cause the variable current source 27 to generate an amplitude insufficient to make Vgate_copy equal to or less than Vgate's Ivar. Therefore, if WL_Leak does not become active when time period T expires, it can be inferred that a word line leakage has occurred, the chip has experienced a process error, and therefore the chip can be discarded.

[0059] On the other hand, if WL_Leak takes effect when time period T expires, it can be assumed that the selected word line is error-free, the selected word line is deselected, and the next word line is selected for testing (block 67). Then, N-bit register 36 waits for time period T again (block 65), reads WL_Leak again (block 66), and can evaluate whether the currently selected word line is subject to word line leakage based on whether WL_Leak is effective. This process is repeated (blocks 66, 67, and 65) until all word lines in the selected sector have been evaluated. Similarly, this test can be performed on each word line of each sector Sector[0], ..., Sector[i] to test all chips on the wafer.

[0060] Now for reference Figure 5 Another embodiment of the non-volatile memory circuit 90 is described. (Compared to...) Figure 2 Unlike the non-volatile memory circuit 20, the non-volatile memory circuit 90 lacks a current mirror device. Instead, the second terminal of the adjustable resistor R is connected to ground via an additional resistor R1, so the feedback signal Fbk is generated at the tap of the voltage divider formed by the adjustable resistor R and the resistor R1. By adjusting / fine-tuning the resistor R and selecting the resistance value of the resistor R1, current I2 is drawn from the drain of the PMOS transistor MP1.

[0061] Here, also due to the lack of a current mirror device, the source of the n-channel transistor MN3 is connected to ground via resistor R2, and its gate is controlled by the output of amplifier 31. The non-inverting terminal of amplifier 31 is connected to receive the bandgap voltage Vbg, its inverting terminal is connected to the source of the n-channel transistor MN3, and as previously described, the output of amplifier 31 is connected to the gate of the n-channel transistor MN3, forming a voltage regulator. Therefore, by selecting the resistance value of resistor R2, current I3 (a copy of current I2) is drawn from node N.

[0062] Therefore, the difference between the non-volatile memory circuit 90 and the non-volatile memory circuit 20 lies in the generation of currents I2 and I3. The actual operation of the non-volatile memory circuit 90 in performing the row decoder leakage test and word line leakage test is the same as described above.

[0063] Now for reference Figure 6Another embodiment of the non-volatile memory circuit 90' is described. Note that the regulator 12' and the generation of currents I2 and I3 remain the same compared to the non-volatile memory circuit 90. The difference here is that instead of using a comparator to compare Vgate with Vgate_copy, the comparison is performed digitally by an analog-to-digital converter (ADC) 35. The ADC 35 has inputs connected to receive Vgate and Vgate_copy. The ADC 35 digitizes these voltages, compares them with each other, and generates WL_Leak as a unit digital signal indicating whether Vgate_copy is less than or equal to Vgate. WL_Leak is provided to an N-bit register 36, which generates configuration bits for the variable current source 27 based on WL_Leak.

[0064] Therefore, the difference between non-volatile memory circuit 90' and non-volatile memory circuit 90 is that non-volatile memory circuit 90' uses ADC 35 to compare Vgate and Vgate_copy instead of a comparator, and uses N-bit register 36 to generate configuration bits instead of a state machine. Apart from this, the actual operation of non-volatile memory circuit 90 in performing line decoder leakage tests and word line leakage tests is the same as described above.

[0065] Now for reference Figure 7 Another embodiment of the non-volatile memory circuit 95 is described. Note that, with Figure 5 Compared to the non-volatile memory circuit 90, the non-volatile memory circuit 95 here is used to test the leakage current of the bit lines of the memory array in the sector. Specifically, the leakage current Ileak to the selected bit line BL is subtracted from the current I2 to generate a voltage VY at the drain of the PMOS transistor MP1. Similarly, a copy voltage VY_copy is generated at node N based on the current I3 (which is a copy of current I2) minus the variable current Ivar. Furthermore, amplifier 24 (configured as a comparator) determines whether VY_copy is equal to or less than the voltage VY.

[0066] Note that VY is a stable voltage, independent of the leakage current Ileak flowing into the selected sector's positioning line. VY is equal to Vbg. (1+R / R1). However, Pgate (used to bias the gate of PMOS transistor MP2) depends on the leakage current Ileak. A higher leakage current results in a lower Pgate, thus enabling PMOS transistor MP1 to provide the necessary current; similarly, a lower leakage current results in a higher Pgate, thus reducing the current pulled out by PMOS transistor MP1 so that VY remains at Vbg. (1+R / R1). Since I3 is a copy of current I2, and the drain current of PMOS transistor MP2 is equal to the drain current of PMOS transistor MP1, if Ivar=Ileak, then VY_copy will depend on Ivar and will be equal to VY.

[0067] Keep this in mind, and now refer to another source. Figure 8 Flowchart 100 describes the operation of the non-volatile memory circuit 95 in the test mode for performing bit line leakage detection. To begin bit line leakage detection, the control bit EN_TEST is set (block 101), enabling the leakage detector arrangement 96 by closing the S_EN_test switch. At this time, the sector to be tested is selected from Sector[0],..., Sector[i] (block 102), but no word lines are selected in the selected sector (e.g., no word line driver is enabled in the selected sector), and a bit line is selected from bit lines BL[0],..., BL[n] to apply a voltage VY to the selected bit line, while the other bit lines are coupled to ground.

[0068] Then, FSM 25 sets the configuration bit so that the current Ivar generated by the variable current generator 27 has a zero amplitude (block 103). At this time, the amplitude of the current Ivar is zero. Therefore, VY_copy is greater than VY at this time. Since amplifier 24 is arranged as a comparator, VY_copy at its inverting terminal being greater than VY at its non-inverting terminal means that its output is not active—BL_Leak is logic low.

[0069] In response to BL_Leak being logic low, FSM 25 increments the configuration bit by a given amount, thereby increasing the current Ivar to a non-zero magnitude (block 104), and waits for a time period T (block 105). As Ivar increases, the value of VY_copy decreases. If VY_copy is still greater than VY when time period T expires (block 106), this means BL_Leak remains logic low. In response to BL_Leak remaining logic low when time period T expires, FSM 25 increments the configuration bit by a given amount again (block 107), thereby increasing the current Ivar, and waits for another time period T (back to block 105). If this increase in Ivar is sufficient to make VY_copy equal to or less than VY, then amplifier 24 activates the signal BL_Leak, which then (at block 106) indicates that the current configuration bit will be stored by FSM 25. These configuration bits, when BL_Leak is first activated, enable the determination of leakage current from the selected positioning line. For example, if these configuration bits are greater than the set value, it means that the leakage current through the selected positioning line is greater than expected, and it can be inferred that the chip has suffered a process error and should be discarded or packaged accordingly.

[0070] Therefore, it should be understood that FSM 25 will continuously increment the configuration bit, wait for a time period T, and read BL_Leak (e.g., repeating steps 107, 105, and 106) until BL_Leak becomes active. In some applications, BL_Leak may never become active, meaning that the variable current source 27 cannot generate a current equal to the leakage current from the bit line—in such a case, once FSM 25 increments the configuration bit to the level it is programmed to reach, and BL_Leak has not yet become active, it is also assumed that the chip has been affected by a process error.

[0071] Repeat this process (blocks 106, 107, and 105) until all bit lines within the selected sector have been evaluated. The above operation can be performed on each sector Sector[0], ..., Sector[i] to test all chips on the wafer.

[0072] It may be desirable to use a digital comparison of VY_copy with VY instead of an analog comparison performed by the non-volatile memory circuit 20.

[0073] Such an embodiment is in Figure 9The regulator 12” is shown in the diagram. Compared to the non-volatile memory circuit 95', the regulator 12” remains unchanged. The difference here is that instead of using a comparator to compare VY with VY_copy, the comparison is performed digitally by the analog-to-digital converter (ADC) 35. That is, the ADC 35 has inputs connected to receive VY and VY_copy. The ADC 35 digitizes these voltages, compares them with each other, and generates BL_Leak as a unit digital signal indicating whether VY_copy is less than or equal to VY. BL_Leak is provided to the N-bit register 36, which generates configuration bits for the variable current source 27 based on BL_Leak.

[0074] Therefore, the difference between the non-volatile memory circuit 95' and the non-volatile memory circuit 95 is that instead of using a comparator, an ADC 35 is used to compare VY and VY_copy, and instead of using a state machine, an N-bit register 36 is used to generate the configuration bits. Apart from this, the actual operation of the non-volatile memory circuit 95' in performing bit-line leakage testing is the same as described above.

[0075] Now refer to another source Figure 8 Flowchart 100 describes the operation of the non-volatile memory circuit 95' in the test mode for performing bit line leakage detection. To begin bit line leakage detection, the control bit EN_TEST is set (block 101), enabling the leakage detector arrangement 96 by closing the S_EN_test switch. At this time, the sector to be tested is selected (block 102), but no word lines are selected in the selected sector (e.g., no word line driver is enabled for its output in the selected sector), and a bit line is selected from the bit lines BL[0], ..., BL[n].

[0076] Initially, when bit line leakage detection begins, the configuration bits stored in N-bit register 36 are zero, and these configuration bits, as the output of variable current source 27, cause current Ivar to have zero amplitude (block 103).

[0077] As explained earlier, at this point, since Ivar is 0, VY_copy is greater than VY. As a result, ADC 35 generates BL_Leak as a logic low.

[0078] In response to BL_Leak being logic low, N-bit register 36 increments the configuration bit by a given amount, thereby increasing the current Ivar to a non-zero magnitude (block 104), and waits for a time period T (block 105). As Ivar increases, the value of VY_copy decreases (because Ivar is subtracted from I3 at node N). When time period T expires, if VY_copy is still greater than VY (block 106), this means BL_Leak remains logic low. In response to BL_Leak remaining logic low when time period T expires, N-bit register 36 again increments the configuration bit by a given amount (block 107), thereby increasing the current Ivar, and waits for time period T again (back to block 105).

[0079] If these increases in Ivar are sufficient to make VY_copy equal to or less than VY, then ADC 35 activates the signal VY_Leak, which in turn activates the signal WL_Leak (at block 106) indicating that the current configuration bits will be stored in N-bit register 36. These configuration bits, activated for the first time by BL_Leak, allow the determination of leakage current from the selected positioning line. For example, if these configuration bits are greater than the set value, this means that the leakage current through the selected positioning line is greater than expected, and it can be inferred that the chip has suffered a process defect and should be discarded or packaged accordingly.

[0080] Therefore, N-bit register 36 will continuously increment the configuration bit, wait for a time period T, and read BL_Leak (e.g., repeat steps 107, 105, and 106) until BL_Leak becomes active. In some applications, BL_Leak may never become active, meaning that variable current source 27 cannot generate a current equal to the leakage current from the selected bit line—in this case, once N-bit register 36 increments the configuration bit to the level it is programmed to reach, and BL_Leak has not yet become active, it is also assumed that the chip has been affected by a process error. This process (blocks 106, 107, and 105) is repeated until all bit lines within the selected sector have been evaluated. The above operations can be performed on each sector Sector[0], ..., Sector[i] to test all chips on the wafer.

[0081] Now for reference Figure 10 Another embodiment of the non-volatile memory circuit 97 is described. (Compared to...) Figure 7 Unlike the non-volatile memory circuit 95, the non-volatile memory circuit 97 uses the aforementioned current mirror device 22 to draw current I2 (a copy of current I1) from the adjustable resistor R and copy current I1 as current I3 drawn from node N.

[0082] Therefore, the difference between the non-volatile memory circuit 97 and the non-volatile memory circuit 95 lies in the generation of currents I2 and I3. The actual operation of the non-volatile memory circuit 97 in performing the bit line leakage test is the same as described above.

[0083] Now for reference Figure 11 Another embodiment of the non-volatile memory circuit 97' is described. Note that the regulator 12' and the generation of currents I2 and I3 remain the same compared to the non-volatile memory circuit 97. The difference here is that instead of using a comparator to compare VY with VY_copy, the comparison is performed digitally by an analog-to-digital converter (ADC) 35. The ADC 35 has inputs connected to receive VY and VY_copy. The ADC 35 digitizes these voltages, compares them with each other, and generates BL_Leak as a unit digital signal indicating whether VY_copy is less than or equal to VY. BL_Leak is provided to an N-bit register 36, which generates configuration bits for the variable current source 27 based on BL_Leak.

[0084] Therefore, the difference between non-volatile memory circuit 97' and non-volatile memory circuit 97 is that non-volatile memory circuit 97' uses ADC 35 to compare VY and VY_copy instead of a comparator, and uses N-bit register 36 to generate configuration bits instead of a state machine. Apart from this, the actual operation of non-volatile memory circuit 97 performing bit-line leakage testing is the same as described above.

[0085] It should be understood that a given integrated circuit die may include a leakage detector arrangement for use in determining row decoder and word line leakage detection, as well as a leakage detector arrangement for use in determining bit line leakage detection.

[0086] In the above embodiments, replica currents I2 and I3, which are replicas of current I1, and replica current I3, which is a replica of current I2, are described. Note that in some applications, these replica currents can be scaled instead, in which case the variable current and the size of transistor MP2 are provided with equal scaling.

[0087] While this disclosure has been described with respect to a limited number of embodiments, those skilled in the art who benefit from this disclosure will understand that other embodiments can be conceived without departing from the scope of this disclosure. Therefore, the scope of this disclosure should be limited only by the appended claims.

Claims

1. An integrated circuit die comprising multiple memory sectors, each memory sector comprising a memory array, the integrated circuit die comprising: A voltage regulator comprising a first transistor driven by an output voltage to generate a gate voltage, the output voltage being generated based on the difference between a constant current and a leakage current; A selection circuit is configured to selectively couple the gate voltage to a selected one of the plurality of memory sectors; as well as Leakage current detector circuit, wherein the leakage current detector circuit is configured as follows: The second transistor is driven by the output voltage to generate a replica voltage based on the difference between the variable current and the replica of the constant current; In response to the replication voltage being greater than the gate voltage, the variable current is increased; as well as In response to the replication voltage being less than the gate voltage, a leakage detection signal is activated, the leakage detection signal indicating excessive leakage within the memory array of the selected memory sector.

2. The integrated circuit die of claim 1, wherein the leakage detector circuit is configured to detect excessive leakage within a line decoder of a selected memory sector by operating as follows: a) Deselect all word lines within the memory array of the selected memory sector; b) Set the variable current to have an amplitude within a zero threshold; c) In response to the replication voltage being greater than the gate voltage, increase the variable current by a given amount and wait for a given period of time; d) When the variable current increases by the given amount, causing the replication voltage to become less than the gate voltage, the leakage detection signal is activated, thereby indicating excessive leakage in the row decoder of the selected one in the memory sector; as well as e) If increasing the given amount of the variable current does not cause the replicated voltage to become less than the gate voltage, return to c).

3. The integrated circuit die of claim 2, wherein the leakage detector circuit is further configured to detect excessive leakage within a word line of a selected memory sector by operating as follows: f) Select a word line within the memory array of the selected sector of the memory while leaving the remaining word lines unselected; g) Wait for a given time period; h) When the selection of the word line causes the gate voltage to become less than the copy voltage, the leakage detection signal is disabled, thereby indicating excessive leakage in the selected word line of the selected one in the memory sector; as well as i) When the selection of the word line does not cause the gate voltage to become less than the replication voltage, the leakage detection signal is activated to indicate that there is no excessive leakage in the selected word line.

4. The integrated circuit die of claim 1, further comprising: A current source configured to generate the constant current; And a current mirror device configured to generate the copy of the constant current.

5. The integrated circuit die according to claim 1, wherein the leakage current detector circuit comprises: A variable current source, the variable current source being configured to generate the variable current in response to a control signal; A comparator configured to compare the gate voltage with the replication voltage, and to activate the leakage detection signal in response to the replication voltage being less than the gate voltage; as well as A control circuit configured to generate the control signal and increment the control signal in response to activating the leakage current detection signal.

6. The integrated circuit die of claim 1, wherein the voltage regulator comprises: A comparator configured to generate an output voltage based on a comparison between a reference voltage and a feedback voltage; as well as The first transistor has a control terminal coupled to receive the output voltage and a first conductive terminal at which the gate voltage is generated.

7. The integrated circuit die according to claim 6, further comprising: The second transistor has a control terminal coupled to receive the output voltage of the comparator from the voltage regulator, and has a first conductive terminal at which the replicated voltage is generated based on the difference between the replicas of the variable current and the constant current; The second transistor is a copy of the first transistor; A variable current source, which is coupled to the first conductive terminal of the second transistor and configured to generate the variable current in response to a control signal; A comparator having a non-inverting input, an inverting input, and an output, the non-inverting input being coupled to receive the gate voltage, the inverting input being coupled to the first conductive terminal of the second transistor, and the leakage detection signal being activated at the output in response to the replication voltage being less than the gate voltage; as well as A control circuit configured to generate the control signal and increment the control signal in response to activating the leakage current detection signal.

8. The integrated circuit die of claim 7, wherein the first transistor comprises a first PMOS transistor having a source, a drain, and a gate, the source of the first PMOS transistor being coupled to a power supply voltage, the gate voltage being generated at the drain of the first PMOS transistor, and the gate of the first PMOS transistor being coupled to receive the output voltage of the comparator; and wherein the second transistor comprises a second PMOS transistor having a source, a drain, and a gate, the source of the second PMOS transistor being coupled to a power supply voltage, the replication voltage being generated at the drain of the second PMOS transistor, and the gate of the second PMOS transistor being coupled to receive the output voltage of the comparator.

9. The integrated circuit die of claim 8, wherein the comparator of the voltage regulator includes a non-inverting terminal, an inverting terminal, and an output, the non-inverting terminal being coupled to receive a reference voltage, the inverting terminal being coupled to receive the feedback voltage, and the output voltage being generated at the output of the comparator; and wherein the voltage regulator further includes a resistor coupled between the drain of the first PMOS transistor and the inverting terminal of the comparator of the voltage regulator.

10. The integrated circuit die according to claim 9, further comprising: A current source, configured to generate the constant current; as well as A current mirror having an input, a first output, and a second output, the input being coupled to receive the constant current, a copy of the constant current being drawn into the first and second outputs, the first output being coupled to the resistor, and the second output being coupled to the inverting input of the comparator of the leakage detector.

11. The integrated circuit die of claim 7, further comprising: A current source configured to generate the constant current; And a current mirror device configured to generate the copy of the constant current.

12. The integrated circuit die according to claim 6, further comprising: The second transistor has a control terminal coupled to receive the output voltage of the comparator from the voltage regulator, and has a first conductive terminal at which the replicated voltage is generated based on the difference between the replicas of the variable current and the constant current; The second transistor is a copy of the first transistor; A variable current source, which is coupled to the first conductive terminal of the second transistor and configured to generate the variable current in response to a control signal; An analog-to-digital converter circuit is configured to digitize the gate voltage and the replication voltage, and then compare the gate voltage with the replication voltage to generate an active leakage detection signal in response to the replication voltage being less than the gate voltage, and to generate an inactive leakage detection signal in response to the replication voltage being greater than the gate voltage. as well as A control circuit configured to generate the control signal and increment the control signal in response to activating the leakage current detection signal.

13. The integrated circuit die according to claim 12, The first transistor includes a first PMOS transistor having a source, a drain, and a gate. The source of the first PMOS transistor is coupled to a power supply voltage, and the gate voltage is generated at the drain of the first PMOS transistor. The gate of the first PMOS transistor is coupled to receive the output voltage of the comparator of the voltage regulator. The second transistor includes a second PMOS transistor having a source, a drain, and a gate. The source of the second PMOS transistor is coupled to a power supply voltage, and the replica voltage is generated at the drain of the second PMOS transistor. The gate of the second PMOS transistor is coupled to receive the output voltage of the comparator of the voltage regulator. The comparator of the voltage regulator includes a non-inverting terminal, an inverting terminal, and an output. The non-inverting terminal is coupled to receive a reference voltage, the inverting terminal is coupled to receive the feedback voltage, and the output voltage is generated at the output. The voltage regulator also includes a resistor coupled between the drain of the first PMOS transistor and the inverting terminal of the comparator of the voltage regulator.

14. The integrated circuit die according to claim 13, further comprising: A current source, configured to generate the constant current; as well as A current mirror having an input, a first output, and a second output, the input being coupled to receive the constant current, a copy of the constant current being drawn into the first and second outputs, the first output being coupled to the resistor, and the second output being coupled to the inverting terminal of the comparator of the leakage current detector.

15. The integrated circuit die according to claim 12, further comprising: A current source configured to generate the copy of the constant current; And the voltage regulator is configured to generate the constant current.

16. The integrated circuit die according to claim 7, further comprising: A current source configured to generate the copy of the constant current; And the voltage regulator is configured to generate the constant current.

17. The integrated circuit die of claim 1, wherein the leakage detector circuit is configured to detect excessive leakage within a bit line of a selected memory sector by operating as follows: a) Deselect all word lines in the memory array of the selected sector of the memory array, and select one bit line in the memory array; b) Set the variable current to have an amplitude within a zero threshold; c) In response to the replication voltage being greater than the gate voltage, increase the variable current by a given amount and wait for a given period of time; d) When the variable current increases by the given amount, causing the replication voltage to become less than the gate voltage, the leakage detection signal is activated, thus causing excessive leakage in the bit line; as well as e) If increasing the given amount of the variable current does not cause the replicated voltage to become less than the gate voltage, return to c).

18. A method for testing an integrated circuit die comprising multiple memory sectors, each memory sector comprising a memory array, the method comprising: The output voltage is generated based on the difference between constant current and leakage current. The first transistor is driven by the output voltage to generate a gate voltage, which is a stable voltage; Connect the gate voltage to a selected one of the plurality of memory sectors; The second transistor is driven by the output voltage to generate a replica voltage based on the difference between the variable current and the replica of the constant current; In response to the replication voltage being greater than the gate voltage, the variable current is increased; as well as In response to the replication voltage being less than the gate voltage, a leakage detection signal is activated, the leakage detection signal indicating excessive leakage within the memory array of the selected memory sector.

19. The method of claim 18, further comprising detecting excessive leakage current within the line decoder of the selected one of the plurality of memory sectors by: a) Deselect all word lines within the memory array of the selected memory sector; b) Set the variable current to have an amplitude within a zero threshold; c) In response to the replication voltage being greater than the gate voltage, increase the variable current by a given amount and wait for a given period of time; d) When the variable current increases by the given amount, causing the replication voltage to become less than the gate voltage, the leakage detection signal is activated, thereby indicating excessive leakage in the row decoder of the selected one in the memory sector; as well as e) If increasing the given amount of the variable current does not cause the replicated voltage to become less than the gate voltage, return to step c).

20. The method of claim 18, further comprising detecting excessive leakage current within a word line of the selected one of the memory sectors by: f) Select a word line within the memory array of the selected sector of the memory while leaving the remaining word lines unselected; g) Wait for a given time period; h) When the selection of the word line causes the gate voltage to become less than the copy voltage, the leakage detection signal is disabled, thereby indicating excessive leakage in the selected word line of the selected one in the memory sector; as well as i) When the selection of the word line does not cause the gate voltage to become less than the replication voltage, the leakage detection signal is activated to indicate that there is no excessive leakage in the selected word line.

21. The method of claim 18, wherein detecting excessive leakage current in a bit line of the selected one of the memory sectors comprises: a) Deselect all word lines in the memory array of the selected sector of the memory array, and select one bit line in the memory array; b) Set the variable current to have an amplitude within a zero threshold; c) In response to the replication voltage being greater than the gate voltage, increase the variable current by a given amount and wait for a given period of time; d) When the variable current increases by the given amount, causing the replication voltage to become less than the gate voltage, the leakage detection signal is activated, thus causing excessive leakage in the bit line; as well as e) If increasing the given amount of the variable current does not cause the replicated voltage to become less than the gate voltage, return to c).

Images