Method for reducing floating gate polysilicon loss in flash memory devices

Abstract

The application provides a method for reducing loss of floating gate polysilicon of a flash memory device, and the method comprises the following steps: providing a semiconductor structure, which comprises a floating gate polysilicon layer, a hard mask layer and a shallow trench isolation structure, wherein the shallow trench isolation structure comprises a first shallow trench isolation structure and a second shallow trench isolation structure; performing wet etching on the shallow trench isolation structure; forming a mask layer in a peripheral device area to protect the second shallow trench isolation structure, and performing a first etching process with a first etching depth and a second etching process with a second etching depth on the first shallow trench isolation structure; removing the mask layer, and performing a third etching process with a third etching depth on the first shallow trench isolation structure and the second shallow trench isolation structure; and removing the hard mask layer by wet etching. The application solves the problem of excessive loss of floating gate polysilicon caused by the existing method for adjusting the height difference between the shallow trench isolation structure and the floating gate polysilicon.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for reducing polysilicon loss in floating gates of flash memory devices. Background Technology

[0002] ETOX (EPROM with Tunnel Oxide or Erasable Programmable Read Only Memory with Tunnel Oxide) NOR flash memory is a type of non-volatile flash memory. Its characteristic is that applications can run directly in the flash memory without having to read the code into the system random access memory, thus giving it high transfer efficiency. Therefore, this type of flash memory is widely used.

[0003] In the process of fabricating ETOX NOR flash memory devices using SAP (Self-Align Poly), the floating gate is already formed before CRS etching. Therefore, when the etching process is performed to form the step height difference between the shallow trench isolation structure and the floating gate polysilicon layer, it will lead to an increase in the loss of floating gate polysilicon and a deterioration in the overall uniformity of the device structure. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for reducing the loss of floating gate polysilicon in flash memory devices, in order to solve the problem that the existing method of adjusting the height difference between the shallow trench isolation structure and the floating gate polysilicon step causes a large loss of floating gate polysilicon.

[0005] To achieve the above and other related objectives, the present invention provides a method for reducing polysilicon loss in floating gate flash memory devices, the method comprising:

[0006] A semiconductor structure is provided, including a floating gate polysilicon layer, a hard mask layer, and a shallow trench isolation structure, wherein the hard mask layer is formed on the surface of the floating gate polysilicon layer, the shallow trench isolation structure passes through the floating gate polysilicon layer and the hard mask layer, and includes a first shallow trench isolation structure and a second shallow trench isolation structure, wherein the first shallow trench isolation structure is located in a memory device region, and the second shallow trench isolation structure is located in a peripheral device region;

[0007] The shallow trench isolation structure is subjected to wet etching;

[0008] A mask layer is formed in the peripheral device area to protect the second shallow trench isolation structure, and the first shallow trench isolation structure is subjected to a first etching process with a first etching depth and a second etching process with a second etching depth using the hard mask layer as a mask.

[0009] Remove the mask layer and use the hard mask layer as a mask to perform a third etching process with a third etching depth on the first shallow trench isolation structure and the second shallow trench isolation structure.

[0010] The hard mask layer is removed by wet etching.

[0011] Optionally, the first etching depth is 150 angstroms to 200 angstroms; the second etching depth is 450 angstroms to 500 angstroms; and the third etching depth is 100 angstroms to 150 angstroms.

[0012] Optionally, the hard mask layer may be made of silicon nitride.

[0013] Optionally, the first etching process is dry etching; the second etching process is wet etching; and the third etching process is dry etching.

[0014] Optionally, the mask layer is made of photoresist.

[0015] Optionally, the photoresist is a negative photoresist.

[0016] Optionally, the mask layer can be removed using dry etching or wet etching processes.

[0017] Optionally, before wet etching the shallow trench isolation structure, the method includes a step of chemical mechanical polishing the shallow trench isolation structure.

[0018] Optionally, the semiconductor structure further includes a semiconductor substrate and a tunneling oxide layer, wherein the tunneling oxide layer is formed on the surface of the semiconductor substrate, and the floating gate polysilicon layer is formed on the surface of the tunneling oxide layer, and the bottom of the shallow trench isolation structure is located inside the semiconductor substrate.

[0019] As described above, the method for reducing floating gate polysilicon loss in flash memory devices according to the present invention involves using a hard mask layer as a mask to perform two dry etching processes on the shallow trench isolation structure, and finally removing the hard mask layer to form a step height difference between the shallow trench isolation structure and the floating gate polysilicon. This method reduces floating gate polysilicon loss, effectively improves the uniformity of the floating gate polysilicon morphology, thereby improving the stability of the PGM (Programming Mode) or ERS (Eraser Mode) voltage (Vt). Furthermore, this method reduces the impact of plasma on the floating gate polysilicon during dry etching, improving the device's PGM efficiency or ERS efficiency, thereby enhancing device performance. Attached Figure Description

[0020] Figures 1-4 The diagram shows a cross-sectional view of the process for adjusting the height difference between the steps of the existing floating gate polysilicon and the shallow trench isolation structure.

[0021] Figure 5 The flowchart shown is a method for reducing polysilicon loss in floating gates of flash memory devices according to the present invention.

[0022] Figures 6 to 11 The diagram shows a cross-sectional view of the process of adjusting the height difference between the floating gate polysilicon and the shallow trench isolation structure steps according to the present invention.

[0023] Explanation of icon numbers

[0024] 10, 20: Semiconductor structure; 11, 24: Semiconductor substrate; 12, 25: Tunneling oxide layer; 13, 21: Floating gate polysilicon layer; 14: Silicon nitride layer; 15, 23: Shallow trench isolation structure; 151, 231: First shallow trench isolation structure; 152, 232: Second shallow trench isolation structure; 16: Photoresist layer; 22: Hard mask layer; 30: Mask layer Detailed Implementation

[0025] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0026] Please see Figures 1 to 11 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation, the shape, quantity and proportion of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0027] Existing methods for adjusting the step height difference between shallow trench isolation structures and floating gate polysilicon layers include: providing a semiconductor structure 10, the semiconductor structure 10 including a semiconductor substrate 11, a tunneling oxide layer 12, a floating gate polysilicon layer 13, a silicon nitride layer 14, and a shallow trench isolation structure 15, the shallow trench isolation structure 15 including a first shallow trench isolation structure 151 located in the memory device region A and a second shallow trench isolation structure 152 located in the peripheral device region B (e.g., Figure 1 As shown), first remove the silicon nitride layer 14 formed on the surface of the floating gate polysilicon layer 13, and then use the photoresist layer 16 to protect the second shallow trench isolation structure 152 (as shown). Figure 2 As shown), and the first shallow trench isolation structure 151 is etched for the first and second times (as shown). Figure 3(As shown), then, the photoresist layer 16 is removed, and the first shallow trench isolation structure 151 is etched for the third time, while the second shallow trench isolation structure 152 is etched for the first time (as shown). Figure 4 (As shown).

[0028] However, when the critical size of the floating gate is large, the loss of floating gate polysilicon caused by adjusting the step height difference between the floating gate polysilicon and the shallow trench isolation structure using the above method is negligible. But as the process node shrinks and the critical size of the floating gate decreases, if the above method is still used to adjust the step height difference between the shallow trench isolation structure and the floating gate polysilicon layer, the loss of floating gate polysilicon will increase and the overall uniformity of the floating gate polysilicon will deteriorate.

[0029] like Figure 5 As shown, this embodiment provides a method for reducing polysilicon loss in floating gate flash memory devices, the method comprising:

[0030] A semiconductor structure 20 is provided, including a floating gate polysilicon layer 21, a hard mask layer 22, and a shallow trench isolation structure 23. The hard mask layer 22 is formed on the surface of the floating gate polysilicon layer 21, and the shallow trench isolation structure 23 passes through the floating gate polysilicon layer 21 and the hard mask layer 22. It includes a first shallow trench isolation structure 231 and a second shallow trench isolation structure 232. The first shallow trench isolation structure 231 is located in a memory device region A, and the second shallow trench isolation structure 232 is located in a peripheral device region B.

[0031] The second shallow trench isolation structure 23 is wet-etched;

[0032] A mask layer 30 is formed in the peripheral device area B to protect the second shallow trench isolation structure 231, and the first shallow trench isolation structure 231 is subjected to a first etching process with a first etching depth and a second etching process with a second etching depth using the hard mask layer 22 as a mask.

[0033] Remove the mask layer 30, and use the hard mask layer 22 as a mask to perform a third etching process with a third etching depth on the first shallow trench isolation structure 231 and the second shallow trench isolation structure 232.

[0034] The hard mask layer 22 is removed by wet etching.

[0035] Specifically, the semiconductor structure 20 further includes a semiconductor substrate 24 and a tunneling oxide layer 25. The tunneling oxide layer 25 is formed on the surface of the semiconductor substrate 24. At this time, the floating gate polysilicon layer 21 is formed on the surface of the tunneling oxide layer 25, and the bottom of the shallow trench isolation structure 23 is located inside the semiconductor substrate 24.

[0036] like Figure 6 As shown, in this embodiment, the semiconductor substrate 24 includes undoped single-crystal silicon, doped single-crystal silicon, or silicon-on-insulator (SOI). Optionally, in this embodiment, the semiconductor substrate 24 is selected as P-type doped single-crystal silicon. The tunneling oxide layer 25 is made of silicon oxide. Furthermore, in this embodiment, the depth of the first shallow trench isolation structure 231 located in the memory device region A is less than the depth of the second shallow trench isolation structure 232 located in the peripheral device region B.

[0037] Specifically, the first etching process is dry etching; the second etching process is wet etching; and the third etching process is dry etching.

[0038] In this embodiment, the etching gas used in the dry etching process includes a mixture of NF3 and NH3 or a mixture of H2 and NF3. The mixture is converted into plasma containing fluoride ions, hydrofluoric acid ions, and NH4 ions. The plasma is then introduced into the etching chamber to react with the filler in the shallow trench isolation structure 23 to generate a volatile complex. Finally, the complex is discharged from the etching chamber to achieve etching of the first shallow trench isolation structure 231 and the second shallow trench isolation structure 232.

[0039] Specifically, before wet etching the shallow trench isolation structure 23, the method includes a step of chemical mechanical polishing the shallow trench isolation structure 23.

[0040] Specifically, the first etching depth is 150 angstroms to 200 angstroms; the second etching depth is 450 angstroms to 500 angstroms; and the third etching depth is 100 angstroms to 150 angstroms.

[0041] like Figures 7-10 As shown, in this embodiment, when the hard mask layer 22 is present, after performing a wet etching process on the first shallow trench isolation structure 231 and the second shallow trench isolation structure 232, the first shallow trench isolation structure 231 is subjected to a three-stage etching process (two dry etching processes and one wet etching process), and the second shallow trench isolation structure 232 is subjected to a single etching process (dry etching) to form a step height difference between the first shallow trench isolation structure 231 and the second shallow trench isolation structure 232 and the floating gate polysilicon layer.

[0042] Specifically, the hard mask layer 22 is made of silicon nitride.

[0043] like Figure 11 As shown, in this embodiment, the etching solution used when removing the silicon nitride using a wet etching process is hot phosphoric acid.

[0044] Specifically, the mask layer 30 is made of photoresist.

[0045] As an example, the photoresist is a negative photoresist.

[0046] In this embodiment, since the mask layer 30 formed on the storage device region A needs to be removed during the first etching process to expose the first shallow trench isolation structure 231, and the storage device region A occupies a large area, the good adhesion of the negative adhesive can be utilized to present a better development effect.

[0047] Specifically, the mask layer 30 is removed using both dry etching and wet etching processes. In this embodiment, the mask layer 30 can be removed using both dry etching and wet etching processes, which means the negative resist can be removed using both dry etching and wet etching processes. Moreover, when removing the mask layer 30, dry etching can be performed first, followed by wet etching.

[0048] In summary, the method for reducing floating gate polysilicon loss in flash memory devices according to the present invention involves using a hard mask layer as a mask to perform two dry etching processes on the shallow trench isolation structure, and finally removing the hard mask layer to create a step height difference between the shallow trench isolation structure and the floating gate polysilicon. This method reduces floating gate polysilicon loss, effectively improves the uniformity of the floating gate polysilicon morphology, and thus improves the stability of the PGM (Programming Mode) or ERS (Eraser Mode) voltage (Vt). Furthermore, this method reduces the impact of plasma on the floating gate polysilicon during dry etching, improving the device's PGM efficiency or ERS efficiency, thereby enhancing device performance. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0049] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for reducing polysilicon loss in floating gate flash memory devices, characterized in that, The method includes: A semiconductor structure is provided, including a floating gate polysilicon layer, a hard mask layer, and a shallow trench isolation structure, wherein the hard mask layer is formed on the surface of the floating gate polysilicon layer, the shallow trench isolation structure passes through the floating gate polysilicon layer and the hard mask layer, and includes a first shallow trench isolation structure and a second shallow trench isolation structure, wherein the first shallow trench isolation structure is located in a memory device region, and the second shallow trench isolation structure is located in a peripheral device region; Wet etching is performed on the first shallow trench isolation structure and the second shallow trench isolation structure; A mask layer is formed in the peripheral device area to protect the second shallow trench isolation structure, and the first shallow trench isolation structure is first subjected to a dry etching process with a first etching depth and then a wet etching process with a second etching depth using the hard mask layer as a mask. The mask layer is removed, and the first shallow trench isolation structure and the second shallow trench isolation structure are subjected to a dry etching process with a third etching depth using the hard mask layer as a mask. The hard mask layer is removed by wet etching.

2. The method for reducing polysilicon loss in floating gate flash memory devices according to claim 1, characterized in that, The first etching depth is 150 angstroms to 200 angstroms; the second etching depth is 450 angstroms to 500 angstroms; and the third etching depth is 100 angstroms to 150 angstroms.

3. The method for reducing polysilicon loss in floating gate flash memory devices according to claim 1, characterized in that, The material of the hard mask layer includes silicon nitride.

4. The method for reducing polysilicon loss in floating gate flash memory devices according to any one of claims 1 to 3, characterized in that, The mask layer is made of photoresist.

5. The method for reducing polysilicon loss in floating gate flash memory devices according to claim 4, characterized in that, The photoresist is a negative photoresist.

6. The method for reducing polysilicon loss in floating gate flash memory devices according to claim 5, characterized in that, The mask layer is removed using both dry and wet etching processes.

7. The method for reducing polysilicon loss in floating gate flash memory devices according to claim 1, characterized in that, Before wet etching the shallow trench isolation structure, the method includes a step of chemical mechanical polishing the shallow trench isolation structure.

8. The method for reducing polysilicon loss in floating gate flash memory devices according to claim 1, characterized in that, The semiconductor structure further includes a semiconductor substrate and a tunneling oxide layer. The tunneling oxide layer is formed on the surface of the semiconductor substrate. At this time, the floating gate polysilicon layer is formed on the surface of the tunneling oxide layer, and the bottom of the shallow trench isolation structure is located inside the semiconductor substrate.

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