Print head control circuit and liquid ejection device

Abstract

The present invention provides a print head control circuit that can reduce the possibility of malfunction in the print head, which enables the print head to perform printing, and the print head performs abnormality detection based on a first signal input to the second terminal when the potential of the first terminal is the first potential and a second signal input to the second terminal when the potential of the first terminal is the second potential, one of the first potential and the second potential is higher than the potential of the first signal and the second signal, and the signal circuit that outputs the first signal and the second signal outputs the first signal to the second wiring electrically connected to the second terminal while supplying a first voltage signal of the first potential to the first wiring electrically connected to the first terminal, and after outputting the first signal, and while supplying a second voltage signal of a second potential different from the first potential to the first wiring, outputs the second signal to the second wiring, and performs abnormality detection based on the first signal, the second signal, the first voltage signal, and the second voltage signal.

Description

Technical Field

[0001] The invention relates to a print head control circuit and a liquid ejection device. Background Art

[0002] Liquid ejection devices such as inkjet printers drive piezoelectric elements provided on print heads using drive signals, thereby ejecting liquids such as ink filled in chambers from nozzles to form text or images on a medium. In such liquid ejection devices, if the print head malfunctions, the ejection accuracy of the liquid is reduced, and the quality of the text or image formed on the medium is reduced.

[0003] As a technique for detecting malfunction of a print head that is a major cause of such reduction in ejection accuracy, Patent Document 1 discloses a technique for diagnosing the presence or absence of abnormality in the print head itself based on a control signal input to the print head.

[0004] [Prior art literature]

[0005] [Patent Document]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 2017-114020

[0007] One of the main causes of malfunction in a print head of a liquid ejection device is malfunction caused by a decrease in the accuracy of a signal supplied to the print head. In a liquid ejection device, in addition to a low voltage signal input to the print head for controlling the operation of the print head, a high voltage signal for driving a driving element to the extent of ejecting liquid is also input. In order to reduce the possibility of malfunction in the print head, it is required to normally supply both a high voltage signal and a low voltage signal to the print head. In contrast, in the invention described in patent document 1, there is no description of a technique for detecting whether both a high voltage signal and a low voltage signal supplied to the print head are normal for the purpose of reducing the possibility of malfunction in the print head. Therefore, there is room for improvement in terms of reducing the possibility of malfunction in the print head.

[0008] In addition, in a liquid ejection device, there is a situation where a part of the liquid ejected from the nozzle to form an image on the medium is atomized before being ejected on the medium and floats inside the liquid ejection device as liquid mist. Furthermore, even after the liquid ejected from the nozzle is ejected on the medium, due to the airflow generated by the transportation of the medium, there is a situation where it floats inside the liquid ejection device again as liquid mist. Since the liquid mist floating inside such a liquid ejection device is very small, it is charged due to the Lenard effect and is guided to the conductive parts such as wiring patterns and terminals that transmit various signals. In a liquid ejection device, since the print head ejects liquid to the medium, a large amount of liquid mist floats near the print head. Therefore, a large amount of liquid mist adheres to the wiring cable or terminal that transmits various signals to the print head, and as a result, the possibility of short circuit abnormality and the like due to the liquid mist increases. Therefore, from the perspective of reducing the possibility of malfunction in the print head, it is strongly required to accurately detect whether the high voltage signal and the low voltage signal supplied to the print head are normal in the liquid ejection device that is worried about the influence of the liquid mist, and control the print head. Summary of the invention

[0009] One embodiment of the print head control circuit according to the present invention is:

[0010] A print head control circuit that causes a print head to perform printing, the print head detecting abnormality based on a first signal input to a second terminal when a potential of a first terminal is a first potential and a second signal input to the second terminal when a potential of the first terminal is a second potential, the print head control circuit comprising:

[0011] a signal circuit, which outputs the first signal and the second signal;

[0012] a first wiring electrically connected to the first terminal; and

[0013] a second wiring electrically connected to the second terminal,

[0014] At least one of the first potential and the second potential is higher than potentials of the first signal and the second signal,

[0015] The signal circuit outputs the first signal to the second wiring while supplying the first voltage signal of the first potential to the first wiring, and after outputting the first signal, outputs the second signal to the second wiring while supplying the first voltage signal of the second potential different from the first potential to the first wiring, and causes the print head to perform the abnormality detection based on the first signal, the second signal, the first voltage signal and the second voltage signal.

[0016] One aspect of the liquid ejection device according to the present invention comprises:

[0017] a print head, which performs printing; and

[0018] a print head control circuit that causes the print head to perform printing,

[0019] The print head detects abnormality based on a first signal input to a second terminal when the potential of the first terminal is a first potential and a second signal input to the second terminal when the potential of the first terminal is a second potential.

[0020] The print head control circuit has:

[0021] a signal circuit, which outputs the first signal and the second signal;

[0022] a first wiring electrically connected to the first terminal; and

[0023] a second wiring electrically connected to the second terminal,

[0024] At least one of the first potential and the second potential is higher than potentials of the first signal and the second signal,

[0025] The signal circuit outputs the first signal to the second wiring while supplying the first voltage signal of the first potential to the first wiring, and after outputting the first signal, outputs the second signal to the second wiring while supplying the first voltage signal of the second potential different from the first potential to the first wiring, and causes the print head to perform the abnormality detection based on the first signal, the second signal, the first voltage signal and the second voltage signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a diagram showing the functional structure of the liquid ejecting device.

[0027] Figure 2 It is a diagram showing the functional structure of a driving circuit.

[0028] Figure 3 This is a diagram showing the functional structure of a print head.

[0029] Figure 4 FIG. 1 is a diagram showing an example of a signal waveform of a driving signal.

[0030] Figure 5 FIG. 1 is a diagram showing an example of a signal waveform of a driving signal.

[0031] Figure 6 2 is a diagram showing the functional structure of a drive signal selection circuit.

[0032] Figure 7 This is a diagram showing an example of decoded content.

[0033] Figure 8 It is a diagram showing the structure of a selection circuit.

[0034] Fig. 9 It is a diagram for explaining the operation of the drive signal selection circuit.

[0035] Fig.10 It is a diagram showing a schematic structure of a liquid ejecting device.

[0036] Fig.11 It is a diagram showing an example of the structure of the discharge control unit.

[0037] Fig.12 This is a diagram showing an example of the configuration of the print head.

[0038] Fig.13 This is a diagram showing an example of the structure of a print head.

[0039] Fig.14 This is a diagram showing an example of the structure of a wiring board.

[0040] Fig.15 It is a diagram showing a schematic structure of a head chip.

[0041] Fig.16 It is a diagram showing a schematic structure of a cable.

[0042] Fig.17 It is a diagram showing a schematic structure of a connector.

[0043] Fig.18 This is a diagram showing an example of a case where a cable is attached to a connector.

[0044] Fig.19 It is a diagram showing the functional structure of the abnormality detection circuit.

[0045] Fig. 20 This is a diagram showing an example of the operation of the abnormality detection circuit when the signal supplied to the print head is normal.

[0046] Fig.21 This is a diagram showing an example of the operation of the abnormality detection circuit when the signal supplied to the print head is normal.

[0047] Fig. 22 This is a diagram showing an example of the operation of the abnormality detection circuit when the signal supplied to the print head is abnormal.

[0048] Fig.23This is a diagram showing an example of the operation of the abnormality detection circuit when the signal supplied to the print head is abnormal.

[0049] Fig.24 This is a diagram showing a method for inspecting a print head in a liquid ejecting device.

[0050] Fig.25 This is a diagram showing an example of the determination process.

[0051] Fig.26 This is a diagram showing an example of an allowed process.

[0052] Fig. 27 It is a diagram showing the functional structure of the print head according to the second embodiment.

[0053] Fig.28 It is a diagram showing the functional structure of a print head according to the third embodiment.

[0054] [Description of symbols]

[0055] 1: liquid ejection device; 2: print head drive circuit; 3: external device; 5: liquid container; 7: commercial AC power supply; 8: pump; 10: main control unit; 11: main control circuit; 12: power supply voltage output circuit; 20: ejection control unit; 21: ejection control circuit; 22-1 to 22-m: differential signal recovery circuit; 35: support member; 40: conveying mechanism; 50: drive voltage output circuit; 51a, 51b: drive circuit; 53: reference voltage output circuit; 60: piezoelectric element; 100: print head; 110: filter unit; 113: filter; 115, 117: opening; 120: sealing member; 123: through opening; 125, 127: opening; 130: cloth Wire substrate; 135: cutout; 136: FPC through hole; 137: FPC cutout; 138: connection terminal; 140: bracket; 141-143: bracket member; 145: liquid flow path; 146: slit hole; 150: fixing plate; 151: plane portion; 152-154: bending portion; 155: opening; 191, 192: short side; 193, 194: long side; 200: drive signal selection circuit; 201: semiconductor device; 210: selection control circuit; 212: register; 214: latch circuit; 216: decoder; 230: selection circuit; 232a, 232b: inverter; 234a, 234b: transmission gate; 250: abnormality detection circuit; 251: Voltage input switching circuit; 300: head chip; 310: nozzle plate; 321: flow path forming substrate; 322: pressure chamber substrate; 323: protection substrate; 324: housing; 330: flexible portion; 331: sealing film; 332: support body; 340: vibration plate; 346: flexible wiring substrate; 351-353: opening; 355: connecting flow path; 360: ink flow path; 361: liquid inlet; 363: separate flow path; 365: connecting flow path; 367: liquid reservoir; 369: pressure chamber; 400: substrate; 401, 402: surface; 403-406: edge; 410: wiring substrate; 411, 412: surface; 413: connection portion; 420: wiring substrate; 421, 422 : surface; 423-427: connection part; 428, 450: semiconductor device; 451: determination control circuit; 452: voltage determination circuit; 453: output switching circuit; 454: storage circuit; 500: integrated circuit; 510: modulation circuit; 512, 513: adder; 514: comparator; 515: inverter; 516: integral attenuator; 517: attenuator; 520: gate drive circuit; 521, 522: gate driver; 550: amplifier circuit; 560: smoothing circuit; 570, 572: feedback circuit; 580: power supply circuit; 600: ejection part; 651: nozzle; AD1: air outlet; AS1, AS2: air inlet; C1-C6: capacitor;CI: cable installation part; CN, CN1, CN2: connector; Cnt: contact part; D1: diode; EC: insulator; EL1: cable holding part; EL2: shell penetration part; EL3: substrate installation part; ER1, ER2: terminal; FC, FC1, FC2: cable; G1: inlet flow path part; G2: supply control part; G3: head support part; G4: ejection control part; HP: shell; ID1: liquid discharge port; IS1~IS3: liquid introduction port; L1: coil; M1, M2, M10, M11: transistor; P: medium; P-CH, P-HS1, P-LAT, P- SCK, P-SI1, P-VDR1, P-VDR2: wiring; R1~R6, R10~R13: resistors; SW: switch group; TM, TM-CH, TM-ES, TM-LAT, TM-SCK, TM-VDD, TM-VDR1, TM-VDR2, TM-VHV: terminals; U: pressure adjustment unit; WI, WI-CH, WI-ES, WI-LAT, WI-SCK, WI-VDD, WI-VDR1, WI-VDR2, WI-VHV: wiring; c1, c2: judgment information; r1, r2: result information; st: stop information. ; DETAILED DESCRIPTION

[0056] Hereinafter, preferred embodiments of the present invention will be described using the accompanying drawings. The accompanying drawings used are for the convenience of description. In addition, the embodiments described below do not unduly limit the contents of the present invention as described in the claims. In addition, all the structures described below are not necessarily necessary constituent conditions of the present invention.

[0057] In the following description, a so-called inkjet printer that forms a desired image on a medium by ejecting ink as an example of a liquid onto the medium is described as an example of a liquid ejecting device, but the liquid ejecting device is not limited to an inkjet printer. For example, it may also be a color material ejecting device used in the manufacture of color filters for liquid crystal displays, etc., an electrode material ejecting device used in the formation of electrodes for organic EL displays, surface luminous displays, etc., and a biological organic matter ejecting device used in the manufacture of biochips.

[0058] Furthermore, in the following description, the inkjet printer serving as the liquid ejection device in the present embodiment will be described as a so-called line head type inkjet printer, in which a print head for ejecting ink is arranged to be larger than the width of a medium being transported, and a desired image is formed on the medium by ejecting ink from the print head in synchronization with the transport of the medium. However, the inkjet printer serving as a liquid ejection device may also be a serial head type inkjet printer having a carriage equipped with a print head for ejecting ink, and the carriage reciprocates in a direction intersecting the transport direction of the medium in synchronization with the transport of the medium, thereby forming a desired image on the medium.

[0059] Here, in describing the present embodiment, the logic level on the high potential side of the digital signal is referred to as a high level or an H level, and the logic level on the low potential side of the digital signal is referred to as a low level or an L level.

[0060] 1. First Implementation

[0061] 1.1 Functional structure of liquid ejection device

[0062] use Figure 1 The functional structure of the liquid ejecting device 1 will be described. Figure 1 1 is a diagram showing the functional structure of the liquid ejection device 1. Figure 1 As shown, the liquid ejection device 1 includes a print head driving circuit 2 and m print heads 100. In addition, the print head driving circuit 2 includes a main control unit 10 that inputs various signals from the outside of the liquid ejection device 1 and an ejection control unit 20 that outputs various signals to the m print heads 100. Moreover, the print head driving circuit 2 drives the m print heads 100 based on the signals input from the outside of the liquid ejection device 1. Here, in the following description, when it is necessary to distinguish the m print heads 100, they are sometimes referred to as print heads 100-1 to 100-m. Here, m is an integer greater than 1 that is equivalent to the number of print heads 100 included in the liquid ejection device 1.

[0063] The main control unit 10 includes a main control circuit 11 and a power supply voltage output circuit 12 .

[0064] An AC voltage AC as a commercial AC voltage is input to the power voltage output circuit 12 from a commercial AC power source (not shown) provided outside the liquid ejection device 1. The power voltage output circuit 12 generates a voltage VHV as a DC voltage with a voltage value of 42V and a voltage VDD as a DC voltage with a voltage value of 3.3V based on the input AC voltage AC. That is, the power voltage output circuit 12 is an AC / DC converter that converts the AC voltage AC into a voltage VHV as a DC voltage, and is, for example, configured to include an insulating flyback circuit that generates the voltage VHV and a step-down converter that generates the voltage VDD by reducing the voltage VHV. Moreover, the power voltage output circuit 12 supplies the generated voltages VHV and VDD to each part of the liquid ejection device 1 including the main control unit 10, the ejection control unit 20, and the m print heads 100.

[0065] Here, the power supply voltage output circuit 12 may generate DC voltages of various voltage values ​​in addition to the voltages VHV and VDD, and supply the DC voltages to the respective parts of the liquid ejection device 1 including the main control unit 10, the ejection control unit 20, and the m print heads 100. The main control unit 10, the ejection control unit 20, and the m print heads 100 operate using the voltages VHV and VDD as power supply voltages or control voltages.

[0066] The main control circuit 11 receives image data PD including image information formed on a medium from an external device such as a host computer provided outside the liquid ejection device 1. The main control circuit 11 generates an image information signal IP by performing a predetermined image processing on the received image data PD. Then, the main control circuit 11 outputs the generated image information signal IP to the ejection control unit 20. The image information signal IP output from the main control circuit 11 may be, for example, an electrical signal capable of high-speed communication such as a differential signal, or an optical signal for optical communication. Here, the image processing performed by the main control circuit 11 includes, for example, a color conversion process of converting the input image signal into red, green, and blue color information and then converting it into color information corresponding to the color of the ink ejected from the liquid ejection device 1, a halftone process of binarizing the color information formed by the color conversion process, and the like. In addition, the image processing performed by the main control circuit 11 is not limited to the above-mentioned color conversion process or halftone process. Such a main control circuit 11 is one or more semiconductor devices having multiple functions, and may be configured to include, for example, a SoC (System on a Chip).

[0067] The discharge control unit 20 includes a discharge control circuit 21 , differential signal restoration circuits 22 - 1 to 22 - m , and a drive voltage output circuit 50 .

[0068] The discharge control circuit 21 receives the image information signal IP outputted from the main control circuit 11. Based on the image information signal IP inputted from the main control circuit 11, the discharge control circuit 21 generates and outputs various signals for controlling the operations of each part of the discharge control unit 20 and the m print heads 100.

[0069] Specifically, the ejection control circuit 21 generates differential signals dHC1 to dHCm, differential signals dSI11 to dSI1n, ..., dSIm1 to dSImn, and differential signals dSCK1 to dSCKm corresponding to control signals for controlling the ejection of ink from the m print heads 100 based on the image information signal IP. Then, the ejection control circuit 21 outputs the generated differential signals dHC1 to dHCm, differential signals dSI11 to dSI1n, ..., dSIm1 to dSImn, and differential signals dSCK1 to dSCKm to the corresponding differential signal restoration circuits 22-1 to 22-m.

[0070] The differential signal restoration circuits 22-1 to 22-m respectively restore the input differential signals dHC1 to dHCm, differential signals dSI11 to dSI1n, ..., dSIm1 to dSImn, and differential signals dSCK1 to dSCKm, thereby generating single-ended diagnostic control signals HC1 to HCm, printing data signals SI11 to SI1n, ..., SIm1 to SImn, and clock signals SCK1 to SCKm. Then, the differential signal restoration circuits 22-1 to 22-m respectively output the generated diagnostic control signals HC1 to HCm, printing data signals SI11 to SI1n, ..., SIm1 to SImn, and clock signals SCK1 to SCKm to the corresponding m print heads 100.

[0071] Specifically, the ejection control circuit 21 generates a differential signal dHC1 including a pair of signals dHC1+ and dHC1-, a differential signal dSI11 to dSI1n including a pair of signals dSI11+ to dSI1n+ and dSI11- to dSI1n-, and a differential signal dSCK1 including a pair of signals dSCK1+ and dSCK1- based on the image information signal IP, and outputs the signals to the differential signal restoration circuit 22-1. The differential signal restoration circuit 22-1 restores the differential signal dHC1 to generate the diagnosis control signal HC1 as a single-ended signal, restores the differential signal dSCK1 to generate the clock signal SCK1 as a single-ended signal, and restores the differential signals dSI11 to dSI1n to generate the printing data signals SI11 to SI1n as single-ended signals. Then, the differential signal restoration circuit 22 - 1 outputs the generated diagnosis control signal HC1 , clock signal SCK1 , and print data signals SI11 to SI1 n to the print head 100 - 1 .

[0072] In addition, the ejection control circuit 21 generates a differential signal dHCm including a pair of signals dHCm+ and dHCm-, a differential signal dSIm1 to dSImn including a pair of signals dSIm1+ to dSImn+ and dSIm1- to dSImn-, and a differential signal dSCKm including a pair of signals dSCKm+ and dSCKm- based on the image information signal IP, and outputs them to the differential signal restoration circuit 22-m. The differential signal restoration circuit 22-m restores the differential signal dHCm to generate the diagnosis control signal HCm as a single-ended signal, restores the differential signal dSCKm to generate the clock signal SCKm as a single-ended signal, and restores the differential signals dSIm1 to dSImn to generate the printing data signals SIm1 to SImn as single-ended signals. Then, the differential signal restoration circuit 22 - m outputs the generated diagnosis control signal HCm, clock signal SCKm, and print data signals SIm1 to SImn to the print head 100 - m.

[0073] That is, the ejection control circuit 21 generates a differential signal dHCi including a pair of signals dHCi+ and dHCi- (i is any integer from 1 to m), a differential signal dSIi1 to dSIin including a pair of signals dSIi1+ to dSIin+ and dSIi1- to dSIin-, and a differential signal dSCKi including a pair of signals dSCKi+ and dSCKi- based on the image information signal IP, and outputs them to the differential signal restoration circuit 22-i. The differential signal restoration circuit 22-i generates the diagnosis control signal HCi as a single-ended signal by restoring the differential signal dHCi, generates the clock signal SCKi as a single-ended signal by restoring the differential signal dSCKi, and generates the printing data signals SIi1 to SIin as single-ended signals by restoring the differential signals dSIi1 to dSIin. Then, the differential signal restoration circuit 22 - i outputs the generated diagnosis control signal HCi, clock signal SCKi, and print data signals SIi1 to SIin to the print head 100 - i.

[0074] Here, the differential signals dHC1 to dHCm, differential signals dSI11 to dSI1n, ..., dSIm1 to dSImn, and differential signals dSCK1 to dSCKm output by the ejection control circuit 21 are differential signals that comply with a high-speed transmission method, for example, differential signals that comply with an LVDS (Low Voltage Differential Signaling) transmission method, differential signals that comply with an LVPECL (Low Voltage Positive Emitter Coupled Logic) transmission method, differential signals that comply with a CML (Current Mode Logic) transmission method, etc. In addition, in Figure 1 In the figure, a case where the differential signal recovery circuits 22-1 to 22-m correspond one-to-one to m print heads 100 is illustrated, but the present invention is not limited to a case where the differential signal recovery circuits 22-1 to 22-m correspond one-to-one to m print heads 100. For example, a differential signal recovery circuit 22-i can also recover differential signals corresponding to multiple print heads 100, and output the recovered single-ended signals to the corresponding multiple print heads 100.

[0075] Here, n is an integer greater than or equal to 1, which is equivalent to the number of head chips 300 respectively included in the print heads 100-1 to 100-m. Furthermore, the print data signal SIij (j is any integer from 1 to n) among the above-mentioned print data signals SI11 to SI1n, ..., SIm1 to SImn corresponds to the print data signal SI input to the head chip 300-j included in the print head 100-i, and the differential signal dSIij corresponds to the differential signal corresponding to the print data signal SIij.

[0076] Furthermore, the discharge control circuit 21 generates a latch signal LAT and a conversion signal CH as control signals for controlling the discharge timing of ink from the m print heads 100 based on the image information signal IP input from the main control circuit 11 , and outputs the signals to the m print heads 100 .

[0077] Furthermore, the discharge control circuit 21 generates basic drive signals dA and dB as the basis of drive voltage signals VDR1 and VDR2 for driving the print head 100 based on the image information signal IP input from the main control circuit 11 , and outputs the basic drive signals dA and dB to the drive voltage output circuit 50 .

[0078] The driving voltage output circuit 50 includes driving circuits 51a and 51b and a reference voltage output circuit 53. The driving voltage output circuit 50 generates driving voltage signals VDR1 and VDR2 based on the basic driving signals dA and dB, and outputs the signals to the corresponding m print heads 100.

[0079] Specifically, the basic drive signal dA is input to the drive circuit 51a. After the drive circuit 51a converts the input basic drive signal dA into an analog signal, it performs a class D amplification on the converted analog signal based on the voltage VHV, thereby generating a drive voltage signal VDR1. Then, the drive circuit 51a outputs the generated drive voltage signal VDR1 to the m print heads 100 respectively. In addition, the basic drive signal dB is input to the drive circuit 51b. After the drive circuit 51b converts the input basic drive signal dB into an analog signal, it performs a class D amplification on the converted analog signal based on the voltage VHV, thereby generating a drive voltage signal VDR2. Then, the drive circuit 51b outputs the generated drive voltage signal VDR2 to the m print heads 100 respectively. In addition, an example of the specific structure and operation of the drive circuits 51a and 51b will be described later.

[0080] Here, in Figure 1 In the example, the driving voltage output circuit 50 includes one driving circuit 51a that outputs the driving voltage signal VDR1 and one driving circuit 51b that outputs the driving voltage signal VDR2, but the driving voltage output circuit 50 may also include multiple driving circuits 51a that output the driving voltage signal VDR1 and multiple driving circuits 51b that output the driving voltage signal VDR2. In this case, the multiple driving circuits 51a may respectively generate the driving voltage signal VDR1 and output the generated driving voltage signal VDR1 to the corresponding print head 100, and the multiple driving circuits 51b may respectively generate the driving voltage signal VDR2 and output the generated driving voltage signal VDR2 to the corresponding print head 100.

[0081] For example, when the driving voltage output circuit 50 includes two driving circuits 51a that output the driving voltage signal VDR1 and two driving circuits 51b that output the driving voltage signal VDR2, one of the two driving circuits 51a that generate the driving voltage signal VDR1 outputs the driving voltage signal VDR1 to the print heads 100-1 to 100-i, and the other of the two driving circuits 51a that generate the driving voltage signal VDR1 outputs the driving voltage signal VDR1 to the print heads 100-i+1 to 100-m. Similarly, one of the two driving circuits 51b that generate the driving voltage signal VDR2 outputs the driving voltage signal VDR2 to the print heads 100-1 to 100-i, and the other of the two driving circuits 51b that generate the driving voltage signal VDR2 outputs the driving voltage signal VDR2 to the print heads 100-i+1 to 100-m.

[0082] The voltage VDD is supplied to the reference voltage output circuit 53. The reference voltage output circuit 53 generates a reference voltage signal VBS, which is a reference potential when ink is ejected from each of the m print heads 100, by boosting or lowering the supplied voltage VDD, and outputs the signal to each of the m print heads 100.

[0083] As described above, the print head driving circuit 2 generates voltages VHV, VDD, diagnostic control signals HC1~HCm, printing data signals SI11~SI1n,..., SIm1~SImn, clock signals SCK1~SCKm, latch signals LAT, conversion signals CH, driving voltage signals VDR1, VDR2 and reference voltage signal VBS based on the AC voltage AC supplied from the commercial AC power supply and the image data PD supplied from the external device, and outputs them to m print heads 100.

[0084] The m print heads 100 use the voltages VHV and VDD as power supply voltages, and switch whether to supply the driving voltage signals VDR1 and VDR2 to the piezoelectric element 60 described later at a timing specified by the diagnostic control signals HC1 to HCm, the printing data signals SI11 to SI1n, ..., SIm1 to SImn, the clock signals SCK1 to SCKm, the latch signals LAT, and the conversion signal CH. As a result, the m print heads 100 eject a predetermined amount of ink at a predetermined timing. That is, the m print heads 100 are controlled by the print head driving circuit 2, respectively.

[0085] In addition, the print heads 100-1 to 100-m generate determination result signals ES1 to ESm indicating whether an abnormality has occurred in the print heads 100-1 to 100-m, and output them to the ejection control circuit 21 included in the ejection control unit 20 of the print head drive circuit 2. Thus, the ejection control circuit 21 can drive or stop the print heads 100-1 to 100-m according to the states of the print heads 100-1 to 100-m. In addition, an example of the specific structure and operation of the m print heads 100 will be described later.

[0086] 1.2 Structure and operation of the drive circuit

[0087] Next, the structure and operation of the drive circuits 51a and 51b of the drive voltage output circuit 50 are described. Here, the drive circuits 51a and 51b are different only in input signals and output signals, and have the same structure and operation. Therefore, in the following description, the structure and operation of the drive circuit 51a that outputs the drive voltage signal VDR1 based on the basic drive signal dA are described, and the structure and operation of the drive circuit 51b that outputs the drive voltage signal VDR2 based on the basic drive signal dB are omitted.

[0088] Figure 2 is a diagram showing the functional structure of the driving circuit 51a. Figure 2 As shown, the driving circuit 51 a has an integrated circuit 500 including a modulation circuit 510 , an amplification circuit 550 , a smoothing circuit 560 , feedback circuits 570 , 572 and other circuit elements.

[0089] The integrated circuit 500 is electrically connected to the outside of the integrated circuit 500 via a plurality of terminals including a terminal In, a terminal Bst, a terminal Hdr, a terminal Sw, a terminal Gvd, a terminal Ldr, a terminal Gnd, a terminal Ifb, and a terminal Vfb. Furthermore, the integrated circuit 500 generates and outputs a gate signal Hgd for driving the transistor M1 and a gate signal Lgd for driving the transistor M2 included in the driving amplifier circuit 550 based on the basic driving signal dA input from the terminal In.

[0090] The integrated circuit 500 includes a DAC (Digital to Analog Converter) 511 , a modulation circuit 510 , a gate driving circuit 520 , and a power supply circuit 580 .

[0091] The power supply circuit 580 generates a voltage signal DAC_HV and a voltage signal DAC_LV, and outputs the signals to the DAC 511 .

[0092] A digital basic drive signal dA is input to DAC511. DAC511 converts the basic drive signal dA into an analog signal of a voltage value between the voltage signal DAC_HV and the voltage signal DAC_LV, and outputs it to the modulation circuit 510 as a basic drive signal aA. Here, the maximum value of the voltage amplitude of the basic drive signal aA is specified by the voltage signal DAC_HV, and the minimum value of the voltage amplitude of the basic drive signal aA is specified by the voltage signal DAC_LV. That is, the voltage signal DAC_HV is the reference voltage on the high voltage side of DAC511, and the voltage signal DAC_LV becomes the reference voltage on the low voltage side of DAC511. The signal amplified by the voltage VHV of the basic drive signal aA becomes the drive voltage signal VDR1. That is, the basic drive signal aA is equivalent to a signal of a waveform that is the target before amplification of the drive voltage signal VDR1, and the basic drive signal dA is equivalent to a digital signal that specifies the waveform of the drive voltage signal VDR1. In addition, the voltage amplitude of the basic drive signal aA in the present embodiment is, for example, 1V to 2V.

[0093] The basic drive signal aA is input to the modulation circuit 510. The modulation circuit 510 generates a modulation signal Ms by modulating the input basic drive signal aA, and outputs the modulation signal Ms to the gate drive circuit 520. Such a modulation circuit 510 includes adders 512 and 513, a comparator 514, an inverter 515, an integral attenuator 516, and an attenuator 517.

[0094] The voltage of the terminal Out inputted via the terminal Vfb, that is, the driving voltage signal VDR1 is inputted to the integral attenuator 516. The integral attenuator 516 attenuates and integrates the driving voltage signal VDR1, and supplies it to the -side input terminal of the adder 512. The basic driving signal aA is inputted to the +side input terminal of the adder 512. The adder 512 subtracts the voltage inputted to the -side input terminal from the voltage inputted to the +side input terminal, and supplies the integrated voltage to the +side input terminal of the adder 513.

[0095] Here, the voltage amplitude of the basic drive signal aA is about 1 V to 2 V as described above, and the maximum value of the voltage of the drive voltage signal VDR1 may exceed 40 V due to the voltage value of the voltage VHV. Therefore, the integral attenuator 516 attenuates the voltage of the drive voltage signal VDR1 input through the terminal Vfb in order to make the amplitude ranges of the two voltages consistent when obtaining the deviation.

[0096] The attenuator 517 is inputted with a voltage in which the high frequency component of the driving voltage signal VDR1 is attenuated via the terminal Ifb. The attenuator 517 supplies the voltage in which the high frequency component of the input driving voltage signal VDR1 is attenuated to the - side input terminal of the adder 513. The voltage outputted from the adder 512 is inputted to the + side input terminal of the adder 513. The adder 513 outputs a voltage obtained by subtracting the voltage inputted to the - side input terminal from the voltage inputted to the + side input terminal as a voltage signal As to the comparator 514.

[0097] The voltage signal As output from the adder 513 is obtained by subtracting the voltage of the signal supplied to the terminal Vfb from the voltage of the basic drive signal aA, and then subtracting the voltage of the signal supplied to the terminal Ifb. That is, the voltage of the voltage signal As output from the adder 513 is a signal obtained by subtracting the attenuation voltage of the drive voltage signal VDR1 from the voltage of the target basic drive signal aA, and corrected with the high-frequency component of the drive voltage signal VDR1.

[0098] The comparator 514 outputs a pulse-modulated modulation signal Ms based on the voltage signal As output from the adder 513. Specifically, the comparator 514 generates a modulation signal Ms, which becomes an H level when the voltage signal As becomes above a predetermined threshold value when the voltage rises, and becomes an L level when the voltage signal As falls below the predetermined threshold value when the voltage drops. The frequency or duty cycle of the modulation signal Ms changes according to the changes in the basic drive signals dA and aA, and the frequency or duty cycle of the modulation signal Ms can be adjusted by adjusting the modulation gain corresponding to the sensitivity through the attenuator 517.

[0099] The modulation signal Ms is input to the gate drive circuit 520. The gate drive circuit 520 includes gate drivers 521 and 522. Specifically, the modulation signal Ms output from the comparator 514 is supplied to the gate driver 521, and after the logic level is inverted by the inverter 515, it is also supplied to the gate driver 522. That is, the modulation signal Ms whose logic levels are mutually exclusive is input to the gate driver 521 and the gate driver 522.

[0100] Here, the logic level of the signal supplied to the gate driver 521 and the logic level of the signal supplied to the gate driver 522 are mutually exclusive. Strictly speaking, it means that the logic level of the signal supplied to the gate driver 521 and the logic level of the signal supplied to the gate driver 522 are both at the H level. That is, it means that the transistor M1 and the transistor M2 included in the amplifier circuit 550 described later will not be turned on at the same time.

[0101] The gate driver 521 performs level shifting on the input modulation signal Ms and outputs it from the terminal Hdr as a gate signal Hgd. A voltage is supplied via the terminal Bst on the high side of the power supply voltage of the gate driver 521, and a voltage is supplied via the terminal Sw on the low side of the power supply voltage. The terminal Bst is connected to one end of the capacitor C5 and the cathode of the diode D1. The terminal Sw is connected to the other end of the capacitor C5. In addition, the anode of the diode D1 is connected to the terminal Gvd. Thus, the voltage Vm is supplied to the anode of the diode D1. That is, the capacitor C5 and the diode D1 constitute a bootstrap circuit. Therefore, the potential difference between the terminal Bst and the terminal Sw is approximately equal to the potential difference between the two ends of the capacitor C5, that is, the voltage Vm. Therefore, the gate driver 521 generates a gate signal Hgd with a voltage greater than the voltage Vm relative to the terminal Sw of the input modulation signal Ms, and outputs it from the integrated circuit 500 via the terminal Hdr.

[0102] The gate driver 522 performs level shifting on the signal inverted in logic level of the input modulation signal Ms, and outputs it from the terminal Ldr as the gate signal Lgd. The gate driver 522 operates on the lower potential side than the gate driver 521. The voltage Vm is supplied to the high side of the power supply voltage of the gate driver 522, and the ground potential is supplied to the low side of the power supply voltage via the terminal Gnd. Then, the gate driver 522 generates the gate signal Lgd having a voltage greater than the voltage Vm with respect to the terminal Gnd of the signal inverted in accordance with the logic level of the input modulation signal Ms, and outputs it from the integrated circuit 500 via the terminal Ldr.

[0103] The gate signals Hgd and Lgd output from the integrated circuit 500 are input to the amplifier circuit 550. The amplifier circuit 550 includes transistors M1 and M2. The voltage VHV is supplied to the drain of the transistor M1. The gate of the transistor M1 is electrically connected to one end of the resistor R1, and the other end of the resistor R1 is electrically connected to the terminal Hdr of the integrated circuit 500. That is, the gate signal Hgd output from the terminal Hdr of the integrated circuit 500 is supplied to the gate of the transistor M1. The source of the transistor M1 is electrically connected to the terminal Sw of the integrated circuit 500.

[0104] The drain of the transistor M2 is electrically connected to the terminal Sw of the integrated circuit 500. That is, the drain of the transistor M2 and the source of the transistor M1 are electrically connected to each other. The gate of the transistor M2 is electrically connected to one end of the resistor R2, and the other end of the resistor R2 is electrically connected to the terminal Ldr of the integrated circuit 500. That is, the gate of the transistor M2 is supplied with a gate signal Lgd output from the terminal Ldr of the integrated circuit 500. The source of the transistor M2 is supplied with a ground potential.

[0105] Here, in the following description, the case where the drain and source of the transistors M1 and M2 are controlled to be conductive is sometimes referred to as “on”, and the case where the drain and source of the transistors M1 and M2 are controlled to be non-conductive is sometimes referred to as “off”.

[0106] In the amplifier circuit 550 constructed as described above, when the transistor M1 is controlled to be cut off and the transistor M2 is controlled to be turned on, the potential of the node connected to the terminal Sw becomes the ground potential. Therefore, the voltage Vm is supplied to the terminal Bst. On the other hand, when the transistor M1 is controlled to be turned on and the transistor M2 is controlled to be cut off, the potential of the node connected to the terminal Sw becomes the voltage VHV. Therefore, a voltage signal with a potential of the voltage VHV+Vm is supplied to the terminal Bst. That is, the gate driver 521 driving the transistor M1 uses the capacitor C5 as a floating power supply (Floating Power Supply), and according to the actions of the transistors M1 and M2, the potential of the terminal Sw changes to 0V or the voltage VHV, thereby generating a gate signal Hgd with a potential of the voltage VHV or 0V at the L level and a potential of the voltage VHV+voltage Vm at the H level, and supplies it from the terminal Hdr to the gate of the transistor M1.

[0107] On the other hand, the gate driver 522 driving the transistor M2 supplies a gate signal Lgd having a ground potential at its L level and a voltage Vm at its H level to the gate of the transistor M2 regardless of the operations of the transistors M1 and M2 .

[0108] The amplifier circuit 550 configured as described above operates by using the modulation signal Ms modulated by the transistors M1 and M2 based on the basic drive signals dA and aA, thereby generating an amplified modulation signal AMs, which is amplified by the modulation signal Ms based on the voltage VHV, at a connection point where the source of the transistor M1 and the drain of the transistor M2 are commonly connected. Then, the amplifier circuit 550 outputs the generated amplified modulation signal AMs to the smoothing circuit 560. That is, the amplified modulation signal AMs is a signal whose voltage value changes between VHV and the ground potential according to the logic level of the modulation signal Ms.

[0109] In addition, a capacitor C6 is electrically connected to a path for supplying the voltage VHV to the amplifier circuit 550. Specifically, the voltage VHV is supplied to one end of the capacitor C6, and a ground potential is supplied to the other end. The capacitor C6 reduces the potential fluctuation of the voltage VHV that may be generated due to the switching operation of the transistors M1 and M2 included in the amplifier circuit 550. Such a capacitor C6 is preferably a large capacitor, for example, an electrolytic capacitor is used.

[0110] The smoothing circuit 560 generates a driving voltage signal VDR1 by smoothing the amplified modulation signal AMs input from the amplifier circuit 550 , and outputs the driving voltage signal VDR1 from the driving circuit 51 a via the terminal Out.

[0111] Specifically, the smoothing circuit 560 includes a coil L1 and a capacitor C1. The amplified modulation signal AMs output from the amplifier circuit 550 is input to one end of the coil L1, and the other end of the coil L1 is connected to the terminal Out which is the output of the drive circuit 51a. In addition, the other end of the coil L1 is also connected to one end of the capacitor C1. Moreover, the ground potential is supplied to the other end of the capacitor C1. That is, the coil L1 and the capacitor C1 constitute a low-pass filter (Low Pass Filter), and the smoothing circuit 560 smoothes the amplified modulation signal AMs output from the amplifier circuit 550 through the low-pass filter, thereby demodulating and outputting it as a drive voltage signal VDR1.

[0112] The feedback circuit 570 includes a resistor R3 and a resistor R4. One end of the resistor R3 is connected to the terminal Out outputting the driving voltage signal VDR1, and the other end is connected to the terminal Vfb and one end of the resistor R4. The voltage VHV is supplied to the other end of the resistor R4. Thus, the driving voltage signal VDR1 from the terminal Out through the feedback circuit 570 is fed back to the terminal Vfb in a pulled-up state.

[0113] Feedback circuit 572 includes capacitors C2, C3, C4 and resistors R5 and R6. One end of capacitor C2 is connected to terminal Out of output drive voltage signal VDR1, and the other end is connected to one end of resistor R5 and one end of resistor R6. In addition, ground potential is supplied to the other end of resistor R5. That is, capacitor C2 and resistor R5 function as a high pass filter. Here, the cut-off frequency of the high pass filter is set to about 9MHz, for example. In addition, the other end of resistor R6 is connected to one end of capacitor C4 and one end of capacitor C3. Ground potential is supplied to the other end of capacitor C3. That is, resistor R6 and capacitor C3 function as a low pass filter. Here, the cut-off frequency of the low pass filter is set to about 160MHz, for example.

[0114] The feedback circuit 572 configured in this way is configured by including a high-pass filter and a low-pass filter, thereby functioning as a band-pass filter (Band Pass Filter) that allows a predetermined frequency domain of the drive voltage signal VDR1 to pass. In addition, by connecting the other end of the capacitor C4 to the terminal Ifb of the integrated circuit 500, a signal in which a DC component of a high-frequency component of the drive voltage signal VDR1 passing through the feedback circuit 572 is cut off and fed back to the terminal Ifb, the feedback circuit 572 functions as a band-pass filter that allows a predetermined frequency component to pass.

[0115] The driving voltage signal VDR1 output from the terminal Out is a signal obtained by smoothing the amplified modulation signal AMs based on the basic driving signal dA through the smoothing circuit 560. The driving voltage signal VDR1 is integrated and attenuated via the terminal Vfb and then fed back to the adder 512. Therefore, the driving circuit 51a self-oscillates at a frequency determined by the delay of the feedback and the transfer function of the feedback. However, in the feedback path via the terminal Vfb, due to the large amount of delay of the signal, the frequency of the self-oscillation cannot be made high enough to fully ensure the accuracy of the driving voltage signal VDR1 only through the feedback of the terminal Vfb. Therefore, unlike the path via the terminal Vfb, by setting a path for feeding back the high-frequency component of the driving voltage signal VDR1 via the terminal Ifb, the delay when observing the entire circuit is reduced. As a result, compared with the case where there is no path via the terminal Ifb, the frequency of the voltage signal As can be high enough to fully ensure the accuracy of the driving voltage signal VDR1.

[0116] The driving circuit 51a configured as described above generates an amplified modulation signal AMs by amplifying the modulation signal Ms based on the basic driving signal dA using the voltage VHV, and generates a driving voltage signal VDR1 by smoothing the amplified modulation signal AMs. That is, the driving circuit 51a can output a signal having a voltage value ranging from 0V as a ground potential to the voltage VHV, and an arbitrary waveform of a DC voltage, as the driving voltage signal VDR1 based on the basic driving signals dA and aA. Similarly, the driving circuit 51b in the present embodiment generates an amplified modulation signal AMs by amplifying the modulation signal Ms based on the basic driving signal dB using the voltage VHV, and generates a driving voltage signal VDR2 by smoothing the amplified modulation signal AMs. That is, the driving circuit 51b can output a signal having a voltage value ranging from 0V as a ground potential to the voltage VHV, and an arbitrary waveform of a DC voltage, as the driving voltage signal VDR2 based on the basic driving signal dB.

[0117] 1.3 Structure and operation of the print head

[0118] Next, the structure and operation of the print head 100 are described. Here, the m print heads 100 provided in the liquid ejection device 1 are only different in input signals, and the structure and operation are the same as any other print head 100. Therefore, in the following description, only the structure and operation of one print head 100 are described, and the description of the structure and operation of other print heads 100 is omitted. In addition, in the following description, the input voltages VHV and VDD to the print head 100, the diagnostic control signal HC as the diagnostic control signal HC1 to HCm, the printing data signals SI1 to SIn as the printing data signals SI11 to SI1n, ..., SIm1 to SImn, the clock signal SCK as the clock signal SCK1 to SCKm, the latch signal LAT, the conversion signal CH, the drive voltage signals VDR1 and VDR2, and the reference voltage signal VBS are described.

[0119] Figure 3 is a diagram showing the functional structure of the print head 100. Figure 3 As shown in FIG. 1 , the print head 100 includes an abnormality detection circuit 250, drive signal selection circuits 200-1 to 200-n, and head chips 300-1 to 300-n. In addition, the head chips 300-1 to 300-n each include p piezoelectric elements 60. Figure 3 In FIG. 1 , voltages VHV and VDD used as power supply voltages and control voltages are omitted. Here, p is an integer equal to or greater than 1, which is the number of ejection units 600 and piezoelectric elements 60 included in one head chip 300 .

[0120] The abnormality detection circuit 250 is input with the diagnosis control signal HC, the printing data signal SI1, the clock signal SCK, the latch signal LAT, the conversion signal CH, and the driving voltage signal VDR1. Then, the abnormality detection circuit 250 performs a determination on whether the signal transmitted to the print head 100 is normal based on the diagnosis control signal HC and the driving voltage signal VDR1. That is, the print head 100 includes the abnormality detection circuit 250 for performing abnormality detection. Moreover, when the abnormality detection circuit 250 determines that the signal transmitted to the print head 100 is normal, it outputs the printing data signal SI1 to the driving signal selection circuit 200-1, and outputs the clock signal SCK, the latch signal LAT, and the conversion signal CH to the driving signal selection circuits 200-1 to 200-n. In addition, the abnormality detection circuit 250 generates a determination result signal ES including a determination result on whether the signal transmitted to the print head 100 is normal, and outputs it to the ejection control unit 20 of the print head driving circuit 2.

[0121] Here, the printing data signal SIj may be input to the abnormality detection circuit 250 instead of the printing data signal SI1, and the driving voltage signal VDR2 may be input instead of the driving voltage signal VDR1. In this case, the abnormality detection circuit 250 outputs the printing data signal SIj to the corresponding driving signal selection circuit 200-j. In addition, the details of the structure and operation of the abnormality detection circuit 250 will be described later.

[0122] The drive signal selection circuits 200-1 to 200-n are provided in one-to-one correspondence with the head chips 300-1 to 300-n. Specifically, the drive signal selection circuit 200-1 outputs various signals to the head chip 300-1, the drive signal selection circuit 200-n outputs various signals to the head chip 300-n, and the drive signal selection circuit 200-j outputs various signals to the head chip 300-j.

[0123] Specifically, the drive signal selection circuit 200-1 inputs the print data signal SI1, the clock signal SCK, the latch signal LAT, the conversion signal CH, and the drive voltage signals VDR1 and VDR2. The drive signal selection circuit 200-1 selects or deselects the signal waveforms of the drive voltage signals VDR1 and VDR2 based on the print data signal SI1 at a timing specified by the latch signal LAT and the conversion signal CH, thereby generating p drive signals VOUT corresponding to the p piezoelectric elements 60 of the head chip 300-1.

[0124] The p driving signals VOUT generated by the driving signal selection circuit 200-1 are input to the head chip 300-1. In addition, the reference voltage signal VBS is also input to the head chip 300-1. The p driving signals VOUT are respectively supplied to one end of the corresponding piezoelectric element 60. The reference voltage signal VBS is commonly supplied to the other end of the p piezoelectric elements 60. Moreover, the p piezoelectric elements 60 are driven according to the potential difference between the driving signal VOUT supplied to one end and the reference voltage signal VBS supplied to the other end. As a result, the amount of ink corresponding to the drive of the corresponding piezoelectric element 60 is ejected from the nozzles (not shown) corresponding to the p piezoelectric elements 60.

[0125] In addition, the drive signal selection circuit 200-1 generates a head state signal HS1 indicating the state of the head chip 300-1 based on the temperature of the drive signal selection circuit 200-1 and the head chip 300-1, the residual vibration generated after the drive signal VOUT is supplied to the piezoelectric element 60, and outputs it to the abnormality detection circuit 250. The abnormality detection circuit 250 determines whether the drive signal selection circuit 200-1 is normal based on the input head state signal HS1. Then, the abnormality detection circuit 250 outputs the determination result of whether the drive signal selection circuit 200-1 is normal as the determination result signal ES to the ejection control unit 20.

[0126] In addition, the printing data signal SIn, the clock signal SCK, the latch signal LAT, the conversion signal CH, and the driving voltage signals VDR1 and VDR2 are input to the driving signal selection circuit 200-n. Based on the printing data signal SIn, the driving signal selection circuit 200-n selects or does not select the signal waveforms of the driving voltage signals VDR1 and VDR2 at the timing specified by the latch signal LAT and the conversion signal CH, thereby generating p driving signals VOUT corresponding to the p piezoelectric elements 60 of the head chip 300-n.

[0127] The p driving signals VOUT generated by the driving signal selection circuit 200-n are input to the head chip 300-n. In addition, the reference voltage signal VBS is also input to the head chip 300-n. The p driving signals VOUT are respectively supplied to one end of the corresponding piezoelectric element 60. The reference voltage signal VBS is commonly supplied to the other end of the p piezoelectric elements 60. Moreover, the p piezoelectric elements 60 are driven according to the potential difference between the driving signals VOUT respectively supplied to one end and the reference voltage signal VBS commonly supplied to the other end. As a result, the amount of ink corresponding to the drive of the corresponding piezoelectric element 60 is ejected from the nozzles not shown in the figure corresponding to the p piezoelectric elements 60.

[0128] In addition, the drive signal selection circuit 200-n generates a head state signal HSn indicating the state of the head chip 300-n based on the temperature of the drive signal selection circuit 200-n and the head chip 300-n, the residual vibration generated after the drive signal VOUT is supplied to the piezoelectric element 60, and outputs it to the abnormality detection circuit 250. The abnormality detection circuit 250 determines whether the drive signal selection circuit 200-n is normal based on the input head state signal HSn. Then, the abnormality detection circuit 250 outputs the determination result of whether the drive signal selection circuit 200-n is normal as the determination result signal ES to the ejection control unit 20.

[0129] As described above, in the print head 100, the abnormality detection circuit 250 determines whether the signal transmitted to the print head 100 is normal and whether the head chip 300 and the like are normal. Moreover, when the abnormality detection circuit 250 determines that the signal transmitted to the print head 100 is normal, the printing data signal SI1 is output to the drive signal selection circuit 200-1, and the clock signal SCK, the latch signal LAT and the conversion signal CH are output to the drive signal selection circuits 200-1 to 200-n. The drive signal selection circuits 200-1 to 200-n generate the drive signal VOUT based on the input print data signals SI1 to SIn, the clock signal SCK, the latch signal LAT, the conversion signal CH and the drive voltage signals VDR1 and VDR2, and output it to the corresponding head chips 300-1 to 300-n. Then, the head chips 300-1 to 300-n eject the ink in an amount corresponding to the input drive signal VOUT.

[0130] Here, in the following description, the process in which the abnormality detection circuit 250 determines whether the signal transmitted to the print head 100 is normal is sometimes referred to as a diagnostic process, and the process in which the drive signal selection circuit 200-1~200-n generates a drive signal VOUT based on the drive voltage signals VDR1 and VDR2 and outputs it to the corresponding head chip 300-1~300-n, thereby ejecting ink from the head chip 300-1~300-n is referred to as a printing process.

[0131] The head status signals HS1 to HSn may be transmitted through one wiring connected by a wired OR gate and input to the abnormality detection circuit 250, or may be transmitted through a plurality of wirings provided separately and input to the abnormality detection circuit 250. In addition, the head status signals HS1 to HSn may include various information indicating the states of the drive signal selection circuits 200-1 to 200-n and the head chips 300-1 to 300-n instead of or in addition to the information on the temperature and the residual vibration.

[0132] 1.4 Structure of the drive signal selection circuit and operation of the drive signal selection circuit in the printing process

[0133] Next, the structure of the drive signal selection circuits 200-1 to 200-n and the operation of the drive signal selection circuits 200-1 to 200-n in the printing process are described. Here, the drive signal selection circuits 200-1 to 200-n all have the same structure, and the head chips 300-1 to 300-n all have the same structure. Therefore, in the following description, when it is not necessary to distinguish the drive signal selection circuits 200-1 to 200-n, they are sometimes simply referred to as the drive signal selection circuit 200, and when it is not necessary to distinguish the head chips 300-1 to 300-n, they are sometimes simply referred to as the head chip 300. In this case, the printing data signal SI, the clock signal SCK, the latch signal LAT, the conversion signal CH, and the drive voltage signals VDR1 and VDR2 input to the drive signal selection circuit 200 are described.

[0134] When describing the structure of the drive signal selection circuit 200 and the operation of the drive signal selection circuit 200 in the printing process, first, an example of the signal waveform of the drive voltage signals VDR1 and VDR2 input to the drive signal selection circuit 200 in the printing process and an example of the signal waveform of the drive signal VOUT output from the drive signal selection circuit 200 in the printing process are described. Here, in the following description, the signal output as the drive voltage signal VDR1 by the ejection control unit 20 in the printing process is referred to as the drive signal COMA, and the signal output as the drive voltage signal VDR2 is referred to as the drive signal COMB.

[0135] Figure 4 FIG. 1 is a diagram showing an example of the signal waveforms of the drive signals COMA and COMB. Figure 4 As shown, the driving signal COMA is a signal waveform that makes the trapezoidal waveform Adp1 configured in the period T1 from the rise of the latch signal LAT to the rise of the conversion signal CH and the trapezoidal waveform Adp2 configured in the period T2 from the rise of the conversion signal CH to the rise of the latch signal LAT continuous. Moreover, when the trapezoidal waveform Adp1 is supplied to the head chip 300, a predetermined amount of ink is ejected from the corresponding nozzle of the head chip 300, and when the trapezoidal waveform Adp2 is supplied to the head chip 300, an amount of ink greater than the predetermined amount is ejected from the corresponding nozzle of the head chip 300. Here, in the following description, the amount of ink ejected when the trapezoidal waveform Adp1 is supplied to the head chip 300 is sometimes referred to as a small amount, and the amount of ink ejected when the trapezoidal waveform Adp2 is supplied to the head chip 300 is sometimes referred to as a medium amount.

[0136] In addition, if Figure 4As shown, the driving signal COMB is a signal waveform that makes the trapezoidal waveform Bdp1 configured in the period T1 and the trapezoidal waveform Bdp2 configured in the period T2 continuous. Moreover, when the trapezoidal waveform Bdp1 is supplied to the head chip 300, the ink is not ejected from the corresponding nozzle of the head chip 300. The trapezoidal waveform Bdp1 is a waveform for vibrating the ink near the opening portion of the nozzle to prevent the increase of the viscosity of the ink. In addition, when the trapezoidal waveform Bdp2 is supplied to the head chip 300, a smaller amount of ink than the amount of ink supplied with the trapezoidal waveform Adp1 is ejected from the corresponding nozzle of the head chip 300.

[0137] Here, if Figure 4 As shown, the voltage values ​​of the start timing and end timing of the trapezoidal waveforms Adp1, Adp2, Bdp1, and Bdp2 are all the same voltage Vc. That is, the trapezoidal waveforms Adp1, Adp2, Bdp1, and Bdp2 are signal waveforms that start at the voltage Vc and end at the voltage Vc. Moreover, the cycle Ta composed of the period T1 and the period T2 is equivalent to the printing cycle of forming a new dot on the medium.

[0138] In addition, Figure 4 , the trapezoidal waveform Adp1 and the trapezoidal waveform Bdp2 are the same signal waveform, but the trapezoidal waveform Adp1 and the trapezoidal waveform Bdp2 may be different signal waveforms. In addition, the case where the trapezoidal waveform Adp1 is supplied to the head chip 300 and the case where the trapezoidal waveform Bdp2 is supplied to the head chip 300 is described, and a small amount of ink is ejected from the corresponding nozzles, but the present invention is not limited to this. That is, the signal waveforms of the drive signals COMA and COMB are not limited to Figure 4 The signal waveform shown may be a combination of signal waveforms of various shapes, depending on the properties of ink ejected from the nozzles of the head chip 300 , the material of the medium on which the ink lands, and the like.

[0139] In addition, Figure 4 In the present invention, the timing of switching the trapezoidal waveform Adp1 and the trapezoidal waveform Adp2 included in the driving signal COMA and the timing of switching the trapezoidal waveform Bdp1 and the trapezoidal waveform Bdp2 included in the driving signal COMB are specified by a conversion signal CH, but the conversion signal CH that specifies the timing of switching the trapezoidal waveform Adp1 and the trapezoidal waveform Adp2 included in the driving signal COMA and the conversion signal CH that specifies the timing of switching the trapezoidal waveform Bdp1 and the trapezoidal waveform Bdp2 included in the driving signal COMB can also be set separately.

[0140] Figure 5This is a diagram showing an example of a signal waveform of the driving signal VOUT when the sizes of dots formed on a medium in a printing process are respectively a large dot LD, a medium dot MD, a small dot SD, and a non-recording ND.

[0141] like Figure 5 As shown in FIG. 1 , the driving signal VOUT for forming a large dot LD on the medium is a signal waveform that makes the trapezoidal waveform Adp1 configured in the period T1 and the trapezoidal waveform Adp2 configured in the period T2 continuous in the cycle Ta. When the driving signal VOUT is supplied to the head chip 300, a small amount of ink and a medium amount of ink are ejected from the corresponding nozzles. Therefore, in the cycle Ta, the inks are ejected onto the medium separately and merged into one, thereby forming a large dot LD on the medium.

[0142] The driving signal VOUT in the case of forming the midpoint MD on the medium is a signal waveform that makes the trapezoidal waveform Adp1 configured in the period T1 and the trapezoidal waveform Bdp2 configured in the period T2 continuous in the cycle Ta. When the driving signal VOUT is supplied to the head chip 300, a small amount of ink is ejected twice from the corresponding nozzle. Therefore, in the cycle Ta, the ink is ejected onto the medium separately and then integrated, thereby forming the midpoint MD on the medium.

[0143] The driving signal VOUT in the case of forming a small dot SD on the medium is a signal waveform that makes the trapezoidal waveform Adp1 configured in the period T1 and the signal waveform configured in the period T2 with a constant voltage Vc continuous in the cycle Ta. When the driving signal VOUT is supplied to the head chip 300, a small amount of ink is ejected once from the corresponding nozzle. Therefore, in the cycle Ta, the ink is ejected onto the medium to form a small dot SD on the medium.

[0144] The driving signal VOUT corresponding to the non-recording ND where no dots are formed on the medium is a signal waveform that makes the trapezoidal waveform Bdp1 configured in the period T1 and the signal waveform configured in the period T2 with a constant voltage Vc continuous in the cycle Ta. When the driving signal VOUT is supplied to the head chip 300, only the ink near the opening of the corresponding nozzle vibrates slightly without ejecting the ink. Therefore, in the cycle Ta, the ink does not fall on the medium and no dots are formed on the medium.

[0145] Here, the signal waveform with a constant voltage Vc in the driving signal VOUT refers to a signal waveform that maintains the voltage value of the previous voltage Vc of the trapezoidal waveforms Adp1, Adp2, Bdp1, and Bdp2 when none of the trapezoidal waveforms Adp1, Adp2, Bdp1, and Bdp2 is selected as the driving signal VOUT. That is, when none of the trapezoidal waveforms Adp1, Adp2, Bdp1, and Bdp2 is selected as the driving signal VOUT, the previous voltage Vc is supplied to the head chip 300 as the driving signal VOUT.

[0146] The drive signal selection circuit 200 generates a separate corresponding drive signal VOUT in p piezoelectric elements 60 and outputs it to the corresponding piezoelectric element 60 by selecting or non-selecting the trapezoidal waveforms Adp1 and Adp2 included in the drive signal COMA as the drive voltage signal VDR1 in the printing process and the trapezoidal waveforms Bdp1 and Bdp2 included in the drive signal COMB as the drive voltage signal VDR2 in the printing process.

[0147] Figure 6 2 is a diagram showing the functional structure of the drive signal selection circuit 200. Figure 6 As shown, the drive signal selection circuit 200 includes a selection control circuit 210 and a plurality of selection circuits 230. Figure 6 2 , an example of a head chip 300 is also shown to supply the driving signal VOUT output from the driving signal selection circuit 200. The head chip 300 includes p ejection units 600 corresponding to the p piezoelectric elements 60, respectively.

[0148] The printing data signal SI, the clock signal SCK, the latch signal LAT, and the conversion signal CH are input to the selection control circuit 210. In the selection control circuit 210, the groups of the register 212, the latch circuit 214, and the decoder 216 are provided corresponding to the p ejection units 600 of the head chip 300. That is, the selection control circuit 210 includes the same number of groups of the register 212, the latch circuit 214, and the decoder 216 as the p ejection units 600.

[0149] The print data signal SI is a signal synchronized with the clock signal SCK, and is a signal of 2p bits in total that serially includes 2-bit print data [SIH, SIL] for selecting any one of the large dot LD, the middle dot MD, the small dot SD, and the non-recording ND for each of the p ejection units 600. The print data signal SI is held in the register 212 for each print data [SIH, SIL] included in the print data signal SI corresponding to the p ejection units 600.

[0150] Specifically, in the selection control circuit 210, the registers 212 are connected in cascade to form a p-stage shift register. The print data [SIH, SIL] serially input as the print data signal SI is sequentially transmitted to the register 212 of the subsequent stage according to the clock signal SCK. Then, by stopping the supply of the clock signal SCK, the print data [SIH, SIL] corresponding to the p ejection units 600 are held in the registers 212 corresponding to the p ejection units 600. In addition, in the following description, in order to distinguish the p registers 212 constituting the shift register, they are sometimes referred to as the 1st stage, the 2nd stage, ..., the pth stage in the order from the upstream side to the downstream side of the transmission of the print data signal SI.

[0151] The p latch circuits 214 are provided corresponding to the p registers 212 , respectively. The latch circuits 214 latch the print data [SIH, SIL] held by the p registers 212 at the same time at the rising edge of the latch signal LAT, and output the print data to the corresponding decoder 216 .

[0152] Figure 7 is a diagram showing an example of the decoding content in the decoder 216. The decoder 216 uses Figure 7 The content shown decodes the print data [SIH, SIL] latched by the latch circuit 214, thereby generating and outputting the selection signals S1 and S2. For example, when the input print data [SIH, SIL] is [1, 0], the decoder 216 outputs the logic level of the selection signal S1 to the selection circuit 230 as the H level and the L level during the periods T1 and T2, and outputs the logic level of the selection signal S2 to the selection circuit 230 as the L level and the H level during the periods T1 and T2.

[0153] The selection circuits 230 are provided corresponding to the p ejecting units 600 , respectively. That is, the drive signal selection circuit 200 includes the same number of p selection circuits 230 as the number of p ejecting units 600 . Figure 8 2 is a diagram showing the structure of the selection circuit 230 corresponding to one of the ejection units 600. Figure 8 As shown, the selection circuit 230 includes inverters 232a, 232b and transmission gates 234a, 234b as NOT circuits.

[0154] The selection signal S1 is input to the positive control end without circular mark in the transmission gate 234a, and on the other hand, it is logically inverted by the inverter 232a and input to the negative control end with circular mark in the transmission gate 234a. In addition, the drive signal COMA as the drive voltage signal VDR1 is supplied to the input end of the transmission gate 234a. The selection signal S2 is input to the positive control end without circular mark in the transmission gate 234b, and on the other hand, it is logically inverted by the inverter 232b and input to the negative control end with circular mark in the transmission gate 234b. In addition, the drive signal COMB as the drive voltage signal VDR2 is supplied to the input end of the transmission gate 234b. Moreover, the output end of the transmission gate 234a is connected to the output end of the transmission gate 234b in common. The signal of the connection end where the output end of the transmission gate 234a and the output end of the transmission gate 234b are connected in common is output as the drive signal VOUT.

[0155] Specifically, when the selection signal S1 is at an H level, the input terminal and the output terminal of the transmission gate 234a are conductive, and when the selection signal S1 is at an L level, the input terminal and the output terminal of the transmission gate 234a are non-conductive. In addition, when the selection signal S2 is at an H level, the input terminal and the output terminal of the transmission gate 234b are conductive, and when the selection signal S2 is at an L level, the input terminal and the output terminal of the transmission gate 234b are non-conductive. That is, the selection circuit 230 switches the conductive state between the input terminal and the output terminal of the transmission gates 234a and 234b based on the selection signals S1 and S2, and generates the drive signal VOUT at the connection terminal commonly connected to the output terminal of the transmission gate 234a and the output terminal of the transmission gate 234b by selecting or non-selecting the signal waveforms of the drive signals COMA and COMB supplied to the input terminals of the transmission gates 234a and 234b.

[0156] use Fig. 9 The operation of the drive signal selection circuit 200 will be described. Fig. 9 This is a diagram for explaining the operation of the drive signal selection circuit 200. The print data [SIH, SIL] included in the print data signal SI is input in series in synchronization with the clock signal SCK. Moreover, the print data [SIH, SIL] is transmitted sequentially from the register 212 constituting the shift register in synchronization with the clock signal SCK in correspondence with the p ejection units 600. Thereafter, by stopping the supply of the clock signal SCK, the print data [SIH, SIL] corresponding to the p ejection units 600 is retained in each register 212. In addition, the print data [SIH, SIL] included in the print data signal SI is input in the order corresponding to the ejection units 600 of the p-level, ..., 2-level, 1-level register 212 constituting the shift register.

[0157] When the latch signal LAT rises, the latch circuit 214 latches the print data [SIH, SIL] held in the register 212 at the same time. Fig. 9 , LS1, LS2, ..., LSp represent the printing data [SIH, SIL] latched by the latch circuits 214 corresponding to the registers 212 of the 1st, 2nd, ..., pth stages.

[0158] The decoder 216 reads the dot size specified by the latched print data [SIH, SIL] in periods T1 and T2, respectively. Figure 7 The content shown outputs the logic levels of the selection signals S1 and S2.

[0159] Specifically, when the input print data [SIH, SIL] is [1, 1], the decoder 216 sets the selection signal S1 to the H, H level in the periods T1 and T2, and sets the selection signal S2 to the L, L level in the periods T1 and T2. In this case, the selection circuit 230 selects the trapezoidal waveform Adp1 in the period T1, and selects the trapezoidal waveform Adp2 in the period T2. As a result, the output terminal of the selection circuit 230 generates Figure 5 The driving signal VOUT corresponding to the large dot LD is shown.

[0160] In addition, when the input print data [SIH, SIL] is [1, 0], the decoder 216 sets the selection signal S1 to the H and L levels in the periods T1 and T2, and sets the selection signal S2 to the L and H levels in the periods T1 and T2. In this case, the selection circuit 230 selects the trapezoidal waveform Adp1 in the period T1 and the trapezoidal waveform Bdp2 in the period T2. As a result, the output terminal of the selection circuit 230 generates Figure 5 The driving signal VOUT corresponding to the midpoint MD is shown.

[0161] In addition, when the input printing data [SIH, SIL] is [0, 1], the decoder 216 sets the selection signal S1 to the H, L level in the periods T1 and T2, and sets the selection signal S2 to the L, L level in the periods T1 and T2. In this case, the selection circuit 230 selects the trapezoidal waveform Adp1 in the period T1, and does not select any of the trapezoidal waveforms Adp2 and Bdp2 in the period T2. As a result, the output terminal of the selection circuit 230 generates Figure 5 The driving signal VOUT corresponding to the small dot SD is shown.

[0162] In addition, when the input printing data [SIH, SIL] is [0, 0], the decoder 216 sets the selection signal S1 to the L, L level in the periods T1 and T2, and sets the selection signal S2 to the H, L level in the periods T1 and T2. In this case, the selection circuit 230 selects the trapezoidal waveform Bdp1 in the period T1, and does not select any of the trapezoidal waveforms Adp2 and Bdp2 in the period T2. As a result, the output terminal of the selection circuit 230 generates Figure 5 The driving signal VOUT corresponding to the non-recording ND is shown.

[0163] As described above, the drive signal selection circuit 200 generates and outputs the drive signal VOUT by selecting the signal waveforms of the drive signal COMA as the drive voltage signal VDR1 in the printing process and the drive signal COMB as the drive voltage signal VDR2 in the printing process based on the printing data signal SI, the clock signal SCK, the latch signal LAT, and the conversion signal CH. That is, the drive signal VOUT is an example of a drive signal. In addition, considering that the drive signal VOUT is generated by selecting the waveforms of the drive signals COMA and COMB, it can be said that the drive signals COMA and COMB are also examples of drive signals.

[0164] 1.5 Structure of liquid ejection device

[0165] 1.5.1 Structure of liquid ejection device

[0166] Next, an example of the structure of the liquid ejecting device 1 will be described. Fig.10 It is a diagram showing a schematic structure of the liquid ejecting device 1 . Fig.10 Arrows indicating the X direction, Y direction, and Z direction orthogonal to each other are shown. Here, the Y direction corresponds to the conveying direction of the conveying medium P, the X direction is a direction orthogonal to the Y direction and parallel to the horizontal plane and corresponds to the main scanning direction, and the Z direction is the up-down direction of the liquid ejection device 1 and corresponds to the vertical direction. In addition, in the following description, when determining the direction along the X direction, the Y direction, and the Z direction, the front end side of the arrow indicating the X direction is sometimes referred to as the +X side, and the starting point side is referred to as the -X side, the front end side of the arrow indicating the Y direction is sometimes referred to as the +Y side, and the starting point side is referred to as the -Y side. The front end side of the arrow indicating the Z direction is sometimes referred to as the +Z side, and the starting point side is referred to as the -Z side.

[0167] like Fig.10As shown, the liquid ejection device 1 includes the main control unit 10, the ejection control unit 20, and the m print heads 100, and further includes a liquid container 5, a pump 8, and a conveying mechanism 40. In the following description, the liquid ejection device 1 is exemplified as a case where the liquid ejection device 1 includes six print heads 100, namely, print heads 100-1 to 100-6, as a plurality of print heads 100.

[0168] In the main control unit 10, an AC voltage AC as a commercial AC voltage is supplied from a commercial AC power source 7 provided outside the liquid ejection device 1. The liquid ejection device 1 starts to operate with the AC voltage AC as the power supply voltage. In addition, image data PD is input to the main control unit 10 from an external device 3 such as a host computer provided outside the liquid ejection device 1 via a LAN (Local Area Network) cable or a USB (Universal Serial Bus) cable. The main control unit 10 generates an image information signal IP based on the input image data PD, and outputs it to the ejection control unit 20. In addition, the main control unit 10 controls the conveyance of the medium P by outputting a conveyance control signal TC to a conveyance mechanism 40 for conveying the medium P, and controls the operation of the pump 8 by outputting a pump control signal AIR to the pump 8.

[0169] The liquid container 5 stores ink to be ejected toward the medium P. Specifically, the liquid container 5 includes four containers, and the four containers store ink of four colors, namely, cyan C, magenta M, yellow Y, and black K. Ink stored in the liquid container 5 is supplied to the ejection control unit 20 via an ink flow path such as a tube. In addition, the ink storage containers of the liquid container 5 are not limited to four, and the colors of the stored ink are not limited to the four colors, namely, cyan C, magenta M, yellow Y, and black K.

[0170] The ejection control unit 20 distributes ink supplied through ink flow paths such as tubes to the print heads 100-1 to 100-6, and generates various signals for driving the print heads 100-1 to 100-6 based on the image information signal IP supplied from the main control unit 10, and supplies the signals to the print heads 100-1 to 100-6.

[0171] The print heads 100-1 to 100-6 are located on the +Z side of the ejection control unit 20, and are arranged in the order of the print head 100-1, the print head 100-2, the print head 100-3, the print head 100-4, the print head 100-5, and the print head 100-6 from the -X side toward the +X side along the X direction to be larger than the width of the medium P. Furthermore, the print heads 100-1 to 100-6 eject ink supplied via the ejection control unit 20 and an ink flow path such as a tube based on various signals input from the ejection control unit 20. In addition, the number of print heads 100 included in the liquid ejection device 1 is not limited to six, and may be five or less or seven or more.

[0172] The transport mechanism 40 transports the medium P in the Y direction based on the transport control signal TC input from the main control unit 10. The transport mechanism 40 includes rollers (not shown) for transporting the medium P, a motor for rotationally driving the rollers, and the like.

[0173] The pump 8 controls whether to supply air to the ejection control unit 20 and the amount of air supplied based on the pump control signal AIR input from the main control unit 10. The pump 8 is connected to the ejection control unit 20 via one or more tubes, for example. Moreover, the pump 8 controls the opening and closing of the valve of the ejection control unit 20 by controlling the air flowing in each tube. In addition, in the following description, the pump 8 is connected to the ejection control unit 20 via two tubes.

[0174] As described above, the main control unit 10 of the liquid ejection device 1 generates an image information signal IP based on the image data PD input from the external device 3 such as the host computer, and supplies it to the ejection control unit 20, and controls the conveyance of the medium P in the conveying mechanism 40 through the conveyance control signal TC. In addition, the ejection control unit 20 controls the ejection of ink from the print heads 100-1 to 100-6 based on the input image information signal IP. Thus, the liquid ejection device 1 controls the conveyance of the medium P and the ejection timing of the ink so that the ink is ejected at a desired position on the medium P. As a result, a desired image is formed on the medium P.

[0175] 1.5.2 Structure of the ejection control unit

[0176] Next, an example of the configuration of the ejection control unit 20 is described. The ejection control unit 20 distributes the ink supplied from the liquid container 5 via the ink flow path such as a tube to the print heads 100-1 to 100-6, and drives the print heads 100-1 to 100-6 based on the image information signal IP supplied from the main control unit 10.

[0177] Fig.11 2 is a diagram showing an example of the structure of the ejection control unit 20. Fig.11, together with the ejection control unit 20, print heads 100-1 to 100-6 located on the +Z side of the ejection control unit 20, and cables FC1 and FC2 that electrically connect the ejection control unit 20 to the print heads 100-1 to 100-6 are also shown.

[0178] like Fig.11 As shown, the ejection control unit 20 includes: an introduction flow path portion G1 for introducing ink supplied from a liquid container 5; a control portion G2 for controlling the supply of the introduced ink to the print heads 100-1 to 100-6; a head support portion G3 for fixing the print heads 100-1 to 100-6; and an ejection control portion G4 for controlling the ejection of ink from the print heads 100-1 to 100-6. Furthermore, the introduction flow path portion G1, the supply control portion G2, the head support portion G3, and the ejection control portion G4 are stacked in the order of the ejection control portion G4, the introduction flow path portion G1, the supply control portion G2, and the head support portion G3 from the -Z side toward the +Z side along the Z direction, and are fixed by a fixing unit such as an adhesive or a screw not shown in the figure.

[0179] The inlet flow path portion G1 has a plurality of liquid inlet ports IS1 corresponding to the number of ink colors supplied to the ejection control unit 20 and a plurality of liquid outlet ports ID1 corresponding to the number of ink colors and the number of print heads 100. The plurality of liquid inlet ports IS1 are respectively located on the surface on the -Z side of the inlet flow path portion G1. Ink is supplied to the plurality of liquid inlet ports IS1 from a liquid container 5 via a tube or the like not shown in the figure. In addition, the plurality of liquid outlet ports ID1 are located on the surface on the +Z side of the inlet flow path portion G1. The plurality of liquid outlet ports ID1 discharge the ink supplied to the ejection control unit 20 in correspondence with the plurality of print heads 100 possessed by the liquid ejection device 1, respectively. That is, the inlet flow path portion G1 has a number of liquid outlet ports ID1 corresponding to the product of the number of the plurality of print heads 100 possessed by the liquid ejection device 1 and the number of ink colors supplied to the ejection control unit 20. Specifically, as shown in this embodiment, the liquid ejection device 1 has six print heads 100, and when four colors of ink are supplied to the ejection control unit 20, the introduction flow path portion G1 has 24 liquid discharge ports ID1. Inside such an introduction flow path portion G1, an ink flow path is formed that connects the liquid introduction port IS1 and the liquid discharge port ID1 corresponding to each ink color.

[0180] In addition, the inlet flow path section G1 has a plurality of air inlet ports AS1 and a plurality of air outlet ports AD1. The plurality of air inlet ports AS1 are respectively provided on the surface on the -Z side of the inlet flow path section G1, and are connected to the pump 8 via a tube not shown in the figure. In addition, the plurality of air outlet ports AD1 are respectively provided on the surface on the +Z side of the inlet flow path section G1. The plurality of air outlet ports AD1 discharge air supplied to the ejection control unit 20 corresponding to the plurality of print heads 100 possessed by the liquid ejection device 1. Inside the inlet flow path section G1, an air flow path is formed that connects one air inlet port AS1 and a plurality of air outlet ports AD1 corresponding to the print heads 100.

[0181] The supply control section G2 has a plurality of pressure adjustment units U corresponding to the plurality of print heads 100 of the liquid ejection device 1. In addition, the plurality of pressure adjustment units U respectively have a plurality of liquid introduction ports IS2 corresponding to the number of ink colors supplied to the ejection control unit 20 and discharge ports (not shown) corresponding one-to-one to the plurality of liquid introduction ports IS2.

[0182] The plurality of liquid introduction ports IS2 are located at positions corresponding to the liquid discharge ports ID1 of the introduction flow path section G1 on the -Z side of the pressure regulating unit U, and are connected to the corresponding liquid discharge ports ID1. In addition, the plurality of discharge ports not shown in the figure are located on the -Z side of the pressure regulating unit U. Furthermore, an ink flow path connecting one liquid introduction port IS2 and one discharge port not shown in the figure is formed inside the pressure regulating unit U.

[0183] In addition, the plurality of pressure regulating units U each have a plurality of air inlet ports AS2 corresponding to the number of tubes connected to the pump 8. The plurality of air inlet ports AS2 are located on the -Z side of the pressure regulating unit U at positions corresponding to the air outlet ports AD1 of the inlet flow path portion G1, and are connected to the corresponding air outlet ports AD1. In addition, a valve not shown in the figure for opening and closing the ink flow path or an adjustment valve not shown in the figure for adjusting the pressure of the ink flowing through the ink flow path is provided inside the pressure regulating unit U. The pressure regulating unit U controls the operation of the valve or the adjustment valve by utilizing the air supplied from the air inlet port AS2, thereby controlling the amount of ink flowing in the ink flow path not shown in the figure connecting the liquid inlet port IS2 and the outlet not shown in the figure.

[0184] The head support section G3 includes a support member 35 that supports the print heads 100-1 to 100-6 included in the liquid ejection device 1. The support member 35 supports the print heads 100-1 to 100-6 by fixing them to the +Z side using fixing means such as adhesive or screws (not shown).

[0185] The support member 35 has an opening 353 formed corresponding to the liquid introduction port IS3 to be described later of the print heads 100-1 to 100-6. The liquid introduction port IS3 to be described later of the print heads 100-1 to 100-6 is exposed on the -Z side of the head support G3 by being inserted through the opening 353. The liquid introduction port IS3 to be described later of the print heads 100-1 to 100-6 is connected to the discharge port (not shown) of the supply control unit G2.

[0186] The ink stored in the liquid container 5 is supplied to the print heads 100-1 to 100-6 via the introduction flow path section G1, the supply control section G2, and the head support section G3 configured as described above. Specifically, the ink stored in the liquid container 5 is supplied to the liquid introduction port IS1 of the introduction flow path section G1 via a tube or the like not shown in the figure. The ink supplied to the liquid introduction port IS1 is distributed corresponding to the print heads 100-1 to 100-6 through an ink flow path not shown in the figure provided inside the introduction flow path section G1, and then supplied to the liquid introduction port IS2 of the pressure regulating unit U via the liquid discharge port ID1. The ink supplied to the liquid introduction port IS2 is supplied to the respective liquid introduction ports IS3 of the print heads 100-1 to 100-6 supported by the head support section G3 via the ink flow path provided inside the pressure regulating unit U and the discharge port not shown in the figure. That is, after the ink supplied from the liquid container 5 is branched through the introduction flow path G1, the supply amount of the ink is controlled in the supply control unit G2, and the ink is supplied to the print heads 100-1 to 100-6 supported by the head support unit G3.

[0187] The discharge control section G4 is located on the −Z side of the introduction flow path section G1 , and includes a wiring substrate 410 and a wiring substrate 420 .

[0188] The wiring substrate 410 includes a surface 411 and a surface 412 located on the opposite side of the surface 411. The wiring substrate 410 is arranged such that the surface 412 faces the introduction flow path section G1, the supply control section G2, and the head support section G3, and the surface 411 faces the opposite side to the introduction flow path section G1, the supply control section G2, and the head support section G3.

[0189] A driving voltage output circuit 50 that outputs driving voltage signals VDR1 and VDR2 is provided on a surface 411 of the wiring substrate 410. In addition, a connection portion 413 is provided on a surface 412 of the wiring substrate 410. The connection portion 413 electrically connects the wiring substrate 410 and the wiring substrate 420, transmits the driving voltage signals VDR1 and VDR2 generated by the driving voltage output circuit 50 to the wiring substrate 420, and transmits a plurality of signals including the basic driving signals dA and dB that are the basis of the driving voltage signals VDR1 and VDR2 output by the driving voltage output circuit 50 to the wiring substrate 410.

[0190] The wiring substrate 420 includes a surface 421 and a surface 422 located on the opposite side of the surface 421. The wiring substrate 420 is arranged such that the surface 422 faces the introduction flow path section G1, the supply control section G2, and the head support section G3, and the surface 421 faces the opposite side to the introduction flow path section G1, the supply control section G2, and the head support section G3.

[0191] On the surface 421 of the wiring substrate 420, a semiconductor device 428, connecting parts 423, 426, and 427 are provided. The connecting part 423 is connected to the connecting part 413 provided on the wiring substrate 410. Thus, the wiring substrate 420 is electrically connected to the wiring substrate 410. As such connecting parts 413 and 423, a BtoB (Board To Board) connector that directly electrically connects the wiring substrate 410 and the wiring substrate 420 is used instead of a cable. The semiconductor device 428 is a circuit component that constitutes at least a part of the above-mentioned ejection control circuit 21, and is constituted by, for example, a SoC or the like. The semiconductor device 428 is provided in a region closer to the -X side of the wiring substrate 420 than the connecting part 423. The voltages VHV and VDD that function as the power supply voltage of the ejection control unit 20 are input to the connecting part 426. The connecting part 426 is located on the -Y side of the semiconductor device 428. The image information signal IP output by the main control unit 10 is input to the connecting part 427. That is, the connection portion 427 has a plurality of terminals for transmitting the input image information signal IP. Such a connection portion 427 is located on the -Y side of the semiconductor device 428 and on the -X side of the connection portion 426. Here, the connection portions 426 and 427 may be constituted by one connection portion.

[0192] On the surface 422 of the wiring substrate 420, a plurality of connection parts 424 and a plurality of connection parts 425 are provided, the same number as the print heads 100 of the liquid ejection device 1. The plurality of connection parts 424 are arranged along the edge of the -Y side of the wiring substrate 420, and the plurality of connection parts 425 are arranged along the edge of the +Y side of the wiring substrate 420. Various control signals generated by the ejection control unit G4 are output via the connection parts 424, 424.

[0193] One end of the cable FC1 is connected to the connection portion 424. The cable FC1 is introduced into the flow path portion G1, the -Y side of the supply control portion G2, and inserted through the opening portion 351 provided in the head support portion G3, thereby being electrically connected to the plurality of print heads 100 located on the -Z side of the head support portion G3.

[0194] In addition, one end of the cable FC2 is connected to the connection portion 425. The cable FC2 is introduced into the flow path portion G1 and the +Y side of the supply control portion G2, and is inserted into and passed through the opening portion 352 provided in the head support portion G3, thereby being electrically connected to the plurality of print heads 100 located on the -Z side of the head support portion G3. That is, the cables FC1 and FC2 are provided in the same number as the print heads 100, respectively, and transmit various control signals generated by the ejection control portion G4 to the corresponding print heads 100. Such cables FC1 and FC2 are composed of, for example, flexible flat cables (FFC: Flexible Flat Cable) or flexible wiring substrates (FPC: Flexible Printed Circuit (flexible printed circuit)).

[0195] In the ejection control unit 20 configured as described above, the image information signal IP input from the main control unit 10 is supplied to the ejection control unit G4. The semiconductor device 428 and the peripheral circuit not shown in the figure of the ejection control unit G4 generate the voltages VHV and VDD for controlling the operation of the print heads 100-1 to 100-6, the diagnostic control signals HC1 to HCm, the printing data signals SI11 to SI1n, ..., SIm1 to SImn, the clock signals SCK1 to SCKm, the latch signal LAT, the conversion signal CH, and the basic drive signals dA and dB based on the image information signal IP input from the main control unit 10. The basic drive signals dA and dB are supplied to the drive voltage output circuit 50 provided on the wiring substrate 410. Thus, the drive voltage output circuit 50 generates the drive voltage signals VDR1 and VDR2 and the reference voltage signal VBS, and outputs them to the wiring substrate 420. Then, the ejection control unit G4 supplies the generated diagnostic control signals HC1~HCm, printing data signals SI11~SI1n, ..., SIm1~SImn, clock signals SCK1~SCKm, latch signals LAT, conversion signals CH, drive voltage signals VDR1, VDR2 and reference voltage signals VBS, voltages VHV, VDD to the corresponding print heads 100-1~100-6 via the corresponding cables FC1, FC2.

[0196] In addition, in this embodiment, the ejection control unit 20 and the print head 100 are connected by two signal cables, namely, the cable FC1 and the cable FC2. However, the ejection control unit 20 and the print head 100 may be electrically connected by using three or more signal cables, or may be electrically connected by one signal cable. In the following description, the cables FC1 and FC2 are described as flexible flat cables.

[0197] Next, an example of the arrangement of the print heads 100 - 1 to 100 - 6 supported by the head support portion G3 will be described. Fig.12 1 is a diagram showing an example of the arrangement of the print heads 100-1 to 100-6. Fig.12 As shown, each of the plurality of print heads 100-1 to 100-6 has six head chips 300 arranged in an array along the X direction. Each head chip 300 has a plurality of nozzles 651 arranged in a row direction RD in a direction perpendicular to the Z direction and in a plane formed by the X direction and the Y direction and ejecting ink. In the following description, the plurality of nozzles 651 arranged in a row direction RD are sometimes referred to as nozzle rows.

[0198] The head chip 300 has two nozzle rows along the row direction RD. The two nozzle rows 651 of the print head 100 include a group that ejects cyan C color ink, a group that ejects magenta M color ink, a group that ejects yellow Y color ink, and a group that ejects black K color ink. In addition, the number of head chips 300 that each of the print heads 100-1 to 100-6 has is not limited to six.

[0199] 1.5.3 Print head structure

[0200] Next, the structure of the print heads 100 - 1 to 100 - 6 will be described. As described above, the print heads 100 - 1 to 100 - 6 all have the same structure, and in the following description, the print heads 100 - 1 to 100 - 6 are simply referred to as the print head 100 .

[0201] Fig.13 1 is a diagram showing an example of the structure of the print head 100. Fig.13 As shown, the print head 100 includes a filter unit 110, a sealing member 120, a wiring substrate 130, a bracket 140, six head chips 300, and a fixing plate 150. The print head 100 is configured such that the filter unit 110, the sealing member 120, the wiring substrate 130, the bracket 140, and the fixing plate 150 are stacked in this order from the -Z side toward the +Z side along the Z direction, and the six head chips 300 are accommodated between the bracket 140 and the fixing plate 150.

[0202] The filter unit 110 is a substantially parallelogram shape with two opposite sides extending in the X direction and two opposite sides extending in the row direction RD. The filter unit 110 has four filters 113 and four liquid introduction ports IS3. The four liquid introduction ports IS3 are located on the -Z side of the filter unit 110 corresponding to the four filters 113 located inside the filter unit 110. Ink is supplied from the liquid container 5 to the four liquid introduction ports IS3 via the ejection control unit 20, and the filters 113 capture bubbles or foreign matter contained in the ink introduced from the liquid introduction ports IS3.

[0203] In addition, openings 115 and 117 are formed in the filter unit 110. The opening 115 opens along the -Y side of the filter unit 110, and communicates with the opening 351 provided in the head support unit G3 when the print head 100 is supported on the head support unit G3. In addition, the opening 117 opens along the +Y side of the filter unit 110, and communicates with the opening 352 provided in the head support unit G3 when the print head 100 is supported on the head support unit G3.

[0204] The sealing member 120 is located on the +Z side of the filter unit 110, and is a roughly parallelogram shape with two opposite sides extending along the X direction and two opposite sides extending along the column direction RD. At the four corners of the sealing member 120, there are through openings 123 for the liquid flow path 145 described later to be inserted and passed through. Such a sealing member 120 is formed, for example, of an elastic member such as rubber. In addition, openings 125 and 127 are formed on the sealing member 120. The opening 125 opens along the edge of the -Y side of the sealing member 120 and is connected to the opening 115 formed in the filter unit 110. In addition, the opening 127 opens along the edge of the +Y side of the sealing member 120 and is connected to the opening 117 formed in the filter unit 110.

[0205] The wiring substrate 130 is located on the +Z side of the sealing member 120 , and has a substantially parallelogram shape in which two opposing sides extend in the X direction and two opposing sides extend in the column direction RD. Fig.14 1 is a diagram showing an example of the structure of the wiring substrate 130. Fig.14 In FIG. 1 , a structure when the wiring substrate 130 is viewed from the −Z side is indicated by a solid line, and a part of a structure that cannot be visually confirmed when the wiring substrate 130 is viewed from the −Z side is indicated by a dotted line.

[0206] like Fig.14As shown, the wiring substrate 130 has a substrate 400, connectors CN1, CN2 and a semiconductor device 450. In addition to the substrate 400, the connectors CN1, CN2 and the semiconductor device 450, the wiring substrate 130 may also have electronic components such as resistors, capacitors, inductors and semiconductor elements that are not shown in the figure.

[0207] The substrate 400 is a substantially parallelogram having sides 403 and 404 that are opposite to each other and sides 405 and 406 that are opposite to each other, and has a surface 401 and a surface 402 that is different from the surface 401 and opposite to the surface 401. The substrate 400 is arranged such that the side 403 extends along the X direction, the side 404 is located on the +Y side of the side 403 and extends along the X direction, the side 405 extends along the column direction RD, the side 406 is located on the -X side of the side 405 and extends along the column direction RD, and the surface 401 is on the -Z side and the surface 402 is on the +Z side. That is, the substrate 400 is arranged such that the sides 403 and 404 are opposite to each other in the direction along the Y direction, the sides 405 and 406 are opposite to each other in the direction along the X direction, and the surface 401 faces upward and the surface 402 faces downward in the vertical direction. In this case, it is preferable that the substrate 400 is located at a position where the surface 401 is perpendicular to the vertical direction.

[0208] In addition, cutouts 135 are formed at the four corners of the substrate 400. A liquid flow path 145 provided on the bracket 140 described later passes through the cutouts 135. Here, the cutouts 135 may be any structure that can connect the liquid flow path 145 provided on the bracket 140 located on the +Z side of the substrate 400 to the liquid introduction port IS3 of the filter unit 110 located on the -Z side of the substrate 400, and may be, for example, a hole provided in a manner penetrating the surface 401 and the surface 402 so that the liquid flow path 145 can be inserted and passed through.

[0209] In addition, four FPC through holes 136 penetrating the surface 401 and the surface 402 of the substrate 400 and two FPC cutouts 137 in which a part of each of the side 405 and the side 406 of the substrate 400 is cut out are formed on the substrate 400. The flexible wiring substrates 346 respectively provided in the six head chips 300 described later pass through the four FPC through holes 136 and the FPC cutouts 137. Furthermore, the flexible wiring substrates 346 respectively passing through the four FPC through holes 136 and the FPC cutouts 137 are electrically connected to the connection terminals 138 formed on the surface 401 of the substrate 400.

[0210] Alternatively, the substrate 400 may be a so-called multi-layer substrate including a plurality of wiring layers between the surface 401 and a surface 402 that faces the surface 401 .

[0211] The connector CN1 has a plurality of terminals TM1. The connector CN1 is provided on the surface 401 of the substrate 400 in such a manner that the positions of the plurality of terminals TM1 are arranged along the edge 403. Moreover, in the print head 100, the connector CN1 is inserted through the opening 115 formed in the filter section 110 and the opening 125 formed in the sealing member 120, and is exposed on the -Z side of the print head 100. In addition, the connector CN2 has a plurality of terminals TM2. The connector CN2 is provided on the surface 401 of the substrate 400 in such a manner that the positions of the plurality of terminals TM2 are arranged along the edge 404. Moreover, in the print head 100, the connector CN2 is inserted through the opening 117 formed in the filter section 110 and the opening 127 formed in the sealing member 120, and is exposed on the -Z side of the print head 100.

[0212] In addition, the semiconductor device 450 is located on the surface 402 of the substrate 400. The semiconductor device 450 constitutes at least a part of the above-mentioned abnormality detection circuit 250. Such a semiconductor device 450 is a surface mounted component, for example, electrically connected to the substrate 400 via a bump electrode. In addition, the semiconductor device 450 is a surface mounted component, for example, it can be a QFN (Quad Flat No leaded package) electrically connected to the substrate 400 via a plurality of electrodes formed along the four sides of the semiconductor device 450, and it can also be a QFP (Quad Flat Package) electrically connected to the substrate 400 via a plurality of terminals instead of the plurality of electrodes of the QFN.

[0213] When an abnormality occurs in the semiconductor device 450 constituting at least a part of the abnormality detection circuit 250, it may be impossible to normally detect an abnormal operation of the print head 100. In this embodiment, by setting the semiconductor device 450 constituting at least a part of the abnormality detection circuit 250 on the surface 402 located below the substrate 400, the possibility of the ink mist floating inside adhering to the semiconductor device 450 and the possibility of the ink leaking inside the print head 100 adhering to the semiconductor device 450 are reduced, and the possibility of the operation abnormality caused by the adhesion of the ink mist on the semiconductor device 450 constituting at least a part of the abnormality detection circuit 250 is reduced.

[0214] return Fig.13The bracket 140 is located at the +Z side of the wiring substrate 130 and is a substantially parallelogram shape with two opposite sides extending along the X direction and two opposite sides extending along the column direction RD. The bracket 140 includes bracket components 141, 142, and 143. The bracket components 141, 142, and 143 are stacked in the order of the bracket component 141, the bracket component 142, and the bracket component 143 from the -Z side toward the +Z side along the Z direction. In addition, the bracket component 141 and the bracket component 142, and the bracket component 142 and the bracket component 143 are bonded by an adhesive or the like.

[0215] A storage space (not shown) having an opening on the +Z side is formed inside the support member 143. The head chips 300 are stored in the storage space formed inside the support member 143. Here, the storage space formed inside the support member 143 may be a plurality of spaces capable of storing six head chips 300 individually, or may be a single space capable of storing six head chips 300 collectively.

[0216] In addition, the bracket 140 is provided with slit holes 146 corresponding to the six head chips 300. The flexible wiring substrates 346 respectively provided in the six head chips 300 described later pass through the slit holes 146. That is, the slit holes 146 formed in the bracket 140 are provided corresponding to the four FPC through holes 136 and the FPC cutout 137 provided in the wiring substrate 130.

[0217] In addition, four liquid flow paths 145 are provided at four corners of the -Z side surface of the holder 140. The liquid flow paths 145 pass through the cutouts 135 of the wiring substrate 130, are inserted through the through openings 123 provided in the sealing member 120, and are connected to the filter unit 110.

[0218] The fixing plate 150 is located on the +Z side of the bracket 140 and seals the storage space for accommodating six head chips 300 formed inside the bracket part 143. The fixing plate 150 has a plane portion 151 and bent portions 152, 153, and 154. The plane portion 151 is a substantially parallelogram shape with two opposite sides extending along the X direction and two opposite sides extending along the row direction RD. Six openings 155 are formed on the plane portion 151 for exposing the head chip 300. The head chip 300 is fixed to the fixing plate 150 in such a manner that two rows of nozzles are exposed on the +Z side of the print head 100 through the openings 155 on the plane portion 151.

[0219] The bending portion 152 is a component connected to an edge of the plane portion 151 extending along the column direction RD and is bent to the -Z side and is integral with the plane portion 151. The bending portion 153 is a component connected to an edge of the plane portion 151 extending along the X direction and is bent to the -Z side and is integral with the plane portion 151. The bending portion 154 is a component connected to another edge of the plane portion 151 extending along the X direction and is bent to the -Z side and is integral with the plane portion 151.

[0220] The head chip 300 is located at the +Z side of the holder 140 and at the −Z side of the fixing plate 150 . The head chip 300 is accommodated in an accommodation space formed by the holder part 143 of the holder 140 and the fixing plate 150 , and is fixed to the holder part 143 and the fixing plate 150 .

[0221] Fig.15 3 is a diagram showing a schematic structure of the head chip 300. Fig.15 , a cross section of the head chip 300 is shown when the head chip 300 is cut in a direction perpendicular to the column direction RD in such a manner that the head chip 300 includes at least one nozzle 651. Fig.15 As shown, the head chip 300 includes: a nozzle plate 310 provided with a plurality of nozzles 651 for ejecting ink; a flow path forming substrate 321 defining a communication flow path 365, a separate flow path 363, and a reservoir 367; a pressure chamber substrate 322 defining a pressure chamber 369; a protective substrate 323; a flexible portion 330; a vibration plate 340; a piezoelectric element 60; a flexible wiring substrate 346; and a housing 324 defining a reservoir 367 and a liquid introduction port 361. That is, the print head 100 includes a piezoelectric element 60 as an example of a driving element.

[0222] Ink is supplied to the head chip 300 from a discharge port (not shown) provided on the bracket 140 via the liquid introduction port 361. The ink supplied to the head chip 300 reaches the nozzle 651 via the ink flow path 360 including the reservoir 367, the individual flow path 363, the pressure chamber 369, and the communication flow path 365. Then, the ink reaching the nozzle 651 is ejected as the piezoelectric element 60 is driven.

[0223] Specifically, the ink flow path 360 is formed by stacking the flow path forming substrate 321, the pressure chamber substrate 322, and the housing 324 in the Z direction. The ink introduced into the interior of the housing 324 from the liquid introduction port 361 is stored in the reservoir 367. The reservoir 367 is a common flow path connected to a plurality of individual flow paths 363 corresponding to the plurality of nozzles 651 constituting the nozzle array. The ink stored in the reservoir 367 is supplied to the pressure chamber 369 via the individual flow path 363.

[0224] The ink stored in the pressure chamber 369 is pressurized, so that the ink supplied to the pressure chamber 369 is ejected from the nozzle 651 through the connecting flow path 365. The vibration plate 340 is located on the -Z side of the pressure chamber 369 in a manner that seals the pressure chamber 369, and the piezoelectric element 60 is located on the -Z side of the vibration plate 340. The piezoelectric element 60 is composed of a piezoelectric body and a pair of electrodes formed on both sides of the piezoelectric body. A driving signal VOUT is supplied to one of the pair of electrodes of the piezoelectric element 60 via the flexible wiring substrate 346, and a reference voltage signal VBS is supplied to the other of the pair of electrodes of the piezoelectric element 60 via the flexible wiring substrate 346. Moreover, the piezoelectric body is displaced according to the potential difference generated between the pair of electrodes. That is, the piezoelectric element 60 including the piezoelectric body is driven. Then, as the piezoelectric element 60 is driven, the vibration plate 340 provided with the piezoelectric element 60 is deformed, so that the internal pressure of the pressure chamber 369 changes, and as a result, the ink stored in the pressure chamber 369 is ejected from the nozzle 651 through the communication flow path 365 .

[0225] In addition, the nozzle plate 310 and the flexible portion 330 are fixed to the +Z side of the flow path forming substrate 321. The nozzle plate 310 is located on the +Z side of the communication flow path 355. On the nozzle plate 310, a plurality of nozzles 651 are arranged along the row direction RD. That is, the nozzle plate 310 has a plurality of nozzles 651 that eject ink. The flexible portion 330 is located on the +Z side of the reservoir 367 and the individual flow path 363, and includes a closing film 331 and a support body 332. The closing film 331 is a flexible film-like member that closes the +Z side of the reservoir 367 and the individual flow path 363. In addition, the outer peripheral edge of the closing film 331 is supported by the frame-shaped support body 332. In addition, the +Z side of the support body 332 is fixed to the flat portion 151 of the fixed plate 150. By the flexible portion 330 configured as above, the head chip 300 is protected and the pressure fluctuation of the ink inside the reservoir 367 or the individual flow path 363 is reduced.

[0226] Here, the structure including the piezoelectric element 60 , the vibration plate 340 , the nozzle 651 , the individual flow path 363 , the pressure chamber 369 , and the communication flow path 365 corresponds to the ejection unit 600 .

[0227] In addition, a semiconductor device 201, i.e., COF (Chip On Film), is mounted on the flexible wiring substrate 346. The semiconductor device 201 includes a drive signal selection circuit 200. Moreover, the printing data signals SI1 to SIn, the clock signal SCK, the latch signal LAT, the conversion signal CH, and the drive voltage signals VDR1, VDR2, the voltages VHV, and VDD are transmitted in the flexible wiring substrate 346 and supplied to the semiconductor device 201. The semiconductor device 201 generates drive signals VOUT corresponding to the plurality of piezoelectric elements 60 based on the supplied printing data signals SI1 to SIn, the clock signal SCK, the latch signal LAT, the conversion signal CH, and the drive voltage signals VDR1, VDR2, the voltages VHV, and VDD. Then, the semiconductor device 201 supplies the generated drive signal VOUT to the piezoelectric element 60 via the flexible wiring substrate 346.

[0228] The ink distributed in the ejection control unit 20 is supplied to the print head 100 via the four liquid inlet ports IS3. Then, after the bubbles and foreign matter are removed in the filter 113, the ink supplied to the print head 100 is supplied to the bracket 140 via the four liquid flow paths 145. The bracket 140 branches the supplied ink corresponding to the head chip 300, and supplies it to the liquid inlet port 361 of the head chip 300 via the discharge port (not shown) provided in the storage space formed inside the bracket member 143. Thus, the ink distributed in the ejection control unit 20 is supplied to the head chip 300. Then, the ink supplied to the head chip 300 reaches the nozzle 651 via the ink flow path 360 composed of the reservoir 367, the separate flow path 363, the pressure chamber 369 and the communication flow path 365.

[0229] In addition, the other end of the cable FC1 is inserted through the opening 351 provided on the head support part G3, the opening 115 of the filter part 110, and the opening 125 of the sealing member 120 through the introduction flow path part G1 and the supply control part G2, and is electrically connected to the connector CN1 provided on the wiring substrate 130. The other end of the cable FC2 is inserted through the opening 352 provided on the head support part G3, the opening 117 of the filter part 110, and the opening 127 of the sealing member 120 through the introduction flow path part G1 and the supply control part G2, and is electrically connected to the connector CN2 provided on the wiring substrate 130. Thus, the diagnostic control signal HC, the printing data signals SI1 to SIn, the clock signal SCK, the latch signal LAT, the conversion signal CH, the drive voltage signals VDR1 and VDR2, and the reference voltage signal VBS, the voltages VHV and VDD outputted from the ejection control unit 20 are supplied to the print head 100.

[0230] The diagnostic control signal HC, the print data signals SI1 to SIn, the clock signal SCK, the latch signal LAT, the conversion signal CH, the drive voltage signals VDR1 and VDR2, the reference voltage signal VBS, and the voltages VHV and VDD supplied to the print head 100 are transmitted on the substrate 400, and supplied to the semiconductor device 201 including the drive signal selection circuit 200 via the semiconductor device 450 constituting at least a part of the abnormality detection circuit 250, the connection terminal 138, and the flexible wiring substrate 346. The semiconductor device 201 generates a drive signal VOUT corresponding to each piezoelectric element 60 of the head chip 300 based on the supplied signal, and supplies the drive signal to the corresponding piezoelectric element 60. As a result, the piezoelectric element 60 is driven based on the drive signal VOUT, and ink is ejected from the nozzle 651 according to the driving of the piezoelectric element 60.

[0231] 1.5.4 Electrical connection structure between ejection control unit and print head

[0232] As described above, the other end of the cable FC1 of the ejection control unit 20 is electrically connected to the connector CN1 provided on the wiring substrate 130, and the other end of the cable FC2 is electrically connected to the connector CN2 provided on the wiring substrate 130. Thus, the ejection control unit 20 is electrically connected to the print head 100, and as a result, various signals including the diagnostic control signal HC, the printing data signals SI1 to SIn, the clock signal SCK, the latch signal LAT, the conversion signal CH, the drive voltage signals VDR1 and VDR2, the reference voltage signal VBS, and the voltages VHV and VDD output by the ejection control unit 20 are supplied to the print head 100. Therefore, an example of the structure of the cables FC1 and FC2 that electrically connect the ejection control unit 20 and the print head 100, and an example of the structure of the connectors CN1 and CN2 that connect the cables FC1 and FC2 are described, and an example of the electrical connection between the cables FC1 and FC2 and the connectors CN1 and CN2 is described. Here, in the following description, the cables FC1 and FC2 are flexible flat cables of the same structure, and when there is no need to distinguish them, they are simply referred to as cables FC. The connector CN1 and the connector CN2 are FFC connectors of the same structure, and are referred to as connector CN unless they need to be distinguished. That is, in the following description, the other end of the cable FC is electrically connected to the connector CN.

[0233] Fig.16 1 is a diagram showing a schematic structure of a cable FC. The cable FC is a substantially rectangular shape having short sides 191 and 192 facing each other and long sides 193 and 194 facing each other. The cable FC has a plurality of terminals ER1 arranged along the short side 191, a plurality of terminals ER2 arranged along the short side 192, and a plurality of wirings WI electrically connecting the plurality of terminals ER1 and the plurality of terminals ER2.

[0234] Specifically, on the short side 191 side of the cable FC, q terminals ER1 are arranged from the long side 193 side toward the long side 194 side. In addition, on the short side 192 side of the cable FC, q terminals ER2 are arranged from the long side 193 side toward the long side 194 side. In addition, in the cable FC, q wirings WI that electrically connect each terminal ER1 and each terminal ER2 are arranged from the long side 193 side toward the long side 194 side. Moreover, the k-th (k is any one of 1 to q) terminal ER1 from the long side 193 side toward the long side 194 side and the k-th terminal ER2 from the long side 193 side toward the long side 194 side are electrically connected through the k-th wiring WI from the long side 193 side toward the long side 194 side.

[0235] In addition, the q wirings WI are insulated from each other and from the outside of the cable FC by insulators EC. Moreover, the q terminals ER1 of the cable FC are electrically connected to the connection portion 424 or the connection portion 425 of the ejection control unit 20, and the q terminals ER2 are electrically connected to the connector CN of the print head 100. In addition, Fig.16 The structure of the cable FC shown is an example and is not limited thereto. For example, q terminals ER1 and q terminals ER2 may be provided on different surfaces of the cable FC. In addition, the number of terminals ER1, ER2 and wiring WI of the cable FC1 may be the same as or different from the number of terminals ER1, ER2 and wiring WI of the cable FC2.

[0236] Here, q is an integer equal to or greater than 1 and corresponding to the number of the terminals ER1 and ER2 and the wirings WI included in the cable FC.

[0237] Next, the structure of the connector CN will be described. Fig.17 : is a diagram showing the schematic structure of the connector CN. Fig.17 As shown, the connector CN has: a cable installation part CI for the cable FC to be inserted and passed through; q terminals TM electrically connected to the q terminals ER2 of the cable FC; and a housing HP that insulates the q terminals TM from each other, holds the q terminals TM, and forms the cable installation part CI. The q terminals TM are arranged in one direction and along the length direction of the cable installation part CI. The cable FC is installed on the cable installation part CI. In this case, the kth terminal ER2 of the q terminals ER2 included in the cable FC is electrically in contact with the kth terminal TM of the q terminals TM included in the connector CN. As a result, the cable FC is electrically connected to the connector CN. Here, the q terminals TM are equivalent to the multiple terminals TM1 in the connector CN1, and are equivalent to the multiple terminals TM2 in the connector CN2.

[0238] Here, use Fig.18 A specific example of the electrical connection between the cable FC and the connector CN will be described. Fig.18 1 is a diagram showing an example of a situation where the cable FC is installed on the connector CN. Fig.18 As shown, the terminal TM of the connector CN has a cable holding portion EL1, a shell penetration portion EL2, and a substrate mounting portion EL3. The substrate mounting portion EL3 is located below the connector CN and is disposed between the shell HP and the substrate 400. Moreover, the substrate mounting portion EL3 is electrically connected to an electrode not shown in the figure disposed on the substrate 400, for example, by welding or the like. The shell penetration portion EL2 is inserted into and passes through the interior of the shell HP. Moreover, the shell penetration portion EL2 electrically connects the substrate mounting portion EL3 and the cable holding portion EL1. The cable holding portion EL1 has a curved shape protruding toward the interior of the cable mounting portion CI. Moreover, when the cable FC is installed on the cable mounting portion CI, the cable holding portion EL1 and the terminal ER2 are electrically contacted via the contact portion Cnt. As a result, the cable FC is electrically connected to the connector CN, and as a result, the ejection control unit 20 is electrically connected to the print head 100, and various signals are transmitted between the ejection control unit 20 and the print head 100.

[0239] 1.6 Print head inspection method

[0240] 1.6.1 Functional Structure of Abnormality Detection Circuit

[0241] In the liquid ejection device 1 configured as described above, a method for checking whether the signal supplied to the print head 100 is normal or abnormal is described. In the liquid ejection device 1 of the present embodiment, as one of the checks on whether the print head 100 has an abnormality, the abnormality detection circuit 250 provided in the print head 100 checks whether the signal supplied from the ejection control unit 20 to the print head 100 is normal. Then, the abnormality detection circuit 250 allows the ink to be ejected from the print head 100 when it is determined that the signal supplied from the ejection control unit 20 is normal, and does not allow the ink to be ejected from the print head 100 when it is determined that the signal supplied from the ejection control unit 20 is abnormal. That is, the abnormality detection circuit 250 allows printing when the signal supplied to the print head 100 is normal, and does not allow printing when the signal supplied to the print head 100 is abnormal. As a result, the possibility of malfunction, failure, etc. in the print head 100 due to the supply of an unexpected voltage signal to the print head 100 is reduced.

[0242] Therefore, when describing a method of checking whether a signal supplied to the print head 100 is normal or abnormal, first, a functional structure of the abnormality detection circuit 250 that performs a check on whether a signal supplied to the print head 100 is normal or abnormal will be described.

[0243] Fig.19 2 is a diagram showing the functional structure of the abnormality detection circuit 250. Fig.19 In addition to the block diagram of the abnormality detection circuit 250 showing the functional structure, there are also illustrated the ejection control unit 20 that outputs various signals to the print head 100 having the abnormality detection circuit 250; the cable FC that transmits the various signals output by the ejection control unit 20 to the print head 100; the connector CN that connects the cable FC; the wiring substrate 130 including the semiconductor device 450 included in the abnormality detection circuit 250; the semiconductor device 201 including the drive signal selection circuit 200-1 that supplies the output of the abnormality detection circuit 250; and the flexible wiring substrate 346 on which the semiconductor device 201 is mounted. In addition, in Fig.19 In the figure, the drive signal selection circuits 200-2 to 200-6 of the print head 100, the print data signals SI2 to SI6 input to the drive signal selection circuits 200-2 to 200-6, and the head status signals HS2 to HS6 output from the drive signal selection circuits 200-2 to 200-6 are omitted.

[0244] In the following description, among the plurality of wirings WI included in the cable FC and the plurality of terminals TM included in the connector CN, the wiring WI for transmitting the power supply voltage VHV is referred to as wiring WI-VHV, the terminal TM is referred to as terminal TM-VHV, the wiring WI for transmitting the power supply voltage VDD is referred to as wiring WI-VDD, the terminal TM is referred to as terminal TM-VDD, the wiring WI for transmitting the driving voltage signal VDR1 is referred to as wiring WI-VDR1, the terminal TM is referred to as terminal TM-VDR1, the wiring WI for transmitting the driving voltage signal VDR2 is referred to as wiring WI-VDR2, the terminal TM is referred to as terminal TM-VDR2, and the wiring WI for transmitting the power supply voltage VDD is referred to as wiring WI-VDD. The wiring WI for transmitting the brush data signal SI1 and the diagnostic control signal HC is called the wiring WI-SI1 / HC, the terminal TM is called the terminal TM-SI1 / HC, the wiring WI for transmitting the clock signal SCK is called the wiring WI-SCK, the terminal TM is called the terminal TM-SCK, the wiring WI for transmitting the latch signal LAT is called the wiring WI-LAT, the terminal TM is called the terminal TM-LAT, the wiring WI for transmitting the conversion signal CH is called the wiring WI-CH, the terminal TM is called the terminal TM-CH, the wiring WI for transmitting the judgment result signal ES is called the wiring WI-ES, and the terminal TM is called the terminal TM-ES.

[0245] That is, the cable FC as a flexible flat cable includes: wiring WI-VDR1, which transmits a driving voltage signal VDR1 including a driving signal COMA supplied to the piezoelectric element 60; wiring WI-VDR2, which transmits a driving voltage signal VDR2 including a driving signal COMB supplied to the piezoelectric element 60; wiring WI-SI1 / HC, which transmits a printing data signal SI1 and a diagnostic control signal HC for performing printing based on the print head 100; wiring WI-VHV, which transmits a voltage VHV as a power supply voltage; wiring WI-VDD, which transmits a voltage VDD as another power supply voltage; wiring WI-SCK, which transmits a clock signal SCK; and wiring WI-ES, which transmits a determination result signal ES indicating the presence or absence of an abnormality in the print head 100.

[0246] In addition, the connector CN installed with the cable FC includes: a terminal TM-VDR1, which transmits a driving voltage signal VDR1 including a driving signal COMA supplied to the piezoelectric element 60; a terminal TM-VDR2, which transmits a driving voltage signal VDR2 including a driving signal COMB supplied to the piezoelectric element 60; a terminal TM-SI1 / HC, which transmits a printing data signal SI1 and a diagnostic control signal HC for performing printing based on the print head 100; a terminal TM-VHV, which transmits a voltage VHV as a power supply voltage; a terminal TM-VDD, which transmits a voltage VDD as another power supply voltage; a terminal TM-SCK, which transmits a clock signal SCK; and a terminal TM-ES, which transmits a determination result signal ES indicating the presence or absence of an abnormality in the print head 100.

[0247] Furthermore, in the following description, the wiring pattern for transmitting the driving voltage signal VDR1 formed in the wiring pattern of the flexible wiring substrate 346 is referred to as wiring P-VDR1; the wiring pattern for transmitting the driving voltage signal VDR2 is referred to as wiring P-VDR2; the wiring pattern for transmitting the clock signal SCK is referred to as wiring P-SCK; the wiring pattern for transmitting the latch signal LAT is referred to as wiring P-LAT; the wiring pattern for transmitting the conversion signal CH is referred to as wiring P-CH; the wiring pattern for transmitting the printing data signal SI1 is referred to as wiring P-SI1; and the wiring pattern for transmitting the head status signal HS1 is referred to as wiring P-HS1.

[0248] like Fig.19 As shown, the abnormality detection circuit 250 includes a semiconductor device 450 and a voltage input switching circuit 251. In addition, the semiconductor device 450 includes a determination control circuit 451, a voltage determination circuit 452, an output switching circuit 453, and a storage circuit 454.

[0249] The determination control circuit 451 is electrically connected to the terminal TM-SI1 / HC and the terminal TM-SCK. Furthermore, the determination control circuit 451 obtains a signal input from the discharge control unit 20 via the wiring WI-SI1 / HC and the terminal TM-SI1 / HC when a signal is input from the discharge control unit 20 via the wiring WI-SCK and the terminal TM-SCK, and controls the operation of each structure of the semiconductor device 450 according to the obtained signal input from the discharge control unit 20 via the wiring WI-SI1 / HC and the terminal TM-SI1 / HC.

[0250] The determination control circuit 451 reads out information stored in the storage circuit 454 based on a signal input from the discharge control unit 20 via the wiring WI-SI1 / HC and the terminal TM-SI1 / HC, generates a storage circuit control signal RW for storing desired information in the storage circuit 454, and outputs it to the storage circuit 454. Such a storage circuit 454 includes a register, a temporary storage area such as a RAM (Random Access Memory), a memory, and a permanent storage area such as a ROM (Read Only Memory).

[0251] Furthermore, the determination control circuit 451 outputs a voltage switching signal SV to the voltage input switching circuit 251 provided outside the semiconductor device 450 based on a signal input from the discharge control unit 20 via the wiring WI-SI1 / HC and the terminal TM-SI1 / HC.

[0252] The voltage input switching circuit 251 includes resistors R10, R11, R12, and R13 and transistors M10 and M11. In this embodiment, the transistor M10 is described as an n-channel FET (Field-Effect Transistor) and the transistor M11 is a p-channel FET.

[0253] One end of the resistor R10 is electrically connected to the terminal TM-VDR1 for transmitting the driving voltage signal VDR1, and the other end of the resistor R10 is electrically connected to one end of the resistor R11. The other end of the resistor R11 is electrically connected to the drain of the transistor M10. The voltage switching signal SV output by the semiconductor device 450 is input to the gate of the transistor M10, and the ground potential is supplied to the source of the transistor M10. In addition, the source of the transistor M11 is electrically connected to the terminal TM-VDR1 for transmitting the driving voltage signal VDR1, the gate of the transistor M11 is electrically connected to the other end of the resistor R10 and one end of R11, and the drain of the transistor M11 is electrically connected to one end of the resistor R12. The other end of the resistor R12 is electrically connected to one end of the resistor R13, and the ground potential is supplied to the other end of the resistor R13. Moreover, the voltage input switching circuit 251 outputs the signal generated at the connection point connecting the other end of the resistor R12 and one end of the resistor R13 as the voltage detection signal DET to the semiconductor device 450. That is, the determination control circuit 451 uses the voltage switching signal SV to control the operation of the transistors M10 and M11 included in the voltage input switching circuit 251, and the voltage input switching circuit 251 outputs the voltage detection signal DET corresponding to the potential of the terminal TM-VDR1 to the semiconductor device 450 based on the voltage switching signal SV.

[0254] In addition, the determination control circuit 451 uses the storage circuit control signal RW to read out information indicating the determination condition in the voltage determination circuit 452 stored in the storage circuit 454. Then, the determination control circuit 451 generates a determination condition signal JC including the read information, and outputs it to the voltage determination circuit 452. In addition, the determination condition signal JC output by the determination control circuit 451 and the voltage detection signal DET output by the voltage input switching circuit 251 are input to the voltage determination circuit 452. The voltage determination circuit 452 determines whether the voltage detection signal DET is normal based on the input determination condition signal JC and the voltage detection signal DET, generates a determination result signal JR indicating the result of the determination, and outputs it to the determination control circuit 451.

[0255] The determination control circuit 451 generates a switch control signal OS based on the determination result signal JR input from the voltage determination circuit 452 , and outputs the switch control signal OS to the output switching circuit 453 .

[0256] The output switching circuit 453 includes a switch group SW including a plurality of switching switches. One end of one of the plurality of switching switches included in the switch group SW is electrically connected to the terminal TM-SI1 / HC, and the other end is electrically connected to the wiring P-SI1. Another one of the plurality of switching switches included in the switch group SW has one end electrically connected to the terminal TM-SCK, and the other end is electrically connected to the wiring P-SCK. Similarly, another one of the plurality of switching switches included in the switch group SW has one end electrically connected to the terminal TM-LAT, and the other end is electrically connected to the wiring P-LAT, and another one of the plurality of switching switches included in the switch group SW has one end electrically connected to the terminal TM-CH, and the other end is electrically connected to the wiring P-CH.

[0257] Furthermore, the plurality of switches included in the switch group SW included in the output switching circuit 453 are controlled to be conductive or non-conductive according to the switch control signal OS input from the determination control circuit 451. That is, the output switching circuit 453 switches whether the signals transmitted at the terminals TM-SI1 / HC, TM-SCK, TM-LAT, and TM-CH are transmitted to the corresponding wirings P-SI1, P-SCK, P-LAT, and P-CH, respectively.

[0258] Here, the switch group SW may include a switch having one end electrically connected to the terminals TM-VDR1 and TM-VDR2, respectively, and the other end electrically connected to the wirings P-VDR1 and PVDR2, respectively. In addition, the switch group SW may not include any of the switches having one end electrically connected to the terminals TM-SI1 / HC, TM-SCK, TM-LAT, and TM-CH, respectively, and the other end electrically connected to the wirings P-SI1, P-SCK, P-LAT, and P-CH, respectively. That is, the output switching circuit 453 only needs to include a switch that can control the electrical connection between the terminals TM-SCK, TM-LAT, TM-CH, TM-VDR1, and TM-VDR2 and at least one of the wirings P-SCK, P-LAT, P-CH, P-VDR1, and P-VDR2.

[0259] The multiple switches included in the switch group SW may be composed of transistors such as FETs. In this case, the multiple switches included in the switch group SW are controlled to be turned on or off according to the logic level of the switch control signal OS output by the determination control circuit 451. Fig.19 The structure shown, for example, can also control the transmission of signals between each terminal TM-SCK, TM-LAT, TM-CH, TM-VDR1, TM-VDR2 and each wiring P-SCK, P-LAT, P-CH, P-VDR1, P-VDR2 by switching whether the wiring transmitting various signals is connected to the ground potential.

[0260] Here, for the multiple switching switches included in the switch group SW of this embodiment, it is explained that when the switch control signal OS of the H level is input from the judgment control circuit 451, one end and the other end are controlled to be conductive, and when the switch control signal OS of the L level is input, one end and the other end are controlled to be non-conductive.

[0261] In addition, the head state signal HS1 indicating the state of the head chip 300-1 corresponding to the drive signal selection circuit 200-1 is input to the determination control circuit 451. Fig.19 The head status signals HS2 to HS6 indicating the states of the head chips 300-2 to 300-6 corresponding to the drive signal selection circuits 200-2 to 200-6 are omitted. Then, the determination control circuit 451 generates a determination result signal ES indicating whether the signal supplied to the print head 100 is normal and whether the drive signal selection circuits 200-1 to 200-6 of the print head 100 are normal based on the determination result signal JR and the head status signals HS1 to HS6, and outputs the determination result signal ES to the ejection control unit 20 via the terminal TM-ES and the wiring WI-ES.

[0262] In the abnormality detection circuit 250 configured as described above, the voltage input switching circuit 251, the determination control circuit 451, and the voltage determination circuit 452 determine whether the potential of the signal transmitted in the wiring WI-VDR1 and the terminal TM-VDR1 is normal based on the signal transmitted in the terminal TM-SI1 / HC. The determination control circuit 451 and the output switching circuit 453 control the plurality of switches included in the switch group SW included in the output switching circuit 453 based on the determination result, thereby switching whether the signal transmitted in the terminals TM-SI1 / HC, TM-SCK, TM-LAT, and TM-CH is supplied to the drive signal selection circuit 200-1 via the wirings P-SI1, P-SCK, P-LAT, and P-CH. Thus, the generation of the drive signal VOUT by the drive signal selection circuits 200-1 to 200-6 is controlled. That is, the abnormality detection circuit 250 allows the ejection of ink from the print head 100 when the signal supplied to the print head 100 is normal, and does not allow the ejection of ink from the print head 100 when the signal supplied to the print head 100 is abnormal.

[0263] Here, if Figure 11 to Figure 14As shown, in the liquid ejection device 1 of the present embodiment, the ejection control unit 20 transmits the drive voltage signals VDR1, VDR2, the voltages VHV, VDD, the diagnostic control signal HC, the printing data signal SI1, the clock signal SCK, the latch signal LAT, the conversion signal CH and the judgment result signal ES via the cable FC1 and the cable FC2 as the cable FC and the connectors CN1 and CN2 as the connectors CN. In such a liquid ejection device 1, the drive voltage signals VDR1, VDR2, the voltages VHV, VDD, the diagnostic control signal HC, the printing data signal SI, the clock signal SCK, the latch signal LAT, the conversion signal CH and the judgment result signal ES supplied to the abnormality detection circuit 250 possessed by the print head 100 are preferably transmitted via the same cable FC and the connector CN. And, in the case as Fig.14 In the wiring substrate 130 shown, it is preferable to perform transmission via the cable FC1 and the connector CN1 provided in the vicinity of the semiconductor device 450 included in the abnormality detection circuit 250 .

[0264] As a result, the wiring length for transmitting the signal supplied to the abnormality detection circuit 250 can be shortened, and the difference in wiring length that may occur between the wirings for transmitting various signals can be reduced. Therefore, the possibility of noise etc. being superimposed on the signal supplied to the abnormality detection circuit 250 is reduced, and the possibility of the accuracy of the signal supplied to the abnormality detection circuit 250 being reduced is reduced.

[0265] 1.6.2 Operation of the Abnormality Detection Circuit

[0266] Next, an example of the operation of the abnormality detection circuit 250 included in the print head 100 will be described. First, the operation of the abnormality detection circuit 250 when the signal supplied to the print head 100 is normal will be described. Fig. 20 as well as Fig.21 This is a diagram showing an example of the operation of the abnormality detection circuit 250 when the signal supplied to the print head 100 is normal.

[0267] like Fig. 20As shown, at time t1, an AC voltage AC, for example, a commercial AC voltage of 100V, is supplied from the commercial AC power supply 7 to the power supply voltage output circuit 12 of the liquid ejection device 1. The power supply voltage output circuit 12 generates voltages VHV and VDD based on the supplied AC voltage AC, and supplies them to various parts of the liquid ejection device 1. As a result, the abnormality detection circuit 250 of the print head 100 and the semiconductor device 450 included in the abnormality detection circuit 250 start to operate. At this time, the semiconductor device 450 performs a power-on reset (POR: Power On Reset) by being supplied with the power supply voltage. As a result, the information retained in the temporary storage area such as the register and RAM included in the storage circuit 454 is initialized.

[0268] After the voltages VHV and VDD are supplied to the print head 100 and the voltage values ​​are stabilized, and at time t2 after the semiconductor device 450 performs POR, the ejection control unit 20 generates a voltage signal VS1 of a DC voltage with a constant potential V1 higher than the threshold voltage Vt as a drive voltage signal VDR1. Then, the ejection control unit 20 supplies the generated voltage signal VS1 to the print head 100 via the wiring WI-VDR1 and the terminal TM-VDR1. At this time, the voltage signal VS1 as the drive voltage signal VDR1 is transmitted through the wiring WI-VDR1 and the terminal TM-VDR1. Therefore, the potential V1 is maintained in the wiring WI-VDR1 and the terminal TM-VDR1.

[0269] Here, in the liquid ejection device 1, whether the voltage values ​​of the voltages VHV and VDD are stable can be based on, for example, the liquid ejection device 1 has a detection circuit not shown in the figure, which detects the voltage values ​​of the voltages VHV and VDD, and makes a judgment based on whether the fluctuation range of the voltage values ​​of the voltages VHV and VDD is within a prescribed range. In addition, it can also be judged by whether a prescribed time has passed after a prescribed circuit such as the semiconductor device 450 included in the abnormality detection circuit 250 starts to operate.

[0270] In addition, the voltage value of the voltage VHV and VDD supplied to the print head 100 is stable, which means that it is not limited to the state that the voltage value of the voltage VHV and VDD supplied to the print head 100 is completely constant, and also includes the case where the voltage VHV and VDD can be regarded as a substantially constant voltage value when the error caused by circuit deviation, temperature characteristics, noise, etc. are taken into account. In addition, in the following description, when the expression "after the voltage value is stabilized" is used for various signals other than the voltage VHV and VDD, the same explanation is used.

[0271] At time t3 after the voltage value of the voltage signal VS1 as the driving voltage signal VDR1 output by the ejection control unit 20 is stabilized at the potential V1, the ejection control unit 20 generates a first instruction cmd1 corresponding to the voltage signal VS1 at the potential V1 as the diagnostic control signal HC synchronized with the clock signal SCK. Then, the ejection control unit 20 supplies the generated first instruction cmd1 to the print head 100 via the wiring WI-SI1 / HC and the terminal TM-SI1 / HC, and supplies the clock signal SCK to the print head 100 via the wiring WI-SCK and the terminal TM-SCK. The first instruction cmd1 and the clock signal SCK supplied to the print head 100 are input to the determination control circuit 451 included in the semiconductor device 450 of the abnormality detection circuit 250.

[0272] The determination control circuit 451 analyzes the input first instruction cmd1 based on the timing specified by the clock signal SCK. Then, at time t4 after the determination control circuit 451 recognizes that the first instruction cmd1 is a normal instruction, the determination control circuit 451 generates a storage circuit control signal RW for reading the determination information c1 corresponding to the first instruction cmd1 from the storage circuit 454, and outputs it to the storage circuit 454. Thus, the determination information c1 corresponding to the voltage signal VS1 of the potential V1 is read from the storage circuit 454. Then, the determination control circuit 451 generates a determination condition signal JC including the read determination information c1, and outputs it to the voltage determination circuit 452. In this embodiment, a potential V1 higher than the threshold voltage Vt is supplied to the wiring WI-VDR1 and the terminal TM-VDR1. Therefore, the determination information c1 includes the following determination condition: when the voltage value of the voltage detection signal DET corresponding to the potential held by the wiring WI-VDR1 and the terminal TM-VDR1 exceeds the threshold voltage Vth corresponding to the threshold voltage Vt, the voltage detection signal DET is determined to be normal. Here, the threshold voltage Vth is a potential obtained by dividing the threshold voltage Vt by the resistors R12 and R13.

[0273] In addition, at time t5 after the determination control circuit 451 recognizes that the first command cmd1 is a normal command, the determination control circuit 451 generates an H-level voltage switching signal SV and outputs it to the voltage input switching circuit 251. As a result, the drain and source of the transistor M10 included in the voltage input switching circuit 251 are controlled to be turned on, and accordingly, the source and drain of the transistor M11 are controlled to be turned on. As a result, the voltage input switching circuit 251 outputs a voltage detection signal DET having a voltage value obtained by dividing the potential V1 of the voltage signal VS1 held in the wiring WI-VDR1 and the terminal TM-VDR1 by the resistor R12 and the resistor R13 to the voltage determination circuit 452.

[0274] Here, in Fig. 20 In an example of the operation of the abnormality detection circuit 250 shown in FIG. 2 , it is illustrated that after the judgment control circuit 451 recognizes that the first instruction cmd1 is a normal instruction, the judgment control circuit 451 reads the judgment information c1 stored in the storage circuit 454 based on the first instruction cmd1, outputs the judgment condition signal JC including the judgment information c1 to the voltage judgment circuit 452, and then the judgment control circuit 451 outputs the H-level voltage switching signal SV to the voltage input switching circuit 251, thereby supplying the voltage judgment circuit 452 with a voltage value corresponding to the potential maintained on the wiring WI-VDR1 and the terminal TM-VDR1. The voltage detection signal DET may also be that after the judgment control circuit 451 recognizes that the first instruction cmd1 is a normal instruction, the judgment control circuit 451 outputs the H-level voltage switching signal SV to the voltage input switching circuit 251, thereby supplying the voltage judgment circuit 452 with a voltage detection signal DET having a voltage value corresponding to the potential maintained on the wiring WI-VDR1 and the terminal TM-VDR1. Then, the judgment control circuit 451 reads out the judgment information c1 stored in the storage circuit 454 based on the first instruction cmd1, and outputs the judgment condition signal JC including the judgment information c1 to the voltage judgment circuit 452. In addition, the following can also be performed in parallel: after the judgment control circuit 451 identifies the first instruction cmd1 as a normal instruction, the judgment control circuit 451 reads out the judgment information c1 stored in the storage circuit 454 based on the first instruction cmd1, and outputs the judgment condition signal JC including the judgment information c1 to the voltage judgment circuit 452; and the judgment control circuit 451 outputs the H-level voltage switching signal SV to the voltage input switching circuit 251, thereby supplying the voltage judgment circuit 452 with a voltage detection signal DET having a voltage value corresponding to the potential maintained on the wiring WI-VDR1 and the terminal TM-VDR1.

[0275] That is, in Fig. 20 Either the action executed at time t4 or the action executed at time t5 may be executed first, or they may be executed in parallel.

[0276] At time t6 after the voltage determination circuit 452 receives the determination condition signal JC including the determination information c1 and the voltage detection signal DET having a voltage value corresponding to the potential held on the wiring WI-VDR1 and the terminal TM-VDR1, the voltage determination circuit 452 compares the voltage detection signal DET with the determination information c1 included in the determination condition signal JC. Fig. 20In the example of the operation of the abnormality detection circuit 250 shown in FIG. 1 , a potential V1 higher than the threshold voltage Vt is maintained on the wiring WI-VDR1 and the terminal TM-VDR1. Therefore, a voltage detection signal DET higher than the threshold voltage Vth is input to the voltage determination circuit 452. As a result, the voltage determination circuit 452 determines that the potential maintained by the wiring WI-VDR1 and the terminal TM-VDR1 is normal, generates a determination result signal JR indicating that the potential maintained by the wiring WI-VDR1 and the terminal TM-VDR1 is normal, and outputs it to the determination control circuit 451. In addition, Fig. 20 In the figure, the determination result signal JR indicating that the potentials held by the wiring WI-VDR1 and the terminal TM-VDR1 are normal is shown as a signal at H level, but the present invention is not limited to this and may be a specific command.

[0277] Then, the determination control circuit 451 generates result information r1 indicating that the potential held by the wiring WI-VDR1 and the terminal TM-VDR1 is normal based on the input determination result signal JR. Then, the determination control circuit 451 outputs a storage circuit control signal RW for storing the generated result information r1 in the storage circuit 454 to the storage circuit 454. Thus, the result information r1 indicating that the potential held by the wiring WI-VDR1 and the terminal TM-VDR1 is normal is stored in the storage circuit 454.

[0278] At time t7 after the result information r1 is stored in the storage circuit 454, the ejection control unit 20 generates the second command cmd2 as the diagnosis control signal HC synchronized with the clock signal SCK. Then, the ejection control unit 20 supplies the generated second command cmd2 to the print head 100 via the wiring WI-SI1 / HC and the terminal TM-SI1 / HC, and supplies the clock signal SCK to the print head 100 via the wiring WI-SCK and the terminal TM-SCK. The second command cmd2 and the clock signal SCK supplied to the print head 100 are input to the determination control circuit 451 included in the semiconductor device 450 of the abnormality detection circuit 250.

[0279] The determination control circuit 451 analyzes the input second instruction cmd2 based on the timing specified by the clock signal SCK. Then, at time t8 after the determination control circuit 451 recognizes that the second instruction cmd2 is a normal instruction, the determination control circuit 451 generates an L-level voltage switching signal SV and outputs it to the voltage input switching circuit 251. As a result, the drain and source of the transistor M10 included in the voltage input switching circuit 251 are controlled to be non-conductive, and along with this, the source and drain of the transistor M11 are controlled to be non-conductive. As a result, the connection point of the resistor R12 and the resistor R13 included in the voltage input switching circuit 251 and the wiring WI-VDR1 and the terminal TM-VDR1 are electrically disconnected, and the voltage input switching circuit 251 outputs the voltage detection signal DET of the ground potential connected via the resistor R13 to the voltage determination circuit 452.

[0280] In addition, at time t8 after the determination control circuit 451 recognizes that the second command cmd2 is a normal command, the determination control circuit 451 generates a determination condition signal JC including stop information st for terminating the determination of whether the potential held on the wiring WI-VDR1 and the terminal TM-VDR1 is normal, which is executed based on the first command cmd1, and outputs it to the voltage determination circuit 452. The voltage determination circuit 452 terminates the determination processing by inputting the determination condition signal JC including the stop information st, and sets the logic level of the determination result signal JR to the L level.

[0281] At time t9 after the voltage determination circuit 452 stops outputting the determination result signal JR, the ejection control unit 20 generates a voltage signal VS2 of a DC voltage constant at a potential V2 lower than the threshold voltage Vt as the drive voltage signal VDR1. Then, the ejection control unit 20 supplies the generated voltage signal VS2 to the print head 100 via the wiring WI-VDR1 and the terminal TM-VDR1. At this time, the voltage signal VS2 as the drive voltage signal VDR1 is transmitted in the wiring WI-VDR1 and the terminal TM-VDR1. Therefore, the potential V2 is maintained in the wiring WI-VDR1 and the terminal TM-VDR1.

[0282] At time t10 after the voltage value of the voltage signal VS2 as the driving voltage signal VDR1 output by the ejection control unit 20 is stabilized at the potential V2, the ejection control unit 20 generates a third instruction cmd3 corresponding to the voltage signal VS2 at the potential V2 as the diagnostic control signal HC synchronized with the clock signal SCK. Then, the ejection control unit 20 supplies the generated third instruction cmd3 to the print head 100 via the wiring WI-SI1 / HC and the terminal TM-SI1 / HC, and supplies the clock signal SCK to the print head 100 via the wiring WI-SCK and the terminal TM-SCK. The third instruction cmd3 and the clock signal SCK supplied to the print head 100 are input to the determination control circuit 451 included in the semiconductor device 450 of the abnormality detection circuit 250.

[0283] The determination control circuit 451 analyzes the input third instruction cmd3 based on the timing specified by the clock signal SCK. Then, at time t11 after the determination control circuit 451 recognizes that the third instruction cmd3 is a normal instruction, the determination control circuit 451 generates a storage circuit control signal RW for reading the determination information c2 corresponding to the third instruction cmd3 from the storage circuit 454, and outputs it to the storage circuit 454. Thus, the determination information c2 corresponding to the voltage signal VS2 of the potential V2 is read from the storage circuit 454. Then, the determination control circuit 451 generates a determination condition signal JC including the read determination information c2, and outputs it to the voltage determination circuit 452. In this embodiment, a potential V2 lower than the threshold voltage Vt is supplied to the wiring WI-VDR1 and the terminal TM-VDR1. Therefore, the judgment information c2 includes the following judgment conditions: a judgment condition for judging that the potential of the voltage detection signal DET is normal when the voltage value of the voltage detection signal DET corresponding to the potential maintained by the wiring WI-VDR1 and the terminal TM-VDR1 is lower than the threshold voltage Vth corresponding to the threshold voltage Vt.

[0284] In addition, at time t12 after the determination control circuit 451 recognizes that the third instruction cmd3 is a normal instruction, the determination control circuit 451 generates an H-level voltage switching signal SV and outputs it to the voltage input switching circuit 251. As a result, the drain and source of the transistor M10 included in the voltage input switching circuit 251 are controlled to be turned on, and accordingly, the source and drain of the transistor M11 are controlled to be turned on. As a result, the voltage input switching circuit 251 outputs the voltage detection signal DET of the voltage value obtained by dividing the potential V2 of the voltage signal VS2 held on the wiring WI-VDR1 and the terminal TM-VDR1 by the resistor R12 and the resistor R13 to the voltage determination circuit 452.

[0285] Here, in Fig. 20 The operation executed at time t11 and the operation executed at time t12 shown in the figure may be executed either one of them first or in parallel, similarly to the operations executed at time t4 and time t5 described above.

[0286] At time t13 after the voltage determination circuit 452 receives the determination condition signal JC including the determination information c2 and the voltage detection signal DET having a voltage value corresponding to the potential held on the wiring WI-VDR1 and the terminal TM-VDR1, the voltage determination circuit 452 compares the voltage detection signal DET with the determination information c2 included in the determination condition signal JC. Fig. 20 In the example of the operation of the abnormality detection circuit 250 shown in FIG. 1 , a potential V2 lower than the threshold voltage Vt is held on the wiring WI-VDR1 and the terminal TM-VDR1. Therefore, a voltage detection signal DET lower than the threshold voltage Vth is input to the voltage determination circuit 452. As a result, the voltage determination circuit 452 determines that the potential held by the wiring WI-VDR1 and the terminal TM-VDR1 is normal, generates an H-level determination result signal JR indicating that the potential held by the wiring WI-VDR1 and the terminal TM-VDR1 is normal, and outputs the signal to the determination control circuit 451.

[0287] Then, the determination control circuit 451 generates result information r2 indicating that the potential held by the wiring WI-VDR1 and the terminal TM-VDR1 is normal based on the input determination result signal JR. Then, the determination control circuit 451 outputs a storage circuit control signal RW for storing the generated result information r2 in the storage circuit 454 to the storage circuit 454. Thus, the result information r2 indicating that the potential held by the wiring WI-VDR1 and the terminal TM-VDR1 is normal is stored in the storage circuit 454.

[0288] At time t14 after the result information r2 is stored in the storage circuit 454, the ejection control unit 20 generates a fourth command cmd4 as a diagnostic control signal HC synchronized with the clock signal SCK. Then, the ejection control unit 20 supplies the generated fourth command cmd4 to the print head 100 via the wiring WI-SI1 / HC and the terminal TM-SI1 / HC, and supplies the clock signal SCK to the print head 100 via the wiring WI-SCK and the terminal TM-SCK. The fourth command cmd4 and the clock signal SCK supplied to the print head 100 are input to the determination control circuit 451 included in the semiconductor device 450 of the abnormality detection circuit 250.

[0289] The determination control circuit 451 analyzes the input fourth instruction cmd4 based on the timing specified by the clock signal SCK. Then, at time t15 after the determination control circuit 451 recognizes that the fourth instruction cmd4 is a normal instruction, the determination control circuit 451 generates an L-level voltage switching signal SV and outputs it to the voltage input switching circuit 251. As a result, the drain and source of the transistor M10 included in the voltage input switching circuit 251 are controlled to be non-conductive, and along with this, the source and drain of the transistor M11 are controlled to be non-conductive. As a result, the connection point of the resistor R12 and the resistor R13 included in the voltage input switching circuit 251 and the wiring WI-VDR1 and the terminal TM-VDR1 are electrically disconnected, and the voltage input switching circuit 251 outputs the voltage detection signal DET of the ground potential connected via the resistor R13 to the voltage determination circuit 452.

[0290] In addition, at time t15 after the determination control circuit 451 recognizes that the fourth command cmd4 is a normal command, the determination control circuit 451 generates a determination condition signal JC including stop information st for terminating the determination of whether the potential held on the wiring WI-VDR1 and the terminal TM-VDR1 is normal, which is executed based on the third command cmd3, and outputs it to the voltage determination circuit 452. The voltage determination circuit 452 sets the logic level of the determination result signal JR to the L level by inputting the determination condition signal JC including the stop information st.

[0291] At time t16 after the voltage determination circuit 452 stops outputting the determination result signal JR, the ejection control unit 20 stops generating the voltage signal VS2 having a constant potential V2 as the drive voltage signal VDR1. Thus, the wiring WI-VDR1 and the terminal TM-VDR1 are kept at the ground potential.

[0292] Then, if Fig.21 As shown, at time t17 after the ejection control unit 20 stops generating the drive voltage signal VDR1 , the determination control circuit 451 generates a storage circuit control signal RW for reading the result information r1 , r2 stored in the storage circuit 454 , and outputs it to the storage circuit 454 .

[0293] exist Fig. 20 , Fig.21In the example of the operation of the abnormality detection circuit 250 shown in FIG. 1 , the storage circuit 454 stores the result information r1 indicating that the signal input to the print head 100 at time t6 is normal and the result information r2 indicating that the signal input to the print head 100 at time t13 is normal. That is, the result information r1 and r2 read from the storage circuit 454 by the judgment control circuit 451 both include information indicating that the signal input to the print head 100 is normal. At time t18 after the judgment control circuit 451 judges that both the result information r1 and r2 read at time t17 are normal, the switch control signal OS of the H level is output. As a result, the plurality of switching switches included in the switch group SW of the output switching circuit 453 are controlled to be turned on. Therefore, the wiring WI-SI1 / SC and the terminal TM-SI1 / HC are connected to the wiring P-SI1, the wiring WI-SCK and the terminal TM-SCK are connected to the wiring P-SCK, the wiring WI-LAT and the terminal TM-LAT are connected to the wiring P-LAT, and the wiring WI-CH and the terminal TM-CH are connected to the wiring P-CH.

[0294] At time t19 after the judgment control circuit 451 outputs the switch control signal OS of the H level, the ejection control unit 20 generates a drive voltage signal VDR1 whose voltage value is constant at the voltage Vc and supplies it to the wiring WI-VDR1 and the terminal TM-VDR1, and generates a drive voltage signal VDR2 whose voltage value is constant at the voltage Vc and supplies it to the wiring WI-VDR2 and the terminal TM-VDR2. Then, at time t20 when the image data PD is input to the liquid ejection device 1, the ejection control unit 20 generates a drive signal COMA including trapezoidal waveforms Adp1 and Adp2 as the drive voltage signal VDR1, and supplies it to the wiring WI-VDR1 and the terminal TM-VDR1, and generates a drive signal COMB including trapezoidal waveforms Bdp1 and Bdp2 as the drive voltage signal VDR2, and supplies it to the wiring WI-VDR2 and the terminal TM-VDR2. Thus, the drive signal COMA is transmitted through the wiring WI-VDR1 and the terminal TM-VDR1 and supplied to the drive signal selection circuit 200-1, and the drive signal COMB is transmitted through the wiring WI-VDR2 and the terminal TM-VDR2 and supplied to the drive signal selection circuit 200-1.

[0295] At time t21 after the supply of the driving signals COMA and COMB is started, the ejection control unit 20 generates a print data signal SI1, a clock signal SCK, a latch signal LAT, and a conversion signal CH for forming an image based on the image data PD on the medium P. Then, the ejection control unit 20 outputs the generated print data signal SI1, the clock signal SCK, the latch signal LAT, and the conversion signal CH to the corresponding wiring WI-SI1 / HC and terminal TM-SI1 / HC, wiring WI-SCK and terminal TM-SCK, wiring WI-LAT and terminal TM-LAT, wiring WI-CH and terminal TM-CH. That is, after transmitting the diagnostic control signal HC1 including the first command cmd1, the second command cmd2, the third command cmd3, and the fourth command cmd4, the wiring WI-SI1 / HC and the terminal TM-SI1 / HC transmit the print data signal SI for causing the print head 100 to perform printing.

[0296] In this case, since the multiple switching switches included in the switch group SW of the output switching circuit 453 are controlled to be turned on by the switch control signal OS, the printing data signal SI1 transmitted through the wiring WI-SI1 / HC and the terminal TM-SI1 / HC is supplied to the drive signal selection circuit 200-1 via the wiring P-SI1, the clock signal SCK transmitted through the wiring WI-SCK and the terminal TM-SCK is supplied to the drive signal selection circuit 200-1 via the wiring P-SCK, the latch signal LAT transmitted in the wiring WI-LAT and the terminal TM-LAT is supplied to the drive signal selection circuit 200-1 via the wiring P-LAT, and the conversion signal CH transmitted in the wiring WI-CH and the terminal TM-CH is supplied to the drive signal selection circuit 200-1 via the wiring P-CH.

[0297] Then, the drive signal selection circuit 200 - 1 generates a drive signal VOUT based on the input printing data signal SI1, the clock signal SCK, the latch signal LAT, the conversion signal CH, the drive signal COMA as the drive voltage signal VDR1, and the drive signal COMB as the drive voltage signal VDR2, and supplies the generated drive signal VOUT to the piezoelectric element 60.

[0298] In addition, although Figure 19 to Figure 21Although not shown in the figure, the drive signal selection circuits 200-2 to 200-6 also supply the following: the clock signal SCK, latch signal LAT and conversion signal CH outputted by the abnormality detection circuit 250, the corresponding printing data signals SI2 to SI6 outputted by the ejection control unit 20, the drive signal COMA as the drive voltage signal VDR1 and the drive signal COMB as the drive voltage signal VDR2. Thus, the drive signal selection circuits 200-2 to 200-6 also generate the drive signal VOUT in the same manner, and supply the generated drive signal VOUT to the corresponding piezoelectric element 60.

[0299] As a result, ink is ejected from the nozzles 651 corresponding to the piezoelectric elements 60 included in the print head 100 , and a desired image is formed on the medium P.

[0300] Next, the operation of abnormality detection circuit 250 will be described when an abnormality occurs in a signal supplied to print head 100 and a short circuit abnormality occurs between wirings WI of cable FC that transmits various signals to print head 100 or between terminals TM of connector CN. Fig. 22 as well as Fig.23 FIG. 2 is a diagram showing an example of the operation of the abnormality detection circuit 250 when the signal supplied to the print head 100 is abnormal. Fig. 22 as well as Fig.23 In the example of the operation of the abnormality detection circuit 250 shown in FIG. 1 , a case where the wiring WI-VDR1 or the terminal TM-VDR1 for transmitting the driving voltage signal VDR1 and the wiring WI or the terminal TM for transmitting the ground potential are short-circuited.

[0301] like Fig. 22 As shown, at time t31, an AC voltage AC, for example, a commercial AC voltage of 100V, is supplied from the commercial AC power supply 7 to the power supply voltage output circuit 12 of the liquid ejection device 1. The power supply voltage output circuit 12 generates voltages VHV and VDD based on the supplied AC voltage AC, and supplies them to various parts of the liquid ejection device 1. As a result, the abnormality detection circuit 250 of the print head 100 and the semiconductor device 450 included in the abnormality detection circuit 250 start to operate. At this time, the semiconductor device 450 performs POR. As a result, the information retained in the temporary storage area such as the register and RAM included in the storage circuit 454 is initialized.

[0302] After the voltages VHV and VDD are supplied to the print head 100 and the voltage values ​​are stabilized, and at time t32 after the semiconductor device 450 performs POR, the ejection control unit 20 generates a voltage signal VS1 of a DC voltage with a constant potential V1 higher than the threshold voltage Vt as a driving voltage signal VDR1. Then, the ejection control unit 20 supplies the generated voltage signal VS1 to the wiring WI-VDR1 and the terminal TM-VDR1. At this time, the wiring WI-VDR1 or the terminal TM-VDR1 is short-circuited with the wiring WI or the terminal TM for transmitting the ground potential. Therefore, the wiring WI-VDR1 and the terminal TM-VDR1 are maintained at the ground potential.

[0303] At time t33 after the voltage value of the voltage signal VS1 as the driving voltage signal VDR1 output by the ejection control unit 20 is stabilized at the potential V1, the ejection control unit 20 generates a first instruction cmd1 corresponding to the voltage signal VS1 at the potential V1 as the diagnostic control signal HC synchronized with the clock signal SCK. Then, the ejection control unit 20 supplies the generated first instruction cmd1 to the print head 100 via the wiring WI-SI1 / HC and the terminal TM-SI1 / HC, and supplies the clock signal SCK to the print head 100 via the wiring WI-SCK and the terminal TM-SCK. The first instruction cmd1 and the clock signal SCK supplied to the print head 100 are input to the determination control circuit 451 included in the semiconductor device 450 of the abnormality detection circuit 250.

[0304] The determination control circuit 451 analyzes the input first instruction cmd1 based on the timing specified by the clock signal SCK. Then, at time t34 after the determination control circuit 451 recognizes that the first instruction cmd1 is a normal instruction, the determination control circuit 451 generates a storage circuit control signal RW for reading the determination information c1 corresponding to the first instruction cmd1 from the storage circuit 454, and outputs it to the storage circuit 454. Thus, the determination information c1 corresponding to the voltage signal VS1 of the potential V1 is read from the storage circuit 454. Then, the determination control circuit 451 generates a determination condition signal JC including the read determination information c1, and outputs it to the voltage determination circuit 452. In this embodiment, when no short circuit abnormality occurs in the wiring WI-VDR1 and the terminal TM-VDR1, a potential V1 higher than the threshold voltage Vt is supplied to the wiring WI-VDR1 and the terminal TM-VDR1. Therefore, the judgment information c1 includes the following judgment condition: when the voltage value of the voltage detection signal DET corresponding to the potential maintained by the wiring WI-VDR1 and the terminal TM-VDR1 exceeds the threshold voltage Vth corresponding to the threshold voltage Vt, the judgment condition that the voltage detection signal DET is normal.

[0305] In addition, at time t35 after the determination control circuit 451 recognizes that the first command cmd1 is a normal command, the determination control circuit 451 generates an H-level voltage switching signal SV and outputs it to the voltage input switching circuit 251. As a result, the drain and source of the transistor M10 included in the voltage input switching circuit 251 are controlled to be conductive, and accordingly, the source and drain of the transistor M11 are controlled to be conductive. As a result, the voltage input switching circuit 251 outputs the voltage detection signal DET maintained at the ground potential of the wiring WI-VDR1 and the terminal TM-VDR1 to the voltage determination circuit 452.

[0306] Here, the operation executed at time t34 and the operation executed at time t35 may be executed first or in parallel, similarly to the operation executed at time t4 and the operation executed at time t5 described above.

[0307] At time t36 after the determination condition signal JC including the determination information c1 and the voltage detection signal DET of the ground potential are input to the voltage determination circuit 452, the voltage determination circuit 452 compares the voltage detection signal DET with the determination information c1 included in the determination condition signal JC. Fig. 22 In an example of the operation of the abnormality detection circuit 250 shown in FIG. 1 , a ground potential lower than the threshold voltage Vt is maintained on the wiring WI-VDR1 and the terminal TM-VDR1. Therefore, a voltage detection signal DET having a ground potential lower than the threshold voltage Vth is input to the voltage determination circuit 452. As a result, the voltage determination circuit 452 determines that the potential maintained by the wiring WI-VDR1 and the terminal TM-VDR1 is abnormal, and does not generate an H-level determination result signal JR indicating that the potential maintained by the wiring WI-VDR1 and the terminal TM-VDR1 is normal. That is, the voltage determination circuit 452 maintains the logic level of the determination result signal JR at an L level. In addition, Fig. 22 In the figure, the determination result signal JR indicating that the potential held by the wiring WI-VDR1 and the terminal TM-VDR1 is abnormal is shown as a signal at an L level, but the present invention is not limited to this and may be a specific command.

[0308] Then, the determination control circuit 451 generates result information r1 indicating that the potential held by the wiring WI-VDR1 and the terminal TM-VDR1 is abnormal based on the input determination result signal JR. Then, the determination control circuit 451 outputs a storage circuit control signal RW for storing the generated result information r1 in the storage circuit 454 to the storage circuit 454. Thus, the result information r1 indicating that the potential held by the wiring WI-VDR1 and the terminal TM-VDR1 is abnormal is stored in the storage circuit 454.

[0309] At time t37 after the result information r1 is stored in the storage circuit 454, the ejection control unit 20 generates the second command cmd2 as the diagnosis control signal HC synchronized with the clock signal SCK. Then, the ejection control unit 20 supplies the generated second command cmd2 to the print head 100 via the wiring WI-SI1 / HC and the terminal TM-SI1 / HC, and supplies the clock signal SCK to the print head 100 via the wiring WI-SCK and the terminal TM-SCK. The second command cmd2 and the clock signal SCK supplied to the print head 100 are input to the determination control circuit 451 included in the semiconductor device 450 of the abnormality detection circuit 250.

[0310] The determination control circuit 451 analyzes the input second instruction cmd2 based on the timing specified by the clock signal SCK. Then, at time t38 after the determination control circuit 451 recognizes that the second instruction cmd2 is a normal instruction, the determination control circuit 451 generates an L-level voltage switching signal SV and outputs it to the voltage input switching circuit 251. As a result, the drain and source of the transistor M10 included in the voltage input switching circuit 251 are controlled to be non-conductive, and along with this, the source and drain of the transistor M11 are controlled to be non-conductive. As a result, the connection point of the resistor R12 and the resistor R13 included in the voltage input switching circuit 251 and the wiring WI-VDR1 and the terminal TM-VDR1 are electrically disconnected, and the voltage input switching circuit 251 outputs the voltage detection signal DET of the ground potential connected via the resistor R13 to the voltage determination circuit 452.

[0311] In addition, at time t38 after the determination control circuit 451 recognizes that the second command cmd2 is a normal command, the determination control circuit 451 generates a determination condition signal JC including stop information st for terminating the determination of whether the potential held on the wiring WI-VDR1 and the terminal TM-VDR1 is normal, which is executed based on the first command cmd1, and outputs it to the voltage determination circuit 452. The voltage determination circuit 452 terminates the determination processing by inputting the determination condition signal JC including the stop information st, and sets the logic level of the determination result signal JR to the L level.

[0312] At time t39 after the voltage determination circuit 452 stops outputting the determination result signal JR, the ejection control unit 20 generates a voltage signal VS2 of a constant DC voltage with a potential V2 lower than the threshold voltage Vt as a driving voltage signal VDR1. Then, the ejection control unit 20 transmits the generated voltage signal VS2 via the wiring WI-VDR1 and the terminal TM-VDR1. At this time, the wiring WI-VDR1 or the terminal TM-VDR1 is short-circuited with the wiring WI or the terminal TM for transmitting the ground potential. Therefore, the wiring WI-VDR1 and the terminal TM-VDR1 are maintained at the ground potential.

[0313] At time t40 after the voltage value of the voltage signal VS2 as the driving voltage signal VDR1 output by the ejection control unit 20 is stabilized at the potential V2, the ejection control unit 20 generates a third instruction cmd3 corresponding to the voltage signal VS2 at the potential V2 as the diagnostic control signal HC synchronized with the clock signal SCK. Then, the ejection control unit 20 supplies the generated third instruction cmd3 to the print head 100 via the wiring WI-SI1 / HC and the terminal TM-SI1 / HC, and supplies the clock signal SCK to the print head 100 via the wiring WI-SCK and the terminal TM-SCK. The third instruction cmd3 and the clock signal SCK supplied to the print head 100 are input to the determination control circuit 451 included in the semiconductor device 450 of the abnormality detection circuit 250.

[0314] The determination control circuit 451 analyzes the input third instruction cmd3 based on the timing specified by the clock signal SCK. Then, at time t41 after the determination control circuit 451 recognizes that the third instruction cmd3 is a normal instruction, the determination control circuit 451 generates a storage circuit control signal RW for reading the determination information c2 corresponding to the third instruction cmd3 from the storage circuit 454, and outputs it to the storage circuit 454. Thus, the determination information c2 corresponding to the voltage signal VS2 of the potential V2 is read from the storage circuit 454. Then, the determination control circuit 451 generates a determination condition signal JC including the read determination information c2, and outputs it to the voltage determination circuit 452. In this embodiment, when no short circuit abnormality occurs in the wiring WI-VDR1 and the terminal TM-VDR1, a potential V2 lower than the threshold voltage Vt is supplied to the wiring WI-VDR1 and the terminal TM-VDR1. Therefore, the judgment information c2 includes the following judgment conditions: a judgment condition for judging that the potential of the voltage detection signal DET is normal when the potential of the voltage detection signal DET corresponding to the potential maintained by the wiring WI-VDR1 and the terminal TM-VDR1 is lower than the threshold voltage Vth corresponding to the threshold voltage Vt.

[0315] In addition, at time t42 after the determination control circuit 451 recognizes that the third command cmd3 is a normal command, the determination control circuit 451 generates an H-level voltage switching signal SV and outputs it to the voltage input switching circuit 251. As a result, the drain and source of the transistor M10 included in the voltage input switching circuit 251 are controlled to be conductive, and accordingly, the source and drain of the transistor M11 are controlled to be conductive. As a result, the voltage input switching circuit 251 outputs the voltage detection signal DET of the ground potential maintained on the wiring WI-VDR1 and the terminal TM-VDR1 to the voltage determination circuit 452.

[0316] Here, the operation executed at time t41 and the operation executed at time t42 may be executed either one of them first or in parallel, similarly to the operations executed at time t11 and time t12 described above.

[0317] At time t43 after the determination condition signal JC including the determination information c2 and the voltage detection signal DET of the ground potential are input to the voltage determination circuit 452, the voltage determination circuit 452 compares the voltage detection signal DET with the determination information c2 included in the determination condition signal JC. Fig. 22 In the example of the operation of the abnormality detection circuit 250 shown in FIG. 1 , a ground potential lower than the threshold voltage Vt is held on the wiring WI-VDR1 and the terminal TM-VDR1. Therefore, a voltage detection signal DET lower than the threshold voltage Vth is input to the voltage determination circuit 452. As a result, the voltage determination circuit 452 determines that the potential held by the wiring WI-VDR1 and the terminal TM-VDR1 is normal, generates an H-level determination result signal JR indicating that the potential held by the wiring WI-VDR1 and the terminal TM-VDR1 is normal, and outputs the signal to the determination control circuit 451.

[0318] Then, the determination control circuit 451 generates result information r2 indicating that the potential held by the wiring WI-VDR1 and the terminal TM-VDR1 is normal based on the input determination result signal JR. Then, the determination control circuit 451 outputs a storage circuit control signal RW for storing the generated result information r2 in the storage circuit 454 to the storage circuit 454. Thus, the result information r2 indicating that the potential held by the wiring WI-VDR1 and the terminal TM-VDR1 is normal is stored in the storage circuit 454.

[0319] At time t44 after the result information r2 is stored in the storage circuit 454, the ejection control unit 20 generates a fourth command cmd4 as a diagnostic control signal HC synchronized with the clock signal SCK. Then, the ejection control unit 20 supplies the generated fourth command cmd4 to the print head 100 via the wiring WI-SI1 / HC and the terminal TM-SI1 / HC, and supplies the clock signal SCK to the print head 100 via the wiring WI-SCK and the terminal TM-SCK. The fourth command cmd4 and the clock signal SCK supplied to the print head 100 are input to the determination control circuit 451 included in the semiconductor device 450 of the abnormality detection circuit 250.

[0320] The determination control circuit 451 analyzes the input fourth instruction cmd4 based on the timing specified by the clock signal SCK. Then, at time t45 after the determination control circuit 451 recognizes that the fourth instruction cmd4 is a normal instruction, the determination control circuit 451 generates an L-level voltage switching signal SV and outputs it to the voltage input switching circuit 251. As a result, the drain and source of the transistor M10 included in the voltage input switching circuit 251 are controlled to be non-conductive, and along with this, the source and drain of the transistor M11 are controlled to be non-conductive. As a result, the connection point of the resistor R12 and the resistor R13 included in the voltage input switching circuit 251 and the wiring WI-VDR1 and the terminal TM-VDR1 are electrically disconnected, and the voltage input switching circuit 251 outputs the voltage detection signal DET of the ground potential connected via the resistor R13 to the voltage determination circuit 452.

[0321] In addition, at time t45 after the determination control circuit 451 recognizes that the fourth command cmd4 is a normal command, the determination control circuit 451 generates a determination condition signal JC including stop information st for terminating the determination of whether the potential held on the wiring WI-VDR1 and the terminal TM-VDR1 is normal, which is executed based on the third command cmd3, and outputs it to the voltage determination circuit 452. The voltage determination circuit 452 sets the logic level of the determination result signal JR to the L level by inputting the determination condition signal JC including the stop information st.

[0322] At time t46 after the voltage determination circuit 452 stops outputting the determination result signal JR, the ejection control unit 20 stops generating the voltage signal VS2 having a constant potential V2 as the drive voltage signal VDR1. Thus, the wiring WI-VDR1 and the terminal TM-VDR1 are kept at the ground potential.

[0323] Then, if Fig.23As shown, at time t47 after the ejection control unit 20 stops generating the drive voltage signal VDR1 , the determination control circuit 451 generates a storage circuit control signal RW for reading the result information r1 , r2 stored in the storage circuit 454 , and outputs it to the storage circuit 454 .

[0324] exist Fig. 22 , Fig.23 In the example of the operation of the abnormality detection circuit 250 shown in FIG. 1 , the storage circuit 454 stores the result information r1 indicating that the signal input to the print head 100 at time t36 is abnormal and the result information r2 indicating that the signal input to the print head 100 at time t43 is normal. That is, at least one of the result information r1 and r2 read from the storage circuit 454 by the determination control circuit 451 includes information indicating that the signal input to the print head 100 is abnormal. At time t48 after the determination control circuit 451 determines that at least one of the result information r1 and r2 read at time t47 is abnormal, it is determined that the signal input to the print head 100 is abnormal, and the output of the switch control signal OS of the L level is continued. As a result, the plurality of switching switches included in the switch group SW of the output switching circuit 453 continue to be non-conductive. Therefore, the wiring WI-SI1 / HC and the terminal TM-SI1 / HC continue to be non-conductive with the wiring P-SI1, the wiring WI-SCK and the terminal TM-SCK and the wiring P-SCK continue to be non-conductive, the wiring WI-LAT and the terminal TM-LAT and the wiring P-LAT continue to be non-conductive, and the wiring WI-CH and the terminal TM-CH and the wiring P-CH continue to be non-conductive.

[0325] At time t49 after the judgment control circuit 451 outputs the switch control signal OS of the L level, the ejection control unit 20 generates a driving voltage signal VDR1 whose voltage value is constant at the voltage Vc and supplies it to the wiring WI-VDR1 and the terminal TM-VDR1, and generates a driving voltage signal VDR2 whose voltage value is constant at the voltage Vc and supplies it to the wiring WI-VDR2 and the terminal TM-VDR2. At this time, the wiring WI-VDR1 or the terminal TM-VDR1 is short-circuited to the ground potential. Therefore, the ground potential is maintained on the wiring WI-VDR1 or the terminal TM-VDR1.

[0326] Then, at time t50 when the image data PD is input to the liquid ejection device 1, the ejection control unit 20 generates a drive signal COMA including trapezoidal waveforms Adp1 and Adp2 as a drive voltage signal VDR1, and supplies it to the wiring WI-VDR1 and the terminal TM-VDR1, and generates a drive signal COMB including trapezoidal waveforms Bdp1 and Bdp2 as a drive voltage signal VDR2, and supplies it to the wiring WI-VDR2 and the terminal TM-VDR2. At this time, since the wiring WI-VDR1 or the terminal TM-VDR1 is short-circuited to the ground potential, the drive signal COMA is not supplied to the drive signal selection circuit 200-1, and only the drive signal COMB is transmitted in the wiring WI-VDR2 and the terminal TM-VDR2, and is supplied to the drive signal selection circuit 200-1.

[0327] At time t51 after the supply of the drive signals COMA and COMB is started, the ejection control unit 20 generates a print data signal SI1, a clock signal SCK, a latch signal LAT, and a conversion signal CH for forming an image based on the image data PD on the medium P. Then, the ejection control unit 20 outputs the generated print data signal SI1, clock signal SCK, latch signal LAT, and conversion signal CH to the corresponding wiring WI-SI1 / HC and terminal TM-SI1 / HC, wiring WI-SCK and terminal TM-SCK, wiring WI-LAT and terminal TM-LAT, wiring WI-CH and terminal TM-CH.

[0328] In this case, the plurality of switching switches included in the switch group SW of the output switching circuit 453 are controlled to be non-conductive by the switch control signal OS. Therefore, the printing data signal SI1 transmitted by the wiring WI-SI1 / HC and the terminal TM-SI1 / HC is not supplied to the wiring P-SI1 and the drive signal selection circuit 200-1, the clock signal SCK transmitted by the wiring WI-SCK and the terminal TM-SCK is not supplied to the wiring P-SCK and the drive signal selection circuit 200-1, the latch signal LAT transmitted in the wiring WI-LAT and the terminal TM-LAT is not supplied to the wiring P-LAT and the drive signal selection circuit 200-1, and the conversion signal CH transmitted in the wiring WI-CH and the terminal TM-CH is not supplied to the wiring P-CH and the drive signal selection circuit 200-1. As a result, the drive signal selection circuit 200-1 does not generate the drive signal VOUT, and does not supply the drive signal VOUT to the piezoelectric element 60.

[0329] In addition, although Fig.19 , Figure 22-23Although the illustration is omitted, the clock signal SCK, latch signal LAT and conversion signal CH output by the abnormality detection circuit 250 are also not supplied to the drive signal selection circuits 200-2 to 200-6. The drive signal selection circuits 200-2 to 200-6 do not generate the drive signal VOUT and do not supply the drive signal VOUT to the piezoelectric element 60.

[0330] As a result, ink is not ejected from the nozzles 651 corresponding to the piezoelectric elements 60 included in the print head 100 to form an image on the medium P.

[0331] Here, the first instruction cmd1 as the diagnostic control signal HC is an instruction for executing the check of whether the voltage signal VS1 of the potential V1 is supplied to the wiring WI-VDR1 and the terminal TM-VDR1, and the second instruction cmd2 as the diagnostic control signal HC is an instruction for ending the check executed by the first instruction cmd1. That is, the check of whether the voltage signal VS1 of the potential V1 is supplied to the wiring WI-VDR1 and the terminal TM-VDR1 is executed by the first instruction cmd1 and the second instruction cmd2. The signal including the first instruction cmd1 and the second instruction cmd2 for executing the check of whether the voltage signal VS1 of the potential V1 is supplied to the wiring WI-VDR1 and the terminal TM-VDR1 is referred to as the first instruction signal HCf. That is, the first instruction signal HCf includes the first instruction cmd1 and the second instruction cmd2 immediately following the first instruction cmd1.

[0332] In addition, the third instruction cmd3 as the diagnostic control signal HC is an instruction for executing the check of whether the voltage signal VS2 of the potential V2 is supplied to the wiring WI-VDR1 and the terminal TM-VDR1, and the fourth instruction cmd4 as the diagnostic control signal HC is an instruction for ending the check executed by the third instruction cmd3. That is, the check of whether the voltage signal VS2 of the potential V2 is supplied to the wiring WI-VDR1 and the terminal TM-VDR1 is executed by the third instruction cmd3 and the fourth instruction cmd4. The signal including the third instruction cmd3 and the fourth instruction cmd4 for executing the check of whether the voltage signal VS2 of the potential V2 is supplied to the wiring WI-VDR1 and the terminal TM-VDR1 is referred to as the second instruction signal HCs. That is, the second instruction signal HCs includes the third instruction cmd3 and the fourth instruction cmd4 immediately following the third instruction cmd3.

[0333] Here, the first command signal HCf is a signal for executing a check whether the voltage signal VS1 of the potential V1 is supplied to the wiring WI-VDR1 and the terminal TM-VDR1, and the first command cmd1 is a command for starting a check whether the voltage signal VS1 of the potential V1 is supplied to the wiring WI-VDR1 and the terminal TM-VDR1. In contrast, the second command signal HCs is a signal for executing a check whether the voltage signal VS2 of the potential V2 is supplied to the wiring WI-VDR1 and the terminal TM-VDR1, and the third command cmd3 is a command for starting a check whether the voltage signal VS2 of the potential V2 is supplied to the wiring WI-VDR1 and the terminal TM-VDR1. Moreover, the determination control circuit 451 reads out the determination information c1 corresponding to the voltage signal VS1 of the potential V1 from the storage circuit 454 when the first command cmd1 is input, and reads out the determination information c2 corresponding to the voltage signal VS2 of the potential V2 from the storage circuit 454 when the third command cmd3 is input. That is, the first command cmd1 and the third command cmd3 are common in that they are commands for starting to check whether the potential supplied to the wiring WI-VDR1 and the terminal TM-VDR1 is normal, but the determination information c1 read by the determination control circuit 451 through the first command cmd1 is different from the determination information c2 read by the determination control circuit 451 through the third command cmd3. Therefore, the first command cmd1 and the third command cmd3 include different information.

[0334] By including different information in the first instruction cmd1 included in the first instruction signal HCf and the third instruction cmd3 included in the second instruction signal HCs, the abnormality detection circuit 250 is not limited to the potential supplied to the wiring WI-VDR1 and the terminal TM-VDR1, but can perform a check on whether the potential supplied to the wiring WI-VDR1 and the terminal TM-VDR1 is normal. That is, by including different information in the first instruction cmd1 and the third instruction cmd3, the abnormality detection circuit 250 can perform a check on whether the potential supplied to the wiring WI-VDR1 and the terminal TM-VDR1 is normal with respect to a wider range of potentials supplied to the wiring WI-VDR1 and the terminal TM-VDR1. As a result, the versatility of the print head 100 including the abnormality detection circuit 250 and the versatility of the print head driving circuit 2 that outputs the diagnostic control signal HC1 and controls the print head 100 can be improved.

[0335] On the other hand, the second instruction cmd2 included in the first instruction signal HCf is an instruction for stopping the check of whether the wiring WI-VDR1 and the terminal TM-VDR1 are supplied, and the fourth instruction cmd4 included in the second instruction signal HCs is an instruction for stopping the check of whether the wiring WI-VDR1 and the terminal TM-VDR1 are supplied. That is, the second instruction cmd2 and the fourth instruction cmd4 are both instructions for ending the check of whether the wiring WI-VDR1 and the terminal TM-VDR1 are supplied. Such a second instruction cmd2 and the fourth instruction cmd4 preferably include the same information, whereby the print head 100 and the print head driving circuit 2 can store the information corresponding to the second instruction cmd2 and the fourth instruction cmd4 together. As a result, the possibility of an increase in the number of instructions that the print head 100 and the print head driving circuit 2 should manage can be reduced, and the use efficiency of the storage area possessed by the print head 100 and the print head driving circuit 2 can be improved.

[0336] In addition, if Figure 20 to Figure 23 As shown, in this embodiment, the potential V1 of the voltage signal VS1 output by the ejection control unit 20 is different from the potential V2 of the voltage signal VS2, and the potential V1 of the voltage signal VS1 is greater than the potential V2 of the voltage signal VS2.

[0337] Specifically, the potential V1 of the voltage signal VS1 is a potential higher than the high-level potential of the image data PD supplied from the external device 3 such as the host computer provided outside the liquid ejection device 1, a potential 5 times higher than the high-level potential of the first command signal HCf output as the diagnosis control signal HC1, or a potential higher than 18.2 V. Such a potential V1 of the voltage signal VS1 is preferably the second highest potential after the voltage VHV in the signal transmitted by the cable FC, and is greater than 10% of the effective value of the AC voltage AC supplied from the outside. For example, the potential V1 of the voltage signal VS1 is greater than 70% of the voltage value of the voltage VHV, that is, greater than 29.4 V.

[0338] The voltage signal VS1 as the driving voltage signal VDR1 is supplied to the abnormality detection circuit 250 together with the diagnosis control signal HC1. In addition, the voltage signal VS1 as the driving voltage signal VDR1 is a DC voltage, while the first command signal HCf output as the diagnosis control signal HC1 is a digital signal that transmits information at a high frequency. Therefore, when the potential V1 of the voltage signal VS1 as the driving voltage signal VDR1 is a high-level potential of the diagnosis control signal HC1 and is a potential near 3.3V specified by the voltage VDD, the diagnosis control signal HC1 is superimposed on the voltage signal VS1, and as a result, the accuracy of the voltage detection signal DET based on the potential V1 of the voltage signal VS1 input to the abnormality detection circuit 250 is reduced. That is, by setting the potential V1 of the voltage signal VS1, which is higher than the potential V2 of the voltage signal VS2, to a potential higher than the high level potential of the image data PD supplied from the outside of the liquid ejection device 1, and during the period when the voltage signal VS1 outputs the potential V1 as the driving voltage signal VDR1, to a potential that is 5 times or 18.2 V higher than the potential in the case of the high level of the first instruction signal HCf output as the diagnostic control signal HC1, the possibility of a decrease in the accuracy of the voltage detection signal DET is reduced even when a low-potential digital signal such as the diagnostic control signal HC1 is superimposed on the potential V1 of the voltage signal VS1. As a result, the inspection accuracy of the potential of the wiring WI-VDR1 and the terminal TM-VDR1 in the abnormality detection circuit 250 can be improved.

[0339] On the other hand, the potential V2 of the voltage signal VS2 is a potential five times lower than the potential of the second command signal HCs output as the diagnosis control signal HC1 when the level is high, or a potential lower than 18.2 V. Such a potential V2 of the voltage signal VS2 is 30% or less of the voltage VHV, for example, 12.6 V or less, and is more preferably a ground potential.

[0340] Thus, the potential difference between the potential V1 of the voltage signal VS1 which is the driving voltage signal VDR1 input to the abnormality detection circuit 250 and the potential V2 of the voltage signal VS2 can be increased. As a result, the inspection accuracy of the potential of the wiring WI-VDR1 and the terminal TM-VDR1 in the abnormality detection circuit 250 can be further improved.

[0341] In addition, by setting the potential V2 of the voltage signal VS2, which is lower than the potential V1 of the voltage signal VS1, to a potential different from the range of potentials judged to be normal for the potential V1, the possibility of the abnormality detection circuit 250 mistakenly detecting an abnormality in the wiring WI-VDR1 or the terminal TM-VDR1 can be reduced when a short circuit abnormality occurs in the wiring WI-VDR1 or the terminal TM-VDR1 for transmitting the driving voltage signal VDR1.

[0342] Here, in Figure 20 to Figure 23 , the potential V1 of the voltage signal VS1 output by the ejection control unit 20 and the potential V2 of the voltage signal VS2 are different potentials, and the potential V1 of the voltage signal VS1 is greater than the potential V2 of the voltage signal VS2, but the potential V2 of the voltage signal VS2 may be greater than the potential V1 of the voltage signal VS1. In this case, the potential V2 of the voltage signal VS2 may be a potential higher than the high-level potential of the image data PD supplied from the external device 3 such as the host computer provided outside the liquid ejection device 1, or may be a potential 5 times higher than the high-level potential of the second command signal HCs output as the diagnosis control signal HC1, or a potential higher than 18.2V. In addition, the potential V2 of the voltage signal VS2 is preferably the second highest potential after the voltage VHV in the signal transmitted by the cable FC, and is greater than 10% of the effective value of the AC voltage AC supplied from the outside. For example, the potential V2 of the voltage signal VS2 is greater than 70% of the voltage value of the voltage VHV, and is greater than 29.4V.

[0343] On the other hand, the potential V1 of the voltage signal VS1 is a potential five times lower than the potential of the high level of the first command signal HCf output as the diagnosis control signal HC1, or a potential lower than 18.2 V. Such a potential V1 of the voltage signal VS1 is 30% or less of the voltage VHV, for example, 12.6 V or less, and is preferably a ground potential. Even in this case, the same effect is achieved.

[0344] As described above, in the liquid ejection device 1 of the present embodiment, the print head 100 performs abnormality detection based on the first command signal HCf and the second command signal HCs, the first command signal HCf includes the first command cmd1 and the second command cmd2 input to the terminal TM-SI1 / HC when the potential of the terminal TM-VDR1 is the potential V1, the second command signal HCs includes the third command cmd3 and the fourth command cmd4 input to the terminal TM-SI1 / HC when the potential of the terminal TM-VDR1 is the potential V2, and the print head driving circuit 2 has: an ejection control unit 20 that outputs the first command signal HCf and the second command signal HCs; a wiring WI-VDR1 electrically connected to the terminal TM-VDR1; and a wiring WI-SI1 / HC electrically connected to the terminal TM-SI1 / HC. Moreover, the ejection control unit 20 outputs a first command signal HCf to the wiring WI-SI1 / HC while supplying a voltage signal VS1 of a potential V1 to the wiring WI-VDR1. After outputting the first command signal HCf, the ejection control unit 20 outputs a second command signal HCs to the wiring WI-SI1 / HC while supplying a voltage signal VS2 of a potential V2 different from the potential V1 to the wiring WI-VDR1. Based on the first command signal HCf, the second command signal HCs, the voltage signal VS1, and the voltage signal VS2, the print head 100 performs abnormality detection.

[0345] Thus, in the liquid ejection device 1 of the present embodiment, the driving voltage signal VDR1 based on the high voltage VHV includes a voltage signal VS1 of a potential V1 and a voltage signal VS2 of a potential V2 different from the potential V1, and in both the voltage signal VS1 and the voltage signal VS2, whether the potential of the wiring WI-VDR1 is normal is detected. Thus, it is possible to detect the presence or absence of an abnormality in the transmission path for transmitting the driving voltage signal VDR1 including the voltage signals VS1 and VS2 of different potentials. That is, in the liquid ejection device 1 of the present embodiment, it is possible to accurately determine whether the high voltage driving voltage signal VDR1 has an abnormality.

[0346] In addition, in the liquid ejection device 1 of the present embodiment, since an abnormality occurs in at least any one of the wiring WI-SI1 / HC, the wiring WI-SCK, the terminal TM-SI1 / HC and the terminal TM-SCK, it is also possible to detect a situation in which at least one of the first command signal HCf and the second command signal HCs is not input into the print head 100 as a normal command.

[0347] As described above, in the liquid ejection device 1 of the present embodiment, the determination control circuit 451 of the abnormality detection circuit 250 controls the operation of the voltage input switching circuit 251, the voltage determination circuit 452, and the storage circuit 454 according to the first command signal HCf or the second command signal HCs input synchronously with the clock signal SCK, thereby determining whether the voltage values ​​of the voltage signals VS1 and VS2 included in the driving voltage signal VDR1 held on the wiring WI-VDR1 or the terminal TM-VDR1 are normal. Therefore, when an abnormality such as a short circuit abnormality or a poor connection occurs in any one of the wiring WI-SI1 / HC, the terminal TM-SI1 / HC, the wiring WI-SCK, and the terminal TM-SCK, and at least one of the clock signal SCK, the first command signal HCf, and the second command signal HCs input to the print head 100 is abnormal, the determination control circuit 451 does not determine whether the voltage values ​​of the voltage signals VS1 and VS2 included in the driving voltage signal VDR1 held on the wiring WI-VDR1 or the terminal TM-VDR1 are normal. After the control circuit 451 executes the POR of the semiconductor device 450, when the first command signal HCf and the second command signal HCs for determining whether the voltage values ​​of the voltage signals VS1 and VS2 included in the driving voltage signal VDR1 are normal are not input within a specified period, an abnormality such as a short circuit or a poor connection occurs in any of the wiring WI-SI1 / HC, the terminal TM-SI1 / HC, the wiring WI-SCK, and the terminal TM-SCK. As a result, it is determined that an abnormality has occurred in at least one of the clock signal SCK input to the print head 100, the first command signal HCf, and the second command signal HCs.

[0348] That is, in the liquid ejection device 1 of the present embodiment, by determining whether the first instruction signal HCf and the second instruction signal HCs for determining whether the voltage values ​​of the voltage signals VS1 and VS2 included in the driving voltage signal VDR1 are normal, it is possible to determine whether an abnormality has occurred in at least one of the low-voltage clock signal SCK, the first instruction signal HCf, and the second instruction signal HCs.

[0349] As described above, in the liquid ejection device 1 of the present embodiment, the print head 100 performs abnormality detection based on the first command signal HCf and the second command signal HCs, wherein the first command signal HCf includes the first command cmd1 and the second command cmd2 input to the terminal TM-SI1 / HC in a state where the potential of the terminal TM-VDR1 is the potential V1, and the second command signal HCs includes the third command cmd3 and the fourth command cmd4 input to the terminal TM-SI1 / HC in a state where the potential of the terminal TM-VDR1 is the potential V2. With respect to the print head 100, the ejection control unit 20 of the print head drive circuit 2 is connected to the wiring WI-VDR1. When the voltage signal VS1 of the potential V1 is supplied, the first command signal HCf is output to the wiring WI-SI1 / HC. After the first command signal HCf is output, and when the voltage signal VS2 of the potential V2 different from the potential V1 is supplied to the wiring WI-VDR1, the second command signal HCs is output to the wiring WI-SI1 / HC. Based on the first command signal HCf, the second command signal HCs, the voltage signal VS1, and the voltage signal VS2, the print head 100 is detected for abnormalities, so that it can be determined whether the high voltage signal and the low voltage signal supplied to the print head 100 are normal. As a result, the possibility of malfunctioning of the print head 100 can be reduced.

[0350] Here, the control circuit 451 is used to determine whether an abnormality occurs in at least any one of the low-voltage clock signal SCK, the first command signal HCf, and the second command signal HCs during a specified period, which is not limited to the period after the execution of the POR of the semiconductor device 450. For example, it may also be the period from the input of the first command cmd1 to the input of the second command cmd2, the period from the input of the second command cmd2 to the input of the third command cmd3, and the period from the input of the third command cmd3 to the input of the fourth command cmd4.

[0351] 1.6.3 Print head inspection method

[0352] As described above, the liquid ejection device 1 of the present embodiment having a print head 100 including an abnormality detection circuit 250 comprises: a print head 100 which supplies a drive signal COMA which is a drive voltage signal VDR1 input to a terminal TM-VDR1 to a piezoelectric element 60 which is a drive element, based on a print data signal SI1 input to a terminal TM-SI1 / HC, thereby performing printing; and a print head drive circuit 2 which enables the print head 100 to perform printing.

[0353] The print head driving circuit 2 comprises: an ejection control unit 20 that outputs a first command signal HCf and a second command signal HCs; a wiring WI-VDR1 electrically connected to the terminal TM-VDR1; and a wiring WI-SI1 / HC electrically connected to the terminal TM-SI1 / HC. The ejection control unit 20 outputs the first command signal HCf to the wiring WI-SI1 / HC while supplying a voltage signal VS1 having a potential V1 to the wiring WI-VDR1. After outputting the first command signal HCf, the ejection control unit 20 outputs the second command signal HCs to the wiring WI-SI1 / HC while supplying a voltage signal VS2 having a potential V2 different from the potential V1 to the wiring WI-VDR1.

[0354] In addition, the print head 100 processes the output of the circuit including the voltage input switching circuit 251 and the voltage determination circuit 452 electrically connected to the terminal TM-VDR1 according to the first command signal HCf input to the terminal TM-SI1 / HC when the potential of the terminal TM-VDR1 is at the potential V1, and processes the output of the circuit including the voltage input switching circuit 251 and the voltage determination circuit 452 electrically connected to the terminal TM-VDR1 according to the second command signal HCs input to the terminal TM-SI1 / HC when the potential of the terminal TM-VDR1 is at the potential V2.

[0355] Specifically, the print head 100 includes a terminal TM-SI1 / HC, a terminal TM-VDR1, a voltage input switching circuit 251, a voltage determination circuit 452, and an output switching circuit 453. The voltage input switching circuit 251 and the voltage determination circuit 452 determine whether the potential of the terminal TM-VDR1 is normal based on the first command signal HCf input to the terminal TM-SI1 / HC, and determine whether the potential of the terminal TM-VDR1 is normal based on the second command signal HCs input to the terminal TM-SI1 / HC. In this case, the voltage input switching circuit 251 and the voltage determination circuit 452 determine whether the potential of the terminal TM-VDR1 is normal based on the first command signal HCf input to the terminal TM-SI1 / HC according to the determination criteria specified by the determination information c1, and determine whether the potential of the terminal TM-VDR1 is normal based on the second command signal HCs input to the terminal TM-SI1 / HC according to the determination criteria specified by the determination information c2 different from the determination information c1. That is, the voltage input switching circuit 251 and the voltage judgment circuit 452 judge whether the potential of the terminal TM-VDR1 is normal based on the first command signal HCf input to the terminal TM-SI1 / HC, and judge whether the potential of the terminal TM-VDR1 is normal based on the second command signal HCs input to the terminal TM-SI1 / HC, using different judgment criteria.

[0356] Moreover, the output switching circuit 453 allows printing when it is judged that the potential of terminal TM-VDR1 is normal in both of the judgments of whether the potential of terminal TM-VDR1 is normal based on the first command signal HCf input to terminal TM-SI1 / HC and the judgment of whether the potential of terminal TM-VDR1 is normal based on the second command signal HCs input to terminal TM-SI1 / HC, and does not allow printing when it is judged that the potential of terminal TM-VDR1 is abnormal in at least one of the judgments of whether the potential of terminal TM-VDR1 is normal based on the first command signal HCf input to terminal TM-SI1 / HC and the judgment of whether the potential of terminal TM-VDR1 is normal based on the second command signal HCs input to terminal TM-SI1 / HC.

[0357] In the liquid ejection device 1 of the present embodiment configured as described above, it is possible to check whether the signal supplied to the print head 100 is normal using the high voltage drive voltage signal VDR1 and the low voltage diagnostic control signal HC1 outputted by the ejection control unit 20 to the print head 100. Thus, it is possible to accurately determine whether the high voltage signal and the low voltage signal supplied to the print head 100 are normal, and as a result, the possibility of malfunction in the print head 100 due to the supply of an abnormal signal to the print head 100 can be reduced, and the print head drive circuit 2 can control the print head 100 according to whether an abnormality occurs in the print head 100.

[0358] The details of such a method of inspecting the print head 100 will be described. Fig.24 1 is a diagram showing a method for inspecting the print head 100 in the liquid ejection device 1. Fig.24 As shown, the inspection method of the print head 100 in the liquid ejecting device 1 includes a determination step (step S100 ) and a permission step (step S300 ) immediately following the determination step (step S100 ).

[0359] Fig.25 FIG. 1 is a diagram showing an example of a determination process. Fig.25 As shown, in the judgment process (step S100), the ejection control unit 20 generates a voltage signal VS1 of a DC voltage with a constant potential V1 as a driving voltage signal VDR1. Then, the ejection control unit 20 supplies the voltage signal VS1 with a constant potential V1 to the wiring WI-VDR1 and the terminal TM-VDR1 (step S110). In addition, the ejection control unit 20 generates a first command signal HCf as a diagnostic control signal HC. Then, the ejection control unit 20 outputs the first command signal HCf to the wiring WI-SI1 / HC and the terminal TM-SI1 / HC (step S120).

[0360] The first command signal HCf outputted by the ejection control unit 20 is inputted to the determination control circuit 451 included in the abnormality detection circuit 250 via the wiring WI-SI1 / HC and the terminal TM-SI1 / HC. The determination control circuit 451 reads the determination information c1 stored in the storage circuit 454 based on the first command signal HCf. That is, the determination control circuit 451 reads the determination information c1 from the storage circuit 454 (step S130). In addition, in step S130, when the first command signal HCf is not inputted to the determination control circuit 451 during a predetermined period, the determination control circuit 451 determines that an abnormality has occurred in the first command signal HCf. Then, the determination control circuit 451 generates a determination result signal ES indicating that an abnormality has occurred in the print head 100, and outputs it to the ejection control unit 20. At this time, the determination control circuit 451 may also end the inspection of the print head 100.

[0361] Then, the determination control circuit 451 controls the voltage input switching circuit 251 to generate the voltage detection signal DET corresponding to the potential held on the wiring WI-VDR1 and the terminal TM-VDR1 based on the first command signal HCf, and the voltage determination circuit 452 determines whether the potential of the voltage detection signal DET is normal based on the voltage detection signal DET and the determination information c1. That is, the determination control circuit 451 determines whether the potential of the terminal TM-VDR1 is normal based on the first command signal HCf input to the terminal TM-SI1 / HC (step S140).

[0362] Then, the determination control circuit 451 stores the result information r1 including the result of the determination whether the potential of the terminal TM-VDR1 is normal or not according to the first command signal HCf input to the terminal TM-SI1 / HC in the storage circuit 454. That is, the determination control circuit 451 stores the result information r1 in the storage circuit 454 (step S150).

[0363] Then, the ejection control unit 20 generates a voltage signal VS2 of a DC voltage constant at a potential V2 different from the potential V1 as a driving voltage signal VDR1. Then, the ejection control unit 20 supplies the voltage signal VS2 constant at the potential V2 to the wiring WI-VDR1 and the terminal TM-VDR1 (step S210). In addition, the ejection control unit 20 generates a second command signal HCs as a diagnostic control signal HC. Then, the ejection control unit 20 outputs the second command signal HCs to the wiring WI-SI1 / HC and the terminal TM-SI1 / HC (step S220).

[0364] The second command signal HCs output by the ejection control unit 20 is input to the determination control circuit 451 of the abnormality detection circuit 250 via the wiring WI-SI1 / HC and the terminal TM-SI1 / HC. The determination control circuit 451 reads the determination information c2 stored in the storage circuit 454 based on the second command signal HCs. That is, the determination control circuit 451 reads the determination information c2 from the storage circuit 454 (step S230). In addition, in step S230, when the second command signal HCs is not input to the determination control circuit 451 during a predetermined period, the determination control circuit 451 determines that an abnormality has occurred in the second command signal HCs. Then, the determination control circuit 451 generates a determination result signal ES indicating that an abnormality has occurred in the print head 100, and outputs it to the ejection control unit 20. At this time, the determination control circuit 451 may also end the inspection of the print head 100.

[0365] Then, the determination control circuit 451 controls the voltage input switching circuit 251 to generate the voltage detection signal DET corresponding to the potential held on the wiring WI-VDR1 and the terminal TM-VDR1 based on the second command signal HCs, and the voltage determination circuit 452 determines whether the potential of the voltage detection signal DET is normal based on the voltage detection signal DET and the determination information c2. That is, the determination control circuit 451 determines whether the potential of the terminal TM-VDR1 is normal based on the second command signal HCs input to the terminal TM-SI1 / HC (step S240).

[0366] Then, the determination control circuit 451 stores the result information r2 including the determination result of whether the potential of the terminal TM-VDR1 is normal or not according to the second command signal HCs input to the terminal TM-SI1 / HC in the storage circuit 454. That is, the determination control circuit 451 stores the result information r2 in the storage circuit 454 (step S250), and ends the determination process (step S100).

[0367] As described above, in the judgment process (step S100), the judgment of step S140 including judging whether the potential of terminal TM-VDR1 is normal based on the first command signal HCf input to terminal TM-SI1 / HC and the judgment of step S240 including judging whether the potential of terminal TM-VDR1 is normal based on the second command signal HCs input to terminal TM-SI1 / HC are performed by different judgment criteria respectively specified by judgment information c1 and judgment information c2.

[0368] Next, an example of the permission process (step S300) will be described. Fig.26 is a diagram showing an example of an allowed process. Fig.26As shown, in the enabling process (step S300), the determination control circuit 451 reads the result information r1 and the result information r2 from the storage circuit 454 (step S310). Then, the determination control circuit 451 determines whether both the read result information r1 and the result information r2 are information indicating that the potential of the terminal TM-VDR1 is normal (step S320).

[0369] When the determination control circuit 451 determines that both the result information r1 and the result information r2 are information indicating that the potential of the terminal TM-VDR1 is normal (Y in step S320), the determination control circuit 451 outputs a switch control signal OS to control the switch group SW to be turned on to the output switching circuit 453 (step S330). As a result, the switching switches included in the switch group SW of the output switching circuit 453 are controlled to be turned on, and as a result, the clock signal SCK, the latch signal LAT, and the conversion signal CH are input to the drive signal selection circuit 200. Then, the drive signal selection circuit 200 supplies the drive signal VOUT to the piezoelectric element 60 by inputting the clock signal SCK, the latch signal LAT, and the conversion signal CH. That is, printing on the medium P is allowed.

[0370] On the other hand, when the determination control circuit 451 determines that at least one of the result information r1 and the result information r2 is not information indicating that the potential of the terminal TM-VDR1 is normal (N in step S320), the determination control circuit 451 outputs a switch control signal OS to control the switch group SW to be non-conductive to the output switching circuit 453 (step S340). As a result, the switching switches included in the switch group SW of the output switching circuit 453 are controlled to be non-conductive, and as a result, the clock signal SCK, the latch signal LAT, and the conversion signal CH are not input to the drive signal selection circuit 200. Therefore, the drive signal selection circuit 200 does not supply the drive signal VOUT to the piezoelectric element 60. That is, printing on the medium P is not allowed.

[0371] As described above, in the enabling process (step S300), in the determination of step S140 and the determination of step S240, printing is enabled when the potential of the terminal TM-VDR1 is determined to be normal, and printing is not enabled when the potential of the terminal TM-VDR1 is determined to be abnormal in the determination of step S140 or the determination of step S240. Specifically, in the enabling process (step S300), by controlling the switching switch included in the switch group SW of the output switching circuit 453, the supply of the clock signal SCK, the latch signal LAT, and the conversion signal CH to the drive signal selection circuit 200 is controlled, and the supply of the drive signal VOUT based on the drive signals COMA and COMB to the piezoelectric element 60 is controlled. That is, in the enabling process (step S300), whether printing is enabled or not is switched according to whether the drive signal VOUT based on the drive signals COMA and COMB is supplied to the piezoelectric element 60.

[0372] Here, when the determination control circuit 451 determines that the potential of the terminal TM-VDR1 is normal based on the first command signal HCf input to the terminal TM-SI1 / HC, the potential V1 is held at the terminal TM-VDR1, and when the determination control circuit 451 determines that the potential of the terminal TM-VDR1 is normal based on the second command signal HCs input to the terminal TM-SI1 / HC, the potential V2 is held at the terminal TM-VDR1. In this case, the potential V1 held at the terminal TM-VDR1 and the potential V2 held at the terminal TM-VDR1 are different potentials.

[0373] For example, when the determination control circuit 451 determines that the potential of the terminal TM-VDR1 is normal based on the first instruction signal HCf input to the terminal TM-SI1 / HC, the potential V1 of the terminal TM-VDR1 may be higher than the potential V2 of the terminal TM-VDR1 when it is determined that the potential of the terminal TM-VDR1 is normal based on the second instruction signal HCs input to the terminal TM-SI1 / HC; or, when the determination control circuit 451 determines that the potential of the terminal TM-VDR1 is normal based on the second instruction signal HCs input to the terminal TM-SI1 / HC, the potential V2 of the terminal TM-VDR1 may be higher than the potential of the terminal TM-VDR1 when it is determined that the potential of the terminal TM-VDR1 is normal based on the first instruction signal HCf input to the terminal TM-SI1 / HC.

[0374] Here, in Figure 24 to Figure 26In the inspection method of the print head 100 shown in the figure, the judgment process (step S100) and the permission process (step S300) are described by exemplifying the case where the abnormality detection circuit 250 of the print head 100 is executed, but at least a part of the judgment process (step S100) and the permission process (step S300) may be executed by the print head driving circuit 2. That is, a part of the structure of the abnormality detection circuit 250 may be provided in the print head driving circuit 2. Even in this case, the same effect can be achieved.

[0375] Here, the terminal TM-VDR1 is an example of a first terminal, and the terminal TM-SI1 / HC is an example of a second terminal. In addition, the wiring WI-VDR1 included in the cable FC is an example of a first wiring, the wiring WI-SI1 / HC is an example of a second wiring, at least one of the wiring WI-VHV and the wiring WI-VDD is an example of a third wiring, the wiring WI-SCK is an example of a fourth wiring, and the wiring WI-ES is an example of a fifth wiring. In addition, the potential V1 is an example of a first potential, the potential V2 is an example of a second potential, the voltage signal VS1 of the potential V1 is an example of a first voltage signal, the voltage signal VS2 of the potential V2 is an example of a second voltage signal, the first command signal HCf is an example of a first signal, the second command signal HCs is an example of a second signal, the printing data signal SI1 is an example of printing data, and the determination result signal ES1 is an example of an abnormality determination signal. Moreover, the print head driving circuit 2 is an example of a print head control circuit, the structure including the main control unit 10 and the ejection control unit 20 included in the print head driving circuit 2 is an example of a signal circuit, the main control circuit 11 included in the main control unit 10 and receiving the image data PD as an example of an image signal input from the external device 3 as an example of a host computer is an example of a receiving circuit, and the semiconductor device 450 including the voltage judgment circuit 452 constituting at least a part of the abnormality detection circuit is an example of a semiconductor integrated circuit.

[0376] 1.7 Effects

[0377] The print head 100 of the liquid ejection device 1 configured as described above includes: a voltage input switching circuit 251 that determines whether the potential of the terminal TM-VDR1 is normal based on the first command signal HCf input to the terminal TM-SI1 / HC and the clock signal SCK input to the terminal TM-SCK, and determines whether the potential of the terminal TM-VDR1 is normal based on the second command signal HCs input to the terminal TM-SI1 / HC and the clock signal SCK input to the terminal TM-SCK; and a voltage determination circuit 452. Thus, if at least one of the low-voltage first command signal HCf, the second command signal HCs, and the clock signal SCK input to the terminal TM-SCK input to the terminal TM-SI1 / HC is abnormal, it is impossible to determine whether the signal input to the print head 100 is normal, and based on the fact that the determination cannot be performed, it can be determined that the signal input to the print head 100 is abnormal. Furthermore, whether the potential of terminal TM-VDR1 is normal is determined based on the first command signal HCf input to terminal TM-SI1 / HC and the clock signal SCK input to terminal TM-SCK, and whether the potential of terminal TM-VDR1 is normal is determined based on the second command signal HCs input to terminal TM-SI1 / HC and the clock signal SCK input to terminal TM-SCK. It is possible to determine whether the high voltage signal supplied to the terminal TM-VDR1 is normal.

[0378] That is, in the print head 100 of the present embodiment, it is possible to determine whether both the diagnostic control signal HC including the low voltage first command signal HCf and the second command signal HCs and the high voltage drive voltage signal VDR1 are abnormal. Thus, it is possible to determine whether the high voltage signal and the low voltage signal supplied to the print head 100 are normal, and the possibility of malfunction in the print head 100 can be reduced.

[0379] Furthermore, after judging whether the potential of terminal TM-VDR1 is normal based on the first command signal HCf input to terminal TM-SI1 / HC and the clock signal SCK input to terminal TM-SCK, and judging whether the potential of terminal TM-VDR1 is normal based on the second command signal HCs input to terminal TM-SI1 / HC and the clock signal SCK input to terminal TM-SCK, in both the judgment of whether the potential of terminal TM-VDR1 is normal based on the first command signal HCf and the judgment of whether the potential of terminal TM-VDR1 is normal based on the second command signal HCs, by allowing printing when the potential of terminal TM-VDR1 is normal, the accuracy of judging whether the high voltage signal and the low voltage signal supplied to the print head 100 are normal can be improved, and the possibility of malfunctioning of the print head 100 can be further reduced.

[0380] In addition, in the liquid ejection device 1 of the present embodiment, the print head 100 processes the output from the voltage input switching circuit 251 and the voltage determination circuit 452 electrically connected to the terminal TM-VDR1 according to the first command signal HCf input to the terminal TM-SI1 / HC in the state where the potential of the terminal TM-VDR1 is the potential V1 and the clock signal SCK input to the terminal TM-SCK, and processes the output from the voltage input switching circuit 251 and the voltage determination circuit 452 electrically connected to the terminal TM-VDR1 according to the second command signal HCs input to the terminal TM-SI1 / HC in the state where the potential of the terminal TM-VDR1 is the potential V2 and the clock signal SCK input to the terminal TM-SCK. The outputs of the switching circuit 251 and the voltage determination circuit 452 are processed so that the print head driving circuit 2 for causing the print head 100 to execute printing outputs a first command signal HCf to the wiring WI-SI1 / HC electrically connected to the terminal TM-SI1 / HC while the ejection control unit 20 supplies a voltage signal VS1 of a potential V1 to the wiring WI-VDR1 electrically connected to the terminal TM-VDR1. After outputting the first command signal HCf, the print head driving circuit 2 outputs a second command signal HCs to the wiring WI-SI1 / HC while supplying a voltage signal VS2 of a potential V2 different from the potential V1 to the wiring WI-VDR1. Therefore, the print head 100 performs printing only when the potentials V1 and V2 input to the terminal TM-VDR1 and the first command signal HCf and the second command signal HCs input to the terminal TM-SI1 / HC are input at a predetermined timing and in a predetermined state, and does not perform printing when at least any one of the potentials V1 and V2 input to the terminal TM-VDR1, the first command signal HCf and the second command signal HCs input to the terminal TM-SI1 / HC and the clock signal SCK input to the terminal TM-SCK is input at a different timing or in a different state.

[0381] That is, the print head driving circuit 2 outputs the first command signal HCf to the wiring WI-SI1 / HC electrically connected to the terminal TM-SI1 / HC and the clock signal SCK to the wiring WI-SCK electrically connected to the terminal TM-SCK, while supplying the voltage signal VS1 of the potential V1 to the wiring WI-VDR1 electrically connected to the terminal TM-VDR1, and after outputting the first command signal HCf, the second command signal HCs is output to the wiring WI-SI1 / HC and the clock signal SCK is output to the wiring WI-SCK electrically connected to the terminal TM-SCK, while supplying the voltage signal VS2 of the potential V2 different from the potential V1 to the wiring WI-VDR1, so that the print head 100 itself diagnoses whether the input signal is normal. Thus, the print head driving circuit 2 can control the print head 100 based on whether the high voltage signal and the low voltage signal supplied to the print head 100 are normal, and as a result, the possibility of malfunction in the print head 100 can be reduced.

[0382] In addition, in the liquid ejection device 1 of the present embodiment, the print head 100 and the print head driving circuit 2 determine whether the signal input to the print head 100 is normal based on the potentials V1 and V2 which are two different potentials and the first command signal HCf and the second command signal HCs corresponding to the potentials V1 and V2, respectively, thereby improving the accuracy of determining whether the high voltage signal and the low voltage signal supplied to the print head 100 are normal, and further reducing the possibility of malfunctioning of the print head 100.

[0383] 1.8 Variations

[0384] In the liquid ejection device 1 of the present embodiment described above, the case where the diagnostic control signal HC is transmitted via the wiring WI-SI1 / HC common to the printing data signal SI1 and supplied to the common terminal TM-SI1 / HC is illustrated, but the diagnostic control signal HC and the printing data signal SI1 may be transmitted via different wirings WI, and may also be input from different terminals TM.

[0385] In addition, in the liquid ejection device 1 of the present embodiment described above, an example is given of a situation in which the voltage signals VS1, VS2 and the drive signal COMA are transmitted as a drive voltage signal VDR1 via a common wiring WI-VDR1 and supplied to a common terminal TM-VDR1, but the voltage signals VS1, VS2 and the drive signal COMA may be transmitted via different wirings WI, respectively, and may also be input from different terminals TM.

[0386] In addition, in the liquid ejection device 1 of the present embodiment described above, the case where the potential V1 of the voltage signal VS1 included in the driving voltage signal VDR1 is greater than the potential V2 of the voltage signal VS2 is illustrated, but the potential V2 of the voltage signal VS2 included in the driving voltage signal VDR1 may also be greater than the potential V1 of the voltage signal VS1.

[0387] Even the liquid ejection device 1 according to the above-described modified example can achieve the above-described operational effects.

[0388] 2. Second Implementation

[0389] Next, the liquid ejection device 1 of the second embodiment will be described. When describing the liquid ejection device 1 of the second embodiment, the same components as those of the liquid ejection device 1 of the first embodiment are denoted by the same reference numerals, and the description thereof may be simplified or omitted.

[0390] Fig. 27 2 is a diagram showing the functional structure of a print head 100 included in a liquid ejection device 1 according to a second embodiment. Fig. 27 As shown, the print head 100 of the second embodiment is different from the liquid ejection device 1 of the first embodiment in that, in addition to the print data signal SI1 , print data signals SI2 to SIn are input to the abnormality detection circuit 250 .

[0391] Specifically, the abnormality detection circuit 250 receives inputs of the diagnosis control signal HC, the print data signals SI1 to SIn, the clock signal SCK, the latch signal LAT, the conversion signal CH, and the drive voltage signal VDR1 .

[0392] The abnormality detection circuit 250 determines whether the signal transmitted to the print head 100 is normal based on the diagnosis control signal HC and the drive voltage signal VDR1, similarly to the first embodiment. Then, when it is determined that the signal transmitted to the print head 100 is normal, the abnormality detection circuit 250 outputs the print data signals SI1 to SIn, the clock signal SCK, the latch signal LAT, and the conversion signal CH to the drive signal selection circuits 200-1 to 200-n.

[0393] Even the liquid ejection device 1 of the second embodiment configured as described above can achieve the same operational effects as those of the liquid ejection device 1 shown in the first embodiment.

[0394] In addition, in the liquid ejection device 1 of the second embodiment, the diagnostic control signal HC may also be transmitted by the wiring for transmitting the printing data signals SI1 to SIn, respectively. In this case, the diagnostic control signal HC may also be a first command signal HCf and include a first command signal HCf1 corresponding to the printing data signal SI1, a first command signal HCfn corresponding to the printing data signal SIn, and a first command signal HCfj corresponding to the printing data signal SIj (j is any one of 1 to n). Similarly, the diagnostic control signal HC may be a second command signal HCs and include a second command signal HCs1 corresponding to the printing data signal SI1, a second command signal HCsn corresponding to the printing data signal SIn, and a second command signal HCsj corresponding to the printing data signal SIj (j is any one of 1 to n).

[0395] Moreover, in the cable FC, the first instruction signal HCf1 and the second instruction signal HCs1 included in the printing data signal SI1 and the diagnostic control signal HC are transmitted in the common wiring WI and the terminal TM, the first instruction signal HCfn and the second instruction signal HCsn included in the printing data signal SIn and the diagnostic control signal HC1 are transmitted in the common wiring WI and the terminal TM, and the first instruction signal HCfj and the second instruction signal HCsj included in the printing data signal SIj and the diagnostic control signal HC1 are transmitted in the common wiring WI and the terminal TM.

[0396] The abnormality detection circuit 250 determines whether the potential of the wiring WI-VDR1 and the terminal TM-VDR1 of the voltage signal VS1 of the potential V1 is normal by recognizing that all the first command signals HCf1 to HCfn are input are normal, and determines whether the potential of the wiring WI-VDR1 and the terminal TM-VDR1 of the voltage signal VS2 of the potential V2 is normal by recognizing that all the second command signals HCs1 to HCsn are normal. Thus, in addition to the wiring WI and the terminal TM for transmitting the printing data signal SI1, it is also possible to determine whether the potentials of the wiring WI and the terminal TM for transmitting the printing data signals SI2 to SIn are normal. As a result, the accuracy of determining whether the high voltage signal and the low voltage signal supplied to the print head 100 are normal can be improved, and the possibility of malfunction in the print head 100 can be further reduced.

[0397] 3. Third Implementation

[0398] Next, a third embodiment of the liquid ejection device 1 is described. When describing the third embodiment of the liquid ejection device 1, the same components as those of the first embodiment and the second embodiment are denoted by the same reference numerals, and their description may be simplified or omitted.

[0399] Fig.28 2 is a diagram showing the functional structure of a print head 100 included in a liquid ejection device 1 according to a third embodiment. Fig.28 As shown, in the print head 100 of the third embodiment, the difference from the liquid ejection device 1 of the first embodiment and the second embodiment is that there are n abnormality detection circuits 250 corresponding to the drive signal selection circuits 200-1 to 200-n, respectively. Here, the abnormality detection circuit 250 corresponding to the drive signal selection circuit 200-1 is referred to as the abnormality detection circuit 250-1, the abnormality detection circuit 250 corresponding to the drive signal selection circuit 200-n is referred to as the abnormality detection circuit 250-n, and the abnormality detection circuit 250 corresponding to the drive signal selection circuit 200-j (j is any one of 1 to n) is referred to as the abnormality detection circuit 250-j.

[0400] Specifically, the diagnosis control signal HC, the printing data signal SI1, the clock signal SCK, the latch signal LAT, the conversion signal CH, and the driving voltage signal VDR1 are input to the abnormality detection circuit 250-1. Then, based on the diagnosis control signal HC and the driving voltage signal VDR1, the abnormality detection circuit 250-1 determines whether the signal transmitted to the print head 100 is normal. If it is determined that the signal transmitted to the print head 100 is normal, the printing data signal SI1, the clock signal SCK, the latch signal LAT, and the conversion signal CH are output to the driving signal selection circuit 200-1.

[0401] Similarly, the abnormality detection circuit 250-n inputs the diagnostic control signal HC, the printing data signal SIn, the clock signal SCK, the latch signal LAT, the conversion signal CH, and the driving voltage signal VDR1. Then, the abnormality detection circuit 250-n determines whether the signal transmitted to the print head 100 is normal based on the diagnostic control signal HC and the driving voltage signal VDR1. When it is determined that the signal transmitted to the print head 100 is normal, the printing data signal SIn, the clock signal SCK, the latch signal LAT, and the conversion signal CH are output to the driving signal selection circuit 200-n.

[0402] Similarly, the abnormality detection circuit 250-j inputs the diagnostic control signal HC, the printing data signal SIj, the clock signal SCK, the latch signal LAT, the conversion signal CH, and the drive voltage signal VDR1. Then, the abnormality detection circuit 250-j determines whether the signal transmitted to the print head 100 is normal based on the diagnostic control signal HC and the drive voltage signal VDR1. If it is determined that the signal transmitted to the print head 100 is normal, the printing data signal SIj, the clock signal SCK, the latch signal LAT, and the conversion signal CH are output to the drive signal selection circuit 200-j.

[0403] Even the liquid ejection device 1 of the third embodiment configured as described above can achieve the same operational effects as those of the liquid ejection device 1 shown in the first embodiment.

[0404] In addition, in the liquid ejection device 1 of the third embodiment, after the diagnosis control signal HC is branched by the ejection control unit 20, one of the branches of the diagnosis control signal HC is transmitted through the same wiring WI and terminal TM as the printing data signal SI1, the other branch of the diagnosis control signal HC is transmitted through the same wiring WI and terminal TM as the printing data signal SIn, and another branch of the diagnosis control signal HC is transmitted through the same wiring WI and terminal TM as the printing data signal SIj. Thus, the abnormality detection circuits 250-1 to 250-n can determine whether the respective potentials of the wiring WI and terminal TM for transmitting the printing data signals SI2 to SIn are normal in addition to the wiring WI and terminal TM for transmitting the printing data signal SI1. As a result, the accuracy of determining whether the high voltage signal and the low voltage signal supplied to the print head 100 are normal can be improved, and the possibility of malfunction in the print head 100 can be further reduced.

[0405] Alternatively, the semiconductor device 450 included in each of the abnormality detection circuits 250-1 to 250-n and the semiconductor device 201 including the drive signal selection circuits 200 corresponding to the abnormality detection circuits 250-1 to 250-n may be formed of a single integrated circuit. This allows the print head 100 to be miniaturized.

[0406] Although the embodiments and modifications have been described above, the present invention is not limited to these embodiments, and can be implemented in various forms within the scope of the gist thereof. For example, the above-described embodiments can be appropriately combined.

[0407] The present invention includes structures that are substantially the same as the structures described in the embodiments (for example, structures with the same functions, methods, and results, or structures with the same purposes and effects). In addition, the present invention includes structures in which non-essential parts of the structures described in the embodiments are replaced. In addition, the present invention includes structures that can play the same role and effect as the structures described in the embodiments or structures that can achieve the same purpose. In addition, the present invention includes structures in which known technologies are added to the structures described in the embodiments.

[0408] The following contents are derived from the above-mentioned embodiments.

[0409] One way of controlling the print head circuit is,

[0410] A print head control circuit that causes a print head to perform printing, the print head detecting abnormality based on a first signal input to a second terminal when a potential of a first terminal is a first potential and a second signal input to the second terminal when a potential of the first terminal is a second potential, the print head control circuit comprising:

[0411] a signal circuit, which outputs the first signal and the second signal;

[0412] a first wiring electrically connected to the first terminal; and

[0413] a second wiring electrically connected to the second terminal,

[0414] At least one of the first potential and the second potential is higher than potentials of the first signal and the second signal,

[0415] The signal circuit outputs the first signal to the second wiring while supplying the first voltage signal of the first potential to the first wiring, and after outputting the first signal, outputs the second signal to the second wiring while supplying the first voltage signal of the second potential different from the first potential to the first wiring, and causes the print head to perform the abnormality detection based on the first signal, the second signal, the first voltage signal and the second voltage signal.

[0416] According to the print head control circuit, the signal circuit outputs a first signal to a second wiring electrically connected to the second terminal in a state where a first voltage signal of a first potential is supplied to a first wiring electrically connected to the first terminal, and after outputting the first signal, outputs a second signal to the second wiring in a state where a second voltage signal of a second potential different from the first potential is supplied to the first wiring. Thus, the print head control circuit causes the print head that performs abnormality detection to perform abnormality detection based on the first signal input to the second terminal in a state where the potential of the first terminal is the first potential and the second signal input to the second terminal in a state where the potential of the first terminal is the second potential. Therefore, the print head performs abnormality detection based on the first signal input to the second terminal in a state where the potential of the first terminal is the first potential and the second signal input to the second terminal in a state where the potential of the first terminal is the second potential.

[0417] That is, the print head control circuit controls the print head in the following manner: based on the first signal input to the second terminal, it determines whether the signal of the first potential input to the first terminal is normal; based on the second signal input to the second terminal, it determines whether the signal of the second potential input to the first terminal is normal, thereby determining whether the high voltage signal supplied to the print head is normal.

[0418] Furthermore, since the print head determines whether the high-voltage signal is normal based on the low-voltage first signal and the second signal, when the first signal and the second signal input to the print head are normal, the print head determines whether the high-voltage signal is normal, and when the first signal and the second signal input to the print head are abnormal, the print head does not determine whether the high-voltage signal is normal. That is, the print head control circuit also determines whether the low-voltage signal in the print head is normal based on whether the print head determines whether the high-voltage signal is normal.

[0419] Therefore, according to the print head control circuit, the print head can detect whether at least one high voltage signal of the first potential and the second potential and both the low voltage signals of the first signal and the second signal are normal, resulting in reducing the possibility of malfunctioning of the print head.

[0420] In one embodiment of the print head control circuit, it may be that:

[0421] The print head has a drive element,

[0422] The first wiring transmits a driving signal supplied to the driving element.

[0423] According to this print head control circuit, the first wiring is used both as a wiring for transmitting a drive signal supplied to a drive element and as a wiring for transmitting a first voltage signal and a second voltage signal, thereby reducing the number of wirings connected to the print head.

[0424] In one embodiment of the print head control circuit, it may be that:

[0425] The first potential is five times greater than a potential when the first signal is at a high level.

[0426] According to the print head control circuit, by setting the first potential of the first voltage signal to be five times greater than the potential when the first signal is at a high level, even when the first signal is superimposed on the first voltage signal, the influence of the first signal on the first voltage signal of the first potential can be reduced. Thus, the detection accuracy of whether both the high voltage signal and the low voltage signal supplied to the print head are normal is improved.

[0427] In one embodiment of the print head control circuit, it may be that:

[0428] The second potential is smaller than five times the potential when the second signal is at a high level.

[0429] According to the print head control circuit, the first voltage signal of the first potential and the second voltage signal of the second potential can be set to different voltage values ​​based on a threshold value as a reference, and further, the potential difference between the first potential and the second potential can be increased. As a result, in the print head, the detection accuracy of the first potential and the second potential is improved, and the detection accuracy of whether the high voltage signal and the low voltage signal supplied to the print head are normal is improved.

[0430] In one embodiment of the print head control circuit, it may be that:

[0431] The second potential is five times greater than a potential when the second signal is at a high level.

[0432] According to the print head control circuit, by setting the second potential of the second voltage signal to be five times greater than the potential when the second signal is at a high level, even when the second signal is superimposed on the second voltage signal, the influence of the second signal on the second voltage signal of the second potential can be reduced. Thus, the detection accuracy of whether both the high voltage signal and the low voltage signal supplied to the print head are normal is improved.

[0433] In one embodiment of the print head control circuit, it may be that:

[0434] The first potential is smaller than five times the potential when the first signal is at a high level.

[0435] According to the print head control circuit, the first voltage signal of the first potential and the second voltage signal of the second potential can be set to different voltage values ​​based on a threshold value as a reference, thereby increasing the potential difference between the first potential and the second potential. As a result, in the print head, the detection accuracy of the first potential and the second potential is improved, and the detection accuracy of whether the high voltage signal and the low voltage signal supplied to the print head are normal is improved.

[0436] In one embodiment of the print head control circuit, it may be that:

[0437] The signal circuit includes a receiving circuit for receiving an image signal supplied from a host computer.

[0438] At least one of the first potential and the second potential is higher than a potential of the image signal.

[0439] In one embodiment of the print head control circuit, it may be that:

[0440] The second wiring transmits printing data for executing printing by the print head after transmitting the second signal.

[0441] According to this print head control circuit, the second wiring is used both as a wiring for transmitting print data for causing the print head to execute a printing operation and as a wiring for transmitting the first signal and the second signal, thereby reducing the number of wirings connected to the print head.

[0442] In one embodiment of the print head control circuit, it may be that:

[0443] The first signal includes a first instruction and a second instruction immediately following the first instruction.

[0444] In one embodiment of the print head control circuit, it may be that:

[0445] The second signal includes a third instruction and a fourth instruction immediately following the third instruction.

[0446] In one embodiment of the print head control circuit, it may be that:

[0447] The first instruction and the third instruction include different information.

[0448] According to the print head control circuit, the processing performed by the print head based on the first signal and the processing performed by the print head based on the second signal can be performed by using different criteria, namely, the judgment criteria specified by the first instruction and the judgment criteria specified by the third instruction. As a result, the detection accuracy of whether the high voltage signal and the low voltage signal supplied to the print head are normal and the versatility of the detection are improved.

[0449] In one embodiment of the print head control circuit, it may be that:

[0450] The second instruction and the fourth instruction include the same information.

[0451] According to this print head control circuit, since at least a part of the command of the first signal and the second signal is common, it is possible to reduce the command information to be managed by the print head control circuit.

[0452] In one embodiment of the print head control circuit, it may be that:

[0453] The first wiring and the second wiring are included in one cable.

[0454] According to this print head control circuit, the possibility of variation in the wiring lengths of the first wiring and the second wiring is reduced, and the possibility of variation in the transmission time of the signal is reduced.

[0455] In one embodiment of the print head control circuit, it may be that:

[0456] The cable is a flexible flat cable.

[0457] In one embodiment of the print head control circuit, it may be that:

[0458] The cable includes a third wiring that transmits a power supply voltage.

[0459] In one embodiment of the print head control circuit, it may be that:

[0460] The cable includes a fourth wiring that transmits a clock signal.

[0461] In one embodiment of the print head control circuit, it may be that:

[0462] The cable includes a fifth wiring that transmits an abnormality determination signal indicating the presence or absence of an abnormality in the print head.

[0463] In one embodiment of the print head control circuit, it may be that:

[0464] The first potential or the second potential is the second highest potential in the signal transmitted by the cable.

[0465] In one embodiment of the print head control circuit, it may be that:

[0466] At least one of the first potential and the second potential is higher than 10% of an effective value of a commercial AC voltage supplied from the outside.

[0467] One embodiment of a liquid ejection device comprises:

[0468] a print head, which performs printing; and

[0469] a print head control circuit that causes the print head to perform printing,

[0470] The print head detects abnormality based on a first signal input to a second terminal when the potential of the first terminal is a first potential and a second signal input to the second terminal when the potential of the first terminal is a second potential.

[0471] The print head control circuit has:

[0472] a signal circuit, which outputs the first signal and the second signal;

[0473] a first wiring electrically connected to the first terminal; and

[0474] a second wiring electrically connected to the second terminal,

[0475] At least one of the first potential and the second potential is higher than potentials of the first signal and the second signal,

[0476] The signal circuit outputs the first signal to the second wiring while supplying the first voltage signal of the first potential to the first wiring, and after outputting the first signal, outputs the second signal to the second wiring while supplying the first voltage signal of the second potential different from the first potential to the first wiring, and causes the print head to perform the abnormality detection based on the first signal, the second signal, the first voltage signal and the second voltage signal.

[0477] According to the liquid ejection device, the signal circuit of the print head control circuit outputs a first signal to the second wiring electrically connected to the second terminal in a state where a first voltage signal of a first potential is supplied to the first wiring electrically connected to the first terminal, and after outputting the first signal, outputs a second signal to the second wiring in a state where a second voltage signal of a second potential different from the first potential is supplied to the first wiring. Thus, the print head control circuit causes the print head to perform abnormality detection based on the first signal input to the second terminal in a state where the potential of the first terminal is the first potential and the second signal input to the second terminal in a state where the potential of the first terminal is the second potential. Therefore, the print head performs abnormality detection based on the first signal input to the second terminal in a state where the potential of the first terminal is the first potential and the second signal input to the second terminal in a state where the potential of the first terminal is the second potential.

[0478] That is, according to the liquid ejection device, the print head control circuit controls the print head in the following manner: based on the first signal input to the second terminal, it is determined whether the signal of the first potential input to the first terminal is normal; based on the second signal input to the second terminal, it is determined whether the signal of the second potential input to the first terminal is normal; and the print head determines whether the supplied high voltage signal is normal.

[0479] Furthermore, since the print head determines whether the high-voltage signal is normal based on the low-voltage first signal and the second signal, when the first signal and the second signal input to the print head are normal, the print head determines whether the high-voltage signal is normal, and when the first signal and the second signal input to the print head are abnormal, the print head does not determine whether the high-voltage signal is normal. That is, the print head control circuit also determines whether the low-voltage signal in the print head is normal based on whether the print head determines whether the high-voltage signal is normal.

[0480] Therefore, according to the liquid ejection device, the print head can detect whether at least one of the high voltage signals of the first potential and the second potential and both the low voltage signals of the first signal and the second signal are normal, resulting in a reduction in the possibility of malfunctioning of the print head.

[0481] In one embodiment of the liquid ejection device, it may be that:

[0482] The print head has a drive element,

[0483] The first wiring transmits a driving signal supplied to the driving element.

[0484] According to this liquid ejection device, the first wiring is used both as a wiring for transmitting a drive signal supplied to a drive element and as a wiring for transmitting a first voltage signal and a second voltage signal, thereby reducing the number of wirings connecting the print head control circuit and the print head.

[0485] In one embodiment of the liquid ejection device, it may be that:

[0486] The first potential is five times greater than a potential when the first signal is at a high level.

[0487] According to the liquid ejection device, by setting the first potential of the first voltage signal to be five times greater than the potential when the first signal is at a high level, even when the first signal is superimposed on the first voltage signal, the influence of the first signal on the first voltage signal of the first potential can be reduced. Thus, the detection accuracy of whether both the high voltage signal and the low voltage signal supplied to the print head are normal is improved.

[0488] In one embodiment of the liquid ejection device, it may be that:

[0489] The second potential is smaller than five times the potential when the second signal is at a high level.

[0490] According to the liquid ejection device, the first voltage signal of the first potential and the second voltage signal of the second potential can be set to different voltage values ​​based on a threshold value as a reference, thereby increasing the potential difference between the first potential and the second potential. As a result, in the print head, the detection accuracy of the first potential and the second potential is improved, and the detection accuracy of whether the high voltage signal and the low voltage signal supplied to the print head are normal is improved.

[0491] In one embodiment of the liquid ejection device, it may be that:

[0492] The second potential is five times greater than a potential when the second signal is at a high level.

[0493] According to the liquid ejection device, by setting the second potential of the second voltage signal to be five times greater than the potential when the second signal is at a high level, even when the second signal is superimposed on the second voltage signal, the influence of the second signal on the second potential of the second voltage signal can be reduced. Thus, the detection accuracy of whether both the high voltage signal and the low voltage signal supplied to the print head are normal is improved.

[0494] In one embodiment of the liquid ejection device, it may be that:

[0495] The first potential is smaller than five times the potential when the first signal is at a high level.

[0496] According to the liquid ejection device, the first voltage signal of the first potential and the second voltage signal of the second potential can be set to different voltage values ​​based on a threshold value as a reference, thereby increasing the potential difference between the first potential and the second potential. As a result, in the print head, the detection accuracy of the first potential and the second potential is improved, and the detection accuracy of whether the high voltage signal and the low voltage signal supplied to the print head are normal is improved.

[0497] In one embodiment of the liquid ejection device, it may be that:

[0498] The signal circuit includes a receiving circuit for receiving an image signal supplied from a host computer.

[0499] At least one of the first potential and the second potential is higher than a potential of the image signal.

[0500] In one embodiment of the liquid ejection device, it may be that:

[0501] The second wiring transmits printing data for executing printing by the print head after transmitting the second signal.

[0502] According to this liquid ejection device, the second wiring is used as both a wiring for transmitting print data for causing the print head to execute a printing operation and a wiring for transmitting the first signal and the second signal, thereby reducing the number of wirings connected to the print head.

[0503] In one embodiment of the liquid ejection device, it may be that:

[0504] The first signal includes a first instruction and a second instruction immediately following the first instruction.

[0505] In one embodiment of the liquid ejection device, it may be that:

[0506] The second signal includes a third instruction and a fourth instruction immediately following the third instruction.

[0507] In one embodiment of the liquid ejection device, it may be that:

[0508] The first instruction and the third instruction include different information.

[0509] According to the liquid ejection device, the processing performed by the print head based on the first signal and the processing performed by the print head based on the second signal can be performed by different criteria, namely, the judgment criteria specified by the first instruction and the judgment criteria specified by the third instruction. As a result, the detection accuracy of whether the high voltage signal and the low voltage signal supplied to the print head are normal and the versatility of the detection are improved.

[0510] In one embodiment of the liquid ejection device, it may be that:

[0511] The second instruction and the fourth instruction include the same information.

[0512] According to this liquid ejection device, since at least a part of the command of the first signal and the second signal is common, it is possible to reduce the command information to be managed by the print head control circuit.

[0513] In one embodiment of the liquid ejection device, it may be that:

[0514] The first wiring and the second wiring are included in one cable.

[0515] According to this liquid ejection device, the possibility of variation in the wiring lengths of the first wiring and the second wiring is reduced, and the possibility of variation in the transmission time of the signal is reduced.

[0516] In one embodiment of the liquid ejection device, it may be that:

[0517] The cable is a flexible flat cable.

[0518] In one embodiment of the liquid ejection device, it may be that:

[0519] The cable includes a third wiring that transmits a power supply voltage.

[0520] In one embodiment of the liquid ejection device, it may be that:

[0521] The cable includes a fourth wiring that transmits a clock signal.

[0522] In one embodiment of the liquid ejection device, it may be that:

[0523] The cable includes a fifth wiring that transmits an abnormality determination signal indicating the presence or absence of an abnormality in the print head.

[0524] In one embodiment of the liquid ejection device, it may be that:

[0525] The first potential or the second potential is the second highest potential in the signal transmitted by the cable.

[0526] In one embodiment of the liquid ejection device, it may be that:

[0527] At least one of the first potential and the second potential is higher than 10% of an effective value of a commercial AC voltage supplied from the outside.

[0528] In one embodiment of the liquid ejection device, it may be that:

[0529] The print head includes an abnormality detection circuit that performs the abnormality detection, and at least a part of the abnormality detection circuit is included in a semiconductor integrated circuit.

Claims

1. A print head control circuit that causes a print head to perform printing, the print head detecting abnormality based on a first signal input to a second terminal when a potential of a first terminal is a first potential and a second signal input to the second terminal when a potential of the first terminal is a second potential, the print head control circuit comprising: a signal circuit, which outputs the first signal and the second signal; a first wiring electrically connected to the first terminal; and a second wiring electrically connected to the second terminal, At least one of the first potential and the second potential is higher than potentials of the first signal and the second signal, The signal circuit outputs the first signal to the second wiring while supplying the first voltage signal of the first potential to the first wiring, and after outputting the first signal, outputs the second signal to the second wiring while supplying the first voltage signal of the second potential different from the first potential to the first wiring, and causes the print head to perform the abnormality detection based on the first signal, the second signal, the first voltage signal and the second voltage signal.

2. The print head control circuit according to claim 1, characterized in that: The print head has a drive element, The first wiring transmits a driving signal supplied to the driving element.

3. The print head control circuit according to claim 1 or 2, characterized in that: The first potential is five times greater than a potential when the first signal is at a high level.

4. The print head control circuit according to claim 3, characterized in that: The second potential is smaller than five times the potential when the second signal is at a high level.

5. The print head control circuit according to claim 1 or 2, characterized in that: The second potential is five times greater than a potential when the second signal is at a high level.

6. The print head control circuit according to claim 5, characterized in that: The first potential is smaller than five times the potential when the first signal is at a high level.

7. The print head control circuit according to claim 1 or 2, characterized in that: The signal circuit includes a receiving circuit for receiving an image signal supplied from a host computer. At least one of the first potential and the second potential is higher than a potential of the image signal.

8. The print head control circuit according to claim 1 or 2, characterized in that: The second wiring transmits printing data for executing printing by the print head after transmitting the second signal.

9. The print head control circuit according to claim 1 or 2, characterized in that: The first signal includes a first instruction and a second instruction immediately following the first instruction.

10. The print head control circuit according to claim 9, characterized in that: The second signal includes a third instruction and a fourth instruction immediately following the third instruction.

11. The print head control circuit according to claim 10, characterized in that: The first instruction and the third instruction include different information.

12. The print head control circuit according to claim 10 or 11, characterized in that: The second instruction and the fourth instruction include the same information.

13. The print head control circuit according to claim 1 or 2, characterized in that: The first wiring and the second wiring are included in one cable.

14. The print head control circuit according to claim 13, characterized in that: The cable is a flexible flat cable.

15. The print head control circuit according to claim 13, characterized in that: The cable includes a third wiring that transmits a power supply voltage.

16. The print head control circuit according to claim 13, characterized in that: The cable includes a fourth wiring that transmits a clock signal.

17. The print head control circuit according to claim 13, characterized in that: The cable includes a fifth wiring that transmits an abnormality determination signal indicating the presence or absence of an abnormality in the print head.

18. The print head control circuit according to claim 13, characterized in that: The first potential or the second potential is the second highest potential in the signal transmitted by the cable.

19. The print head control circuit according to claim 1 or 2, characterized in that: At least one of the first potential and the second potential is higher than 10% of an effective value of a commercial AC voltage supplied from the outside.

20. A liquid ejection device, characterized in that: have: a print head, which performs printing; and a print head control circuit that causes the print head to perform printing, The print head detects abnormality based on a first signal input to a second terminal when the potential of the first terminal is a first potential and a second signal input to the second terminal when the potential of the first terminal is a second potential. The print head control circuit has: a signal circuit, which outputs the first signal and the second signal; a first wiring electrically connected to the first terminal; as well as a second wiring electrically connected to the second terminal, At least one of the first potential and the second potential is higher than potentials of the first signal and the second signal, The signal circuit outputs the first signal to the second wiring while supplying the first voltage signal of the first potential to the first wiring, and after outputting the first signal, outputs the second signal to the second wiring while supplying the first voltage signal of the second potential different from the first potential to the first wiring, and causes the print head to perform the abnormality detection based on the first signal, the second signal, the first voltage signal and the second voltage signal.

21. The liquid ejection device according to claim 20, characterized in that: The print head has a drive element, The first wiring transmits a driving signal supplied to the driving element.

22. The liquid ejection device according to claim 20 or 21, characterized in that: The first potential is five times greater than a potential when the first signal is at a high level.

23. The liquid ejection device according to claim 22, characterized in that: The second potential is smaller than five times the potential when the second signal is at a high level.

24. The liquid ejection device according to claim 20 or 21, characterized in that: The second potential is five times greater than a potential when the second signal is at a high level.

25. The liquid ejection device according to claim 24, characterized in that: The first potential is smaller than five times the potential when the first signal is at a high level.

26. The liquid ejection device according to claim 20 or 21, characterized in that: The signal circuit includes a receiving circuit for receiving an image signal supplied from a host computer. At least one of the first potential and the second potential is higher than a potential of the image signal.

27. The liquid ejection device according to claim 20 or 21, characterized in that: The second wiring transmits printing data for executing printing by the print head after transmitting the second signal.

28. The liquid ejection device according to claim 20 or 21, characterized in that: The first signal includes a first instruction and a second instruction immediately following the first instruction.

29. The liquid ejection device according to claim 28, characterized in that: The second signal includes a third instruction and a fourth instruction immediately following the third instruction.

30. The liquid ejection device according to claim 29, characterized in that: The first instruction and the third instruction include different information.

31. The liquid ejection device according to claim 29 or 30, characterized in that: The second instruction and the fourth instruction include the same information.

32. The liquid ejection device according to claim 20 or 21, characterized in that: The first wiring and the second wiring are included in one cable.

33. The liquid ejection device according to claim 32, characterized in that: The cable is a flexible flat cable.

34. The liquid ejection device according to claim 32, characterized in that: The cable includes a third wiring that transmits a power supply voltage.

35. The liquid ejection device according to claim 32, characterized in that: The cable includes a fourth wiring that transmits a clock signal.

36. The liquid ejection device according to claim 32, characterized in that: The cable includes a fifth wiring that transmits an abnormality determination signal indicating the presence or absence of an abnormality in the print head.

37. The liquid ejection device according to claim 32, characterized in that: The first potential or the second potential is the second highest potential in the signal transmitted by the cable.

38. The liquid ejection device according to claim 20 or 21, characterized in that: At least one of the first potential and the second potential is higher than 10% of an effective value of a commercial AC voltage supplied from the outside.

39. The liquid ejection device according to claim 20 or 21, characterized in that: The print head includes an abnormality detection circuit that performs the abnormality detection, and at least a part of the abnormality detection circuit is included in a semiconductor integrated circuit.

Images