Incremental magnetic encoder anti-interference circuit design method and incremental magnetic encoder

Abstract

The present invention relates to the field of encoder anti-interference technology, and in particular to an incremental magnetic encoder anti-interference circuit design method and an incremental magnetic encoder, the method comprising: S1, detecting the magnetic field change generated by the magnetic drum element installed on the incremental magnetic encoder shaft as the shaft rotates, and outputting a corresponding voltage signal; S2, processing the voltage signal to obtain three pulse signals A, B and Z; S3, for each pulse signal, designing an ASIC anti-interference hysteresis comparison method to realize the incremental magnetic encoder signal from single-channel output to dual-channel differential output; S4, analyzing the dual-channel differential output signal, and outputting the physical information of the shaft. The present invention improves the reliability and anti-interference ability of the incremental magnetic encoder.

Description

Technical Field

[0001] The invention relates to the technical field of encoder anti-interference, in particular to an incremental magnetic encoder anti-interference circuit design method and an incremental magnetic encoder. Background Art

[0002] With the rapid development of existing science and technology, industrial automatic control technology represented by CNC technology and robots is also innovating frequently. The development of intelligent and refined industrial equipment has put forward higher requirements on the robustness and accuracy of position positioning technology. In order to achieve the required control accuracy, suitable position sensors need to be used in the system.

[0003] Position sensors can sense the position changes of the object being measured and convert the changes into electrical signals for output. As a detection element, position sensors are widely used in various automation equipment scenarios and have become an important part of automation in industrial production and real life.

[0004] As a position sensor, the encoder is a new type of sensor for position information detection and positioning, and is widely used in various fields. At present, there are three main types of encoder products commonly used in the domestic and foreign markets, namely photoelectric encoders, rotary transformers and magnetic encoders. Magnetic encoders are new precision encoders based on the principle of electromagnetic sensors. According to the different signal output methods, they can be divided into absolute magnetic encoders and incremental magnetic encoders.

[0005] The incremental magnetic encoder consists of a magnetic drum and a magnetic sensor, which converts the magnetic field changes generated by the shaft rotation into pulse signals in order to obtain physical information about the encoder angle, speed and position. Incremental magnetic encoders have many advantages, such as high reliability, simple structure, no need for complex protocols, easy application and low cost, so they are widely used in industry.

[0006] Incremental magnetic encoders are generally used in motor control. The output signal is connected to the servo drive system. The working environment has strong electromagnetic interference. In the case of strong electromagnetic interference, the reliability and anti-interference ability of the magnetic encoder are the key technical indicators of the magnetic encoder. Summary of the invention

[0007] The present invention provides an incremental magnetic encoder anti-interference circuit design method and an incremental magnetic encoder, so as to improve the reliability and anti-interference ability of the incremental encoder. The technical solution is as follows:

[0008] On the one hand, a method for designing an anti-interference circuit of an incremental magnetic encoder is provided, the method comprising:

[0009] S1, detecting the change of magnetic field generated by the magnetic drum element installed on the shaft of the incremental magnetic encoder as the shaft rotates, and outputting a corresponding voltage signal;

[0010] S2, processing the voltage signal to obtain three pulse signals A, B and Z;

[0011] S3. For each pulse signal, design an ASIC anti-interference hysteresis comparison method to realize the incremental magnetic encoder signal from single-channel output to dual-channel differential output;

[0012] S4. Analyze the dual-path differential output signals and output physical information of the rotating shaft.

[0013] Optionally, for the pulse signals A, B, and Z, it is assumed that the pulse signal level values ​​are U A , U B , U Z ;

[0014] The S3 specifically includes:

[0015] Design two hysteresis comparison voltage signals U1 and U2;

[0016] For pulse signal A:

[0017] Design subtraction circuit to achieve:

[0018] U A -U1

[0019] U A -U2

[0020] Design of hysteresis comparator circuit:

[0021] Will U A -U1 is compared with 0. If U A -U1>0, then A + is high level, otherwise A + is low level;

[0022] Will U A -U2 is compared with 0. If U A -U2<0, then A - is low level, otherwise A - is high level;

[0023] Among them: A + , A - is the dual-channel output level signal value obtained after the A-phase pulse signal is processed by the hysteresis comparison circuit, and A + , A - The level signal value is opposite;

[0024] For pulse signal B:

[0025] Design subtraction circuit circuit implementation:

[0026] U B -U1

[0027] U B -U2

[0028] Design of hysteresis comparator circuit:

[0029] Will U B -U1 is compared with 0. If U B -U1>0, then B + is high level, otherwise B + is low level;

[0030] Will U B -U2 is compared with 0. If U B -U2<0, then B - is low level, otherwise B - is high level;

[0031] Among them: B + , B - is the dual-channel output level signal value obtained after the B-phase pulse signal is processed by the hysteresis comparison circuit, and B + , B - The level signal value is opposite;

[0032] For the pulse signal Z:

[0033] Design subtraction circuit to achieve:

[0034] U Z -U1

[0035] U Z -U2

[0036] Design of hysteresis comparator circuit:

[0037] Will U Z -U1 is compared with 0. If U Z -U1>0, then Z + is high level, otherwise Z + is low level;

[0038] Will U Z -U2 is compared with 0. If U Z -U2<0, then Z - is low level, otherwise Z - is high level;

[0039] Where: Z + , Z -is the dual-channel output level signal value obtained after the Z-phase pulse signal is processed by the hysteresis comparison circuit, and Z + , Z - The level signal values ​​are opposite.

[0040] Optionally, for the pulse signals A, B, and Z, it is assumed that the pulse signal level amplitudes are U' and A , U' B , U' Z , and because U' A =U' B =U' Z , so we can set U'=U' A =U' B =U' Z , where U' is the level signal amplitude;

[0041] The design of two hysteresis comparison voltage signals U1 and U2 specifically includes:

[0042]

[0043] On the other hand, an ASIC control circuit is provided, which is a special integrated circuit ASIC. The ASIC control circuit realizes the conversion of the incremental magnetic encoder signal from a single-channel output to a dual-channel differential output. The ASIC control circuit includes: three subtraction circuits and three hysteresis comparison circuits, and each subtraction circuit is connected to each hysteresis comparison circuit.

[0044] Optionally, the incremental magnetic encoder signal includes three pulse signals A, B, and Z. Assume that the level signal values ​​of the pulse signals are U A , U B , U Z ;

[0045] For pulse signal A:

[0046] The subtraction circuit realizes:

[0047] U A -U1

[0048] U A -U2

[0049] U1 and U2 are designed two hysteresis comparison voltage signals;

[0050] The hysteresis comparison circuit:

[0051] Will U A -U1 is compared with 0. If U A -U1>0, then A + is high level, otherwise A +is low level;

[0052] Will U A -U2 is compared with 0. If U A -U2<0, then A - is low level, otherwise A - is high level;

[0053] Among them: A + , A - is the dual-channel output level signal value obtained after the A-phase pulse signal is processed by the hysteresis comparison circuit, and A + , A - The level signal value is opposite;

[0054] For pulse signal B:

[0055] The subtraction circuit realizes:

[0056] U B -U1

[0057] U B -U2

[0058] U1 and U2 are designed two hysteresis comparison voltage signals;

[0059] The hysteresis comparison circuit:

[0060] Will U B -U1 is compared with 0. If U B -U1>0, then B + is high level, otherwise B + is low level;

[0061] Will U B -U2 is compared with 0. If U B -U2<0, then B - is low level, otherwise B - is high level;

[0062] Among them: B + , B - is the dual-channel output level signal value obtained after the B-phase pulse signal is processed by the hysteresis comparison circuit, and B + , B - The level signal value is opposite;

[0063] For the pulse signal Z:

[0064] The subtraction circuit realizes:

[0065] U Z -U1

[0066] U Z -U2

[0067] U1 and U2 are designed two hysteresis comparison voltage signals;

[0068] The hysteresis comparison circuit:

[0069] Will U Z -U1 is compared with 0. If U Z -U1>0, then Z + is high level, otherwise Z + is low level;

[0070] Will U Z -U2 is compared with 0. If U Z -U2<0, then Z - is low level, otherwise Z - is high level;

[0071] Where: Z + , Z - is the dual-channel output level signal value obtained after the Z-phase pulse signal is processed by the hysteresis comparison circuit, and Z + , Z - The level signal values ​​are opposite.

[0072] Optionally, for the pulse signals A, B, and Z, it is assumed that the pulse signal level amplitudes are U' and A , U' B , U' Z , and because U' A =U' B =U' Z , so we can set U'=U' A =U' B =U' Z , where U' is the level signal amplitude;

[0073] The U1 and U2 specifically include:

[0074]

[0075] On the other hand, an incremental magnetic encoder is also provided, the incremental magnetic encoder comprising:

[0076] A signal generating module, used for collecting physical information of the incremental magnetic encoder shaft during rotation and outputting a corresponding voltage signal;

[0077] A signal processing module, used for processing the voltage signal to obtain three pulse signals A, B and Z;

[0078] ASIC control circuit, used to design ASIC anti-interference hysteresis comparison method for each pulse signal, so as to realize the incremental magnetic encoder signal from single-channel output to dual-channel differential output;

[0079] The analysis module is used to analyze the signals of the dual-path differential outputs and output the physical information of the rotating shaft.

[0080] Optionally, the ASIC control circuit is an application specific integrated circuit ASIC, and the ASIC control circuit realizes the conversion of the incremental magnetic encoder signal from a single-channel output to a dual-channel differential output. The ASIC control circuit includes: three subtraction circuits and three hysteresis comparison circuits, and each subtraction circuit is connected to each hysteresis comparison circuit.

[0081] Optionally, the incremental magnetic encoder signal includes three pulse signals A, B, and Z. Assume that the level signal values ​​of the pulse signals are U A , U B , U Z ;

[0082] For pulse signal A:

[0083] The subtraction circuit realizes:

[0084] U A -U1

[0085] U A -U2

[0086] U1 and U2 are designed two hysteresis comparison voltage signals;

[0087] The hysteresis comparison circuit:

[0088] Will U A -U1 is compared with 0. If U A -U1>0, then A + is high level, otherwise A + is low level;

[0089] Will U A -U2 is compared with 0. If U A -U2<0, then A - is low level, otherwise A - is high level;

[0090] Among them: A + , A - is the dual-channel output level signal value obtained after the A-phase pulse signal is processed by the hysteresis comparison circuit, and A + , A - The level signal value is opposite;

[0091] For pulse signal B:

[0092] The subtraction circuit realizes:

[0093] U B -U1

[0094] U B -U2

[0095] U1 and U2 are designed two hysteresis comparison voltage signals;

[0096] The hysteresis comparison circuit:

[0097] Will U B -U1 is compared with 0. If U B -U1>0, then B + is high level, otherwise B + is low level;

[0098] Will U B -U2 is compared with 0. If U B -U2<0, then B - is low level, otherwise B - is high level;

[0099] Among them: B + , B - is the dual-channel output level signal value obtained after the B-phase pulse signal is processed by the hysteresis comparison circuit, and B + , B - The level signal value is opposite;

[0100] For the pulse signal Z:

[0101] The subtraction circuit realizes:

[0102] U Z -U1

[0103] U Z -U2

[0104] U1 and U2 are designed two hysteresis comparison voltage signals;

[0105] The hysteresis comparison circuit:

[0106] Will U Z -U1 is compared with 0. If U Z -U1>0, then Z + is high level, otherwise Z + is low level;

[0107] Will U Z -U2 is compared with 0. If U Z -U2<0, then Z- is low level, otherwise Z - is high level;

[0108] Where: Z + , Z - is the dual-channel output level signal value obtained after the Z-phase pulse signal is processed by the hysteresis comparison circuit, and Z + , Z - The level signal values ​​are opposite.

[0109] Optionally, for the pulse signals A, B, and Z, it is assumed that the pulse signal level amplitudes are U' and A , U' B , U' Z , and because U' A =U' B =U' Z , so we can let U'=U' A =U' B =U' Z , where U' is the level signal amplitude;

[0110] The U1 and U2 specifically include:

[0111]

[0112] The beneficial effects brought about by the technical solution provided by the present invention at least include: the reliability and anti-interference ability of the incremental magnetic encoder are improved by adopting the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0113] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0114] Figure 1 It is a flow chart of an anti-interference circuit design method for an incremental magnetic encoder provided by an embodiment of the present invention;

[0115] Figure 2 It is a schematic diagram of the structure of an existing incremental magnetic encoder;

[0116] Figure 3 It is a pulse signal waveform diagram generated by signal processing of the voltage signal output by the incremental magnetic encoder;

[0117] Figure 4 It is a block diagram of the ASIC control circuit structure implemented by the present invention;

[0118] Figure 5It is a waveform diagram of a dual-channel output pulse signal obtained after the A-phase pulse signal of an embodiment of the present invention is processed by an ASIC control circuit;

[0119] Figure 6 It is a waveform diagram of a dual-channel output pulse signal obtained after the B-phase pulse signal of an embodiment of the present invention is processed by an ASIC control circuit;

[0120] Figure 7 It is a dual-channel output pulse signal waveform diagram obtained after the Z-phase pulse signal of the embodiment of the present invention is processed by the ASIC control circuit;

[0121] Figure 8 4 is a structural block diagram of an incremental magnetic encoder according to an embodiment of the present invention. DETAILED DESCRIPTION

[0122] In order to make the technical problems, technical solutions and advantages to be solved by the present invention more clear, a detailed description will be given below with reference to the accompanying drawings and specific embodiments.

[0123] like Figure 1 As shown, an embodiment of the present invention provides a method for designing an anti-interference circuit of an incremental magnetic encoder, the method comprising:

[0124] S1, detecting the change of magnetic field generated by the magnetic drum element installed on the shaft of the incremental magnetic encoder as the shaft rotates, and outputting a corresponding voltage signal;

[0125] S2, processing the voltage signal to obtain three pulse signals A, B and Z;

[0126] S3. For each pulse signal, design an ASIC anti-interference hysteresis comparison method to realize the incremental magnetic encoder signal from single-channel output to dual-channel differential output;

[0127] S4. Analyze the dual-path differential output signals and output physical information of the rotating shaft.

[0128] The following is combined with Figure 2-7 , a method for designing an anti-interference circuit for an incremental magnetic encoder according to an embodiment of the present invention is described in detail.

[0129] like Figure 2As shown in the figure, the structure of the existing incremental magnetic encoder is mainly divided into two parts according to different functions: the signal generation part and the signal processing part. The work focus of the signal generation part is to collect and output the physical information such as the angle, speed, position, etc. during the rotation of the incremental magnetic encoder shaft in a certain way. It mainly detects the magnetic field changes generated by the magnetic drum element installed on the incremental magnetic encoder shaft as the shaft rotates through the magnetic sensor, and outputs the corresponding voltage signal. The signal processing part processes the voltage signal obtained from the front-end structure to obtain three pulse signals A, B and Z, analyzes them, and outputs the physical information such as the angle, speed, position, etc. of the shaft.

[0130] In addition, the incremental magnetic encoder also has a signal conditioning part, which is used to perform zero adjustment analog filtering, A / D conversion, and digital filtering noise reduction on the voltage signal output by the signal generating part.

[0131] Figure 3 The waveform of the pulse signal generated after the voltage signal is processed, where A and B are two pulse signals with a phase difference of 90°. The rotation direction of the rotor can be determined by the relationship between the two pulse signals. When the phase of pulse signal A leads the phase of pulse signal B by 90°, the motor rotor rotates forward; when the phase of pulse signal A lags the phase of pulse signal B by 90°, the motor rotor reverses. The Z-phase pulse signal is used for cycle counting, that is, every time a high level appears in the Z-phase pulse signal, the incremental magnetic encoder runs a cycle; the number of pulses per cycle of the two pulse signals A and B is equal to the resolution of the incremental magnetic encoder, so the resolution of the incremental magnetic encoder can be calculated by the three-phase pulse signals A, B, and Z.

[0132] The embodiment of the present invention improves the existing incremental magnetic encoder and provides an incremental magnetic encoder anti-interference circuit design method to improve the reliability and anti-interference ability of the incremental magnetic encoder.

[0133] An embodiment of the present invention provides a method for designing an anti-interference circuit of an incremental magnetic encoder, the method comprising:

[0134] S1, detecting the change of magnetic field generated by the magnetic drum element installed on the shaft of the incremental magnetic encoder as the shaft rotates, and outputting a corresponding voltage signal;

[0135] S2, processing the voltage signal to obtain three pulse signals A, B and Z;

[0136] S3. For each pulse signal, design an ASIC anti-interference hysteresis comparison method to realize the incremental magnetic encoder signal from single-channel output to dual-channel differential output;

[0137] Optionally, for the pulse signals A, B, and Z, it is assumed that the pulse signal level values ​​are U A , U B , U Z ;

[0138] The S3 specifically includes:

[0139] Design two hysteresis comparison voltage signals U1 and U2;

[0140] For pulse signal A:

[0141] Design a subtraction circuit to achieve:

[0142] U A -U1

[0143] U A -U2

[0144] The subtraction circuit is composed of Figure 4 The subtraction function generator is implemented by writing code in a dedicated integrated circuit ASIC.

[0145] Design of hysteresis comparator circuit:

[0146] Will U A -U1 is compared with 0. If U A -U1>0, then A + is high level, otherwise A + is low level;

[0147] Will U A -U2 is compared with 0. If U A -U2<0, then A - is low level, otherwise A - is high level;

[0148] Among them: Figure 5 As shown, A + , A - is the dual-channel output level signal value obtained after the A-phase pulse signal is processed by the hysteresis comparison circuit, and A + , A - The level signal value is opposite;

[0149] The hysteresis comparison circuit is composed of Figure 4 The comparison function generator is implemented by writing code in an application-specific integrated circuit ASIC.

[0150] For pulse signal B:

[0151] Design subtraction circuit circuit implementation:

[0152] U B -U1

[0153] U B -U2

[0154] The subtraction circuit is composed of Figure 4 The subtraction function generator is implemented by writing code in a dedicated integrated circuit ASIC.

[0155] Design of hysteresis comparator circuit:

[0156] Will U B -U1 is compared with 0. If U B -U1>0, then B + is high level, otherwise B + is low level;

[0157] Will U B -U2 is compared with 0. If U B -U2<0, then B - is low level, otherwise B - is high level;

[0158] Among them: Figure 6 As shown, B + , B - is the dual-channel output level signal value obtained after the B-phase pulse signal is processed by the hysteresis comparison circuit, and B + , B - The level signal value is opposite;

[0159] The hysteresis comparison circuit is composed of Figure 4 The comparison function generator is implemented by writing code in an application-specific integrated circuit ASIC.

[0160] For the pulse signal Z:

[0161] Design subtraction circuit to achieve:

[0162] U Z -U1

[0163] U Z -U2

[0164] The subtraction circuit is composed of Figure 4 The subtraction function generator is implemented by writing code in a dedicated integrated circuit ASIC.

[0165] Design of hysteresis comparator circuit:

[0166] Will U Z -U1 is compared with 0. If U Z-U1>0, then Z + is high level, otherwise Z + is low level;

[0167] Will U Z -U2 is compared with 0. If U Z -U2<0, then Z - is low level, otherwise Z - is high level;

[0168] Among them: Figure 7 As shown, Z + , Z - is the dual-channel output level signal value obtained after the Z-phase pulse signal is processed by the hysteresis comparison circuit, and Z + , Z - The level signal values ​​are opposite.

[0169] The hysteresis comparison circuit is composed of Figure 4 The comparison function generator is implemented by writing code in an application-specific integrated circuit ASIC.

[0170] Optionally, for the pulse signals A, B, and Z, it is assumed that the pulse signal level amplitudes are U' and A , U' B , U' Z , and because U' A =U' B =U' Z , so we can set U'=U' A =U' B =U' Z , where U' is the level signal amplitude;

[0171] The design of two hysteresis comparison voltage signals U1 and U2 specifically includes:

[0172]

[0173] S4. Analyze the dual-path differential output signals and output physical information of the rotating shaft.

[0174] The embodiment of the present invention designs the above subtraction circuit. When a pulse signal interference is generated, assuming that the pulse signal interference is U f , the level signal value of pulse signal A changes to U' after being disturbed A , then

[0175] U′ A =(U A +U f )

[0176] After the hysteresis comparison voltage signals U1 and U2 are disturbed, the level signal values ​​become U'1 and U'2, then

[0177]

[0178] Then the above subtraction circuit realizes the following results:

[0179]

[0180] It can be seen from the above formula that the output result of the subtraction circuit after interference is exactly the same as the output result of the subtraction circuit when not interfered, so the subtraction circuit has a higher anti-interference ability.

[0181] At the same time, design the above comparison circuit, when U A -U1>0, that is Then there is A + is high level; at this time there must also be That is U A -U2>0, so A - is low level.

[0182] Similarly, when U A -U2<0, that is When A - is high level; at this time there must also be That is U A -U1<0, so A + is low level.

[0183] Compared with the traditional hysteresis comparator circuit, the hysteresis comparator circuit designed above uses U A Compare with U1 and U2 respectively to replace the original U A Compared with 0, that is, when U A -When U1>0, there must be U A -0>0, then A is high level, A + A is high level. - is low level; when U A -U2<0, there must be U A -0<0, A is low level at this time, A + A is low level. - It is a high level. It can be seen that the use of this comparison circuit can further improve the anti-interference ability and reliability of the magnetic encoder.

[0184] By designing an ASIC control circuit composed of the above subtraction circuit and comparison circuit, the single-channel A pulse signal is converted into a dual-channel differential output A + and A -signal, and the level signal values ​​of the two signals are opposite. When the level signal values ​​of the two signals are not opposite, that is, A + and A - When they are both high or low at the same time, it means that the incremental magnetic encoder is faulty. Therefore, the ASIC control circuit also has the function of detecting whether the incremental magnetic encoder is faulty.

[0185] The same is true for pulse signals B and Z, which will not be elaborated here.

[0186] In addition, the incremental magnetic encoder provided by the embodiment of the present invention composed of the ASIC control circuit also has the above-mentioned effects, which will not be described in detail here.

[0187] like Figure 4 As shown, the circuit of the embodiment of the present invention realizes the conversion of the incremental magnetic encoder signal from a single-channel output to a dual-channel differential output. The ASIC control circuit includes: three subtraction circuits and three hysteresis comparison circuits, and each subtraction circuit is connected to each hysteresis comparison circuit.

[0188] Optionally, the incremental magnetic encoder signal includes three pulse signals A, B, and Z. Assume that the level signal values ​​of the pulse signals are U A , U B , U Z ;

[0189] For pulse signal A:

[0190] The subtraction circuit realizes:

[0191] U A -U1

[0192] U A -U2

[0193] U1 and U2 are designed two hysteresis comparison voltage signals;

[0194] The subtraction circuit is composed of Figure 4 The subtraction function generator is implemented by writing code in a dedicated integrated circuit ASIC.

[0195] The hysteresis comparison circuit:

[0196] Will U A -U1 is compared with 0. If U A -U1>0, then A + is high level, otherwise A + is low level;

[0197] Will U A -U2 is compared with 0. If U A-U2<0, then A - is low level, otherwise A - is high level;

[0198] Among them: Figure 5 As shown, A + , A - is the dual-channel output level signal value obtained after the A-phase pulse signal is processed by the hysteresis comparison circuit, and A + , A - The level signal value is opposite;

[0199] The hysteresis comparison circuit is composed of Figure 4 The comparison function generator is implemented by writing code in an application-specific integrated circuit ASIC.

[0200] For pulse signal B:

[0201] The subtraction circuit realizes:

[0202] U B -U1

[0203] U B -U2

[0204] U1 and U2 are designed two hysteresis comparison voltage signals;

[0205] The subtraction circuit is composed of Figure 4 The subtraction function generator is implemented by writing code in a dedicated integrated circuit ASIC.

[0206] The hysteresis comparison circuit:

[0207] Will U B -U1 is compared with 0. If U B -U1>0, then B + is high level, otherwise B + is low level;

[0208] Will U B -U2 is compared with 0. If U B -U2<0, then B - is low level, otherwise B - is high level;

[0209] Among them: Figure 6 As shown, B + , B - is the dual-channel output level signal value obtained after the B-phase pulse signal is processed by the hysteresis comparison circuit, and B + , B - The level signal value is opposite;

[0210] The hysteresis comparison circuit is composed of Figure 4 The comparison function generator is implemented by writing code in an application-specific integrated circuit ASIC.

[0211] For the pulse signal Z:

[0212] The subtraction circuit realizes:

[0213] U Z -U1

[0214] U Z -U2

[0215] U1 and U2 are designed two hysteresis comparison voltage signals;

[0216] The subtraction circuit is composed of Figure 4 The subtraction function generator is implemented by writing code in a dedicated integrated circuit ASIC.

[0217] The hysteresis comparison circuit:

[0218] Will U Z -U1 is compared with 0. If U Z -U1>0, then Z + is high level, otherwise Z + is low level;

[0219] Will U Z -U2 is compared with 0. If U Z -U2<0, then Z - is low level, otherwise Z - is high level;

[0220] Among them: Figure 7 As shown, Z + , Z - is the dual-channel output level signal value obtained after the Z-phase pulse signal is processed by the hysteresis comparison circuit, and Z + , Z - The level signal values ​​are opposite.

[0221] The hysteresis comparison circuit is composed of Figure 4 The comparison function generator is implemented by writing code in an application-specific integrated circuit ASIC.

[0222] Optionally, for the pulse signals A, B, and Z, it is assumed that the pulse signal level amplitudes are U' and A , U' B , U' Z , and because U' A =U'B =U' Z , so we can let U'=U' A =U' B =U' Z , where U' is the level signal amplitude;

[0223] The U1 and U2 specifically include:

[0224]

[0225] like Figure 8 As shown, the present invention also provides an incremental magnetic encoder, the incremental magnetic encoder comprising:

[0226] A signal generating module, used for collecting physical information of the incremental magnetic encoder shaft during rotation and outputting a corresponding voltage signal;

[0227] A signal processing module, used for processing the voltage signal to obtain three pulse signals A, B and Z;

[0228] ASIC control circuit, used to design ASIC anti-interference hysteresis comparison method for each pulse signal, so as to realize the incremental magnetic encoder signal from single-channel output to dual-channel differential output;

[0229] The analysis module is used to analyze the signals of the dual-path differential outputs and output the physical information of the rotating shaft.

[0230] Optionally, the signal generating module specifically includes a magnetic sensor, which detects the change of the magnetic field generated by the magnetic drum element installed on the shaft of the incremental magnetic encoder as the shaft rotates, and outputs a corresponding voltage signal.

[0231] Optionally, the ASIC control circuit is an application specific integrated circuit ASIC, and the ASIC control circuit realizes the conversion of the incremental magnetic encoder signal from a single-channel output to a dual-channel differential output. The ASIC control circuit includes: three subtraction circuits and three hysteresis comparison circuits, and each subtraction circuit is connected to each hysteresis comparison circuit.

[0232] Optionally, for the three pulse signals A, B, and Z, it is assumed that the pulse signal level values ​​are U A , U B , U Z ;

[0233] Optionally, the incremental magnetic encoder signal includes three pulse signals A, B, and Z. Assume that the level signal values ​​of the pulse signals are U A , U B , U Z ;

[0234] For pulse signal A:

[0235] The subtraction circuit realizes:

[0236] U A -U1

[0237] U A -U2

[0238] U1 and U2 are designed two hysteresis comparison voltage signals;

[0239] The subtraction circuit is composed of Figure 8 The subtraction function generator is implemented by writing code in a dedicated integrated circuit ASIC.

[0240] The hysteresis comparison circuit:

[0241] Will U A -U1 is compared with 0. If U A -U1>0, then A + is high level, otherwise A + is low level;

[0242] Will U A -U2 is compared with 0. If U A -U2<0, then A - is low level, otherwise A - is high level;

[0243] Among them: Figure 5 As shown, A + , A - is the dual-channel output level signal value obtained after the A-phase pulse signal is processed by the hysteresis comparison circuit, and A + , A - The level signal value is opposite;

[0244] The hysteresis comparison circuit is composed of Figure 8 The comparison function generator is implemented by writing code in an application-specific integrated circuit ASIC.

[0245] For pulse signal B:

[0246] The subtraction circuit realizes:

[0247] U B -U1

[0248] U B -U2

[0249] U1 and U2 are designed two hysteresis comparison voltage signals;

[0250] The subtraction circuit is composed of Figure 8 The subtraction function generator is implemented by writing code in a dedicated integrated circuit ASIC.

[0251] The hysteresis comparison circuit:

[0252] Will U B -U1 is compared with 0. If U B -U1>0, then B + is high level, otherwise B + is low level;

[0253] Will U B -U2 is compared with 0. If U B -U2<0, then B - is low level, otherwise B - is high level;

[0254] Among them: Figure 6 As shown, B + , B - is the dual-channel output level signal value obtained after the B-phase pulse signal is processed by the hysteresis comparison circuit, and B + , B - The level signal value is opposite;

[0255] The hysteresis comparison circuit is composed of Figure 8 The comparison function generator is implemented by writing code in an application-specific integrated circuit ASIC.

[0256] For the pulse signal Z:

[0257] The subtraction circuit realizes:

[0258] U Z -U1

[0259] U Z -U2

[0260] U1 and U2 are designed two hysteresis comparison voltage signals;

[0261] The subtraction circuit is composed of Figure 8 The subtraction function generator is implemented by writing code in a dedicated integrated circuit ASIC.

[0262] The hysteresis comparison circuit:

[0263] Will U Z -U1 is compared with 0. If U Z -U1>0, then Z + is high level, otherwise Z+ is low level;

[0264] Will U Z -U2 is compared with 0. If U Z -U2<0, then Z - is low level, otherwise Z - is high level;

[0265] Among them: Figure 7 As shown, Z + , Z - is the dual-channel output level signal value obtained after the Z-phase pulse signal is processed by the hysteresis comparison circuit, and Z + , Z - The level signal values ​​are opposite.

[0266] The hysteresis comparison circuit is composed of Figure 8 The comparison function generator is implemented by writing code in an application-specific integrated circuit ASIC.

[0267] Optionally, for the pulse signals A, B, and Z, it is assumed that the pulse signal level amplitudes are U' and A , U' B , U' Z , and because U' A =U' B =U' Z , so we can set U'=U' A =U' B =U' Z , where U' is the level signal amplitude;

[0268] The U1 and U2 specifically include:

[0269]

[0270] Optionally, the physical information includes: information such as angle, rotation speed, position, etc. during the rotation of the incremental magnetic encoder shaft.

[0271] In addition, the incremental magnetic encoder of the embodiment of the present invention also has a signal conditioning module for performing zero adjustment analog filtering, A / D conversion, and digital filtering noise reduction on the voltage signal output by the magnetic sensor.

[0272] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for designing an anti-interference circuit for an incremental magnetic encoder, characterized in that: The method comprises: S1, detecting the change of magnetic field generated by the magnetic drum element installed on the shaft of the incremental magnetic encoder as the shaft rotates, and outputting a corresponding voltage signal; S2. Process the voltage signal to obtain three pulse signals A, B and Z, wherein A and B are two pulse signals with a phase difference of 90°, and the Z phase pulse signal is used for cycle counting; S3. For each pulse signal, design an ASIC anti-interference hysteresis comparison method to realize the incremental magnetic encoder signal from single-channel output to dual-channel differential output; S4, analyzing the dual-path differential output signals, and outputting the physical information of the rotating shaft; For the pulse signals A, B, and Z, it is assumed that the pulse signal level values ​​are U A , U B , U Z ; The S3 specifically includes: Design two hysteresis comparison voltage signals U1 and U2; For pulse signal A: Design subtraction circuit to achieve: U A -U1 U A -U2 Design of hysteresis comparator circuit: Will U A -U1 is compared with 0. If U A -U1>0, then A + is high level, otherwise A + is low level; Will U A -U2 is compared with 0. If U A -U2<0, then A - is low level, otherwise A - is high level; Among them: A + , A - is the dual-channel output level signal value obtained after the A-phase pulse signal is processed by the hysteresis comparison circuit, and A + , A - The level signal value is opposite; For pulse signal B: Design subtraction circuit to achieve: U B -U1 U B -U2 Design of hysteresis comparator circuit: Will U B -U1 is compared with 0. If U B -U1>0, then B + is high level, otherwise B + is low level; Will U B -U2 is compared with 0. If U B -U2<0, then B - is low level, otherwise B - is high level; Among them: B + , B - is the dual-channel output level signal value obtained after the B-phase pulse signal is processed by the hysteresis comparison circuit, and B + , B - The level signal value is opposite; For the pulse signal Z: Design subtraction circuit to achieve: U Z -U1 U Z -U2 Design of hysteresis comparator circuit: Will U Z -U1 is compared with 0. If U Z -U1>0, then Z + is high level, otherwise Z + is low level; Will U Z -U2 is compared with 0. If U Z -U2<0, then Z - is low level, otherwise Z - is high level; Where: Z + , Z - is the dual-channel output level signal value obtained after the Z-phase pulse signal is processed by the hysteresis comparison circuit, and Z + , Z - The level signal value is opposite; For the pulse signals A, B, and Z, it is assumed that the pulse signal level amplitudes are U′ respectively. A , U′ B , U′ Z , and because U′ A =U′ B =U′ Z , so we can let U′=U′ A =U′ B =U′ Z , where U′ is the level signal amplitude; The design of two hysteresis comparison voltage signals U1 and U2 specifically includes:

2. An ASIC control circuit, characterized in that: The ASIC control circuit is a special integrated circuit ASIC, and the ASIC control circuit realizes the incremental magnetic encoder signal from a single-channel output to a dual-channel differential output. The ASIC control circuit includes: three subtraction circuits and three hysteresis comparison circuits, each subtraction circuit is connected to each hysteresis comparison circuit; The incremental magnetic encoder signal includes three pulse signals A, B, and Z, wherein A and B are two pulse signals with a phase difference of 90°, and the Z-phase pulse signal is used for cycle counting. Assume that the pulse signal level values ​​are U A , U B , U Z ; For pulse signal A: The subtraction circuit realizes: U A -U1 U A -U2 U1 and U2 are designed two hysteresis comparison voltage signals; The hysteresis comparison circuit: Will U A -U1 is compared with 0. If U A -U1>0, then A + is high level, otherwise A + is low level; Will U A -U2 is compared with 0. If U A -U2<0, then A - is low level, otherwise A - is high level; Among them: A + , A - is the dual-channel output level signal value obtained after the A-phase pulse signal is processed by the hysteresis comparison circuit, and A + , A - The level signal value is opposite; For pulse signal B: The subtraction circuit realizes: U B -U1 U B -U2 U1 and U2 are designed two hysteresis comparison voltage signals; The hysteresis comparison circuit: Will U B -U1 is compared with 0. If U B -U1>0, then B + is high level, otherwise B + is low level; Will U B -U2 is compared with 0. If U B -U2<0, then B - is low level, otherwise B - is high level; Among them: B + , B - is the dual-channel output level signal value obtained after the B-phase pulse signal is processed by the hysteresis comparison circuit, and B + , B - The level signal value is opposite; For the pulse signal Z: The subtraction circuit realizes: U Z -U1 U Z -U2 U1 and U2 are designed two hysteresis comparison voltage signals; The hysteresis comparison circuit: Will U Z -U1 is compared with 0. If U Z -U1>0, then Z + is high level, otherwise Z + is low level; Will U Z -U2 is compared with 0. If U Z -U2<0, then Z - is low level, otherwise Z - is high level; Where: Z + , Z - is the dual-channel output level signal value obtained after the Z-phase pulse signal is processed by the hysteresis comparison circuit, and Z + , Z - The level signal value is opposite; For the pulse signals A, B, and Z, it is assumed that the pulse signal level amplitudes are U′ respectively. A , U′ B , U′ Z , and because U′ A =U′ B =U′ Z , so we can let U′=U′ A =U′ B =U′ Z , where U′ is the level signal amplitude; The U1 and U2 specifically include:

3. An incremental magnetic encoder, characterized in that: The incremental magnetic encoder comprises: A signal generating module, used for collecting physical information of the incremental magnetic encoder shaft during rotation and outputting a corresponding voltage signal; A signal processing module, used for processing the voltage signal to obtain three pulse signals A, B and Z, wherein A and B are two pulse signals with a phase difference of 90°, and the Z phase pulse signal is used for cycle counting; ASIC control circuit, used to design ASIC anti-interference hysteresis comparison method for each pulse signal, so as to realize the incremental magnetic encoder signal from single-channel output to dual-channel differential output; An analysis module, used for analyzing the dual-path differential output signal and outputting the physical information of the rotating shaft; The ASIC control circuit is a special integrated circuit ASIC, and the ASIC control circuit realizes the incremental magnetic encoder signal from a single-channel output to a dual-channel differential output. The ASIC control circuit includes: three subtraction circuits and three hysteresis comparison circuits, each subtraction circuit is connected to each hysteresis comparison circuit; The incremental magnetic encoder signal includes three pulse signals A, B, and Z. Assume that the pulse signal level values ​​are U A , U B , U Z ; For pulse signal A: The subtraction circuit realizes: U A -U1 U A -U2 U1 and U2 are designed two hysteresis comparison voltage signals; The hysteresis comparison circuit: Will U A -U1 is compared with 0. If U A -U1>0, then A + is high level, otherwise A + is low level; Will U A -U2 is compared with 0. If U A -U2<0, then A - is low level, otherwise A - is high level; Among them: A + , A - is the dual-channel output level signal value obtained after the A-phase pulse signal is processed by the hysteresis comparison circuit, and A + , A - The level signal value is opposite; For pulse signal B: The subtraction circuit realizes: U B -U1 U B -U2 U1 and U2 are designed two hysteresis comparison voltage signals; The hysteresis comparison circuit: Will U B -U1 is compared with 0. If U B -U1>0, then B + is high level, otherwise B + is low level; Will U B -U2 is compared with 0. If U B -U2<0, then B - is low level, otherwise B - is high level; Among them: B + , B - is the dual-channel output level signal value obtained after the B-phase pulse signal is processed by the hysteresis comparison circuit, and B + , B - The level signal value is opposite; For the pulse signal Z: The subtraction circuit realizes: U Z -U1 U Z -U2 U1 and U2 are designed two hysteresis comparison voltage signals; The hysteresis comparison circuit: Will U Z -U1 is compared with 0. If U z -U1>0, then Z + is high level, otherwise Z + is low level; Will U Z -U2 is compared with 0. If U Z -U2<0, then Z - is low level, otherwise Z - Is high level; where: Z + , Z - is the dual-channel output level signal value obtained after the Z-phase pulse signal is processed by the hysteresis comparison circuit, and Z + , Z - The level signal value is opposite; For the pulse signals A, B, and Z, it is assumed that the pulse signal level amplitudes are U′ respectively. A , U′ B , U′ Z , and because U′ A =U′ B =U′ Z , so we can let U′=U′ A =U′ B =U′ Z , where U′ is the level signal amplitude; The U1 and U2 specifically include:

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