A current mirror type equivalent capacitance boosting circuit

Abstract

The application discloses a current mirror type equivalent capacitor boosting circuit, wherein the current mirror unit comprises an N1 node, an N2 node, an N3 node and an N4 node, the N1 node and the N2 node are connected to the ground through a first resistor and a second resistor respectively, the N3 node and the N4 node are connected to a first current source and a second current source respectively, a first plate of a capacitor is connected to a signal end, a second plate of the capacitor is connected to the N1 node, a drain of an equivalent MOS tube is connected to the signal end, a source of the equivalent MOS tube is connected to the N2 node, and a gate of the equivalent MOS tube is connected to the N3 node. Through the current mirror unit, the capacitor and the equivalent MOS tube, the current mirror type equivalent capacitor boosting circuit is formed, the multiplication of a small capacitor can be realized, that is, a smaller area is used in the circuit, the same equivalent capacitor as that occupying a larger area in a traditional process is obtained, and the current mirror type equivalent capacitor boosting circuit has the advantages of simple structure and low production cost.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and specifically to a current mirror-type equivalent capacitance boosting circuit. Background Technology

[0002] Capacitors are fundamental components in integrated circuits, serving functions such as coupling AC signals, constructing delay and phase shift networks, and filtering. They are widely used in delay circuits, filtering circuits, and rectifier circuits. However, traditional integrated circuit processes for fabricating large-capacitance capacitors often employ a method of isolating dielectrics between metals. This method occupies a large area, hindering chip miniaturization and integration. Furthermore, if the chip has strict area requirements and the capacitor used also needs to be large, traditional solutions are completely inadequate. Therefore, for applications requiring the integration of large capacitors, a smaller capacitor can be integrated, and then the circuit structure can be used to achieve a larger equivalent capacitance.

[0003] Chinese patent CN113904656B provides an equivalent capacitor module, an equivalent capacitor single circuit, and a chip, relating to the field of analog integrated circuit technology. The equivalent capacitor circuit consists of a startup module, a composite switch module, and the equivalent capacitor module connected in sequence. The startup module provides the required reference voltage and internal operating voltage VDD. The composite switch module, through the received first switch voltage V1 and second switch voltage V2, causes the voltage at the non-inverting input terminal of the equivalent capacitor module to rise or fall slowly, making the non-inverting input terminal exhibit the same impedance characteristics as a capacitor to the gnd terminal. Thus, the equivalent capacitor module can be equivalent to a nanofarad-level capacitor, solving the technical problem that integrated circuits cannot integrate capacitors exceeding several hundred picofarads. Although this method simplifies the circuit structure and reduces costs to some extent compared to existing technologies using an off-chip approach, its circuit structure is still relatively complex, requiring multiple NPN and PNP transistors to form the startup module and composite switch module, resulting in a relatively large footprint in the manufacturing process. Therefore, providing a solution to the above-mentioned technical problems is a problem that those skilled in the art need to solve. Summary of the Invention

[0004] To address the shortcomings of the prior art, the present invention aims to provide a current mirror type equivalent capacitance enhancement circuit that can achieve the same equivalent capacitance as the larger area required in conventional processes using a smaller area in the circuit under BiCMOS technology.

[0005] To achieve the above objectives, the technical solution of the present invention is as follows: The present invention provides a current mirror type equivalent capacitance boosting circuit, including a capacitor, an equivalent MOS transistor, a signal terminal, and a current mirror unit. The current mirror unit includes nodes N1, N2, N3, and N4. Nodes N1 and N2 are grounded through a first resistor and a second resistor, respectively, with the first resistor having a greater resistance than the second resistor. Nodes N3 and N4 are connected to a first current source and a second current source, respectively, with the current value of the first current source being less than the current value of the second current source. The first plate of the capacitor is connected to the signal terminal, and the second plate of the capacitor is connected to node N1. The drain of the equivalent MOS transistor is connected to the signal terminal, the source of the equivalent MOS transistor is connected to node N2, and the gate of the equivalent MOS transistor is connected to node N3.

[0006] Furthermore, the current mirror unit also includes a first transistor and a second transistor that are mirror images of each other. The collector of the first transistor is connected to the N3 node, the emitter of the first transistor is connected to the N1 node, the collector of the second transistor is connected to the N4 node, the emitter of the second transistor is connected to the N2 node, and the base of the first transistor is connected to the base of the second transistor and is also connected to the N4 node.

[0007] Furthermore, the first transistor and the second transistor are NPN bipolar transistors.

[0008] Furthermore, the area ratio of the emitter of the first transistor to the emitter of the second transistor is 1:n.

[0009] Furthermore, the current ratio of the first current source to the second current source is 1:n, and the resistance ratio of the first resistor to the second resistor is n:1.

[0010] Furthermore, the value of n ranges from 1 to 10.

[0011] Furthermore, the equivalent MOS transistor is an NMOS transistor.

[0012] Compared with the prior art, the beneficial effects of the present invention are as follows: by setting a current mirror unit, a capacitor and an equivalent MOS transistor to form a current mirror type equivalent capacitance boosting circuit, it is possible to multiply the small capacitance, that is, to obtain the same equivalent capacitance with a smaller area in the circuit as in the traditional process, while having the advantages of simple structure and low production cost. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the current mirror type equivalent capacitance boosting circuit of the present invention;

[0014] Figure 2The simulation results show the frequency characteristics of the current mirror type equivalent capacitance boosting circuit of the present invention. Detailed Implementation

[0015] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0016] In the description of this invention, it should be noted that, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, it can refer to a direct connection or an indirect connection through an intermediate medium, enabling communication between the internal components of two elements. The terminology used in this specification is for the purpose of describing specific embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a," "an," and "the" are intended to include the plural forms.

[0017] like Figure 1 As shown, this embodiment provides a current mirror type equivalent capacitance C. T The boost circuit includes capacitor C. T The circuit consists of a signal terminal (in), an equivalent MOSFET (MP), and a current mirror unit. The current mirror unit includes a first transistor Q1, a second transistor Q2, nodes N1, N2, N3, and N4. The collector of the first transistor Q1 is connected to the positive electrode of the first current source IB1 through node N3, providing the first current IB1 to the first transistor Q1. The emitter of the first transistor Q1 is connected to node N1 as the first output terminal of the current mirror circuit. The collector of the second transistor Q2 is connected to the positive electrode of the first current source IB2 through node N4, providing the second current IB2 to the second transistor Q2. The emitter of the second transistor Q2 is connected to node N2 as the second output terminal of the current mirror circuit. The bases of the first transistor Q1 and the second transistor Q2 are connected and also connected to node N4. Therefore, the first transistor Q1 and the second transistor Q2 are mirror images of each other, forming a current mirror connection.

[0018] Specifically, both the first transistor Q1 and the second transistor Q2 are NPN bipolar transistors. Each NPN transistor consists of an N-type emitter, a P-type base, and an N-type collector. The collector current is proportional to the base current and less than the emitter current. When the base voltage is slightly higher than the emitter's forward voltage, the transistor conducts. Therefore, when a small current is injected into the base, a larger current is generated between the emitter and collector, thus achieving current gain. In this invention, a current mirror structure is formed using a common-base NPN bipolar transistor. The basic idea is that one collector collects a portion of the diffused carriers, while the other collector collects the remaining carriers, offering advantages such as optimized chip area and reduced cost.

[0019] Furthermore, nodes N1 and N2 are grounded through the first resistor R1 and the second resistor R2, respectively, and capacitor C... T The first plate is connected to the signal terminal in, and the capacitor C T The second plate is connected to node N1, where capacitor C T The type can be a multilayer metal MOM capacitor or a MOS capacitor, with capacitance C. T The value is generally around tens of pF, offering advantages such as low cost, small chip footprint, and high integration. The first resistor R1 and the second resistor R2 provide negative feedback for the current mirror structure, thereby improving the stability of current changes.

[0020] Furthermore, the drain of the equivalent MOS transistor MP is connected to the signal terminal in, the source is connected to node N2, and the gate is connected to node N3. The equivalent MOS transistor MP is an NMOS transistor. The NMOS transistor substrate is a P-type silicon wafer, with two highly doped N-regions fabricated using a diffusion process, and the source and drain are brought out. A silicon dioxide insulating layer is fabricated on the semiconductor, followed by a layer of aluminum, from which the gate is brought out. When the voltage between the gate and source changes, it alters the amount of induced charge near the insulating layer on the substrate, thereby controlling the drain current. In this invention, the drain of the equivalent MOS transistor MP is the input terminal, the source is the output terminal, and the gate is connected to a high potential as the control terminal. Turning the high potential on or off at the control terminal controls the conduction or cutoff of the NMOS transistor.

[0021] Furthermore, the area ratio of the emitter of the first transistor Q1 to the emitter of the second transistor Q2 is 1:n, the current ratio of the first current IB1 to the first current source IB2 is 1:n, and the resistance ratio of the first resistor R1 to the second resistor R2 is n:1. The NPN bipolar transistor determines the emitter current separation ratio based on the emitter area ratio. Simultaneously, considering power consumption, increasing the emitter junction area of ​​the NPN transistor can improve the device's current handling capability.

[0022] Preferably, the value of n is in the range of 1-10.

[0023] Working principle: In this invention, the first transistor Q1 and the second transistor Q2 are connected to the first current I. B1 Second current I B2 Together with the first resistor R1 and the second resistor R2, they form a current mirror structure, with the first current I... B1 An input current I is supplied to the collector of the first transistor Q1. B1 Input current is supplied to the collector of the second transistor Q2. First current source I B1 The positive terminal is connected to the bases of the first transistor Q1 and the second transistor Q2, so that the voltage carrying the input current can be used to trigger the first transistor Q1 and the second transistor Q2 to conduct. That is, the voltage applied to the base of the transistors is forward biased and turns on, and the current begins to flow from the collector to the emitter. This driving voltage is 0.7V. Based on the current mirror, the current flowing through the NPN bipolar transistor Q2 is n times that of the NPN bipolar transistor Q1. Since the base voltage drop Vbe of bipolar transistors Q1 and Q2 is the same, the potentials at points N1 and N2 in the current mirror are the same. Let the current flowing through the capacitor be I. C The current flowing through the NMOS transistor MP is I. MP Then there is

[0024] R1×(I B1 +I C )=R2×(I B2 +I MP )

[0025] Solving the equation yields

[0026] I MP =n×I C

[0027] It can be seen that the current flowing through the NMOS transistor MP is equal to the current flowing through the capacitor C. T The current is n times the original. From the signal terminal in, the voltage remains unchanged, but the current increases to (n+1) times the original, so the equivalent capacitance also increases to (n+1) times the original.

[0028] The structure is placed as a capacitor in a basic RC circuit, and the circuit is simulated. The resistance is 100kΩ, the capacitance is set to 1pF, and the current mirror is set to n=10. Therefore, theoretically, the current mirror equivalent capacitance boosting circuit should be equivalent to an 11pF capacitor. AC small-signal simulation is performed, obtaining a 3dB bandwidth, such as... Figure 2 As shown by the midpoint position, the pole position is 162.4kHz. According to the 3dB bandwidth formula for an RC circuit:

[0029]

[0030] Where BW represents the signal bandwidth, R represents the resistance, and C represents the capacitance.

[0031] The actual capacitance value introduced in the actual circuit can be calculated as follows:

[0032]

[0033] Therefore, it can be seen that the equivalent capacitance has actually increased by 9.8 times. This is slightly less than the theoretical 11 times because the transistors and MOSFETs used in the simulation are based on models with actual process parameters. This reflects the result after considering leakage current and the mismatch caused by the increased load on the current mirror, which is normal. Adjusting the parameters of the transistors and MOSFETs appropriately according to actual needs can make the multiplication factor closer to the theoretical value.

[0034] It is understood that all devices in the embodiments of the present invention are compatible with CMOS technology, and the equivalent amplification of the capacitor can be achieved through only a current mirror unit, a capacitor, and an NMOS transistor, which has the advantages of simple structure and low production cost.

[0035] As those skilled in the art will understand, aspects of the present invention, particularly the current mirror equivalent capacitance circuit described herein, can be implemented in various ways, for example, as a method or system. The following detailed description provides various descriptions of certain specific embodiments. However, the innovations described herein can be embodied in many different ways, as defined and covered by the claims or selected examples. For example, although some descriptions are provided herein with regard to bipolar or NMOS transistors, other embodiments of the current mirror arrangement described herein may include any combination of bipolar and NMOS transistors. In the following description, reference is made to the accompanying drawings, wherein similar reference numerals may indicate the same or functionally similar elements. It will be understood that the structures, proportions, sizes, etc., illustrated in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the implementation of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and purposes achieved by this application, should still fall within the scope of the technical content disclosed herein. Furthermore, it will be understood that some embodiments may include more elements and / or a subset of the elements shown in the figures than are shown in the figures. Furthermore, some embodiments may incorporate any suitable combination of features from two or more figures.

[0036] Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A current mirror-type equivalent capacitance boosting circuit, characterized in that, The device includes a capacitor, an equivalent MOSFET, a signal terminal, and a current mirror unit. The current mirror unit includes nodes N1, N2, N3, and N4. Nodes N1 and N2 are grounded through a first resistor and a second resistor, respectively, with the first resistor having a greater resistance than the second resistor. Nodes N3 and N4 are connected to a first current source and a second current source, respectively, with the first current source having a less current than the second current source. The first plate of the capacitor is connected to the signal terminal, and the second plate of the capacitor is connected to node N1. The drain of the equivalent MOSFET is connected to the signal terminal, the source of the equivalent MOSFET is connected to node N2, and the gate of the equivalent MOSFET is connected to node N3. The current mirror unit further includes a first transistor and a second transistor that are mirror images of each other. The collector of the first transistor is connected to the N3 node, the emitter of the first transistor is connected to the N1 node, the collector of the second transistor is connected to the N4 node, the emitter of the second transistor is connected to the N2 node, and the base of the first transistor is connected to the base of the second transistor and is also connected to the N4 node.

2. The current mirror type equivalent capacitance boosting circuit according to claim 1, characterized in that, The capacitor is a metal-layered MOM capacitor or a MOS capacitor.

3. The current mirror type equivalent capacitance boosting circuit according to claim 1, characterized in that, The first transistor and the second transistor are NPN bipolar transistors.

4. The current mirror type equivalent capacitance boosting circuit according to claim 1, characterized in that, The area ratio of the emitter of the first transistor to the emitter of the second transistor is 1:n.

5. A current mirror-type equivalent capacitance boosting circuit according to claim 4, characterized in that, The current ratio of the first current source to the second current source is 1:n, and the resistance ratio of the first resistor to the second resistor is n:

1.

6. The current mirror type equivalent capacitance boosting circuit according to claim 5, characterized in that, The value of n ranges from 1 to 10.

7. The current mirror type equivalent capacitance boosting circuit according to claim 1, characterized in that, The equivalent MOS transistor is an NMOS transistor.

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