Instruction compression method, instruction decompression method, and flow compression method

Abstract

The embodiments of the present application disclose an instruction compression method, an instruction decompression method and a flow compression method. The flow compression method is used for compressing a flow. The flow includes a jump instruction. The flow compression method includes: dividing the flow into multiple blocks according to a position of the jump instruction in the flow and a destination of the jump instruction; recording a jump relationship between the multiple blocks; performing instruction compression on the multiple blocks; recalculating a jump address of the jump instruction according to the jump relationship; determining multiple groups according to sizes of the multiple blocks and the jump relationship; and determining that the jump instruction is a first type of jump instruction or a second type of jump instruction according to a relationship between the jump instruction and the multiple groups.

Description

Technical Field

[0001] This application relates to instruction compression and decompression, specifically to instruction compression methods, instruction decompression methods, and flow compression methods related to jump instructions (or branch instructions). Background Technology

[0002] Generally, a workflow (e.g., image processing workflow, startup workflow, etc.) typically includes at least one jump instruction. However, existing platforms cannot simultaneously enable variable-length instruction compression when handling jump logic, resulting in larger instruction register space requirements, an increased number of long jump instructions, and decreased workflow execution efficiency. Therefore, an instruction compression method, an instruction decompression method, and a workflow compression method are needed to reduce the space required for instruction registers and the number of long jump instructions. Summary of the Invention

[0003] This application provides an instruction compression method, an instruction decompression method, and a process compression method to improve upon the shortcomings of prior art.

[0004] This application provides an instruction decompression method applied to a hardware circuit. The hardware circuit decompresses and executes an instruction, which includes a header and a reference value. The method includes: when the reference value of the instruction is a preset value, reading a first parameter of the instruction to obtain a number of dissimilar parameters; and setting a plurality of corresponding parameters of the hardware circuit with a plurality of second parameters of the instruction, wherein the number of the plurality of second parameters is equal to the number of dissimilar parameters.

[0005] This application provides an instruction compression method for compressing an instruction to generate a compressed instruction. The instruction includes a header and multiple parameters. The header includes a reference value. The method includes: comparing the instruction with a previous instruction to find multiple dissimilar parameters in the instruction that are different from the previous instruction; setting the reference value of the compressed instruction to a preset value; setting a target parameter of the compressed instruction to the number of the multiple dissimilar parameters; and setting other parameters of the compressed instruction to the multiple dissimilar parameters.

[0006] This application provides a process compression method for compressing a process, the process including a jump instruction. The method includes: dividing the process into multiple blocks according to a position of the jump instruction in the process and a destination of the jump instruction; recording a jump relationship between the multiple blocks; compressing the instructions in the multiple blocks; recalculating a jump address of the jump instruction according to the jump relationship; determining multiple groups according to the size of the multiple blocks and the jump relationship; and determining whether the jump instruction is a first type of jump instruction or a second type of jump instruction according to the relationship between the jump instruction and the multiple groups.

[0007] The technical means embodied in the embodiments of this application can improve at least one of the disadvantages of the prior art. Therefore, compared with the prior art, this application can reduce the space required for the instruction register and / or reduce the number of long jump instructions.

[0008] The features, implementation, and effects of this application are described in detail with reference to the accompanying drawings. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a functional block diagram of the intelligent processor provided in the embodiments of this application;

[0011] Figure 2 This is a flowchart of the process compression method provided in the embodiments of this application;

[0012] Figure 3 This is a schematic diagram of a process including multiple instructions and the jump relationship between blocks of the process provided in the embodiments of this application;

[0013] Figure 4 This is a schematic diagram illustrating the jump relationship between blocks provided in an embodiment of this application;

[0014] Figure 5 yes Figure 2 Details of step S210;

[0015] Figure 6 This is a flowchart of the instruction compression method provided in the embodiments of this application;

[0016] Figure 7 These are schematic diagrams of the instruction structure before compression and the instruction structure after compression provided in the embodiments of this application;

[0017] Figure 8 and Figure 9 yes Figure 2 Details of step S250;

[0018] Figure 10A and Figure 10B This is a schematic diagram illustrating the division of multiple blocks of a process into multiple groups, as provided in an embodiment of this application.

[0019] Figure 11 yes Figure 2 Details of step S260;

[0020] Figure 12 This is a schematic diagram of group division provided in an embodiment of this application;

[0021] Figure 13 This is a flowchart of the instruction decompression method provided in the embodiments of this application;

[0022] Figure 14 This is a schematic diagram illustrating the execution of uncompressed instructions by a hardware circuit provided in an embodiment of this application; and

[0023] Figure 15 This is a schematic diagram of the hardware circuit provided in the embodiment of this application executing compression instructions.

[0024] [Symbol Explanation]

[0025] 100: Intelligent Processor

[0026] 110: Decoder

[0027] 112: Memory

[0028] 114: Instruction prefetching circuit

[0029] 116: Instruction dispatch circuit

[0030] 118: Jump Logic Circuit

[0031] 120: Direct Memory Access (DMA)

[0032] 130: Vector Circuit

[0033] 140: Convolutional Circuit

[0034] 122, 132, 142: Instruction decompression circuit

[0035] 124, 134, 144: Calculation circuits

[0036] 310: Process

[0037] INST1~INST15,INST_k-1,INST_k,INST_y: Instructions

[0038] 320: Inter-block redirection relationships

[0039] BB: Block boundary

[0040] BLK1, BLK2, BLK3, BLK4: Blocks

[0041] INST_k', INST_z: Compressed instructions

[0042] HD: Header

[0043] InstFlag: Flag

[0044] HDLen: Reference value

[0045] P1,P2,P3,P4,P5,Pn,P1',P2',P3',P4',P5': Parameters

[0046] Nd: Number of dissimilar parameters

[0047] SR: Threshold value

[0048] GB: Group Boundaries

[0049] GRP1, GRP2, GRP3: Groups

[0050] INST_n: Jump instruction

[0051] REGP: Temporary Registry Group

[0052] REG1, REG2, REG3, REG4, REG5: Temporary registers

[0053] S210, S220, S230, S240, S250, S260, S510, S520, S530, S540, S550, S610, S620, S630, S640, S650, S660, S670, S680, S810, S820, S830, S840, S850, S860, S870, S910, S920, S930, S940, S950, S960, S970, S1110, S1120, S1130, S1140, S1150, S1160, S1310, S1320, S1330, S1340, S1350, S1360: Steps Detailed Implementation

[0054] The technical terms used in the following description refer to the common terms in this technical field. If this specification provides explanations or definitions for certain terms, the explanations or definitions in this specification shall prevail.

[0055] The disclosure of this application includes an instruction compression method, an instruction decompression method, and a process compression method. Since some components of the intelligent processor in this application may be known individually, details of known components will be omitted in the following description without affecting the full disclosure and implementability of the device invention. Furthermore, some or all of the processes of the instruction compression method, instruction decompression method, and process compression method of this application may be in the form of software and / or firmware.

[0056] Figure 1 This is a functional block diagram of the Intelligent Processing Unit (IPU) provided in this application embodiment. The intelligent processor 100 includes a decoder 110, a direct memory access (DMA) circuit 120, a vector circuit 130, and a convolution circuit 140. The DMA circuit 120, vector circuit 130, and convolution circuit 140 each include instruction decompression circuits 122, 132, and 142, and calculation circuits 124, 134, and 144. The instruction decompression circuits 122, 132, and 142 are used to decompress instructions (details of instruction decompression will be provided later). Figure 13 (Details to follow), while computing circuits 124, 134, and 144 respectively perform the main functions of direct memory access 120, vector circuit 130, and convolution circuit 140. Since those skilled in the art are familiar with the main functions of direct memory access 120, vector circuit 130, and convolution circuit 140, they will not be described in detail here.

[0057] The decoder 110 includes a memory 112 (e.g., Static Random Access Memory (SRAM)), an instruction prefetch circuit 114, an instruction delivery circuit 116, and a jump logic circuit 118. The memory 112 can store instructions that the intelligent processor 100 will execute. The instruction prefetch circuit 114 is used to fetch instructions from the memory 112, and then the instruction delivery circuit 116 determines the instructions based on the instruction's flag (InstFlag). Figure 7 The instruction is then distributed to the corresponding hardware circuit (i.e., direct memory access 120, vector circuit 130, or convolution circuit 140). Jump logic circuit 118 determines whether the instruction is a jump instruction and / or the type of jump instruction (long jump instruction or short jump instruction). When a jump instruction is encountered, jump logic circuit 118 determines the destination of the jump instruction, and then instruction prefetching circuit 114 retrieves the next instruction based on that destination.

[0058] In some embodiments, if the difference between the destination of a jump instruction (i.e., the address of the target instruction in memory 112) and the address of the jump instruction itself in memory 112 is less than a threshold value (e.g., the size of the instruction buffer in memory 112), then the jump instruction is a short jump instruction; otherwise, the jump instruction is a long jump instruction. That is, the jump range of a short jump instruction is smaller than that of a long jump instruction. When the decoder 110 processes a long jump instruction, direct memory access 120 needs to fetch more instructions from the external memory of the intelligent processor 100 (e.g., Dynamic Random Access Memory (DRAM), not shown), while short jump instructions do not require this; therefore, long jump instructions are more time-consuming and resource-intensive than short jump instructions.

[0059] Figure 2 This is a flowchart of the process compression method provided in an embodiment of this application. In some embodiments, Figure 2 The steps are performed by development tools (e.g., a general-purpose computer) during the development phase of the intelligent processor 100. Figure 2 The workflow compression method can be used to compress a specific workflow (e.g., image processing workflow, startup workflow, etc.), where the workflow includes multiple instructions (e.g., ...). Figure 3 The process 310 includes 15 instructions, from INST1 to INST15. These instructions are variable-length instructions, and at least one of them is a jump instruction. Figure 3 (To be detailed below). Figure 2 It includes the following steps.

[0060] Step S210: Based on the location of the jump instruction within a flow (e.g., the address of the jump instruction in memory 112) and the destination of the jump instruction (e.g., the address of the destination in memory 112), the flow is divided into multiple blocks. More specifically, step S210 scans the instructions in a flow and sets block boundaries BB to divide the flow into multiple blocks. Details of step S210 will be provided below. Figure 5 Detailed explanation. In Figure 3 In the example, process 310 is divided into 4 blocks (blocks BLK1 to BLK4, which include instructions INST1 to INST5, instructions INST6 to INST8, instructions INST9 to INST11, and instructions INST12 to INST15, respectively. Instructions INST5 and INST11 are jump instructions, and their destinations are instructions INST9 and INST6, respectively).

[0061] Step S220: Record the jump relationships between blocks. Please refer to [link / reference]. Figure 3After step S210, the inter-block jump relationship 320 is obtained: the target block of block BLK1 is block BLK3 (because block BLK3 includes the destination of instruction INST5 (i.e., instruction INST9)); the source block of block BLK2 is block BLK3 (because block BLK2 includes the destination of instruction INST11 (i.e., instruction INST6)); and the source and target blocks of block BLK3 are block BLK1 and block BLK2, respectively. Please refer to [link / reference]. Figure 4 , Figure 4 This is a diagram illustrating the jump relationships between blocks, corresponding to... Figure 3 The jump relationships between blocks 320; in other words, the jump relationships between blocks can also be represented or recorded graphically.

[0062] Step S230: Compress the multiple blocks one by one to obtain multiple compressed blocks. This step will be explained below. Figure 6 Detailed explanation.

[0063] Step S240: Recalculate the jump address (i.e., the destination address of the jump instruction) based on the jump relationship between blocks. Because the block was compressed in step S230, the destination address of the compressed jump instruction is no longer the original address, so the jump address must be recalculated or updated. For example, please refer to... Figure 3 Since almost every block becomes smaller after compression, the positions of instructions INST9 and INST6 change. Therefore, the destination addresses of instructions INST5 and INST11 must be updated or adjusted accordingly.

[0064] Step S250: Determine the groups based on block size and jump relationships. The purpose of this step is to divide multiple blocks into multiple groups. Details of step S250 will be provided below. Figures 8-9 illustrate.

[0065] Step S260: Determine whether the jump instruction is a first-type jump instruction (e.g., a short jump instruction) or a second-type jump instruction (e.g., a long jump instruction) based on its relationship with the group. By dividing the block into multiple groups, this application can more accurately classify short and long jump instructions to avoid errors during execution. Step S260 will be explained below. Figure 11 illustrate.

[0066] Figure 5 This pertains to the details of step S210, including steps S510 to S550. Please also refer to the following explanations. Figure 3 and Figure 4 .

[0067] Step S510: Read an instruction.

[0068] Step S520: Determine whether the instruction is a jump instruction or the destination of a jump instruction. If not, proceed to step S510 to read the next instruction; if so, proceed to step S530.

[0069] Step S530: Set the block boundary BB to determine the block. More specifically, if the instruction is a jump instruction, then step S530 sets the block boundary BB after the instruction (e.g., Figure 3 Between instructions INST5 and INST6, and between instructions INST11 and INST12; if the instruction is the destination of a jump instruction, then step S530 sets the block boundary BB before the instruction (e.g., Figure 3 (between instructions INST5 and INST6, and between instructions INST8 and INST9).

[0070] Step S540: Determine if there are still any instructions to be processed in the process. If yes, proceed to step S510 to read the next instruction; otherwise, proceed to step S550.

[0071] Step S550: Set the block boundary BB, then end.

[0072] by Figure 3 For example, Figure 5 The method splits process 310 at instruction INST5 (i.e., sets the block boundary BB) to generate block BLK1. Similarly, since instructions INST9 and INST11 are the destination and jump instructions, respectively, the block boundary BB is set before instruction INST9 and after instruction INST11, thus generating blocks BLK2 and BLK3 respectively. The block boundary BB is also set at the end of process 310 to generate block BLK4.

[0073] Figure 6 This is a flowchart of the instruction compression method provided in the embodiments of this application. Figure 7 This is a schematic diagram of the instruction structure before compression and the instruction structure after compression provided in the embodiments of this application. Figure 7As shown, the instructions INST_k-1 and INST_k are uncompressed instructions (they are consecutive instructions, with INST_k-1 preceding INST_k). Instructions INST_k-1, INST_k, and the compressed instruction INST_k' all include a header HD and at least one parameter (e.g., instructions INST_k-1 and INST_k each include n parameters P1 to Pn, while the compressed instruction INST_k' includes one parameter P1'). In some embodiments, the header HD and each parameter are each a word. The header HD includes a flag InstFlag and a reference value HDLen. The flag InstFlag records the hardware circuit to which the instruction belongs. For uncompressed instructions, the reference value HDLen records the number of parameters (e.g., the reference value HDLen for instructions INST_k-1 and INST_k is n); for the compressed instruction INST_k', the reference value HDLen is a preset value (e.g., 0). Figure 6 The compression method is based on blocks and includes the following steps.

[0074] Step S610: Read one instruction from a block.

[0075] Step S620: Determine if the instruction is the first instruction of the block. If yes, proceed to step S610 to read the next instruction of the block; otherwise, proceed to step S630. The first instruction of a block is not compressed (because there is no previous instruction as a reference).

[0076] Step S630: Compare this instruction with the previous instruction to identify any dissimilar parameters in this instruction that differ from the previous instruction. Figure 7 For example, since the parameters P2 to Pn of the instruction INST_k-1 are equal to the parameters P2 to Pn of the instruction INST_k respectively, and only parameter P1 is not equal to parameter P1', the dissimilar parameter found in step S630 is parameter P1'.

[0077] Step S640: Set the reference value HDLen of the header HD of the compressed instruction to a preset value, the purpose of which is to mark the compressed instruction.

[0078] Step S650: Set the first parameter of the compressed instruction to the number of dissimilar parameters Nd. Figure 7 For example, since the number of different parameters Nd between the instruction INST_k-1 and the instruction INST_k is 1, this step sets the first parameter of the compressed instruction INST_k' to 1 (i.e., "Len=1").

[0079] Step S660: Set the other parameters of the compressed instruction to the same or multiple different parameters. This step sets the 2nd to xth (x = 1 + Nd) parameters of the compressed instruction INST_k' to the different parameters obtained in step S630. Figure 7 For example, since the only difference between the instruction INST_k-1 and the instruction INST_k is parameter P1' (i.e., the number of different parameters Nd is 1), this step sets the second parameter of the compressed instruction INST_k' to parameter P1'. After step S660, the compressed instruction INST_k' can be obtained.

[0080] Step S670: Determine if there are any pending instructions for this block. If yes, proceed to step S610 to read the next instruction for the block; otherwise, end the process. Figure 6 The method (step S680).

[0081] Figure 8 and Figure 9 yes Figure 2 Details of step S250. Step S250 includes two main steps: first, determining the group based on the block size ( Figure 8 Then adjust the groups according to the redirection relationship. Figure 9 Please refer to the following instructions as well. Figure 10A and Figure 10B , Figure 10A and Figure 10B This is a schematic diagram provided in an embodiment of the present application, illustrating the division of multiple blocks of a process into multiple groups, corresponding to... Figure 3 The process is 310. Figure 8 It includes the following steps.

[0082] Step S810: Select a block and update the size of the current group based on the size of that block. The size of a group is the sum of the sizes of all the blocks it contains. This step involves adding the size of the block to the size of the current group to update the current group size. Figure 10A For example, assuming the current group only includes block BLK1, the selected block is block BLK2, and the updated size of the current group is the sum of the sizes of block BLK1 and block BLK2.

[0083] Step S820: Determine whether the size of the current group is greater than a threshold value. In some embodiments, the threshold value may be the size of the instruction temporary storage area of ​​memory 112. If the determination result of step S820 is negative, then proceed to step S830; otherwise, proceed to steps S840 and S850.

[0084] Step S830: Set the block as part of the current group. The result of step S820 being negative indicates that adding the selected block to the current group will not make the current group too large (greater than the threshold value), so step S830 sets the block as part of the current group. Continuing the example, assuming the sum of the sizes of block BLK1 and block BLK2 does not exceed the threshold value SR, then in this step, block BLK2 is set to the same group as block BLK1.

[0085] Step S840: Set the block as part of a new group. The result of step S820 indicates that adding the selected block to the current group would make the current group too large (greater than the threshold value). Therefore, step S840 determines the current group (i.e., sets the group boundary GB), and then sets the selected block as part of a new group (at this point, the new group only includes this block). Figure 10A For example, when the selected block is block BLK3, in step S840, the group boundary GB will be set first (that is, group GRP1 will be determined), and then group GRP2 will be established (at this time, group GRP2 only includes block BLK3 and has not yet been determined).

[0086] Step S850: Set the size of the new group to the size of the block. Continuing the previous example, since group GRP2 now only includes block BLK3, the size of the new group is equal to the size of block BLK3. Note that the new group becomes the current group in the next round (i.e., when step S810 is executed again).

[0087] Step S860: Determine if there are still blocks to be processed. If yes, proceed to step S810 to select the next block; otherwise, proceed to step S870.

[0088] Step S870: Set group boundaries, then end. Figure 10A For example, when the selected block is block BLK4, the judgment in step S860 is negative, and then step S870 sets the group boundary GB after block BLK4 to determine group GRP2.

[0089] Please refer to Figure 10A , Figure 8 After the method ends, Figure 4 The four blocks are divided into two groups. However, because there is a jump instruction destination (i.e., the destination of instruction INST11 is block BLK2) in the middle of group GRP1 (i.e., between the first and last blocks of a group), this will cause a jump error during process execution, so further adjustments are necessary. Figure 9 The method is to adjust the group. Figure 9 It includes the following steps.

[0090] Step S910: Select a group.

[0091] Step S920: Select a block of the group.

[0092] Step S930: Determine if the following conditions are met: the block is not the first block of the group, and the block is the destination of a jump instruction from another group. Figure 10A For example, if steps S910 and S920 select group GRP1 and block BLK1 respectively, then the judgment result of step S830 is no (because block BLK1 is the first block of group GRP1); if steps S910 and S920 select group GRP1 and block BLK2 respectively, then the judgment result of step S830 is yes (because block BLK2 is not the first block of group GRP1, and is the destination of instruction INST11).

[0093] Step S940: Determine if there are still blocks to be processed in the group. If yes, proceed to step S920 to select the next block for the group; otherwise, proceed to step S960.

[0094] Step S950: Set group boundary GB, that is, divide the current group into 2 groups. Figure 10A and Figure 10B For example, in step S950, the group boundary GB is set before block BLK2 (i.e., the destination of instruction INST11), so that the original group GRP1 becomes group GRP1 and group GRP3.

[0095] Step S960: Determine if there are still groups to be processed. If yes, proceed to step S910 to select the next group; otherwise, end the process. Figure 9 The method (step S970).

[0096] Figure 11 yes Figure 2 The details of step S260 include the following steps.

[0097] Step S1110: Select a jump instruction. Figure 10B For example, this step will select either the INST5 instruction or the INST11 instruction.

[0098] Step S1120: Determine whether the destination of the jump instruction is within the group to which the jump instruction belongs. Figure 10B For example, for instruction INST5, since its destination (block BLK3) is not within the group to which instruction INST5 belongs (i.e., group GRP1), the result of step S1120 is negative. Similarly, for instruction INST11, the result of step S1120 is also negative.

[0099] Step S1130: Set the jump instruction to a long jump instruction.

[0100] Step S1140: Set the jump instruction to a short jump instruction.

[0101] Step S1150: Determine if there are still jump instructions. If yes, proceed to step S1110 to select the next jump instruction; otherwise, end. Figure 11 The method (step S1160).

[0102] exist Figure 10B In the examples, both INST5 and INST11 are inter-group jump instructions (long jump instructions). Please refer to [link / reference]. Figure 12 , Figure 12 This is a schematic diagram of group division provided in an embodiment of this application. For example... Figure 12 As shown, group GRP1 includes blocks BLK1, BLK2, and BLK3, while group GRP2 only includes block BLK4. Since the jump instruction INST_n is in group GRP1 and its destination (block BLK3) is also in group GRP1, the jump instruction INST_n is an intra-group jump instruction; therefore, the jump instruction INST_n will... Figure 11 In the method, it is determined to be a short jump instruction (that is, step S1120 determines it to be yes).

[0103] Figure 13 This is a flowchart of the instruction decompression method provided in the embodiments of this application. Figure 13 Depend on Figure 1 The instruction decompression circuit (i.e., instruction decompression circuit 122, instruction decompression circuit 132, or instruction decompression circuit 142) of the hardware circuit (i.e., direct memory access 120, vector circuit 130, or convolution circuit 140) is executed. Figure 13 It includes the following steps.

[0104] Step S1310: Read or receive an instruction, for example, read an instruction from memory, or receive an instruction distributed by the instruction dispatch circuit 116.

[0105] Step S1320: Determine whether the reference value HDLen of the header HD of the instruction is a preset value. If not (meaning the instruction is not a compressed instruction), then execute step S1330; if yes (meaning the instruction is a compressed instruction), then execute steps S1340 and S1350.

[0106] Step S1330: Set the corresponding parameters of the hardware circuit using all the parameters of this instruction (e.g., set the temporary value of the register). See also... Figure 14 , Figure 14This is a schematic diagram of the hardware circuit of this application executing uncompressed instructions. Assuming that before executing the uncompressed instruction INST_y (including five parameters: P1', P2', P3', P4', and P5'), the hardware circuit's register group REGP stores the five parameters P1, P2, P3, P4, and P5 (the temporary values ​​of registers REG1, REG2, REG3, REG4, and REG5, respectively), then after the hardware circuit executes the instruction INST_y, the register group REGP stores these five parameters of the instruction INST_y (e.g., ...). Figure 14 (As shown in the temporary register group REGP on the right). In other words, the purpose of step S1330 is to set the parameters of the hardware circuit with the parameters of the instruction INST_y. After the parameters of the hardware circuit are set, the hardware circuit (more specifically, the computing circuit of the hardware circuit) can execute the instruction (step S1360).

[0107] Step S1340: Read the first parameter of the instruction to obtain the number of dissimilar parameters Nd. See also... Figure 15 , Figure 15 This is a schematic diagram of the hardware circuit executing compression instructions according to this application. Figure 15 The instruction INST_z in the code is a compressed instruction with 2 distinct parameters Nd (i.e., "Len=2").

[0108] Step S1350: Set the corresponding parameters of the hardware circuit using the 2nd to Nd+1th parameters of this instruction (e.g., set the temporary value of the register). Figure 15 In the example, the instruction decompression circuit obtains the parameters P1' and P2' of the compressed instruction INST_z based on the number of different parameters Nd, and then sets the registers REG1 and REG2 with parameters P1' and P2' respectively. The purpose of step S1350 is to set the parameters of the hardware circuit with the parameters of the compressed instruction INST_z. After the parameters of the hardware circuit are set, the hardware circuit can execute the instruction (step S1360).

[0109] In summary, this application reduces the space required for the instruction register (i.e., reduces the size of memory 112) by compressing instructions, thereby saving costs. Furthermore, because of instruction compression, this application can also reduce the number of long jump instructions, thus improving the execution efficiency of the process.

[0110] Although the foregoing embodiments use variable-length instructions and intelligent processors as examples, this is not a limitation of this application. Those skilled in the art can appropriately apply this application to other types of instruction and control circuits based on the disclosure of this application.

[0111] The instruction compression method, instruction decompression method, and process compression method provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the methods and core ideas of this application; at the same time, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for decompressing instructions, characterized in that, Applied to a hardware circuit, the hardware circuit decompresses and executes an instruction, the instruction including a header, the header including a reference value, the method comprising: When the reference value of the instruction is a preset value, a first parameter of the instruction is read to obtain a number of dissimilar parameters, wherein the value of the first parameter represents the number of dissimilar parameters; and Multiple corresponding dissimilar parameters of the hardware circuit are set by multiple second parameters of the instruction, wherein the number of the multiple second parameters is equal to the number of dissimilar parameters.

2. The method as described in claim 1, characterized in that, The method further includes: When the reference value of the instruction is not the preset value, the plurality of corresponding parameters of the hardware circuit are set with all the parameters of the instruction.

3. The method as described in claim 1, characterized in that, The hardware circuit includes multiple registers, and the multiple corresponding parameters are the temporary values ​​stored in the multiple registers.

4. The method as described in claim 1, characterized in that, When the number of dissimilar parameters is N, the plurality of second parameters are the second to the (N+1)th parameters of the instruction.

5. The method as described in claim 1, characterized in that, The instruction is a variable-length instruction.

6. A method for compressing instructions, characterized in that, A method for compressing an instruction to produce a compressed instruction, the instruction including a header and multiple parameters, the header including a reference value, the method comprising: Compare the instruction with a previous instruction to identify multiple dissimilar parameters in the instruction that differ from the previous instruction; Set the reference value of the compressed instruction to a preset value; Set a target parameter of the compressed instruction to the number of the plurality of dissimilar parameters; and Set the other parameters of the compressed instruction to the plurality of dissimilar parameters.

7. The method as described in claim 6, characterized in that, The method is applied to a hardware circuit that executes a process, wherein the instruction and the preceding instruction are consecutive instructions of the process, and the instruction is later than the preceding instruction.

8. The method as described in claim 7, characterized in that, The process includes multiple blocks, each block includes multiple instructions, the instructions and the previous instruction belong to the same target block among the multiple blocks, and the instructions are not the first instructions of the target block.

9. The method as described in claim 6, characterized in that, The target parameter is the first parameter of the compressed instruction.

10. The method as described in claim 6, characterized in that, The instruction is a variable-length instruction.

11. A process compression method, characterized in that, The method for compressing a process, the process including a jump instruction, includes: (A) The process is divided into multiple blocks according to a position of the jump instruction in the process and a destination of the jump instruction; (B) Record the jump relationship between the multiple blocks; (C) Perform instruction compression on the plurality of blocks; (D) Recalculate a jump address for the jump instruction based on the jump relationship; (E) Determine multiple groups based on the size of the multiple blocks and the jump relationships; and (F) Determine whether the jump instruction is a first type of jump instruction or a second type of jump instruction based on the relationship between the jump instruction and the plurality of groups.

12. The method as described in claim 11, characterized in that, The process also includes multiple instructions, and step (A) includes: Read one of the plurality of instructions; and When the instruction to be read is the jump instruction or the destination of the jump instruction, a block boundary is set.

13. The method as described in claim 12, characterized in that, The multiple instructions are multiple variable-length instructions.

14. The method as described in claim 11, characterized in that, Step (E) includes: Select a block; Update the size of a current group based on the size of the block; When the size of the current group exceeds a threshold value, the block is set as part of a new group; and When the size of the current group is not greater than the threshold value, the block is set as part of the current group.

15. The method as described in claim 14, characterized in that, The step (E) further includes: When the size of the current group is greater than the threshold value, the size of the new group is set to the size of the block.

16. The method as described in claim 14, characterized in that, The jump instruction is a first jump instruction, the destination is a first destination, and step (E) further includes: Select the first group; Select a target block of the first group; and When the target block is not the first block of the first group, and the target block is the second destination of a second jump instruction of a second group, a group boundary is set.

17. The method as described in claim 11, characterized in that, Step (F) includes: Select the jump instruction; When the destination of the jump instruction is located within a target group to which the jump instruction belongs, the jump instruction is set as a short jump instruction.

18. The method as described in claim 17, characterized in that, The step (F) further includes: When the destination of the jump instruction is not located within the target group, the jump instruction is set as a long jump instruction; The jump range of the short jump instruction is smaller than that of the long jump instruction.

Images