A method for fast variable cacheline switching

Abstract

The present invention proposes a method for quickly implementing variable cacheline switching, which solves the problem that conventional cache designs have a mixture of low locality (such as control logic) and high locality (such as data flow logic), resulting in reduced access efficiency. Its main technical solutions include: S1, taking the original cacheline size of the cache as the benchmark unit, merging consecutive benchmark cachelines to form a new cacheline, the size of which is recorded as Xn gear, indicating that the cacheline of this gear is the size of n benchmark cachelines, with n being a minimum of 1 and a maximum of all benchmark cachelines in the cache; S2, the tag flags corresponding to the benchmark cacheline size in the cache are all retained. When a hit is missed, the X1 gear only updates and replaces one benchmark cacheline, while the Xn gear updates and replaces n benchmark cachelines; that is, the switching of the Xn gear is changed from replacing one to replacing n benchmark cachelines by continuing to use and amplifying the original replacement logic processing unit; S3, the switching of the Xn gear sets the switching control register through the configuration interface, and the internal switching selection logic is controlled by the register. The switching process occurs during any cache request processing interval.

Description

Technical Field

[0001] The present invention relates to the technical field of cache design, and in particular to a method for quickly implementing variable cacheline switching. Background Art

[0002] Cache design is used to improve the efficiency of data access. Its theoretical basis is data space (continuous data near the data that has just been used may be used in the near future) and time continuity (data that has just been used may be used again in the near future). A cache design is inserted between the request end and the storage. According to the locality design algorithm, a part of the data is selected from the large-capacity storage (slow access speed, responding to a request in tens to hundreds of cycles, such as DDR) to be copied to the small-capacity storage in the cache (fast access speed, responding to a request in several cycles, such as SRAM). If the requested data happens to be in the cache, it can be responded to quickly. Otherwise, it will be taken from the large storage. In theory, the better the request locality, the closer the data response rate is to the response efficiency of the small cache storage, thereby greatly improving the memory access efficiency.

[0003] The general principle of cache design is explained as follows: first, the entire DDR is divided into smaller continuous data units (denoted as cache lines). Each cache line stores a specific valid part of the corresponding address as a unique identifier (denoted as a tag) to distinguish the cache line from other cache lines. The entire cache is composed of several cache lines. When the cache receives a read or write request, it determines whether the requested data is in a certain cache line based on the tag (if it is, it is denoted as a hit, if not, it is denoted as a miss). If it is a hit, the corresponding read or write request is executed. If it is a miss, the DDR is requested to contain the cache line corresponding to the miss request, which is used to replace a cache line determined by the replacement algorithm. In this way, under the joint control of the request and the replacement algorithm, several cache lines related to the most recent request are always retained in the cache. From the principle of locality, it can be seen that future accesses are likely to exist in a certain cache line in the cache. The response rate of these requests is accelerated from the DDR response level to the cache response level, thereby achieving the purpose of accelerating memory access.

[0004] A cacheline consists of several consecutive data (referred to as data). The size of a cacheline is closely related to locality. The better the locality, the larger the cacheline. Conversely, the smaller the cacheline, the smaller the cacheline. For example, if the address is accessed consecutively, the data in the cacheline is used continuously, and a large cacheline will achieve a higher hit rate. In loop logic, some data is used repeatedly, and the jump logic address jumps significantly before being continuous in a small range. This is suitable for a small cacheline to avoid excessive useless data in the large cacheline, which will lead to a lower hit rate.

[0005] In actual designs, control logic requests are changeable and weak in locality, making them suitable for small cachelines. Data processing logic requests are regular and strong in locality, making them suitable for large cachelines. Some designs adopt separate processing methods, but many designs are still limited by implementation resources, power consumption, and difficulty in splitting control data flows, requiring a single cache to handle access requests with a mixture of strong and weak locality. Summary of the Invention

[0006] The present invention proposes a variable cacheline switching technology that can dynamically switch the cacheline size during operation, thereby improving the hit rate under requests with different localities, allowing more request response cycles to be increased to the cache response level, thereby achieving the purpose of improving the access efficiency of mixed requests with strong and weak localities.

[0007] To solve the above technical problems, the present invention adopts a technical solution: a method for rapidly implementing variable cacheline switching, characterized by comprising the following steps:

[0008] S1. Using the original cacheline size as the base unit, merge consecutive base cachelines to form a new cacheline. The size is recorded as Xn, which means that the cacheline of this cacheline is the size of n base cachelines. The minimum value of n is 1 and the maximum value is all base cachelines in the cache.

[0009] S2. All cache tag flags corresponding to the base cacheline size are retained. The original cache processing request is equivalent to working in the X1 file. When the cache request hits, the X1 and Xn files remain consistent. When it misses, the X1 file only updates and replaces one base cacheline. The switching of the Xn file is done by using the original replacement logic processing unit, changing from replacing one to replacing n base cachelines.

[0010] The S3 and Xn gear switching is performed by setting the switching control register through the configuration interface. The internal switching selection logic is controlled by this register. The entire switching process is in any cache request processing interval.

[0011] Furthermore, in step S1, the reference cacheline is divided into consecutive exponential numbers of 2.

[0012] Furthermore, the tag in step S2 is a marker of the only valid information of the cacheline and will not be added.

[0013] Furthermore, in step S2, the original hit judgment logic and subsequent processing logic after a hit are retained; when a miss occurs, the original replacement logic processing unit is enlarged, changing from replacing 1 to replacing n base cachelines.

[0014] Compared with the existing technology, the beneficial effects of the present invention include: by completing the modification of two nodes, the internal flag and the replacement request sending logic, and adding the control switching logic, the dynamic switching of the cacheline can be realized, thereby improving the original cache access efficiency. The overall implementation has the characteristics of low cost, low complexity and good improvement effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The disclosure of the present invention is illustrated with reference to the accompanying drawings. It should be understood that the drawings are for illustrative purposes only and are not intended to limit the scope of protection of the present invention. In the accompanying drawings, the same reference numerals are used to refer to the same components. Among them:

[0016] Figure 1 This is a flow chart of the conventional cache principle of a preferred embodiment of the present invention;

[0017] Figure 2 This is a schematic diagram of a conventional cache internal judgment process in a preferred embodiment of the present invention;

[0018] Figure 3 A simplified diagram of conventional cache internal judgment according to a preferred embodiment of the present invention;

[0019] Figure 4 A comparison diagram of a cache design according to a preferred embodiment of the present invention and a conventional design;

[0020] Figure 5 This is a flow chart of internal judgment of cache design in a preferred embodiment of the present invention;

[0021] Figure 6 A flowchart of cache design replacement logic expansion in a preferred embodiment of the present invention;

[0022] Figure 7Flowchart of the cache design replacement logic correction process of a preferred embodiment of the present invention

[0023] Figure 8 A simplified flowchart of cache design replacement logic for a preferred embodiment of the present invention;

[0024] Figure 9 A flowchart of the cache design replacement logic synchronization process of a preferred embodiment of the present invention;

[0025] Figure 10 This is an overall flow chart of cache design according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0026] It is easy to understand that according to the technical solution of the present invention, without changing the essential spirit of the present invention, a person skilled in the art can propose a variety of interchangeable structural modes and implementation modes. Therefore, the following specific embodiments and drawings are only exemplary descriptions of the technical solution of the present invention and should not be regarded as the entire invention or as a limitation or restriction of the technical solution of the present invention.

[0027] According to one embodiment of the present invention, Figures 1-10 Shown.

[0028] like Figure 1-Figure 2 As shown in the figure, a common cache design includes the following parts:

[0029] Storage mem (sram): used to store data copied from the main storage. It is divided into several storage spaces, each of which is recorded as a cacheline.

[0030] Internal flag: records the relevant information of each cacheline location in mem;

[0031] Among them, vld: cacheline position validity flag, which corresponds to cacheline one by one. When a cacheline position is put into data, it becomes valid (1 is valid, 0 is invalid);

[0032] Tag: The location of the data stored at the cacheline location in the main storage. The specific content comes from some bits in the corresponding request address.

[0033] lru: cacheline location read and write access record, recorded once each time it is read / written;

[0034] Hit / miss determination: Compare some bits of the request address (the same position as when saving the tag) with the tags corresponding to all valid cacheline positions. If they match, it is a hit; otherwise, it is a miss.

[0035] Replacement request sending logic: When a request misses, the current request is aligned and adjusted according to the cacheline size and sent to the primary storage to request the cacheline data block containing the missed request data;

[0036] Mem read and write requests: Summarizes and generates read and write requests for cache internal mem in different situations, including read / write on hit, replacement write on miss, and write / read after replacement on miss.

[0037] It can be seen from this that Figure 3 As shown (triangle numbers and Figure 2 The entire cache process consists of two processing steps: hit and miss:

[0038] For the hit process, first compare the request address and the internal flag to determine whether it is a hit or not. If it is a hit, the mem read and write request is generated by the mem read and write request logic, and mem then executes the read and write request (read request returns read data, write request only writes mem). The above process execution process updates the internal flag at the same time.

[0039] For the miss process, the request address and the internal flag are first compared to determine whether it is a hit or not. If it is a miss, a logical request is sent through a replacement request to the cacheline data block containing the miss data. The cacheline data block returns and ends to generate a mem write request. After the write is completed, a mem read request is generated to read the miss data. Mem executes the read and write requests. The above process is executed and the internal flag is updated at the same time.

[0040] The replacement described above reflects the locality laws that exist in cache operation, including temporal locality (data that has just been used is likely to be used again in the near future) and spatial locality (data adjacent to data that has just been used is likely to be used in the near future). The first cache access is always a miss, and the cacheline data block containing the requested data is selected, that is, several data adjacent to the data are selected while retaining the requested data itself, utilizing both types of locality. The probability that the subsequently accessed data happens to be the previously moved cacheline data is proportional to the strength of the locality. The stronger the locality, the more data in the cacheline is accessed and the less invalid data is accessed.

[0041] The better the locality in the design, the larger the cacheline should be, reducing the number of times data is copied and moved from the main storage (in addition to the data transmission time per cycle, the main storage access also includes the time to interpret and process the request, and the latter accounts for the majority of the entire request response time of the main storage). Otherwise, a small cacheline is needed. This rule is very common in practice. For example, in continuous address access, data in the cacheline is used continuously, locality is good, and a large cacheline will achieve a higher hit rate; in loop logic, some data is used repeatedly, and the jump logic address jumps significantly and then continues in a small range. The data locality is weak and is suitable for a small cacheline. This avoids too much useless data in the large cacheline, which takes up precious small storage space and reduces the hit rate.

[0042] In this regard, the present application implements a switchable cacheline function by identifying and modifying key nodes based on a conventional fixed cacheline cache design, thereby improving the cache's memory access efficiency when facing requests with local changes.

[0043] like Figure 4 As shown, the core principle is to use the cacheline size of the regular cache as the benchmark, which is counted as X1 gear; merge two X1-grade cachelines as one cacheline, that is, when a replacement occurs, request a data block of 2 times the size of the X1 cacheline to update the position of the merged two cachelines, which is recorded as X2 gear, and so on, there are X4, X8,.. until Xn gear, n increases exponentially by 2 to a maximum of the entire mem size; switching different gears in this way means that the size of the cacheline is within the range of 1 to n times the size of the X1-grade cacheline. When the locality is good, n is cut to a larger value, making full use of the locality to reduce the corresponding overhead of multiple requests. On the contrary, when the locality is poor, n is cut to a smaller value to avoid the overhead caused by retrieving too much invalid data.

[0044] like Figure 5-Figure 6 As shown in the figure, the implementation details of the modification to cacheline switchability are as follows: In the cache design, there is always a one-to-one correspondence between cacheline and corresponding flag signal. The flag signal corresponding to each cacheline in the X1 gear is the basic unit. The Xn gear is to update the flag signals corresponding to n cachelines at the same time, so that n X1 cachelines are equivalent to updating one Xn cacheline.

[0045] For the replacement logic: it is used to generate the cacheline object to be replaced when a miss occurs (the X1 file points to a certain cacheline, and the Xn version extends to n caches); the specific implementation is to record the read and write order history of the cacheline, and then decide the replacement object based on some algorithms. There are various algorithms here. Take the common least recently used algorithm (Least Recently Used, abbreviated LRU) as an example. Suppose there are 8 cachelines in the X1 file cache, numbered 0 to 7 in sequence, and assuming that the access order is 0 to 7, then number 0 is the earliest used cacheline, also called the least recently used cacheline. From the principle of locality, it has the lowest probability of being accessed again, so it is the object to be replaced; the specific implementation is to assign a weight value to each cacheline, and adjust the weight according to the more recent the access, the higher the weight. The cacheline with the lowest weight at the same time is the object to be replaced in the future.

[0046] Regarding the cacheline valid flag (vld): Assuming there are eight cachelines in the X1 cache, one of the eight is set to 1 when an update occurs, indicating valid. When switching to the Xn cache, the original control signal is expanded from 1 to n cachelines simultaneously under the control of the switch control command (from the switch control logic). An example of the expansion method is as follows: Assuming the eight cachelines in the X1 cache are numbered 0 through 8, to switch to the X2 cache, {0,1}, {2,3}, {4,5}, and {6,7} are merged to obtain four X2 cachelines. The merging adheres to the principle of consecutive alignment, meaning combinations such as {1,2} or {3,5} cannot occur. The original control signal generation logic still follows the X1 cache design, fixedly pointing to a number between 0 and 7. A simple inspection of the grouping reveals the corresponding X2 cacheline number. For example, the original signal pointing to 6 corresponds to X2 cachelines {6,7}, indicating that when an update occurs, the X2 cacheline must simultaneously set the vld values corresponding to cachelines 6 and 7 to 1 to indicate that the data in the corresponding cacheline is valid.

[0047] The specific implementation method of the corresponding grouping is illustrated by an example. The original pointing number is 3. When switching to the X2 gear, the lowest 1 position of its binary 11 is set to 0 to obtain 10 (decimal 2), which is the first number of the X2 gear corresponding combination {2,3}, and the two consecutive numbers starting from 2 are all the numbers of the combination it belongs to; when switching to the X4 gear, the lowest 2 positions of its binary 11 are set to 0 to obtain 00 (decimal 0), which is the first number of the X4 gear corresponding combination {0,1,2,3}, and the four consecutive numbers starting from 0 are all the numbers of the combination it belongs to; the generalization and summary is that switching the Xn gear is to point the original signal to the cacheline number binary low x = log2 (n) position 0 to obtain the first number of the Xn gear cacheline combination, and the subsequent n-1 consecutive numbers are the remaining numbers.

[0048] Cacheline tags in main storage: In X1 mode, when an update occurs, some bits of the cacheline's corresponding address are retained and stored in a corresponding tag location. Switching to Xn mode means that n tag locations are updated simultaneously. The expansion method from 1 to n is consistent with VLD processing. The tag storage value requires alignment correction and incremental expansion.

[0049] Alignment correction: Assume that the switch is to X2 gear. The tags corresponding to the two X1 cachelines are recorded as tag_A and tag_B in order. In practice, the corresponding tag value received by the request may be tag_B. In this case, tag_B needs to be corrected to tag_A (because the replacement request logic will first request the cacheline corresponding to tag_A). The alignment method follows the principle of sequential continuous alignment because of the extension. Refer to the above low position 0 method for processing and implementation;

[0050] Incremental expansion, alignment expansion and correction of the first updated tag. When updating multiple tags, add 1 to the first tag to get the tag value corresponding to the subsequent cacheline;

[0051] like Figure 7 As shown, the replacement request sending logic is: when the internal switching command is valid, the original read and write request is corrected according to the lru output extended replacement object to obtain a replacement request and send it to the main storage. The correction method refers to the aforementioned principle.

[0052] Switching control logic: First, the input switching control signal is synchronously processed to avoid possible asynchronous sampling and improve design compatibility. Specifically, it is implemented by switching two signals: a valid signal and a switching code. The former is a single-bit signal that marks the validity of the switching code. After the signal is valid, it needs to wait for the cache to receive and feedback before it ends. This ensures that the switching code received by the cache is reliable. The switching code is a digital code corresponding to different cacheline size gears.

[0053] The reason for switching protection after synchronization is that during cache read and write processing, its internal flag signal directly affects the execution action. Therefore, it is necessary to wait until the cache is in the intermission period after executing the request before switching, and no new requests can be received before the switching is completed. After the switching protection, an internal switching command for directing the switching logic is generated;

[0054] In summary, after completing the modifications to the internal flag and replacement request sending logic nodes, and adding the control switching logic, the cacheline switchable function can be implemented.

[0055] The idea of implementing a large cacheline by splicing small cachelines is to avoid the problems caused by tedious alignment when switching cachelines. Based on this principle, the implementation method based on only two control node corrections is simple and easy to implement. The logic cost is one adder with the same bit width as the tag, no more than 20 registers, and several combinational logic units.

[0056] The cacheline size tends to an optimal value during continuous accesses with similar locality characteristics. This countermeasure can flexibly provide multiple switching levels, allowing the cacheline setting value to approach the optimal value as much as possible, thereby achieving better switching efficiency. The detailed derivation process is as follows.

[0057] Read operations are analyzed. As shown in the following figure, the request response is divided into three stages: cache return to the requesting end, cache replacement write, and storage return to the cache.

[0058] The cache returns to the requesting end - indicating that the request is directly hit or the replacement operation is completed after the request is missed. This time is usually fixed at 1-2 cycles, which is recorded here as A;

[0059] Cache replacement write - indicates the time it takes to write data to the cache during the replacement process. Each data return requires one cycle, and the total time is equal to the number of requested data items that can be accommodated in the cache line. For example, if the requested data is 32 bytes and the cache line is 256 bytes, the cache line can accommodate 256 / 32 = 8 requested data items.

[0060] Store return to cache - represents the time from when the storage receives the request to when the data is returned. This time usually varies from tens to hundreds of cycles and is denoted as B here.

[0061] Based on this, the cache request response is shown in the following table:

[0062]

[0063] From this analysis, we can see that in the case of a hit, there is no replacement operation, and the request response cycle is always A, regardless of the cacheline size; in the case of a miss, the average request response cycle is A+B+m, where A and B are constant;

[0064] Assuming there are X requests in total, and an average of n data items are used in each cacheline (the requesting application or program determines the distribution of the data in main memory. After the main memory is split according to the cachelines, the average number of items used in each cacheline is calculated), the average request response period can be expressed as (X / n*(A+B+m)+(XX / n)*A) / X=A+B / n+m / n, where A and B are constant and n is determined by the locality of the requesting data. The optimal result is achieved when m / n approaches 1. The flexibility of this scheme in switching gears allows the selection of m values close to n, thereby achieving a better average request response.

[0065] The technical scope of the present invention is not limited to the contents of the above description. Those skilled in the art can make various deformations and modifications to the above embodiments without departing from the technical concept of the present invention, and these deformations and modifications should all fall within the protection scope of the present invention.

Claims

1. A method for rapidly implementing variable cacheline switching, characterized in that The steps include: S1. Using the original cacheline size as the base unit, merge consecutive base cachelines to form a new cacheline. The size is recorded as Xn, which means that the cacheline of this cacheline is the size of n base cachelines. The minimum value of n is 1 and the maximum value is all base cachelines in the cache. S2. All cache tag flags corresponding to the base cacheline size are retained. The original cache processing request is equivalent to working in the X1 file. When the cache request hits, the X1 and Xn files remain consistent. When it misses, the X1 file only updates and replaces one base cacheline. The switching of the Xn file is done by using the original replacement logic processing unit, changing from replacing one to replacing n base cachelines. The S3 and Xn gear switching is performed by setting the switching control register through the configuration interface. The internal switching selection logic is controlled by this register. The entire switching process is in any cache request processing interval.

2. The method for rapidly implementing variable cacheline switching according to claim 1, wherein: In step S1, the reference cacheline is divided into consecutive exponential numbers of 2.

3. The method for rapidly implementing variable cacheline switching according to claim 1, wherein: The tag in step S2 is a mark of the only valid information of the cacheline and will not be added.

4. The method for rapidly implementing variable cacheline switching according to claim 1, wherein: In step S2, the original hit judgment logic and subsequent processing logic after a hit are retained; when a miss occurs, the original replacement logic processing unit is enlarged, changing from replacing 1 to replacing n base cachelines.

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