A wave control system and data transmission method for a multi-array phased subarray antenna

Abstract

This invention discloses a beam control system and data transmission method for a multi-array phased subarray antenna. The system includes multiple phased subarray antenna elements and an SPI bus master device. The phased subarray antenna elements are arranged in a P-row, Q-column array, with odd-numbered and even-numbered columns interleaved. Every four antenna elements form one antenna chip, which is an SPI bus slave device. P and Q are positive integers greater than or equal to 2. The system uses a daisy-chain configuration to control the antenna chips. This invention solves the problem of beam control data transmission when the number of phased subarray elements is large by implementing the SPI communication bus in a daisy-chain manner.

Description

Technical Field

[0001] This invention belongs to the field of phased array antenna beam control design technology, and particularly relates to a multi-array phased subarray antenna beam control system and data transmission method. Background Technology

[0002] A phased array antenna is an array antenna composed of multiple radiating elements connected to phase shifters and amplifiers. Beam scanning can be achieved by controlling the phase of the radiating elements in the array antenna to change the radiation pattern. It is currently widely used in satellite communication, radar, telemetry and control and other fields.

[0003] Phased array antennas can be divided into brick-type phased array antennas and tile-type phased array antennas. Brick-type phased array antennas have simpler design and manufacturing processes, but they have high integration density, large vertical dimensions, and higher costs. Tile-type phased array antennas, on the other hand, have high integration density, small vertical dimensions, short heat dissipation paths, and relatively low costs, and are gradually becoming a new trend in phased array antenna development. However, the design and implementation of tile-type phased array antennas are also more challenging, involving the arrangement of components and circuits within a single layer, signal distribution between layers, and antenna fabrication processes, among other things.

[0004] Phased array antennas typically consist of multiple phased array subarrays joined together to form a single antenna. This invention will use a single phased array subarray as an example for explanation. When the number of elements in the phased array subarray is small, its beam control design generally employs a one-to-one direct control of the radiating elements in the array antenna using an SPI bus with the same number of elements as the number of subarray elements to achieve beam scanning. However, when the phased array subarray has a large number of elements, the one-to-one direct control method using the SPI bus poses significant implementation difficulties for FPGA I / O resources, circuit signal arrangement, and fabrication.

[0005] Existing patents, such as the invention patent with application number 201911008814.9 entitled "Data Transmission Method of Row-Column Matrix Beam Control System Based on Parallel SPI Bus," disclose a beam control method using group control and time-division data input. However, each subarray of its phased array antenna has only 64 elements, which still falls under the category of a small number of subarray elements. When the phased array antenna has hundreds or even thousands of elements, this patent's method is unsuitable for situations with a large number of subarray elements. In such cases, significant delays occur during data transmission, greatly increasing the probability of data misalignment or packet loss, thus significantly reducing the effectiveness of the phased array antenna. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a wave control system and data transmission method for a multi-array phased subarray antenna, thereby solving the problem of wave control data transmission when the number of phased subarray elements is huge. At the same time, this invention fully considers the design and fabrication issues of the phased subarray antenna PCB board, reducing a large number of digital signal traces, making the PCB board component and circuit layout, signal distribution between layers, and fabrication processes easier to implement.

[0007] The objective of this invention is achieved through the following technical solution:

[0008] A multi-array phased subarray antenna beam control system is disclosed. The system includes multiple phased subarray antenna elements and an SPI bus master device. The phased subarray antenna elements are arranged in a P-row, Q-column array, with odd-numbered and even-numbered columns of elements interleaved. Every four antenna elements form one antenna chip, which is an SPI bus slave device. P and Q are positive integers greater than or equal to 2. The system uses a daisy-chain mode to control the antenna chips.

[0009] Furthermore, the number of array elements is greater than 256.

[0010] Furthermore, the number of antenna chips connected in each daisy chain of the system is calculated based on the estimated time delay of data transmission of the entire beam control system in the daisy chain mode.

[0011] Furthermore, the system divides the entire phased array into M*N / X groups of data according to the number of antenna chips connected in each daisy chain. The SPI bus master device simultaneously outputs SPI communication data to the M*N / X group of SPI bus slave devices, where M*N = P*Q / 4 represents the number of antenna chips and X represents the number of antenna chips connected in each daisy chain.

[0012] Furthermore, the PCB board wiring of the system adopts a tree layout and equal-length line wiring.

[0013] Furthermore, the SPI bus master device includes an FPGA chip.

[0014] On the other hand, the present invention also provides a data transmission method for transmitting data from any of the aforementioned wave control systems, the method comprising:

[0015] Obtain the azimuth and elevation angles of the control antenna beam;

[0016] Calculate the required wave control data based on the azimuth and elevation angles;

[0017] The beam control data is packaged and transmitted to each antenna element in a daisy chain.

[0018] Furthermore, while the antenna unit receives data, it feeds back the current status to the SPI bus master device in a daisy chain and then packages it back to the computer.

[0019] Furthermore, the SPI bus master device uses a shift register method for data transmission.

[0020] Furthermore, the shift register specifically includes:

[0021] The SPI bus master device sends data signals to the first slave device in each SPI communication bus group;

[0022] The first slave device of each SPI communication bus then forwards the data signal sequentially to the last slave device of each SPI communication bus.

[0023] The last slave device in each SPI communication bus group feeds back all feedback data signals from that group of slave devices to the SPI bus master device.

[0024] The beneficial effects of this invention are as follows:

[0025] (1) Compared with the one-to-one direct control array antenna element transmission structure, the daisy chain data transmission structure adopted in this invention can effectively reduce the clock delay of data transmission, reduce the packet loss rate of data transmission, and increase the accuracy of data transmission.

[0026] (2) This invention significantly reduces the resource usage of FPGA chip IO, increases the working efficiency of FPGA and the computing power of its algorithm. Under the above conditions, FPGA chip resources can be transferred to other aspects, which objectively reduces the control time of the entire beam algorithm. In addition, the layout of the PCB board greatly simplifies the placement of electronic components and reduces the area of ​​the entire PCB board.

[0027] (3) The PCB board of this invention adopts a tree-like layout and equal-length wiring, which reduces the delay of SPI communication data from a hardware perspective, and also reduces the digital interference between different data lines, thereby enhancing the accuracy of the data and the anti-interference capability of signals between different layers of the PCB board. It simplifies the PCB manufacturing process, reduces the manufacturing cost, is suitable for large-scale mass production, and greatly improves production capacity. Attached Figure Description

[0028] Figure 1 This is a diagram showing the row and column arrangement of phased subarray antenna elements according to an embodiment of the present invention;

[0029] Figure 2 This is a schematic diagram of the phased subarray antenna chip arrangement in an embodiment of the present invention;

[0030] Figure 3This is a schematic diagram of the daisy chain principle used in an embodiment of the present invention;

[0031] Figure 4 This is a data transmission timing diagram of a single SPI master device according to an embodiment of the present invention;

[0032] Figure 5 This is a schematic diagram of the SPI communication bus of the phased subarray antenna according to an embodiment of the present invention;

[0033] Figure 6 This is a schematic diagram of the phased array antenna chip distribution and SPI serial control data flow in an embodiment of the present invention. Detailed Implementation

[0034] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0035] Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0036] When there are many subarray antenna elements in a phased array, the one-to-one direct control method via SPI bus will cause great difficulty in implementing FPGA I / O resources, circuit signal arrangement and manufacturing.

[0037] When a phased array antenna has hundreds or even thousands of elements, existing technology is not suitable for situations with a large number of phased array elements. In such cases, significant delays occur during data transmission, and data misalignment or packet loss is highly probable, which greatly reduces the effectiveness of the phased array antenna.

[0038] To address the aforementioned technical problems, the following embodiments of a multi-array phased subarray antenna wave control system and data transmission method of the present invention are proposed.

[0039] Example 1

[0040] This embodiment provides a multi-array phased subarray antenna beam control system. The system includes multiple phased subarray antenna elements and an SPI bus master device. The antenna chip is an SPI bus slave device, where P and Q are positive integers greater than or equal to 2. The system uses a daisy-chain mode to control the antenna chip.

[0041] Reference Figure 1 ,like Figure 1 The diagram shown is a row and column arrangement of the phased subarray antenna elements in this embodiment. The phased subarray antenna elements are arranged in a P-row, Q-column array, with odd-numbered and even-numbered columns of elements interleaved.

[0042] For multi-element arrays, the larger the subarray, the more antenna elements it contains. In this embodiment, the P×Q phased array has a total of P×Q (P×Q is greater than 256) antenna elements. This embodiment uses a 16x16 arrangement of phased array antenna chips, with each chip containing 4 antenna elements, as an example. Each SPI daisy-chain bus connects 8 antenna chips, and the phased array is divided into 32 SPI communication buses.

[0043] One antenna chip has four antenna elements, and P×Q antenna elements require M×N (P×Q÷4=M×N) antenna chips. To effectively reduce control lines and improve control efficiency, a daisy-chain mode is used to control the antenna chips, that is, multiple antenna chips are treated as a group link to send control data.

[0044] This embodiment uses a daisy chain pattern to control multiple antenna chips to control the entire subarray elements. Each daisy chain is characterized as follows: the first antenna chip is connected to the control chip, the second antenna chip is connected to the first antenna chip, the third antenna chip is connected to the second antenna chip, the fourth antenna chip is connected to the third antenna chip, and so on until the last antenna chip. The last antenna chip is then connected back to the control chip, forming a chain loop.

[0045] This embodiment estimates the data transmission time delay of the entire beam control system based on the daisy-chain pattern, and then calculates the number of slave devices (phased array antenna chips) controlled by the daisy chain. Each daisy chain can connect up to X antenna chips in series.

[0046] In this embodiment, the SPI master sends data to slave 1, which then sends the data to slave 2, and so on up to slave N. Finally, the feedback data from slave N is returned to the master.

[0047] In this embodiment, the number of SPI communication slave devices in each group is determined to be X based on the maximum number of array elements in the daisy chain. The entire phased array is divided into M*N / X groups of data, and the master device outputs the above-mentioned SPI communication data to the M*N / X groups of slave devices simultaneously.

[0048] The PCB layout and routing features in this embodiment are: tree-structured layout and equal-length line routing, which ensures that the delay of all groups of SPI communication data remains consistent during transmission, reduces mutual interference between each group of SPI data lines, and makes the process easier to manufacture.

[0049] The data transmission lines in this embodiment are characterized by reducing the number of data transmission lines from M*N lines to M*N / X lines, and the required FPGA chip IO resources are also reduced from M*N / X to M*N / X.

[0050] Compared to the one-to-one direct control array antenna element transmission structure, the daisy-chain data transmission structure used in this embodiment can effectively reduce the clock delay of data transmission, reduce the packet loss rate of data transmission, and increase the accuracy of data during transmission.

[0051] This significantly reduces the resource usage of FPGA chip I / O, increases the working efficiency of FPGA and the computing power of its algorithms. Under the above conditions, FPGA chip resources can be transferred to other aspects, which objectively reduces the control time of the entire beam algorithm. Furthermore, it greatly simplifies the layout of electronic components and reduces the area of ​​the entire PCB board.

[0052] The PCB board adopts a tree-like layout and equal-length wiring, which reduces the latency of SPI communication data from a hardware perspective, reduces digital interference between different data lines, enhances data accuracy, and also enhances the anti-interference capability of signals between different layers of the PCB board.

[0053] It simplifies the PCB manufacturing process, reduces processing costs, is suitable for large-scale mass production, and greatly increases production capacity.

[0054] Figure 2 This is a schematic diagram of the phased subarray antenna chip arrangement in this embodiment. Each black dot represents an antenna chip, where M=N=16 and dx=dy ensures that the distance between adjacent antenna chips in rows and columns is consistent.

[0055] Figure 3 This is a schematic diagram of the daisy chain principle used in this embodiment. Figure 4 This is a timing diagram of data transmission for a single SPI master device in this embodiment, which uses a shift register method for data transmission. Data is sent from the Master to IC1, then from IC1 to IC2 via a shift register, then from IC2 to IC3 via a shift register, and so on until the data is sent to ICn. Finally, ICn transmits the feedback data back to the Master via a shift register.

[0056] Figure 5This is a schematic diagram of the SPI communication bus for the phased subarray antenna in this embodiment. Data signals are sent from the master device (FPGA chip) to the first slave device (antenna chip) of each SPI communication bus group. Different data signals must correspond one-to-one during the sending process. The first slave device then forwards the various data signals to the second slave device, and so on, until the last slave device. The last slave device of each SPI communication bus group then sends all the feedback data signals from the slave devices in that group back to the master device.

[0057] Figure 4 and Figure 5 Signal definitions: FPGA_SPI_CLK1 sends SPI clock signal data to the master device; FPGA_SPI_CSB1_A sends A group SPI bus chip select signal data to the master device; FPGA_SPI_CSB1_B sends B group SPI bus chip select signal data to the master device; FPGA_SPI_SDO1 sends SPI bus input control signal data to the master device; FPGA_SPI_SDI1 reads back SPI bus output control signal data to the master device; SPI_CLK is the slave device clock signal data; SPI_CSB is the slave device chip select signal data; SPI_SDI is the slave device input signal data; SPI_SDO is the slave device output signal data.

[0058] Figure 6 This is a schematic diagram of the phased array antenna chip distribution and SPI serial control data flow in this embodiment. The antenna chips are arranged in a row-column aligned manner, which facilitates the tree-like layout of the antenna chips and the routing of each data signal line of equal length during PCB layout and routing. This ensures the consistency of data signal transmission delay while reducing digital interference between different data lines and enhancing the anti-interference capability of signals between different layers of the PCB.

[0059] The top layer of the data transmission method of the entire beam control system in this embodiment includes a beam control algorithm module, an SPI bus transmission module, and a UART communication module. The specific beam control transmission process is as follows: the computer sends the azimuth and elevation angles of the control antenna beam to the UART communication chip, which then packages and forwards them to the FPGA chip to calculate the beam control algorithm. The calculated beam control data is then packaged and transmitted to each antenna element in a daisy chain through the SPI module. When the antenna element receives the data, it feeds back its current status to the FPGA chip in a daisy chain through the SPI module, which then packages and forwards it to the UART communication chip. Finally, the processed data is fed back to the computer.

[0060] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A multi-array phased subarray antenna wave control system, characterized in that, The system comprises a plurality of phased subarray antenna elements and an SPI bus master device, the phased subarray antenna elements are arranged in a P-row and Q-column array, the elements of odd columns and even columns are staggered, every four antenna elements form an antenna chip, the antenna chip is an SPI bus slave device, wherein P and Q are positive integers greater than or equal to 2, the system controls the antenna chip in a daisy chain mode; The number of antenna chips in each daisy chain is calculated according to the time delay of the entire wave control system data transmission estimated in the daisy chain mode; the entire phased subarray is divided into M*N / X groups of data according to the number of antenna chips in each daisy chain, and the SPI bus master device simultaneously outputs SPI communication data to M*N / X groups of SPI bus slave devices, wherein M*N=P*Q / 4 represents the number of antenna chips, and X represents the number of antenna chips in each daisy chain.

2. The multiple array phased subarray antenna wave control system of claim 1, wherein, The number of elements is greater than 256.

3. The multiple array phased subarray antenna wave control system of claim 1, wherein, The PCB board wiring of the system adopts a tree layout and equal-length line wiring.

4. The multiple array phased subarray antenna wave control system of claim 1, wherein, The SPI bus master device comprises an FPGA chip.

5. A data transmission method, characterized by, The method is used for transmitting data of the wave control system according to any one of claims 1-4, and the method comprises: obtaining an azimuth angle and an elevation angle of a controlled antenna beam; calculating required wave control data according to the azimuth angle and the elevation angle; packaging the wave control data in the form of a daisy chain and transmitting the wave control data to each antenna unit.

6. The data transmission method of claim 5, wherein, At the same time when the antenna unit receives the data, the current state is fed back to the SPI bus master device in the form of a daisy chain and then packaged and fed back to a computer.

7. The data transmission method of claim 5, wherein, The SPI bus master device adopts a shift register mode for data transmission.

8. The data transmission method of claim 7, wherein, The shift register specifically comprises: The SPI bus master device sends a data signal to the first slave device of each group of SPI communication buses; the first slave device of each group of SPI communication buses sequentially forwards the data signal to the last slave device of each group of SPI communication buses; the last slave device of each group of SPI communication buses feeds back the feedback data signal of all the slave devices in the group to the SPI bus master device.

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