Source amplifier and display device including the same

Abstract

Disclosed are a source amplifier and a display device including the source amplifier. The source amplifier includes a first circuit and a second circuit. The first circuit outputs a first current to an output terminal of the source amplifier by amplifying an input voltage. The second circuit is connected to the first circuit and outputs a second current to the output terminal based on the input voltage. The second circuit includes a third circuit that adjusts the level of the second current in response to an enable signal.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2021-0084204 filed on June 28, 2021, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Embodiments relate to a source amplifier and a display device including the source amplifier. Background Art

[0003] An electronic device may include a display driver integrated circuit (DDI) for displaying image data on a display panel. The display driver integrated circuit may include a source driver that provides an input data signal associated with the image data to a plurality of pixels included in the display panel via source lines. The source driver may include a plurality of source channels connected to the plurality of source lines, respectively. One source channel may include a source decoder and a source amplifier. The source decoder selects one of a plurality of gamma voltages generated by a gamma voltage generator based on the input data signal, and the source amplifier amplifies or buffers the selected voltage so that it is provided as a data voltage to the associated pixel within a given time.

[0004] As the distance between the source driver and the pixel increases, the resistance and capacitance of the source line increase. Therefore, the time it takes to charge the pixel located far from the source driver with the data voltage increases. Summary of the Invention

[0005] According to an embodiment, a source amplifier that outputs a data voltage to a display panel based on a first driving voltage, a second driving voltage, a first input voltage, and a second input voltage may include: a first circuit that generates first to fourth currents based on the first driving voltage, the second driving voltage, the first input voltage, and the second input voltage, and outputs the data voltage to an output terminal of the source amplifier based on the first to fourth currents; and a second circuit that is connected to the first circuit and supplies a fifth current to the output terminal based on the first driving voltage, the second driving voltage, and the second input voltage. The second circuit may include a first mirror circuit that is connected to the first terminal to which the first driving voltage is applied and supplies a sixth current to the output terminal, and a second mirror circuit that is connected to the second terminal to which the second driving voltage is applied and supplies a seventh current from the output terminal to the second terminal.

[0006] According to an embodiment, a display device may include a display panel and a display driver integrated circuit, wherein the display panel includes a plurality of pixels. The display driver integrated circuit may include a gate driver, a source driver, and a logic block. The gate driver is connected to the plurality of pixels via first to m-th gate lines and enables the first to m-th gate lines. The source driver is connected to the plurality of pixels via first to n-th source lines and includes a plurality of source amplifiers connected to the first to n-th source lines, respectively. The logic block generates signals for controlling the gate driver and the source driver. A first source amplifier among the plurality of source amplifiers may include a first circuit and a second circuit. The first circuit outputs a first current to an output terminal of the first source amplifier by amplifying an input voltage. The second circuit is connected to the first circuit and outputs a second current to the output terminal based on the input voltage. The second circuit may include a third circuit for adjusting the level of the second current in response to an enable signal.

[0007] According to an embodiment, a display device may include a display panel and a display driver integrated circuit. The display panel includes a plurality of pixels. The display driver integrated circuit may include a gate driver and a source driver. The gate driver is connected to the plurality of pixels via first to m-th gate lines and enables the first to m-th gate lines. The source driver is connected to the plurality of pixels via first to n-th source lines and includes a plurality of source amplifiers respectively connected to the first to n-th source lines. A first source amplifier among the plurality of source amplifiers may include a first circuit and a second circuit. The first circuit generates first to fourth currents based on a first driving voltage, a second driving voltage, a first input voltage, and a second input voltage, and outputs a first data voltage to an output terminal of the first source amplifier based on the first to fourth currents. The second circuit is connected to the first circuit and supplies a fifth current to the output terminal based on the first driving voltage, the second driving voltage, and the second input voltage. The second circuit may include a first mirror circuit that supplies a sixth current to the output terminal based on the first driving voltage; and a second mirror circuit that supplies a seventh current from the output terminal to the first terminal to which the second driving voltage is applied. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Features will become apparent to those skilled in the art by describing example embodiments in detail with reference to the accompanying drawings, in which:

[0009] Figure 1 A block diagram illustrating a display device according to example embodiments is shown.

[0010] Figure 2 A block diagram of a source driver according to example embodiments is shown.

[0011] Figure 3A block diagram illustrating a source amplifier, an output switch, and an output pad according to example embodiments is shown.

[0012] Figure 4A and Figure 4B is a circuit diagram illustrating portions of a source amplifier according to example embodiments.

[0013] Figure 5 A circuit diagram of a fast switching block according to an example embodiment is shown.

[0014] Figure 6 A frame displayed on a display panel and a pad area connected thereto according to example embodiments are illustrated.

[0015] Figure 7 A timing diagram for describing an operation of a display apparatus according to example embodiments is shown.

[0016] Figure 8 A block diagram illustrates an electronic device according to example embodiments. DETAILED DESCRIPTION

[0017] Figure 1 A block diagram of a display device 10 according to an example embodiment is shown.

[0018] Reference Figure 1 , the display device 10 may include a display driver integrated circuit (DDI) 100 and a display panel 11 .

[0019] The display driver integrated circuit 100 may include a logic block 110 , a source driver 120 , a gate driver 130 , a memory 140 , and a power supply 150 .

[0020] The display device 10 may be included in a portable communication terminal (such as a smart phone), a small electronic device (such as a personal digital assistant (PDA), a portable media player (PMP), a wearable device, a camera, a portable game console, an e-book reader or a tablet PC, or a large electronic product (such as a television or a monitor).

[0021] The display panel 11 may include a plurality of pixels. The display device 10 may receive image data from another component of the electronic device in which the display device 10 is included, such as an application processor (AP). The display device 10 may display the received image data or an image corresponding to the received image data through the plurality of pixels of the display panel 11.

[0022] Each of the plurality of pixels may be connected to a corresponding gate line among gate lines GL1 to GLm and a corresponding source line among source lines SL1 to SLn. In response to a voltage (or signal) of the corresponding gate line and the corresponding source line, each of the plurality of pixels may display image information corresponding to the voltage (or signal). Each of the plurality of pixels may display one of a plurality of colors. For example, a pixel may display one of red, green, or blue.

[0023] The display panel 11 may be implemented using an organic light emitting diode (OLED) display panel. In this case, each of the plurality of pixels may include a Figure 1 The transistor and diode shown in FIG. The gate terminal of the transistor can be connected to one of the gate lines GL1 to GLm. The first terminal (e.g., source) of the transistor can be connected to one of the source lines SL1 to SLn. The second terminal (e.g., drain) of the transistor can be connected to the diode.

[0024] In other embodiments, the display panel 11 may be implemented as various types of display panels including a liquid crystal display (LED) panel. In this case, the plurality of pixels may also include Figure 1 For example, in the case where the display panel 11 is implemented using an LED panel, Figure 1 Unlike the example shown in , each of the plurality of pixels may include liquid crystal instead of a diode. In this case, the display device 10 may further include other components such as a backlight (not shown).

[0025] In the display driver integrated circuit 100 , the logic block 110 may receive the following timing signals from outside the display device 10 : image data “DATA” to be displayed on the display panel 11 , a horizontal synchronization signal HSYNC, a vertical synchronization signal VSYNC, a dot clock signal DCLK, and a data enable signal DE.

[0026] The logic block 110 may generate various control signals for controlling the source driver 120, the gate driver 130, the memory 140, and the power supply 150 based on the timing signals. For example, the logic block 110 may generate control signals for controlling the source driver 120 and the gate driver 130 so that each of the plurality of pixels included in the display panel 11 displays corresponding image information. For example, the logic block 110 may generate a control signal CTRLC for controlling the source driver 120 based on the timing signals received from an external device.

[0027] The logic block 110 may be referred to as a “timing controller” or may include a timing controller.

[0028] Under the control of the logic block 110, the source driver 120 may provide image information to be displayed to a plurality of pixels through the source lines SL1 to SLn. For example, in response to the control signal CTRLC generated by the logic block 110, the source driver 120 may convert image data "DATA" into data voltages for displaying the image data "DATA" on the display panel 11. The source driver 120 may provide the data voltages to the plurality of pixels through the source lines SL1 to SLn.

[0029] The gate driver 130 may control the gate lines GL1 to GLm under the control of the logic block 110. For example, the gate driver 130 may sequentially provide gate signals to the gate lines GL1 to GLm. The gate signals may represent signals for activating a plurality of pixels connected to the gate lines corresponding to the gate signals.

[0030] The memory 140 may also be referred to as a “graphics memory” or a “graphics random access memory (GRAM)”. The memory 140 may receive and store data to be output through the source driver 120 from the logic block 110. For example, the logic block 110 may provide image data “DATA” received from outside the display device 10 to the memory 140.

[0031] In another embodiment (not shown), the memory 140 may directly transmit the stored data to the source driver 120 under the control of the logic block 110 .

[0032] When a still image is displayed by the display device 10, the memory 140 can output the stored image data, which can prevent the display device 10 from continuously receiving other image data from an external device. The memory 140 can reduce power consumption of the display device 10 and reduce heat generation of the display device 10.

[0033] In other embodiments (not shown), the display driver integrated circuit 100 may not include the memory 140 , or the display driver integrated circuit 100 may include two or more memories.

[0034] The power supply 150 may supply power to the logic block 110, the source driver 120, the gate driver 130, and the memory 140. The power supply 150 may supply power used to drive various components of the display device 10.

[0035] The display device 10 can display images in frames. The time required to display one frame can be defined as a vertical period. The vertical period can be determined by the scan rate of the display device 10. For example, when the scan rate of the display device 10 is 60 Hz, the vertical period can be 1 / 60 second, that is, approximately 16.7 ms.

[0036] The gate driver 130 may scan all the gate lines GL1 to GLm during one vertical period. For example, under the control of the logic block 110, the gate driver 130 may apply gate signals to the gate lines GL1 to GLm in sequence. The time for the gate driver 130 to scan each of all the gate lines GL1 to GLm may be defined as a horizontal period.

[0037] During one horizontal period, the source driver 120 may apply gray voltages to pixels of the display panel 11. The gray voltages may represent data voltages output based on image data "DATA" from the source driver 120. The brightness of each pixel of the display panel 11 may be determined by the gray voltages.

[0038] Figure 2 A block diagram of the source driver 120 according to example embodiments is shown.

[0039] Reference Figure 1 and Figure 2 The source driver 120 may include a data latch circuit 121 , a decoder 122 , a source amplifier circuit 123 , and a switch circuit 124 .

[0040] The data latch circuit 121 may receive image data "DATA" and a latch signal SLATCH from the logic block 110. The latch signal SLATCH may indicate a signal indicating that new data to be output by the source driver 120 is input to the data latch circuit 121 (or a signal indicating that the data stored in the data latch circuit 121 is updated). The data latch circuit 121 may sample and store the image data "DATA" under the control of the logic block 110. The data latch circuit 121 may provide the sampled image data to the decoder 122. The data latch circuit 121 may include a sampling circuit for sampling data and a holding latch for storing the data sampled by the sampling circuit.

[0041] The decoder 122 may receive the sampled image data from the data latch circuit 121 and may receive the gamma voltage VG.

[0042] The display driver integrated circuit 100 may further include a gamma voltage generator (not shown) that generates gamma voltages VG corresponding to various brightness levels. The number of gamma voltages VG may be determined based on the number of colors to be represented by the display panel 11 or the number of bits of digital data provided from outside the display device 10.

[0043] The decoder 122 may select one of the gamma voltages VG based on the sampled image data. The decoder 122 may output the selected gamma voltage to the source amplifier circuit 123. The decoder 122 may be implemented as a digital-to-analog converter.

[0044] The source amplifier circuit 123 may receive the selected gamma voltage from the decoder 122 and may receive the enable signals AMPEN, FSEN, and FSMREN and the complementary enable signals AMPENB, FSENB, and FSMRENB from the logic block 110. In response to the enable signals AMPEN, FSEN, and FSMREN and the complementary enable signals AMPENB, FSENB, and FSMRENB, the source amplifier circuit 123 may amplify the gamma voltage selected by the decoder 122 to provide the amplified gamma voltage to the switch circuit 124.

[0045] The source amplifier circuit 123 may include a plurality of source amplifiers SAMP, each of which is connected to any one of the source lines SL1 to SLn. Each of the source amplifiers SAMP may be implemented as an operational amplifier. Each of the source amplifiers SAMP may amplify the gamma voltage selected by the decoder 122 to provide the data voltage (or grayscale voltage) to the switch circuit 124.

[0046] The switch circuit 124 may receive the data voltage from the source amplifier circuit 123 and the enable signal SOUTEN from the logic block 110. The switch circuit 124 may include a plurality of output switches SOUTSW each connected to any one of the source amplifiers SAMP. In response to the enable signal SOUTEN, the switch circuit 124 may transmit the data voltage to the plurality of pixels of the display panel 11 through the source lines SL1 to SLn.

[0047] The data latch signal SLATCH, the enable signals AMPEN, FSEN, FSMREN, SOUTEN, and the complementary enable signals AMPENB, FSENB, and FSMRENB may be included in the control signal CTRLC generated by the logic block 110 .

[0048] Figure 3 1 is a block diagram illustrating a source amplifier SAMP, an output switch SOUTSW, and an output pad (also referred to as a pad) PADk according to example embodiments.

[0049] Reference Figures 1 to 3 , the output voltage VOUT output from the source amplifier SAMP may be applied to an output pad PADk (k is any integer between 1 and N) connected to the source line SLk through an output switch SOUTSW.

[0050] The source amplifier SAMP can receive voltages VDD and VSS from the power supply 150. The source amplifier SAMP may also include a positive input terminal (to which the input voltage Vip is applied), a negative input terminal (to which the input voltage Vin is applied), and an output terminal (from which the output voltage VOUT is output). The negative input terminal of the source amplifier SAMP may be connected to the output terminal of the source amplifier SAMP. For example, the output voltage VOUT may be input to the source amplifier SAMP as the input voltage Vin. The source amplifier SAMP may be implemented as a unity buffer.

[0051] The input voltage Vip applied to the source amplifier SAMP may be a gamma voltage selected by the decoder 122. The source amplifier SAMP may amplify or buffer the input voltage Vip based on the voltages VDD and VSS and the output voltage VOUT. The output voltage VOUT may be a data voltage to be transmitted to the source line SLk.

[0052] The source amplifier SAMP can output the output voltage VOUT to the output switch SOUTSW. The output switch SOUTSW can connect or disconnect the source amplifier SAMP from the output pad PADk in response to an enable signal SOUTEN. For example, the output switch SOUTSW can be turned on or off in response to the enable signal SOUTEN. When the output switch SOUTSW is turned on, the output voltage VOUT can be applied to the output pad PADk. The output voltage VOUT can be applied to the source line SLk via the output pad PADk.

[0053] Figure 4A and Figure 4B is a circuit diagram illustrating portions of a source amplifier SAMP according to an example embodiment.

[0054] In detail, Figure 4A A circuit diagram of the source amplifier input section SAMPa is shown. Figure 4B 1 shows a circuit diagram of a source amplifier output section SAMPb. The source amplifier input section SAMPa may correspond to the input portion of the source amplifier SAMP. The source amplifier output section SAMPb may correspond to the output portion of the source amplifier SAMP.

[0055] Now refer to Figures 1 to 4A and Figure 4B An example structure and operation of the source amplifier SAMP are described in detail.

[0056] The display driver integrated circuit 100 may further include a bias voltage generator (not shown) that generates bias voltages VBP1 to VBP5 and VBN1 to VBN5. Under the control of the logic block 110, the bias voltage generator may generate the bias voltages VBP1 to VBP5 and VBN1 to VBN5 to be applied to the source amplifier SAMP based on the voltage supplied from the power supply 150. The source amplifier SAMP may output the output voltage VOUT based on the input voltages Vip and Vin and the bias voltages VBP1 to VBP5 and VBN1 to VBN5.

[0057] The source amplifier input portion SAMPa may include transistors MPT1 , MNI1 , MNI2 , MPI1 , MPI2 , and MNT1 .

[0058] The transistors MPT1 , MPI1 , and MPI2 may be implemented as PMOS transistors, and the transistors MNI1 , MNI2 , and MNT1 may be implemented as NMOS transistors.

[0059] Based on bias voltages VBP1 and VBN1, source amplifier input section SAMPa can provide a voltage or current corresponding to the difference between input voltages Vip and Vin to nodes NN, PN, PP, and NP. For example, source amplifier input section SAMPa can output currents INN, IPN, IPP, and INP to nodes NN, PN, PP, and NP, respectively.

[0060] The transistor MPT1 may include a first terminal to which the voltage VDD is applied, a gate receiving the bias voltage VBP1 , and a second terminal connected to the transistors MPI1 and MPI2 .

[0061] The transistor MPI1 may include a first terminal connected to the second terminal of the transistor MPT1 , a gate receiving the input voltage Vin, and a second terminal connected to the node PN.

[0062] The transistor MPI2 may include a first terminal connected to the second terminal of the transistor MPT1 , a gate receiving the input voltage Vip, and a second terminal connected to the node PP.

[0063] Nodes PN, PP, NN and NP can be connected with Figure 4B The source amplifier output section SAMPb is connected.

[0064] The transistor MNI1 may include a first terminal connected to the node NN, a gate receiving the input voltage Vin, and a second terminal connected to the transistor MNT1 .

[0065] The transistor MNI2 may include a first terminal connected to the node NP, a gate receiving the input voltage Vip, and a second terminal connected to the transistor MNT1 .

[0066] The transistor MNT1 may include a first terminal connected to the second terminal of the transistor MNI1 and the second terminal of the transistor MNI2 , a gate to which the bias voltage VBN1 is applied, and a second terminal to which the voltage VSS is applied.

[0067] The source amplifier output section SAMPb may include transistors MPL1, MPL2, MPL3, MPC1, MPC2, MPF1, MPF2, MPF3, MPF4, MP1, MPO, MNF1, MNF2, MNF3, MNF4, MNC1, MNC2, MNL1, MNL2, MNL3, MN1 and MNO, switches AMPSW1, AMPSW2, AMPSW3 and AMPSW4, capacitors C1 and C2 and a fast slew block 200.

[0068] Transistors MPL1, MPL2, MPL3, MPC1, MPC2, MPF1, MPF2, MPF3, MPF4, MP1, and MPO may be implemented as PMOS transistors, while transistors MNF1, MNF2, MNF3, MNF4, MNC1, MNC2, MNL1, MNL2, MNL3, MN1, and MNO may be implemented as NMOS transistors.

[0069] The source amplifier output part SAMPb can output the output voltage VOUT in response to the voltages VDD and VSS, the bias voltages VBP2, VBP3, VBP4, VBP5, VBN2, VBN3, VBN4 and VBN5, the signal provided from the source amplifier input component SAMPa through the nodes NN, PN, NP and PP, and the enable signal AMPEN and the complementary enable signal AMPENB received from the logic block 110.

[0070] The transistor MPL1 may include a first terminal to which the voltage VDD is applied, a gate connected to the second terminal of the transistor MPC1 , and a second terminal connected to the node NN.

[0071] The transistor MPC1 may include a first terminal connected to the node NN and the second terminal of the transistor MPL1 , a gate to which the bias voltage VBP2 is applied, and a second terminal connected to the transistors MNF3 and MPF1 .

[0072] The transistor MNF3 may include a first terminal connected to the second terminal of the transistor MPC1 , a gate to which the bias voltage VBP5 is applied, and a second terminal connected to the first terminal of the transistor MNF1 .

[0073] The transistor MNF1 may include a first terminal connected to the second terminal of the transistor MNF3 , a gate to which the bias voltage VBN3 is applied, and a second terminal connected to the first terminal of the transistor MNC1 .

[0074] The transistor MPF1 may include a first terminal connected to the second terminal of the transistor MPC1 , a gate to which the bias voltage VBP3 is applied, and a second terminal connected to the first terminal of the transistor MPF3 .

[0075] The transistor MPF3 may include a first terminal connected to the second terminal of the transistor MPF1 , a gate to which the bias voltage VBN5 is applied, and a second terminal connected to the first terminal of the transistor MNC1 .

[0076] The transistor MNC1 may include a first terminal connected to the second terminal of the transistor MNF1 and the second terminal of the transistor MPF3 , a gate to which the bias voltage VBN2 is applied, and a second terminal connected to the first terminal of the transistor MNL1 .

[0077] The transistor MNL1 may include a first terminal connected to the node PN and the second terminal of the transistor MNC1 , a gate connected to the first terminal of the transistor MNC1 , and a second terminal to which a voltage VSS is applied.

[0078] The transistor MPL2 may include a first terminal to which the voltage VDD is applied, a gate connected to the gate of the transistor MPL1 and the second terminal of the transistor MPL3 , and a second terminal connected to the node NP.

[0079] The transistor MPC2 may include a first terminal connected to the node NP and the switch AMPSW1 , a gate to which the bias voltage VBP2 is applied, and a second terminal connected to the switch AMPSW2 . The gate of the transistor MPC2 may be connected to the gate of the transistor MPC1 .

[0080] The transistor MPL3 may include a first terminal to which the voltage VDD is applied, a gate receiving the enable signal AMPEN, and a second terminal connected to the gate of the transistor MPL2 .

[0081] The transistor MNF4 may include a first terminal connected to the second terminal of the transistor MPC2 , a gate to which the bias voltage VBP5 is applied, and a second terminal connected to the first terminal of the transistor MNF2 .

[0082] The transistor MNF2 may include a first terminal connected to the second terminal of the transistor MNF4 , a gate to which the bias voltage VBN4 is applied, and a second terminal connected to the first terminal of the transistor MNC2 .

[0083] The transistor MPF2 may include a first terminal connected to the second terminal of the transistor MPC2 , a gate to which the bias voltage VBP4 is applied, and a second terminal connected to the first terminal of the transistor MPF4 .

[0084] The transistor MPF4 may include a first terminal connected to the second terminal of the transistor MPF2 , a gate to which the bias voltage VBN5 is applied, and a second terminal connected to the first terminal of the transistor MNC2 .

[0085] The transistor MNC2 may include a first terminal connected to the second terminal of the transistor MNF2 , the second terminal of the transistor MPF4 , and the switch AMPSW3 , a gate to which the bias voltage VBN2 is applied, and a second terminal connected to the switch AMPSW4 .

[0086] Transistor MNL2 may include a first terminal connected to the second terminal of transistor MNC2 , node PP, and switch AMPSW4 , a gate connected to the first terminal of transistor MNL3 and the gate of transistor MNL1 , and a second terminal to which voltage VSS is applied.

[0087] The transistor MNL3 may include a first terminal connected to the gate of the transistor MNL2 , a gate to which the complementary enable signal AMPENB is applied, and a second terminal to which the voltage VSS is applied.

[0088] The transistor MP1 may include a first terminal to which the voltage VDD is applied, a gate to which the enable signal AMPEN is applied, and a second terminal connected to the gate of the transistor MPO.

[0089] Transistor MPO may include a first terminal to which voltage VDD is applied, a gate connected to the second terminal of transistor MP1 and switch AMPSW2, and a second terminal connected to the first terminal of transistor MNO. The second terminal of transistor MPO may be connected to a node where capacitors C1 and C2 are connected. The voltage at the second terminal of transistor MPO may be output voltage VOUT.

[0090] The transistor MNO may include a first terminal connected to the second terminal of the transistor MPO, a gate connected to the switch AMPSW3, and a second terminal to which the voltage VSS is applied. The voltage of the first terminal of the transistor MNO may be the output voltage VOUT.

[0091] The transistor MN1 may include a first terminal connected to the switch AMPSW3 and the gate of the transistor MNO, a gate to which the complementary enable signal AMPENB is applied, and a second terminal to which the voltage VSS is applied.

[0092] In other embodiments ( Figure 4BIn the embodiment of the present invention (not shown), each of the transistors MPL1, MPL2, MNL1, and MNL2 can be implemented as two or more substantially identical transistors connected in parallel. For example, the transistor MPL1 can be implemented as two substantially identical PMOS transistors connected in parallel. When both PMOS transistors included in the transistor MPL1 are turned on, current can flow through the two PMOS transistors based on the gate voltage applied to the two PMOS transistors. When one of the two PMOS transistors is turned on and the other is turned off, current can flow through the turned-on PMOS transistor based on the gate voltage applied to the turned-on PMOS transistor, and current can not flow through the turned-off PMOS transistor based on the gate voltage applied to the turned-off PMOS transistor. In other words, the amount of current flowing through the transistor MPL1 can vary depending on whether the two PMOS transistors included in the transistor MPL1 are turned on or off.

[0093] The switch AMPSW1 may be connected between “a node at which the first terminal of the transistor MPC2 is connected to the node NP” and the fast switching block 200 .

[0094] Switch AMPSW2 may be connected between the second terminal of transistor MPC2 and the gate of transistor MPO.

[0095] The switch AMPSW3 may be connected between a node to which the transistors MNF2 , MPF4 , and MNC2 are connected and the gate of the transistor MNO.

[0096] The switch AMPSW4 may be connected between “a node at which the second terminal of the transistor MNC2 is connected to the node PP” and the fast switching block 200 .

[0097] Each of the switches AMPSW1, AMPSW2, AMPSW3, and AMPSW4 may receive an enable signal AMPEN and a complementary enable signal AMPENB from the logic block 110. Each of the switches AMPSW1, AMPSW2, AMPSW3, and AMPSW4 may be turned on or off in response to the enable signal AMPEN and the complementary enable signal AMPENB. The enable signal AMPEN and the complementary enable signal AMPENB may be complementary.

[0098] Capacitor C1 may be connected between the node where switch AMPSW1 is connected to the fast switching block 200 and capacitor C2, and capacitor C2 may be connected between capacitor C1 and the node where switch AMPSW4 is connected to the fast switching block 200. The node where capacitors C1 and C2 are connected may be connected to the second terminal of transistor MPO and the first terminal of transistor MNO and may function as the output terminal of source amplifier SAMP. Therefore, the voltage at the node where capacitors C1, capacitor C2, the second terminal of transistor MPO, and the first terminal of transistor MNO are connected may be the output voltage VOUT of source amplifier SAMP.

[0099] The fast switching block 200 can adjust the operating speed of the source amplifier SAMP. For example, the fast switching block 200 can supply additional current to the source amplifier SAMP, thereby improving the source amplifier SAMP's ability to drive the output voltage VOUT. The fast switching block 200 can receive enable signals FSEN and FSMREN and complementary enable signals FSENB and FSMRENB from the logic block 110. In response to the input voltage Vip, the enable signals FSEN and FSMREN, and the complementary enable signals FSENB and FSMRENB, the fast switching block 200 can supply the additional current to the node to which the output voltage VOUT is applied.

[0100] Figure 5 A circuit diagram of a fast switching block 200 according to an example embodiment is shown.

[0101] from Figure 5 It will be understood that for ease of description, only some components of the source amplifier SAMP are shown (eg, transistors MP1 , MPO, MNO, and MN1 , switches AMPSW1 , AMPSW2 , AMPSW3 , and AMPSW4 , and capacitors C1 and C2 ).

[0102] Now refer to Figures 1 to 4A 、 Figure 4B and Figure 5 The fast conversion block 200 is described in detail.

[0103] The fast switching block 200 may include transistors MPFS1 to MPSF8 and MNFS1 to MNFS8 , switches FSSW1 and FSSW2 , and mirror blocks 211 and 212 .

[0104] The transistors MPFS1 to MPSF8 may be implemented as PMOS transistors, and the transistors MNFS1 to MNFS8 may be implemented as NMOS transistors.

[0105] The transistor MPFS1 may include a first terminal to which the voltage VDD is applied, a gate connected to the second terminal of the transistor MPFS2 and the gate of the transistor MPFS3 , and a second terminal connected to the switch AMPSW1 .

[0106] The transistor MPFS2 may include a first terminal to which the voltage VDD is applied, a gate to which the enable signal FSEN is applied, and a second terminal connected to the gate of the transistor MPFS3 .

[0107] The transistor MPFS3 may include a first terminal to which the voltage VDD is applied, a gate connected to the gate of the transistor MPFS1 and the second terminal of the transistor MPFS2 , and a second terminal connected to the gate of the transistor MPFS3 .

[0108] The transistor MPFS4 may include a first terminal to which the voltage VDD is applied, a gate connected to the second terminal of the transistor MPM3 of the mirror block 211 , and a second terminal connected to the second terminal of the transistor MPM1 of the mirror block 211 .

[0109] Transistor MPFS5 may include a first terminal to which voltage VDD is applied, a gate to which enable signal FSEN is applied, and a second terminal connected to the gate of transistor MPFS4 and the gate of transistor MPFS6. Transistor MPFS6 may include a first terminal to which voltage VDD is applied, a gate connected to the second terminal of transistor MPFS5 and the gate of transistor MPFS4, and a second terminal connected to the first terminal of transistor MNFS8.

[0110] The transistor MPFS7 may include a first terminal to which the voltage VDD is applied, a gate to which the enable signal FSEN is applied, and a second terminal connected to the gate of the transistor MPFS8 .

[0111] The transistor MNFS1 may include a first terminal connected to the switch AMPSW4 , a gate connected to the first terminal of the transistor MNFS2 and the gate of the transistor MNFS3 , and a second terminal to which the voltage VSS is applied.

[0112] The transistor MNFS2 may include a first terminal connected to the gate of the transistor MNFS1 and the gate of the transistor MNFS3 , a gate to which the complementary enable signal FSENB is applied, and a second terminal to which the voltage VSS is applied.

[0113] The transistor MNFS3 may include a first terminal connected to the gate of the transistor MNFS3 , a gate connected to the gate of the transistor MNFS1 and the first terminal of the transistor MNFS2 , and a second terminal to which the voltage VSS is applied.

[0114] The transistor MNFS4 may include a first terminal connected to the first terminal of the transistor MNM1 of the mirror block 212 , a gate connected to the second terminal of the transistor MNM3 of the mirror block 212 , and a second terminal to which the voltage VSS is applied.

[0115] Transistor MNFS5 may include a first terminal connected to the gate of transistor MNFS4 and the gate of transistor MNFS6, a gate to which a complementary enable signal FSENB is applied, and a second terminal to which voltage VSS is applied. Transistor MNFS6 may include a first terminal connected to the second terminal of transistor MPFS8, a gate connected to the gate of transistor MNFS4 and the first terminal of transistor MNFS5, and a second terminal to which voltage VSS is applied.

[0116] The transistor MNFS7 may include a first terminal connected to the gate of the transistor MNFS8 , a gate to which the complementary enable signal FSENB is applied, and a second terminal to which the voltage VSS is applied.

[0117] Transistor MNFS8 may include a first terminal connected to the second terminal of transistor MPFS6 , a gate connected to the first terminal of transistor MNFS7 and switch FSSW1 , and a second terminal connected to the first terminal of transistor MPFS8 .

[0118] Transistor MPFS8 may include a first terminal connected to the second terminal of transistor MNFS8, a gate connected to the second terminal of transistor MPFS7 and switch FSSW2, and a second terminal connected to the first terminal of transistor MNFS6. The voltage at the node where the second terminal of transistor MNFS8 and the first terminal of transistor MPFS8 are connected may be output voltage VOUT. Current I1 may be output from the second terminal of transistor MNFS8 to the output terminal of source amplifier SAMP. Current I2 may be applied to the first terminal of transistor MPFS8.

[0119] When the transistor MNFS8 is turned on, the source amplifier SAMP can supply current to the corresponding source line. On the other hand, when the transistor MPFS8 is turned on, the source amplifier SAMP can reduce the amount of current to be supplied to the corresponding source line.

[0120] Switch FSSW1 may be connected between the gate of transistor MNFS8 and a node to which input voltage Vip is applied, and switch FSSW2 may be connected between the gate of transistor MPFS8 and a node to which input voltage Vip is applied. Each of switches FSSW1 and FSSW2 may receive an enable signal FSEN and a complementary enable signal FSENB from logic block 110 and may be turned on (or enabled) or off (or disabled) in response to the enable signal FSEN and the complementary enable signal FSENB. The enable signal FSEN and the complementary enable signal FSENB may be complementary.

[0121] The fast switching block 200 can be enabled in response to a logic high enable signal FSEN. In this way, the fast switching block 200 can supply additional current based on the voltages VDD and VSS to the node from which the output voltage VOUT is output. The fast switching block 200 can be disabled in response to a logic low enable signal FSEN.

[0122] The mirror blocks 211 and 212 can adjust the level (e.g., the magnitude) of the additional current (e.g., the sum of the current I1 and the current I2) supplied from the fast switching block 200 to the node from which the output voltage VOUT is output. The mirror blocks 211 and 212 can be enabled or disabled in response to the enable signal FSMREN and the complementary enable signal FSMRENB.

[0123] In the following, it is assumed that the fast switching block 200 is already enabled when the mirror blocks 211 and 212 are enabled. For example, when the enable signal FSMREN transitions to logic high, the enable signal FSEN may transition to logic high simultaneously with or before the enable signal FSMREN. When the enable signal FSMREN transitions to logic low, the enable signal FSEN may transition to logic low simultaneously with or after the enable signal FSMREN.

[0124] When the mirror blocks 211 and 212 are enabled, the mirror blocks 211 and 212 can further increase the amount of additional current supplied to the node from which the output voltage VOUT is output, thereby improving the driving capability of the source amplifier SAMP. For example, when the mirror blocks 211 and 212 are enabled, the mirror blocks 211 and 212 can additionally provide a path for current to flow, thereby increasing the amount of additional current supplied to the node from which the output voltage VOUT is output. In this way, the slew rate of the output voltage VOUT of the source amplifier SAMP can be increased, and the data voltage can be supplied to the multiple pixels of the display panel 11 more quickly.

[0125] The length of time during which the mirror blocks 211 and 212 are enabled may vary depending on the location of the pixel. For example, as the pixel is farther from the source driver 120, the length of time during which the mirror blocks 211 and 212 associated with the pixel are enabled may increase. This will be referred to as Figure 6 Describe in more detail.

[0126] The mirror block 211 may include transistors MPM1 , MPM2 , and MPM3 .

[0127] The transistor MPM1 may include a first terminal to which the voltage VDD is applied, a gate connected to the second terminal of the transistor MPM2 and the first terminal of the transistor MPM3 , and a second terminal connected to the second terminal of the transistor MPFS4 .

[0128] The transistor MPM2 may include a first terminal to which the voltage VDD is applied, a gate to which the enable signal FSMREN is applied, and a second terminal connected to the first terminal of the transistor MPM3 and the gate of the transistor MPM1 .

[0129] The transistor MPM3 may include a first terminal connected to the gate of the transistor MPM1 and the second terminal of the transistor MPM2 , a gate to which the complementary enable signal FSMRENB is applied, and a second terminal connected to the gate of the transistor MPFS4 .

[0130] The mirror block 212 may include transistors MNM1 , MNM2 , and MNM3 .

[0131] The transistor MNM1 may include a first terminal connected to the first terminal of the transistor MNFS4 , a gate connected to the first terminal of the transistor MNM2 and the first terminal of the transistor MNM3 , and a second terminal to which the voltage VSS is applied.

[0132] The transistor MNM2 may include a first terminal connected to the gate of the transistor MNM1 and the first terminal of the transistor MNM3 , a gate to which the complementary enable signal FSMRENB is applied, and a second terminal to which the voltage VSS is applied.

[0133] The transistor MNM3 may include a first terminal connected to the gate of the transistor MNM1 and the first terminal of the transistor MNM2 , a gate to which the enable signal FSMREN is applied, and a second terminal connected to the gate of the transistor MNFS4 .

[0134] In response to a logic high enable signal FSMREN, mirror block 211 can supply additional current to the node outputting voltage VOUT, and mirror block 212 can sink additional current from the node outputting voltage VOUT. Mirror block 211 can be a current source block, and mirror block 212 can be a current sink block.

[0135] Referring to mirror block 211, when input voltage Vip is sufficiently large (e.g., when a gamma voltage is applied to source amplifier SAMP), transistor MPM3 may be turned on, and transistor MPM2 may be turned off, in response to a logic-high enable signal FSMREN and a logic-low complementary enable signal FSMRENB. In this manner, additional current based on voltage VDD may be supplied to the second terminal of transistor MPFS4 via transistor MPM1. Due to this additional current, the gate voltages of transistors MPFS4 and MNFS6 may increase, and thus the magnitude of the current supplied to the second terminal of transistor MNFS6 may increase. Therefore, mirror block 211 can provide a path for supplying additional current to the node for output voltage VOUT using transistor MPM1. As a result, the driving capability of source amplifier SAMP can be improved. For example, source amplifier SAMP can charge pixels with data voltages at a faster rate.

[0136] Similar to the above description, mirror block 212 can provide a path for supplying additional current from the node of output voltage VOUT to the terminal to which voltage VSS is applied, using transistor MNM1. For example, when input voltage Vip is sufficiently low (e.g., when a gamma voltage is not applied to source amplifier SAMP), transistor MNM3 can be turned on, and transistor MNM2 can be turned off, in response to a logic-high enable signal FSMREN and a logic-low complementary enable signal FSMRENB. In this manner, additional current based on voltage VSS can be supplied from the first terminal of transistor MNFS4 to the terminal to which voltage VSS is applied, via transistor MNM1. Due to this additional current, the gate voltages of transistors MNFS4 and MNFS6 may increase, thereby increasing the magnitude of the current supplied from the first terminal of transistor MNFS6 to the second terminal of MNFS6 (or flowing through transistor MNFS6). In other words, mirror block 212 can provide a path for supplying additional current from the node of output voltage VOUT to the terminal to which voltage VSS is applied, using transistor MNM1. As a result, the voltage regulation capability of source amplifier SAMP can be improved. For example, when a data voltage to be supplied to a source line is lower than a voltage of the source line, the source amplifier SAMP may more quickly reduce the voltage of the source line to the data voltage.

[0137] Figure 6 A frame 'FRAME' displayed on the display panel 11 and a pad area PAD connected thereto according to an example embodiment are shown.

[0138] Reference Figure 1 、 Figure 2 、 Figure 5 and Figure 6, a frame “FRAME” displayed on the display panel 11 may be divided into one or more areas AREA1 to AREAi (i is a positive integer).

[0139] The display panel 11 may be connected to the pad area PAD of the source driver 120 via the source lines SL. The pad area PAD may include a plurality of pads (e.g., pads PADn) corresponding to the source lines SL1 to SLn, respectively. Each of the plurality of pads may receive a corresponding output voltage VOUT (or data voltage) from a corresponding source amplifier SAMP via a corresponding output switch SOUTSW, and transmit the output voltage VOUT (or data voltage) to the corresponding source line.

[0140] For example, the pad PADn of the pad area PAD may correspond to the source line SLn. The pad PADn may receive the output voltage VOUTn from the corresponding source amplifier SAMP. The output voltage VOUTn may be provided to the pixel connected to the source line SLn through the pad PADn and the source line SLn.

[0141] Each of the areas AREA1 to AREAi may correspond to one or more gate lines. For example, the area AREAi may include pixels connected to the gate line GL1. For another example, the area AREAi may include pixels connected to the gate line GL1 and pixels connected to the gate line GL2.

[0142] When the pixel (i.e., gate line) is disposed farther from the pad area PAD of the source driver 120, the length of the source line from the pad area PAD to the corresponding pixel may increase. In this case, the resistance and capacitance of the source line from the pad area PAD to the pixel may increase, thereby increasing the time required to charge the data voltage to the pixel. For example, referring to Figure 1 , the length of the source line from the pad area PAD to the pixel connected to the gate line GLm may be longer than the length of the source line from the pad area PAD to the pixel connected to the gate line GL1. As such, the time taken to charge the pixel connected to the gate line GLm with the data voltage may be longer than the time taken to charge the pixel connected to the gate line GL1 with the data voltage.

[0143] When the enable signal FSMREN is maintained at logic high, the mirror blocks 211 and 212 of the fast switching block 200 can be enabled. In this way, the driving capability of the source driver 120 can be improved, thereby shortening the time it takes to charge the pixels of the display panel 11 with the data voltage. As a result, the operating speed of the display device 10 can be increased.

[0144] In the present example embodiment, the length of time during which the enable signal FSMREN is maintained at logic high may be set differently for each of the areas AREA1 to AREAi.

[0145] The length of time during which the enable signal FSMREN remains at a logic high level may be based on the distance between the corresponding pixel of the source line associated with the enable signal FSMREN and the pad area PAD. For example, as the distance from the pad area PAD of the source driver 120 increases, the time during which the enable signal FSMREN remains at a logic high level may increase. In this way, as a region becomes increasingly distant from the pad area PAD of the source driver 120, the voltage regulation capability (e.g., driving capability and recovery capability) of the source driver 120 may increase relative to that region, thereby shortening the time it takes to charge the pixels included in that region with the data voltage. As a result, the time it takes to display image data on the display panel 11 (e.g., stabilization time) may be shortened.

[0146] On the other hand, for regions close to the pad area PAD of the source driver 120 (e.g., regions AREAi-2, AREAi-1, and AREAi), the driving capability of the source driver 120 may be enhanced to a lesser extent or not at all. For example, when pixels included in the region close to the pad area PAD of the source driver 120 are charged with a data voltage, the output voltage of the source driver 120 may be prevented from undershooting or overshooting. Therefore, the stabilization time may be prevented from being prolonged due to unnecessary enhancement of the driving capability of the source driver 120.

[0147] When the data voltage is supplied to the pixels of area AREA1, the length of time during which the enable signal FSMREN corresponds to a logic high (or the duty cycle of the enable signal FSMREN corresponding to area AREA1) can be longer than the length of time during which the enable signal FSMREN corresponds to a logic high when the data voltage is supplied to the pixels of area AREAi (or the duty cycle of the enable signal FSMREN corresponding to area AREA1). In this way, the time taken to charge the pixels of area AREA1 with the data voltage can be reduced by the mirror blocks 211 and 212. In addition, when the data voltage is supplied to the pixels of area AREAi, the output voltage of the source driver 120 can be prevented from undershooting or overshooting.

[0148] The length of time during which the enable signal FSMREN remains at (or corresponds to) a logic high level may be gradually reduced when transitioning from area AREA1 to area AREAi. Thus, even if the slew rate of the source driver 120 changes relative to area AREA1 to area AREAi, landscape noise may be prevented from occurring at the boundary between area AREA1 and area AREAi. For example, when a data voltage is supplied to a pixel in area AREA1 among areas AREA1 to area AREAi, the length of time during which the enable signal FSMREN corresponds to a logic high level may be the longest, while when a data voltage is supplied to a pixel in area AREAi among areas AREA1 to area AREAi, the length of time during which the enable signal FSMREN corresponds to a logic high level may be the shortest.

[0149] In an embodiment (not shown), the logic block 110 of the display driver integrated circuit 100 may include a display clock generator. Under the control of the logic block 110, the display clock generator may generate a display clock to be used in the display device 10 based on the dot clock DCLK. The logic block 110 may generate an enable signal FSMREN based on the display clock.

[0150] As will be referred to below Figure 7 In more detail, the duty cycle of the enable signal FSMREN may be determined as a multiple of one cycle of the display clock. For example, the length of time during which the enable signal FSMREN corresponds to a logic high may be a multiple of the length of time during which one display clock corresponds to a logic high. For another example, the enable signal FSMREN may remain at a logic high level for multiple cycles of the display clock and then transition to a logic low level.

[0151] The duty cycle of the enable signal FSMREN corresponding to each of the areas AREA1 to AREAi can be adjusted in units of one cycle of the display clock. For example, the duty cycle of the enable signal FSMREN corresponding to each of the areas AREA1 to AREAi can decrease sequentially. For example, when the duty cycle of the enable signal FSMREN corresponding to area AREA1 is j times (j is a positive integer) the cycle of the display clock, the duty cycle of the enable signal FSMREN corresponding to area AREA2 can be (j-1) times the cycle of the display clock. In other words, the enable signal FSMREN corresponding to area AREA1 can remain at a logic high level for "j" cycles of the display clock, and the enable signal FSMREN corresponding to area AREA2 can remain at a logic high level for (j-1) cycles of the display clock. In this way, a user of the display device 10 may not visually perceive the difference between the slew rate of the source driver 120 associated with area AREA1 and the slew rate of the source driver 120 associated with area AREA2.

[0152] As described above, the magnitude of the current output from the source driver 120 can be adjusted based on the settling time of pixels located far from the pad area PAD (e.g., pixels in area AREA1). The source driver 120, including the mirror blocks 211 and 212, can increase the switching rate of pixels located farthest from the pad area PAD. This shortens the settling time when the display device 10 operates at high speed. Furthermore, when the display device 10 operates at low speed, the source driver 120 can charge the pixels with a smaller amount of current, thereby providing low-power operation.

[0153] Figure 7 A timing chart for describing the operation of the display apparatus 10 according to an example embodiment is shown.

[0154] Will refer to Figure 1 、 Figure 2 、 Figure 5 、 Figure 6 and Figure 7 How to determine the length of time during which the enable signal FSMREN corresponds to (or remains at) logic high for the areas AREA1 to AREAi is described. For ease of explanation, it is assumed that the areas AREA1, AREA2, AREA3, AREAi-2, AREAi-1, and AREAi correspond to the gate lines GLm, GLm-1, GLm-2, GL3, GL2, and GL1, respectively.

[0155] Reference Figure 7At time t1, the enable signal SOUTEN may transition to logic low. Thus, the output switch SOUTSW may be turned off. After time t1, the latch signal SLATCH input to the data latch circuit 121 of the source driver 120 may be activated, thereby updating the data latch circuit 121 with new image data.

[0156] During a time interval tFSMR1 from time t1 , the enable signal FSMREN may correspond to (or maintain) logic high. Thus, the mirror blocks 211 and 212 may be enabled.

[0157] At time t2, the enable signal SOUTEN may transition to logic high. In this case, the output switch SOUTSW may be turned on, and thus, the data voltage may begin to be supplied from the source amplifier SAMP to the pixels included in the area AREA1 (e.g., the pixels connected to the gate line GLm). For example, the source amplifier SAMP may supply the data voltage based on the image data updated in response to the latch signal SLATCH to the pixels in the area AREA1. The source amplifier SAMP may supply a current greater than the current amount when the mirror blocks 211 and 212 are disabled to the pixels in the area AREA1.

[0158] At time t3, the enable signal SOUTEN may transition to logic low. Thus, the output switch SOUTSW may be turned off. After time t3, the latch signal SLATCH input to the data latch circuit 121 of the source driver 120 may be triggered, thereby updating the data latch circuit 121 with new image data.

[0159] During a time interval tFSMR2 from time t3 , the enable signal FSMREN may correspond to (or maintain) logic high. In this way, the mirror blocks 211 and 212 may be enabled.

[0160] At time t4, the enable signal SOUTEN may transition to logic low. In this case, the output switch SOUTSW may be turned on, and thus, the data voltage may begin to be supplied from the source amplifier SAMP to the pixels included in the area AREA2 (e.g., the pixels connected to the gate line GLm-1). For example, the source amplifier SAMP may supply the data voltage based on the image data updated in response to the latch signal SLATCH to the pixels in the area AREA2. The source amplifier SAMP may supply a current greater than the current amount when the mirror blocks 211 and 212 are disabled to the pixels in the area AREA2.

[0161] In the above example, the time interval tFSMR1 may be longer than the time interval tFSMR2. For example, the difference between the time interval tFSMR1 and the time interval tFSMR2 may be a multiple of the time during which one display clock remains at a logic high.

[0162] At time t5, the enable signal SOUTEN may transition to logic low. Thus, the output switch SOUTSW may be turned off. After time t5, the latch signal SLATCH input to the data latch circuit 121 of the source driver 120 may be triggered, thereby updating the data latch circuit 121 with new image data.

[0163] During a time interval tFSMR3 from time t5 , the enable signal FSMREN may correspond to (or maintain) logic high. The mirror blocks 211 and 212 may be enabled.

[0164] At time t6, the enable signal SOUTEN may transition to logic high. In this case, the output switch SOUTSW may be turned on, and thus, data voltages may begin to be supplied from the source amplifier SAMP to the pixels included in the area AREA3. For example, the source amplifier SAMP may supply data voltages based on image data updated in response to the latch signal SLATCH to the pixels in the area AREA3. The source amplifier SAMP may supply a current greater than the current amount when the mirror blocks 211 and 212 are disabled to the pixels in the area AREA3 (e.g., the pixels connected to the gate line GLm-2).

[0165] In the above example, similar to the relationship between the time interval tFSMR1 and the time interval tFSMR2 , the time interval tFSMR2 may be longer than the time interval tFSMR3 .

[0166] Similarly, the source driver 120 may sequentially supply data voltages for pixels of area AREA4 to area AREAi-3 from time t6 to time t7, and the time during which the enable signal FSMREN remains at logic high may gradually decrease with the transition from area AREA4 to area AREAi-3.

[0167] At time t7, the enable signal SOUTEN may transition to logic low. Thus, the output switch SOUTSW may be turned off. After time t7, the latch signal SLATCH input to the data latch circuit 121 of the source driver 120 may be triggered, thereby updating the data latch circuit 121 with new image data.

[0168] During the time interval tFSMRi-2 from time t7, the enable signal FSMREN may correspond to (or maintain) logic high. As such, the mirror blocks 211 and 212 may be enabled during the time interval tFSMRi-2. The mirror blocks 211 and 212 may be disabled in response to the enable signal FSMREN transitioning to logic low.

[0169] At time t8, the enable signal SOUTEN may transition to a logic high. In this case, the output switch SOUTSW may be turned on, and thus, the data voltage may begin to be supplied from the source amplifier SAMP to the pixels included in the area AREAi-2 (e.g., the pixels connected to the gate line GL2). For example, the source amplifier SAMP may supply the data voltage based on the image data updated in response to the latch signal SLATCH to the pixels in the area AREAi-2. The source amplifier SAMP may supply a current greater than the amount of current when the mirror blocks 211 and 212 are disabled to the pixels in the area AREAi-2. When the mirror blocks 211 and 212 are disabled after a time interval tFSMRi-2 has passed since time t7, the magnitude of the current output from the source amplifier SAMP may decrease, thereby preventing overshoot or undershoot of the data voltage.

[0170] At time t9, the enable signal SOUTEN may transition to logic low. Thus, the output switch SOUTSW may be turned off. After time t9, the latch signal SLATCH input to the data latch circuit 121 of the source driver 120 may be triggered, thereby updating the data latch circuit 121 with new image data.

[0171] During the time interval tFSMRi-1 from time t9, the enable signal FSMREN may correspond to (or maintain) logic high. As such, the mirror blocks 211 and 212 may be enabled during the time interval tFSMRi-1. The mirror blocks 211 and 212 may be disabled in response to the enable signal FSMREN transitioning to logic low.

[0172] At time t10, the enable signal SOUTEN may transition to a logic high. In this case, the output switch SOUTSW may be turned on, and thus, the data voltage may begin to be supplied from the source amplifier SAMP to the pixels included in the area AREAi-1 (e.g., the pixels connected to the gate line GL2). For example, the source amplifier SAMP may supply the data voltage based on the image data updated in response to the latch signal SLATCH to the pixels in the area AREAi-1. The source amplifier SAMP may supply a current greater than the amount of current when the mirror blocks 211 and 212 are disabled to the pixels in the area AREAi-1. When the mirror blocks 211 and 212 are disabled after a time interval tFSMRi-1 has passed since time t9, the magnitude of the current output from the source amplifier SAMP may decrease, thereby preventing overshoot or undershoot of the data voltage.

[0173] In the above example, similar to the relationship between the time interval tFSMR1 and the time interval tFSMR2 , the time interval tFSMRi- 2 may be longer than the time interval tFSMRi- 1 .

[0174] At time t11, the enable signal SOUTEN may transition to logic low. Thus, the output switch SOUTSW may be turned off. After time t11, the latch signal SLATCH input to the data latch circuit 121 of the source driver 120 may be triggered, thereby updating the data latch circuit 121 with new image data.

[0175] During the time interval tFSMRi from time t11, the enable signal FSMREN may correspond to (or maintain) logic high. Thus, the mirror blocks 211 and 212 may be enabled during the time interval tFSMRi. The mirror blocks 211 and 212 may be disabled in response to the enable signal FSMREN transitioning to logic low.

[0176] At time t12, the enable signal SOUTEN may transition to a logic high. In this case, the output switch SOUTSW may be turned on, and thus, data voltages may begin to be supplied from the source amplifier SAMP to the pixels included in the area AREAi (e.g., pixels connected to the gate line GL1). For example, the source amplifier SAMP may supply data voltages based on image data updated in response to the latch signal SLATCH to the pixels in the area AREAi. The source amplifier SAMP may supply a current greater than the amount of current when the mirror blocks 211 and 212 are disabled to the pixels in the area AREAi. When the mirror blocks 211 and 212 are disabled after a time interval tFSMRi has elapsed from time t11, the magnitude of the current output from the source amplifier SAMP may decrease, thereby preventing overshoot or undershoot of the data voltage.

[0177] In the above example, similar to the relationship between the time interval tFSMR1 and the time interval tFSMR2 , the time interval tFSMRi- 1 may be longer than the time interval tFSMRi.

[0178] During a frame, when transitioning from area AREA1 to area AREAi, the time during which mirror blocks 211 and 212 are enabled can be gradually reduced. Thus, the slew rate of the source amplifier SAMP (or the driving capability of the source amplifier SAMP's driving output) can be optimized. Consequently, the slew rate of the source amplifier SAMP associated with pixels located in an area away from the pad area PAD (i.e., pixels connected to a source line with a large load (e.g., large capacitance and / or large resistance)) can be improved. Furthermore, the output voltage VOUT of the source amplifier SAMP associated with pixels located in an area close to the pad area PAD (e.g., areas AREAi-2, AREAi-1, and AREAi) (i.e., pixels connected to a source line with a small load (e.g., small capacitance and / or small resistance)) can be prevented from unnecessarily overshooting or undershooting.

[0179] The time during which the enable signal FSMREN is maintained at logic high may decrease linearly across areas AREA1 to AREAi. For example, the difference between time interval tFSMR1 and time interval tFSMR2 and the difference between time interval tFSMR2 and time interval tFSMR3 may be the same.

[0180] In the implementation method ( Figure 7 (not shown in FIG), when the pixels of the area AREAi are selected, the mirror blocks 211 and 212 may not be enabled.

[0181] In another embodiment, when the first region and the second region are adjacent to each other, the difference between the time during which the enable signal FSMREN associated with the first region remains at logic high and the time during which the enable signal FSMREN associated with the second region remains at logic high may be uniform.

[0182] Figure 8 A block diagram of an electronic device 1000 according to an example embodiment is shown.

[0183] Reference Figure 8 , the electronic device 1000 may include a processor 1100, a memory 1200, a storage device 1300, a display device 1400, and a communication device 1500. The processor 1100, the memory 1200, the storage device 1300, the display device 1400, and the communication device 1500 may exchange data with each other through an internal bus.

[0184] The processor 1100 may control the overall operation of the electronic device 1000. The processor 1100 may execute various software, firmware, or program codes loaded on the memory 1200. The processor 1100 may serve as a central processing unit of the electronic device 1000. The processor 1100 may include one or more processor cores.

[0185] The memory 1200 may store data and program codes that are processed by the processor 1100 or that are scheduled to be processed by the processor 1100. For example, software, firmware, program codes, or instructions to be executed by the processor 1100 may be loaded onto the memory 1200. The memory 1200 may serve as a main storage device of the electronic device 1000. The memory 1200 may include dynamic random access memory (DRAM), static random access memory (SRAM), phase change random access memory (PRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FeRAM), resistive random access memory (RRAM), etc. The memory 1200 may also be referred to as a "buffer memory" or "cache memory." Unlike the example shown, the electronic device 1000 may include two or more memories 1200. Unlike the example shown, the memory 1200 may be implemented as an external device capable of communicating with the electronic device 1000.

[0186] The storage device 1300 can store data generated by the processor 1100 for long-term storage, files to be driven by the processor 1100, or various software, firmware, program codes, or instructions executable by the processor 1100. The storage device 1300 can be used as an auxiliary memory device for the electronic device 1000. The storage device 1300 can include a NAND flash memory, a NOR flash memory, or the like. Unlike the example shown, the electronic device 1000 can include two or more storage devices 1300. Unlike the example shown, the storage device 1300 can be implemented as an external device capable of communicating with the electronic device 1000.

[0187] The display device 1400 may provide an image to a user under the control of the processor 1100. For example, the display device 1400 may include the display device 10, wherein the display device 10 includes a display device 10 implemented therein. Figure 5 The mirror blocks 211 and 212 of the fast conversion block 200.

[0188] The communication device 1500 can communicate with external devices of the electronic device 1000 according to various wired or wireless protocols. For example, under the control of the processor 1100, the communication device 1500 can receive data from the external device or can transmit data stored in the memory 1200 or the storage device 1300 to the external device. The communication device 1500 may include a user interface that receives data from a user of the electronic device 1000 or outputs data to the user.

[0189] As described above, the source amplifier may include a fast switching block for supplying a higher current to the source line. The fast switching block may also include a mirror block for increasing the magnitude of the current to be output from the fast switching block. A frame may be divided into multiple regions arranged perpendicular to the source amplifier, and the time during which the mirror block is enabled may be set differently for each region. In this way, the slew rate of the source amplifier can be optimized according to the length of the source line from the source amplifier to each pixel.

[0190] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a generic and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art upon filing this application, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise specifically stated. Therefore, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A source amplifier configured to output a data voltage to a display panel based on a first driving voltage, a second driving voltage, a first input voltage, and a second input voltage, the source amplifier comprising: a first circuit configured to generate a first current, a second current, a third current, and a fourth current based on a first driving voltage, a second driving voltage, a first input voltage, and a second input voltage, and output a data voltage to an output terminal of the source amplifier based on the first current to the fourth current; as well as The second circuit is connected to the first circuit and is configured to supply a fifth current to the output terminal based on the first driving voltage, the second driving voltage, and the second input voltage. The second circuit includes: a first mirror circuit connected to the first terminal to which the first driving voltage is applied and configured to supply a sixth current to the output terminal; and a second mirror circuit connected to the second terminal to which the second driving voltage is applied and configured to supply a seventh current from the output terminal to the second terminal, and Wherein, the first mirror circuit includes: a first transistor connected between the first terminal and the second circuit, a second transistor connected between the first terminal and the gate of the first transistor, and The third transistor is connected between the gate of the first transistor and the second circuit.

2. The source amplifier according to claim 1 , wherein: The second transistor includes a gate to which the first enable signal is applied, The third transistor includes a gate to which a second enable signal is applied, and The first enable signal and the second enable signal are complementary.

3. The source amplifier according to claim 1, wherein The second circuit comprises: a fourth transistor connected between the first terminal and the first transistor; a fifth transistor connected between the gate of the fourth transistor and the output terminal; and a sixth transistor connected between the first terminal and the gate of the fourth transistor, The gate of the fourth transistor is connected to the third transistor.

4. The source amplifier according to claim 1, wherein: The second mirror circuit includes: a seventh transistor connected between the second circuit and the second terminal; an eighth transistor connected between the gate of the seventh transistor and the second terminal; and The ninth transistor is connected between the gate of the seventh transistor and the second circuit.

5. The source amplifier according to claim 4, wherein: The eighth transistor includes a gate to which the first enable signal is applied, The ninth transistor includes a gate to which a second enable signal is applied, and The first enable signal and the second enable signal are complementary.

6. The source amplifier according to claim 4, wherein: The second circuit comprises: a tenth transistor connected between the seventh transistor and the second terminal; an eleventh transistor connected between the output terminal and the gate of the tenth transistor; and a twelfth transistor connected between the gate of the tenth transistor and the second terminal, The gate of the tenth transistor is connected to the ninth transistor.

7. A display device comprising: a display panel comprising a plurality of pixels; as well as Display driver integrated circuit, the display driver integrated circuit includes: a gate driver connected to the plurality of pixels through the first to m-th gate lines and configured to enable the first to m-th gate lines; a source driver connected to the plurality of pixels through first to n-th source lines and comprising a plurality of source amplifiers respectively connected to the first to n-th source lines; and a logic block configured to generate signals for controlling the gate driver and the source driver, wherein: A first source amplifier among the plurality of source amplifiers includes a first circuit configured to output a first current to an output terminal of the first source amplifier by amplifying an input voltage, and a second circuit connected to the first circuit and configured to output a second current to the output terminal based on the input voltage, and The second circuit includes a third circuit configured to adjust the level of the second current in response to the enable signal, and Wherein, the third circuit includes: a first transistor connected between a first terminal to which a first driving voltage is applied and a second circuit; a second transistor connected between the first terminal and the gate of the first transistor; and The third transistor is connected between the gate of the first transistor and the second circuit.

8. The display device according to claim 7, wherein: The third circuit further comprises: a fourth transistor connected between the second circuit and the second terminal to which the second driving voltage is applied; a fifth transistor connected between the gate of the fourth transistor and the second terminal; and The sixth transistor is connected between the gate of the fourth transistor and the second circuit.

9. The display device according to claim 7, wherein: The second transistor includes a gate to which a first enable signal from the logic block is applied, The third transistor includes a gate to which a second enable signal from the logic block is applied, and The first enable signal and the second enable signal are complementary.

10. The display device according to claim 9, wherein: The display panel is divided into a plurality of regions along a first direction, the plurality of regions including a first region corresponding to a first gate line and a second region corresponding to a second gate line. When the first gate line is enabled by the gate driver, the first enable signal has a first duty cycle, When the second gate line is enabled by the gate driver, the first enable signal has a second duty cycle, The distance between the source driver and the first gate line is greater than the distance between the source driver and the second gate line, and The first duty cycle is greater than the second duty cycle.

11. The display device according to claim 9, wherein: The display panel is divided into a plurality of regions along a first direction, the plurality of regions including a first region corresponding to the first gate line and the second gate line and a second region corresponding to the third gate line and the fourth gate line. When one of the first gate line and the second gate line is enabled by the gate driver, the first enable signal has a first duty cycle, When one of the third gate line and the fourth gate line is enabled by the gate driver, the first enable signal has a second duty cycle, The distance between the source driver and the first gate line is longer than the distance between the source driver and the third gate line, and The first duty cycle is greater than the second duty cycle.

12. A display device comprising: a display panel comprising a plurality of pixels; as well as Display driver integrated circuit, the display driver integrated circuit includes: a gate driver connected to the plurality of pixels through the first to m-th gate lines and configured to enable the first to m-th gate lines; and A source driver is connected to the plurality of pixels through a first source line to an nth source line, and includes a plurality of source amplifiers respectively connected to the first source line to the nth source line, wherein: A first source amplifier among the plurality of source amplifiers comprises: a first circuit configured to generate first to fourth currents based on the first driving voltage, the second driving voltage, the first input voltage, and the second input voltage, and output a first data voltage to an output terminal of the first source amplifier based on the first to fourth currents; and a second circuit connected to the first circuit and configured to supply a fifth current to the output terminal based on the first driving voltage, the second driving voltage, and the second input voltage, and The second circuit comprises: a first mirror circuit connected to the first terminal to which the first driving voltage is applied and configured to supply a sixth current to the output terminal based on the first driving voltage; and a second mirror circuit configured to supply a seventh current from the output terminal to the second terminal to which the second driving voltage is applied, and Wherein, the first mirror circuit includes: a first transistor connected between the first terminal and the second circuit, a second transistor connected between the first terminal and the gate of the first transistor, and The third transistor is connected between the gate of the first transistor and the second circuit.

13. The display device according to claim 12, wherein: The second transistor includes a gate to which the first enable signal is applied, The third transistor includes a gate to which a second enable signal is applied, and The first enable signal and the second enable signal are complementary.

14. The display device according to claim 12, wherein: The second circuit comprises: a fourth transistor connected between the first terminal and the first transistor; a fifth transistor connected between the gate of the fourth transistor and the output terminal; and a sixth transistor connected between the first terminal and the gate of the fourth transistor, The gate of the fourth transistor is connected to the third transistor.

15. The display device according to claim 12, wherein: The second mirror circuit includes: a seventh transistor connected between the second circuit and the second terminal; an eighth transistor connected between the gate of the seventh transistor and the second terminal; and The ninth transistor is connected between the gate of the seventh transistor and the second circuit.

16. The display device according to claim 15, wherein: The eighth transistor includes a gate to which the first enable signal is applied, The ninth transistor includes a gate to which a second enable signal is applied, and The first enable signal and the second enable signal are complementary.

17. The display device according to claim 15, wherein: The second circuit comprises: a tenth transistor connected between the seventh transistor and the second terminal; an eleventh transistor connected between the output terminal and the gate of the tenth transistor; and a twelfth transistor connected between the gate of the tenth transistor and the second terminal, and The gate of the tenth transistor is connected to the ninth transistor.

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