Pixel circuit, method for driving pixel circuit, and display device

Abstract

Disclosed are a pixel circuit, a method for driving the pixel circuit, and a display device. The pixel circuit includes: a driving element including a first electrode connected to a first node, a first gate electrode connected to a second node, a second electrode connected to a third node, and a second gate electrode to which a preset voltage is applied; a light-emitting element including an anode electrode connected to a fourth node and a cathode electrode to which a low-potential power supply voltage is applied, the light-emitting element being driven according to a current from the driving element; a first switching element connected between the first node and the second node; and a second switching element connected between the third node and the fourth node. The present disclosure applies a preset voltage to the second gate electrode of the driving element, and the voltage applied between the second gate electrode and the source electrode of the driving element can shift the threshold voltage of the driving element to a voltage range that can be sensed.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2021-0089629, filed on July 8, 2021, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a pixel circuit, a method for driving the pixel circuit, and a display device. Background Art

[0004] Based on the material of the light-emitting layer, electroluminescent display devices are roughly divided into inorganic light-emitting display devices and organic light-emitting display devices. Active matrix organic light-emitting display devices include organic light-emitting diodes (hereinafter referred to as "OLEDs") that emit light themselves, and their advantages are fast response speed, high luminous efficiency, high brightness, and a wide viewing angle. In an organic light-emitting display device, an OLED is formed in each pixel. Organic light-emitting display devices not only have fast response speed, excellent luminous efficiency, brightness, and viewing angle, but also have excellent contrast and color reproduction because they can express black grayscale in full black.

[0005] The pixel circuit of an electroluminescent display device includes an OLED serving as a light-emitting element and a driver element for driving the OLED. The electrical characteristics of the driver element may change due to degradation of the driver element. In this case, the quality of the image reproduced on the screen deteriorates, so it is necessary to compensate for the electrical characteristics of the driver element. In particular, when the threshold voltage of the driver element shifts, it becomes difficult to sense the threshold voltage of the driver element when the shift range exceeds the voltage that can be sensed.

[0006] For example, in the case where a driver element is implemented as a transistor including an oxide semiconductor, if the threshold voltage of the transistor is close to 0 V, it is difficult to compensate for a shift in the threshold voltage of the driver element.

[0007] When the driving frequency of the display device increases or the resolution of the display device increases, one horizontal period becomes smaller. In this case, since the time for sensing and sampling the threshold voltage of the driving element is insufficient, the compensation performance deteriorates, making it difficult to achieve the brightness of the black grayscale. Summary of the Invention

[0008] The present disclosure is intended to address the above-mentioned needs and / or problems. The present disclosure provides a pixel circuit capable of accurately sampling the threshold voltage of a driving element, and also provides a method for driving the pixel circuit and a display device.

[0009] Problems to be solved by the present disclosure are not limited to the above-mentioned problems, and other unmentioned problems will be clearly understood by those skilled in the art from the following description.

[0010] According to an embodiment of the present disclosure, a pixel circuit includes: a driving element, wherein the driving element includes a first electrode connected to a first node, a first gate electrode connected to a second node, a second electrode connected to a third node, and a second gate electrode to which a preset voltage is applied; a light-emitting element, wherein the light-emitting element includes an anode electrode connected to a fourth node and a cathode electrode to which a low-potential power supply voltage is applied, and the light-emitting element is driven according to a current from the driving element; a first switching element, wherein the first switching element is connected between the first node and the second node; and a second switching element, wherein the second switching element is connected between the third node and the fourth node.

[0011] According to an embodiment of the present disclosure, a method for driving a pixel circuit includes a light-emitting element and a driving element, and the driving element has a first electrode, a second electrode, a first gate electrode, and a second gate electrode. The method includes: an initialization step of applying an initialization voltage to the first gate electrode of the driving element through the anode electrode of the light-emitting element and a first capacitor, and applying a pixel driving voltage higher than the initialization voltage to the first electrode of the driving element; a sampling step of applying a reference voltage lower than the pixel driving voltage to the second electrode of the driving element and applying it to the first electrode of the driving element through a second capacitor; an addressing step of applying a data voltage of pixel data to the first electrode of the driving element through the second capacitor; and a light-emitting step of forming a current path between the light-emitting element and a power line to which the pixel driving voltage is applied, and cutting off the initialization voltage and the reference voltage applied to the driving element and the light-emitting element.

[0012] In the initialization step, the sampling step, and the addressing step, the initialization voltage is applied to the second gate electrode of the driving element.

[0013] According to an embodiment of the present disclosure, a display device includes the pixel circuit. Specifically, the display device includes: a display panel, in which a plurality of data lines, a plurality of gate lines crossing the data lines, a first power line to which a pixel driving voltage is applied, a second power line to which an initialization voltage is applied, a third power line to which a reference voltage is applied, a fourth power line to which a low potential power supply voltage is applied, and a plurality of pixel circuits connected to the data lines, the gate lines, and the power lines; a data driver, the data driver providing a data voltage of pixel data to the data lines; and a gate driver, the gate driver providing a gate signal to the gate lines, wherein each of the pixel circuits includes: a driving element, the driving element including a first electrode connected to a first node, a first gate electrode connected to a second node, a second electrode connected to a third node, and a second gate electrode to which a preset voltage is applied; a light-emitting element, the light-emitting element including an anode electrode connected to a fourth node and a cathode electrode to which a low potential power supply voltage is applied, the light-emitting element being driven according to a current from the driving element; a first switching element, the first switching element connected between the first node and the second node; and a second switching element, the second switching element connected between the third node and the fourth node.

[0014] The present disclosure applies a preset voltage, such as an initialization voltage, to the second gate electrode of a driver element in an internal compensation circuit of a diode connection scheme, and thereby shifts the threshold voltage of the driver element to a voltage range that can be sensed using a voltage applied between the second gate electrode and the source electrode of the driver element. Consequently, by shifting the threshold voltage of the driver element, which has been shifted to a voltage of 0V or less, to a voltage that can be sensed, the present disclosure can sense the threshold voltage of the driver element and compensate for the threshold voltage of the driver element.

[0015] The present disclosure can reduce power consumption, improve the reliability of a display panel, and ensure the reliability of elements constituting a pixel circuit by using an oxide TFT whose threshold voltage is shifted to 0V or less as a driving element of a pixel circuit.

[0016] By separating the sampling step and the addressing step in the pixel circuit applying the internal compensation circuit, the present disclosure can ensure sufficient time required to sample the threshold voltage of the driving element, solve the problem of achieving black brightness and degradation of compensation performance, allow high-speed driving of the display device, and improve the image quality of high-resolution and high-speed driven display devices.

[0017] The effects of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art through the following description and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0019] Figure 1 is a block diagram illustrating a display device according to one embodiment of the present disclosure;

[0020] Figure 2 is a circuit diagram illustrating a pixel circuit according to one embodiment of the present disclosure;

[0021] Figure 3 It is a diagram used to verify that Figure 2 Graph showing simulation results of the effect of a threshold voltage shift Vbs on a driving element shown in FIG.

[0022] Figure 4 is a cross-sectional view schematically illustrating a cross-sectional structure of a driving element;

[0023] Figure 5 is a circuit diagram illustrating a pixel circuit according to another embodiment of the present disclosure;

[0024] Figure 6 It is a diagram for driving Figure 5 A waveform diagram of the method of the pixel circuit shown in ;

[0025] Figure 7 It is a diagram Figure 5 A circuit diagram of an initialization step of a pixel circuit shown in ;

[0026] Figure 8 It is a diagram Figure 5 A circuit diagram of a sampling step of a pixel circuit shown in ;

[0027] Figure 9 It is a diagram Figure 5 A circuit diagram of an addressing step of a pixel circuit shown in ; and

[0028] Figure 10 It is a diagram Figure 5 The circuit diagram of the light-emitting step of the pixel circuit shown in FIG. DETAILED DESCRIPTION

[0029] The advantages and features of the present disclosure and their implementation methods will be more clearly understood from the embodiments described below with reference to the accompanying drawings. However, the present disclosure is not limited to the following embodiments, but can be implemented in a variety of different forms. On the contrary, the present embodiments will complete the disclosure of the present disclosure and enable those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is limited only within the scope of the appended claims.

[0030] The shapes, sizes, proportions, angles, quantities, etc. shown in the accompanying drawings for describing the embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout this application, similar reference numerals generally represent similar elements. In addition, when describing the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0031] As used herein, terms such as "include," "comprising," "having," and "consisting of" are generally intended to allow for the addition of other components unless these terms are used with the term "only." Any reference to the singular may include the plural unless expressly stated otherwise.

[0032] Even if not explicitly stated, the components are interpreted as including the ordinary error range.

[0033] When terms such as “on,” “above,” “below,” and “next” are used to describe a positional relationship between two components, one or more components may be located between the two components unless these terms are used with the term “immediately” or “directly.”

[0034] Terms such as “first” and “second” may be used to distinguish components, but the function or structure of a component is not limited by the sequence number or name preceding the component.

[0035] Like reference numerals may refer to substantially like elements throughout this disclosure.

[0036] The following embodiments may be combined or combined with each other in part or in whole, and may be linked and operated in various technical ways. The embodiments may be performed independently or in association with each other.

[0037] Each pixel may include multiple sub-pixels with different colors to reproduce the colors of the image on the screen of the display panel. Each sub-pixel includes a transistor that serves as a switching element or driving element. Such a transistor can be implemented as a TFT (thin film transistor).

[0038] The driving circuit of the display device writes pixel data of the input image into the pixels on the display panel. To this end, the driving circuit of the display device may include a data driving circuit configured to provide data signals to the data lines, a gate driving circuit configured to provide gate signals to the gate lines, etc.

[0039] In the display device of the present disclosure, the pixel circuit and the gate driver circuit may include a plurality of transistors. The transistors may be implemented as oxide thin film transistors (oxide TFTs) including oxide semiconductors, low-temperature polysilicon (LTPS) TFTs including low-temperature polysilicon, and the like. In the embodiment, the example in which the transistors of the pixel circuit and the gate driver circuit are implemented as n-channel oxide TFTs will be described, but the present disclosure is not limited thereto.

[0040] Typically, a transistor is a three-electrode component consisting of a gate, a source, and a drain. The source is the electrode that supplies carriers to the transistor. In a transistor, carriers begin to flow out from the source. The drain is the electrode through which carriers exit the transistor. In a transistor, carriers flow from the source to the drain. In the case of an n-channel transistor, since the carriers are electrons, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. An n-channel transistor has a current flow direction from the drain to the source. In the case of a p-channel transistor (p-channel metal oxide semiconductor (PMOS)), since the carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In the case of a p-channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. It is important to note that the source and drain of a transistor are not fixed. For example, the source and drain can change depending on the applied voltage. Therefore, the present disclosure is not limited by the source and drain of the transistor.In the following description, the source and drain of the transistor will be referred to as a first electrode and a second electrode.

[0041] The gate signal swings between a gate-on voltage and a gate-off voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor.

[0042] The transistor is turned on in response to a gate-on voltage and turned off in response to a gate-off voltage. In the case of an n-channel transistor, the gate-on voltage may be a gate high voltage VGH or VEH, and the gate-off voltage may be a gate low voltage VGL or VEL.

[0043] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following embodiments, the display device will be described focusing on an organic light emitting display device, but the present disclosure is not limited thereto.

[0044] Reference Figure 1 , a display device according to an embodiment of the present disclosure includes: a display panel 100, a display panel driver for writing pixel data to pixels of the display panel 100, and a power supply 140 for generating power required to drive the pixels and the display panel driver.

[0045] The display panel 100 may be a rectangular display panel having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. The display panel 100 includes a pixel array that displays an input image on a screen. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 crossing the data lines 102, and pixels arranged in a matrix form. The display panel 100 may further include power lines commonly connected to the pixels. Figure 5 The power lines may include a first power line VDDL to which the pixel driving voltage VDD is applied, a second power line INL to which the initialization voltage Vinit is applied, and a third power line REFL to which the reference voltage Vref is applied. The display panel 100 may further include a fourth power line to which the low potential power voltage VSS is applied.

[0046] The pixel array includes a plurality of pixel rows L1 to Ln. Each of the pixel rows L1 to Ln includes a row of pixels arranged along the row direction X in the pixel array of the display panel 100. The pixels arranged in one pixel row share the same gate line 103. The sub-pixels arranged in the column direction Y along the data line direction share the same data line 102. One horizontal period 1H is the time obtained by dividing one frame period by the total number of pixel rows L1 to Ln.

[0047] The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device that displays an image on a screen with an actual background visible.

[0048] The display panel can be manufactured as a flexible display panel. The flexible display panel can be implemented as an OLED panel using a plastic substrate. The pixel array and light-emitting elements can be set on an organic thin film attached to the backplane of the plastic OLED panel.

[0049] An organic film may be provided on the backplane of the plastic OLED panel. Pixel circuits and light-emitting elements may be stacked on the organic film, and a touch sensor array may be formed on the pixel circuits and light-emitting elements. The backplane blocks moisture from penetrating toward the organic film, thereby preventing the pixel array from being exposed to moisture. The organic film may be a thin polyimide (PI) film substrate. A multilayer buffer film of an insulating material (not shown) may be formed on the organic film. Lines of the pixel array may be formed on the organic film to provide power or applied signals to the pixel circuits and the touch sensor array.

[0050] Each pixel 101 can be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel to realize color. Each pixel can further include a white sub-pixel. Each sub-pixel includes a pixel circuit. Hereinafter, a pixel can be interpreted as having the same meaning as a sub-pixel. Each pixel circuit is connected to a data line, a gate line, and a power line.

[0051] Pixels can be arranged as true color pixels and pentile pixels. Pentile pixels can achieve higher resolution than true color pixels by driving two sub-pixels with different colors as a single pixel 101 using a preset pixel rendering algorithm. The pixel rendering algorithm can compensate for insufficient color representation in each pixel using the color of light emitted from adjacent pixels.

[0052] The circuit layer of the display panel 100 may include a TFT array including pixel circuits connected to lines such as data lines, gate lines, power lines, etc., a demultiplexer array 112, a gate driver 120, etc. The wiring and circuit elements of the circuit layer may include multiple insulating layers, two or more metal layers separated by insulating layers therebetween, and an active layer including a semiconductor material. All transistors formed in the circuit layer 12 may be implemented as n-channel oxide TFTs.

[0053] A touch sensor may be provided on the display panel 100. A separate touch sensor may be used to sense touch input or the touch input may be sensed by pixels. The touch sensor may be provided as an on-cell type or an add-on type on the screen of the display panel, or may be implemented as an in-cell type touch sensor built into a pixel array.

[0054] The power supply 140 generates the DC power required to drive the pixel array and the display panel driver of the display panel 100 using a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply 140 can adjust the level of the DC input voltage applied from the host system (not shown) to generate DC voltages such as the gamma reference voltage VGMA, gate-on voltages VGH and VEH, gate-off voltages VGL and VEL, pixel driving voltage VDD, low-potential power supply voltage VSS, reference voltage Vref, and initialization voltage Vinit. The gamma reference voltage VGMA is provided to the data driver 110. The gate-on voltages VGH and VEH and the gate-off voltages VGL and VEL are provided to the gate driver 120. The pixel driving voltage VDD, low-potential power supply voltage VSS, reference voltage Vref, and initialization voltage Vinit are commonly provided to the pixels. The reference voltage Vref and initialization voltage Vinit can be generated by the data driver 110.

[0055] The display panel driver writes pixel data of an input image into pixels of the display panel 100 under the control of a timing controller (TCON) 130 .

[0056] The display panel driver includes a data driver 110 and a gate driver 120. The display panel driver may further include a demultiplexer array 112 disposed between the data driver 110 and the data lines 102.

[0057] The demultiplexer array 112 sequentially connects the channels of the data driver 110 to the data lines 102 by using a plurality of demultiplexers (DEMUX) to transmit the data voltage output from the data driver 110 to the data lines 102. The demultiplexer array 112 may include a plurality of switching elements provided on the display panel 100. When the demultiplexer array 112 is provided between the output terminal of the data driver 110 and the data lines 102, the number of channels of the data driver 110 may be reduced. The demultiplexer array 112 may be omitted.

[0058] The display panel driver may further include a touch sensor driver for driving the touch sensor. Figure 1 The touch sensor driver is omitted. The data driver and touch sensor driver can be integrated into one driver integrated circuit (IC). In a mobile device or wearable device, the timing controller 130, power supply 140, data driver 110, etc. can be integrated into one driver IC.

[0059] The display panel driver may operate in a low-speed drive mode under the control of the timing controller 130. When the input image does not change a preset number of frames under analysis of the input image, the low-speed drive mode may be set to reduce the power consumption of the display device. In the low-speed drive mode, when a still image is input for a predetermined time or longer, the power consumption of the display panel driver and the display panel 100 may be reduced by reducing the refresh rate of the pixels. The low-speed drive mode is not limited to the case where a still image is input. For example, when the display device is operating in a standby mode, or when no user command or input image is input to the display panel driver circuit for a predetermined time or longer, the display panel driver circuit may operate in a low-speed drive mode.

[0060] The data driver 110 generates data voltages by converting pixel data of an input image received as a digital signal from the timing controller 130 using a digital-to-analog converter (DAC) in each frame period using a gamma compensation voltage. The gamma reference voltage VGMA is divided into gamma compensation voltages for each grayscale by a voltage divider circuit. The gamma compensation voltage for each grayscale is provided to the DAC of the data driver 110. The data voltages are output through an output buffer in each channel of the data driver 110.

[0061] The gate driver 120 can be implemented as a gate-in-panel (GIP) circuit directly formed on the display panel 100 along with the TFT array and wiring of the pixel array. The GIP circuit can be provided in the bezel (BZ) area of the display panel 100, which serves as a non-display area, or can be dispersed throughout the pixel array that reproduces an input image. Under the control of the timing controller 130, the gate driver 120 sequentially outputs gate signals to the gate lines 103. The gate driver 120 can sequentially provide the gate signals to the gate lines 103 by shifting the gate signals using a shift register. The gate signals may include scan signals and emission control signals (hereinafter referred to as "EM signals") in an organic light emitting diode display. The scan signals include scan pulses that swing between a gate-on voltage (VGH) and a gate-off voltage (VGL). The EM signals may include EM pulses that swing between a gate-on voltage (VEH) and a gate-off voltage (VEL).

[0062] The scan pulse is synchronized with the data voltage to select the pixels of the row to be written with data. The EM signal defines the light emission time of the pixels.

[0063] The gate driver 120 may include a first gate driver 121 and a second gate driver 122. The first gate driver 121 outputs a scan pulse in response to a start pulse and a shift clock from the timing controller 130, and shifts the scan pulse according to the shift clock. The second gate driver 122 outputs an EM pulse in response to a start pulse and a shift clock from the timing controller 130, and sequentially shifts the EM pulse according to the shift clock.

[0064] The timing controller 130 receives digital video data DATA of an input image and timing signals synchronized therewith from the host system. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock CLK, a data enable signal DE, and the like. Because the vertical and horizontal periods can be determined by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted. The data enable signal DE has a period of one horizontal period (1H).

[0065] The host system may be a television (TV) system, a tablet computer, a laptop computer, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, or an in-vehicle system. The host system may scale the image signal from the video source to fit the resolution of the display panel 100 and transmit it along with the timing signal to the timing controller 130.

[0066] The timing controller 130 multiplies the input frame frequency by i ("i" is a natural number) and controls the operation timing of the display panel driver at a frame frequency of input frame frequency × i Hz. The input frame frequency is 60 Hz in the NTSC (National Television Standards Committee) scheme and 50 Hz in the PAL (Phase Alternation Line) scheme. In order to reduce the refresh rate of the pixels in the low-speed drive mode, the timing controller 130 can reduce the driving frequency of the display panel driver by reducing the frame frequency to a frequency between 1 Hz and 30 Hz.

[0067] Based on the timing signals Vsync, Hsync, and DE received from the host system, the timing controller 130 generates data timing control signals for controlling the operation timing of the data driver 110, MUX signals MUX1 and MUX2 for controlling the operation timing of the demultiplexer array 112, and gate timing control signals for controlling the operation timing of the gate driver 120. By controlling the operation timing of the display panel driver, the timing controller 130 synchronizes the data driver 110, the demultiplexer array 112, the touch sensor driver, and the gate driver 120.

[0068] The voltage levels of the gate timing control signals output from the timing controller 130 can be converted into gate-on voltages VGH and VEH and gate-off voltages VGL and VEL by a level converter (not shown) and then provided to the gate driver 120. The level converter converts the low-level voltage of the gate timing control signal into the gate-off voltages VGL and VEL, and converts the high-level voltage of the gate timing control signal into the gate-on voltages VGH and VEH. The gate timing control signal includes a start pulse and a shift clock.

[0069] Due to the device characteristic deviation and process deviation caused during the manufacturing process of the display panel 100, there may be differences in the electrical characteristics of the driving elements between pixels, and this difference may increase as the driving time of the pixels passes. In order to compensate for the differences in the electrical characteristics of the driving elements between pixels, internal compensation technology or external compensation technology may be applied to the organic light emitting diode display. The internal compensation technology samples the threshold voltage of the driving element of each sub-pixel by using an internal compensation circuit implemented in each pixel circuit, and compensates the gate-source voltage Vgs of the driving element by the threshold voltage. The external compensation technology senses the current or voltage of the driving element that changes according to the electrical characteristics of the driving element in real time by using an external compensation circuit. The external compensation technology compensates for the deviation (or change) of the electrical characteristics of the driving element in each pixel in real time by modulating the pixel data (digital data) of the input image with the deviation (or change) of the electrical characteristics of the driving element sensed for each pixel. The display panel driver may drive pixels using external compensation technology and / or internal compensation technology. The pixel circuit may be implemented as a circuit to which an internal compensation circuit is applied, for example, Figures 5 to 10 The circuit shown in .

[0070] Figure 2 is a circuit diagram illustrating a pixel circuit according to one embodiment of the present disclosure.

[0071] Reference Figure 2 The pixel circuit includes a light emitting element EL, a driving element DT for driving the light emitting element EL, a first switching element T1 connected between a first gate electrode G1 and a first electrode D of the driving element DT, and a second switching element T2 connected between a second electrode S of the driving element DT and the light emitting element EL. The driving element DT and the switching elements T1 and T2 may be implemented as n-channel oxide TFTs.

[0072] The light-emitting element EL can be implemented as an OLED. The OLED includes an organic compound layer formed between an anode electrode and a cathode electrode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), a light-emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When a voltage is applied to the anode electrode and the cathode electrode of the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the light-emitting layer (EML) to form excitons, thereby emitting visible light from the light-emitting layer (EML). The OLED used as the light-emitting element EL may have a series structure in which multiple light-emitting layers are stacked. The OLED with a series structure can improve the brightness and lifespan of the pixel.

[0073] The driving element DT may be a MOSFET having a dual-gate structure including a first gate electrode G1 and a second gate electrode G2. The second gate electrode G2 may be a bulk electrode. The first gate electrode G1 and the second gate electrode G2 may overlap with each other with a semiconductor active pattern therebetween. A predetermined voltage, such as an initialization voltage Vinit, which will be described later, may be applied to the second gate electrode G2.

[0074] A voltage Vbs between the second gate electrode G2 of the driving element DT and the second electrode S of the driving element DT can shift the threshold voltage of the driving element DT to a desired voltage. The first electrode may be a drain electrode, and the second electrode may be a source electrode. Hereinafter, the voltage between the second gate electrode G2 of the driving element DT and the second electrode S of the driving element DT is referred to as "Vbs."

[0075] The first switching element T1 includes a first electrode connected to the first electrode D of the driving element DT, a second electrode connected to the first gate electrode G1 of the driving element DT, and a gate electrode to which a scan pulse is applied. The first switching element T1 is turned on in response to the gate-on voltage VGH of the scan pulse and is turned off in response to the gate-off voltage VGL. When the first switching element T1 is turned on, the driving element DT operates as a diode due to the connection between the first gate electrode G1 and the first electrode D. When the first switching element T1 is turned off, the first gate electrode G1 of the driving element DT is separated from the first electrode D.

[0076] The second switching element T2 includes a first electrode connected to the second electrode S of the driving element DT, a second electrode connected to the anode electrode of the light-emitting element EL, and a gate electrode to which an EM pulse is applied. The second switching element T2 is turned on in response to a gate-on voltage VEH of the EM pulse and turned off in response to a gate-off voltage VEL. When the second switching element T2 is turned on, a current path is formed between the driving element DT and the light-emitting element EL, thereby supplying current to the light-emitting element EL. When the second switching element T2 is turned off, the current path between the driving element DT and the light-emitting element EL is cut off.

[0077] exist Figure 3 In FIG, the horizontal axis represents the gate-source voltage Vgs[V] of the driving element DT, and the vertical axis represents the drain-source current Ids[A] of the driving element DT. When sensing the threshold voltage of the driving element DT, Vbs can shift the threshold voltage of the driving element DT to a range that can be sensed, such as Figure 3 As shown in . Therefore, even if the threshold voltage of the driving element DT shifts beyond the range that can be sensed, the threshold voltage of the driving element DT can be accurately sensed. For example, if the threshold voltage of the driving element DT shifts to a voltage of 0V or less, the threshold voltage of the driving element DT cannot be sensed. However, using Vbs, the threshold voltage of the driving element DT can shift to a positive voltage higher than 0V. The degree of the threshold voltage shift of the driving element DT depends on Vbs, the parasitic capacitance connected to the first gate electrode G1 ( Figure 4 Cgi in) and the parasitic capacitance connected to the second gate electrode G2 ( Figure 4 Cbuf in ), so that the threshold voltage of the driving element can be shifted to the desired voltage.

[0078] When the reference voltage Vref is applied to the first gate electrode G1 of the driving element DT and the initialization voltage Vinit is applied to the second gate electrode G2, the voltage of the first gate electrode G1 may be Figure 2Vref+Vth' in Vbs. Vref is a reference voltage, and Vth' is a threshold voltage of the driving element DT shifted by Vbs. In this case, if Vref>Vinit, the threshold voltage of the driving element DT may shift to a positive voltage.

[0079] Figure 4 is a cross-sectional view schematically illustrating a cross-sectional structure of a driving element DT in the display panel 100 .

[0080] Reference Figure 4 A first metal pattern may be formed on a substrate GLS of the display panel 100. The first metal pattern may include a light shielding layer LS integral with the second gate electrode G2 of the driving element DT. The light shielding layer LS blocks light irradiated to the semiconductor active pattern ACT of the driving element DT to prevent a threshold voltage shift of the driving element DT, and is applied with an initialization voltage Vinit.

[0081] A first insulating layer BUF may be formed on the substrate GLS to cover the first metal pattern, and a semiconductor layer may be formed on the first insulating layer BUF. The semiconductor layer includes a semiconductor active pattern ACT of the driving element DT.

[0082] A second insulating layer GI may be formed on the first insulating layer BUF to cover the semiconductor pattern. A second metal pattern may be formed on the second insulating layer GI. The second metal pattern may include the first gate electrode G1 of the driving element DT.

[0083] A third insulating layer ILD may be formed on the second insulating layer GI to cover the second metal pattern. A third metal pattern may be formed on the third insulating layer ILD. The third metal pattern may include the first electrode D and the second electrode S of the driving element DT.

[0084] exist Figure 4 In , “Cgi” is a parasitic capacitance formed between the first gate electrode G1 and the semiconductor active pattern ACT in the driving element DT, and “Cbuf” is a parasitic capacitance formed between the second gate electrode G2 and the semiconductor active pattern ACT in the driving element DT.

[0085] Figure 5 is a circuit diagram illustrating a pixel circuit according to another embodiment of the present disclosure. Figure 5 The pixel circuit shown in FIG. 4 includes an internal compensation circuit that samples the threshold voltage of the driving element DT and compensates for variations in the threshold voltage of the driving element DT. Figure 6 It is a diagram for driving Figure 5 The waveform diagram of the pixel circuit method shown in FIG.

[0086] Reference Figure 5 and Figure 6The pixel circuit includes a light emitting element EL, a driving element DT, a first capacitor C1, a second capacitor C2, and first to seventh switching elements T1 to T7. The driving element DT and the switching elements T1 to T7 may be implemented as n-channel oxide TFTs.

[0087] This pixel circuit includes DC voltages such as a pixel drive voltage VDD, a low-potential power supply voltage VSS, a reference voltage Vref, and an initialization voltage Vinit; a data voltage Vdata that varies according to the grayscale of the pixel data; scan pulses SC1, SC2, and SC3; and EM pulses EM1 and EM2. The voltages of the scan pulses SC1, SC2, and SC3 and the EM pulses EM1 and EM2 swing between gate-on voltages VGH and VEH and gate-off voltages VGL and VEL.

[0088] The voltage relationship generally applied to a pixel can be set as VDD > Vref > Vinit > VSS. The data voltage Vdata can be generated as a gamma compensation voltage selected according to the grayscale of the pixel data from the data driver 110 within a voltage range lower than the pixel driving voltage VDD and higher than the low potential power supply voltage VSS. The gate-on voltages VGH and VEH can be set higher than the pixel driving voltage VDD. The gate-off voltages VGL and VEL can be set lower than the low potential power supply voltage VSS.

[0089] The scan pulses SC1, SC2, and SC3 may include a first scan pulse SC1 applied to the first gate line GL1, a second scan pulse SC2 applied to the second gate line GL2, and a third scan pulse SC3 applied to the third gate line GL3. The EM pulses EM1 and EM2 may include a first EM pulse EM1 applied to the fourth gate line GL4 and a second EM pulse EM2 applied to the fifth gate line GL5.

[0090] The driving period of the pixel circuit can be divided into an initialization step INIT for initializing the pixel circuit, a sampling step SMPL for sampling the threshold voltage Vth of the driving element DT, an addressing step ADDR for charging the data voltage Vdata and writing the pixel data, and an emission step EMIS for the light-emitting element EL to emit light with a brightness corresponding to the grayscale of the pixel data.

[0091] During the initialization step INIT, the sampling step SMPL, and the addressing step ADDR, the voltage of the first scan pulse SC1 may be the gate-on voltage VGH. During the light-emitting step EMIS, the voltage of the first scan pulse SC1 may be the gate-off voltage VGL. The second scan pulse SC2 may rise later than the first scan pulse SC1 and fall earlier than the first scan pulse SC1. During the sampling step SMPL, the voltage of the second scan pulse SC2 may be the gate-on voltage VGH. During the initialization step INIT, the addressing step ADDR, and the light-emitting step EMIS, the voltage of the second scan pulse SC2 may be the gate-off voltage VGL. The third scan pulse SC3 is synchronized with the data voltage Vdata. During the addressing step ADDR, the voltage of the third scan pulse SC3 may be the gate-on voltage VGH. During the initialization step INIT, the sampling step SMPL, and the light-emitting step EMIS, the voltage of the third scan pulse SC3 may be the gate-off voltage VGL.

[0092] During at least a portion of the initialization step INIT and at least a portion of the emission step EMIS, the first EM pulse EM1 may be generated at the gate-on voltage VEH. During the sampling step INIT and the addressing step ADDR, the voltage of the first EM pulse EM1 may be the gate-off voltage VEL. During at least a portion of the emission step EMIS, the second EM pulse EM2 may be generated at the gate-on voltage VEH. During the initialization step INIT, the sampling step INIT, and the addressing step ADDR, the voltage of the second EM pulse EM2 may be the gate-off voltage VEL. The second EM pulse EM2 may rise to the gate-on voltage VGH earlier than the first EM pulse EM1 at the start of the emission step EMIS, or may rise to the gate-on voltage VGH simultaneously with the first EM pulse EM1.

[0093] In the address step ADDR, a data voltage Vdata of pixel data is supplied to the pixel circuit through the data line DL in synchronization with the third scan pulse SC3.

[0094] The light emitting element EL may be implemented as an OLED. An anode electrode of the light emitting element EL may be connected to the fourth node n4, and a low potential power supply voltage VSS may be applied to a cathode electrode of the light emitting element EL.

[0095] The first capacitor C1 is connected between the second node n2 and the fourth node n4. The first capacitor C1 is a storage capacitor that maintains the gate-source voltage Vgs of the driving element DT during the light emission step EMIS. The second capacitor C2 is connected between the first node n1 and the fifth node n5. The second capacitor C2 transmits the reference voltage Vref and the data voltage Vdata to the first node n1.

[0096] The driving element DT may be a MOSFET having a dual-gate structure. The driving element DT includes a first gate electrode connected to the second node n2, a second gate electrode connected to the fourth node n4, a first electrode connected to the first node n1, and a second electrode connected to the third node n3. Figure 4 As shown in , the first gate electrode and the second gate electrode of the driving element DT may overlap each other with a semiconductor active pattern therebetween.

[0097] The first switching element T1 includes a first electrode connected to a first node n1, a second electrode connected to a second node n2, and a gate electrode to which a first scan pulse SC1 is applied. During the initialization step INIT, the sampling step SMPL, and the addressing step ADDR, the first switching element T1 is turned on in response to a gate-on voltage VGH of the first scan pulse SC1 and connects the first node n1 to the second node n2. When the first switching element T1 is turned on, the driving element DT operates as a diode due to the connection between the first gate electrode G1 and the first electrode.

[0098] The second switching element T2 includes a first electrode connected to the third node n3, a second electrode connected to the fourth node n4, and a gate electrode to which the second EM pulse EM2 is applied. During at least a portion of the light-emitting step EMIS, the second switching element T2 is turned on in response to the gate-on voltage VEH of the second EM pulse EM2, thereby forming a current path between the driving element DT and the light-emitting element EL. During the initialization step INIT, the sampling step SMPL, and the addressing step ADDR, the second switching element T2 is in an off state, and the current path between the driving element DT and the light-emitting element EL is cut off, so that the light-emitting element EL does not emit light.

[0099] The third switching element T3 includes a first electrode connected to the second power line INL to which the initialization voltage Vinit is applied, a second electrode connected to the fourth node n4, and a gate electrode to which the first scan pulse SC1 is applied. During the initialization step INIT, the sampling step SMPL, and the addressing step ADDR, the third switching element T3 is turned on in response to the gate-on voltage VGH of the first scan pulse SC1 and supplies the initialization voltage Vinit to the fourth node n4. During the light-emitting step EMIS, the third switching element T3 is turned off, and the current path between the second power line INL and the fourth node n4 is cut off.

[0100] The fourth switching element T4 includes a first electrode connected to the fifth node n5, a second electrode connected to the data line DL to which the data voltage Vdata of the pixel data is applied, and a gate electrode to which the third scan pulse SC3 is applied. During the addressing step ADDR, the fourth switching element T4 is turned on in response to the gate-on voltage VGH of the third scan pulse SC3 and supplies the data voltage Vdata to the fifth node n5. During the initialization step INIT, the sampling step SMPL, and the light-emitting step EMIS, the fourth switching element T4 is turned off, and the current path between the data line DL and the fifth node n5 is cut off.

[0101] The fifth switching element T5 includes a first electrode connected to a first power line VDDL to which a pixel driving voltage VDD is applied, a second electrode connected to a first node n1, and a gate electrode to which a first EM pulse EM1 is applied. During the initialization step INIT and the light-emitting step EMIS, the fifth switching element T5 is turned on in response to a gate-on voltage VEH of the first EM pulse EM1 and supplies the pixel driving voltage VDD to the first node n1. During the sampling step SMPL and the addressing step ADDR, the fifth switching element T5 is turned off, thereby cutting off the current path between the first power line VDDL and the first node n1.

[0102] The sixth switching element T6 includes a first electrode connected to the third power line REFL to which the reference voltage Vref is applied, a second electrode connected to the third node n3, and a gate electrode to which the second scan pulse SC2 is applied. During the sampling step SMPL, the sixth switching element T6 is turned on in response to the gate-on voltage VGH of the second scan pulse SC2 and supplies the reference voltage Vref to the third node n3. During the initialization step INIT, the addressing step ADDR, and the light-emitting step EMIS, the sixth switching element T6 is turned off, and the current path between the third power line REFL and the third node n3 is cut off.

[0103] The seventh switching element T7 includes a first electrode connected to the fifth node n5, a second electrode connected to the third node n3, and a gate electrode to which the second scan pulse SC2 is applied. During the sampling step SMPL, the seventh switching element T7 is turned on in response to the gate-on voltage VGH of the second scan pulse SC2 and connects the fifth node n5 to the third node n3. When the seventh switching element T7 is turned on, the reference voltage Vref is applied to the fifth node n5, and the reference voltage Vref is applied to the first node n1 via the second capacitor C2. During the initialization step INIT, the addressing step ADDR, and the light-emitting step EMIS, the seventh switching element T7 is turned off, and the current path between the third node n3 and the fifth node n5 is cut off.

[0104] The threshold voltage Vth of the driving element DT can be sampled by applying the data voltage Vdata to the gate electrode of the driving element DT. In this case, because the threshold voltage sampling and data addressing of the driving element DT are performed simultaneously, the sampling time is limited to one horizontal period (1H). On the other hand, in the present disclosure, the threshold voltage Vth' of the driving element DT is sampled by applying the reference voltage Vref to the third node n3 in the sampling step SMPL and stored in the capacitor C1, and the data voltage Vdata is applied to the first node n1 in the addressing step ADDR, making the sampling step SMPL and the addressing step ADDR separable. As a result, according to the present disclosure, by ensuring a sufficiently long sampling step SMPL, for example, two or more horizontal periods, the threshold voltage Vth of the driving element DT can be accurately sensed, thereby compensating for any shift in the threshold voltage Vth'.

[0105] During the EMIS, the initialization voltage Vinit applied to the second gate electrode of the driving element DT is substantially the same as the source voltage of the driving element DT. Therefore, during the EMIS, the threshold voltage of the driving element DT is not shifted by the voltage of the second gate electrode of the driving element DT.

[0106] like Figure 7 and Figure 8 As shown in FIG, in the initialization step INIT, the initialization voltage Vinit is applied to the first gate electrode of the driving element DT through the anode electrode of the light emitting element EL and the first capacitor C1, and the pixel driving voltage VDD higher than the initialization voltage Vinit is applied to the first electrode of the driving element DT. In the sampling step SMPL, the reference voltage Vref lower than the pixel driving voltage VDD is applied to the second electrode of the driving element DT and is applied to the first electrode of the driving element DT through the second capacitor C2.

[0107] In the addressing step ADDR, the data voltage Vdata of the pixel data is applied to the first electrode of the driving element DT through the second capacitor C2. In the light-emitting step EMIS, a current path is formed between the light-emitting element EL and the power line to which the pixel driving voltage VDD is applied, and the initialization voltage Vinit and the reference voltage Vref applied to the driving element DT and the light-emitting element EL are also cut off.

[0108] In the initialization step INIT, the sampling step SMPL, and the addressing step ADDR, the initialization voltage Vinit is applied to the second gate electrode of the driving element DT. Due to the initialization voltage Vinit applied to the second gate electrode of the driving element DT in the initialization step INIT and the sampling step SMPL, the threshold voltage of the driving element DT may shift to a voltage higher than 0 V. The initialization voltage Vinit is set to a voltage higher than 0 V.

[0109] In the following, reference will be made to Figures 7 to 10 A step-by-step driving method of a pixel circuit is described in detail.

[0110] Figure 7 It is a diagram Figure 5 . The circuit diagram of the initialization step INIT of the pixel circuit is shown in FIG.

[0111] Reference Figure 7 During the initialization step INIT, the first switching element T1 and the fifth switching element T5 are turned on, thereby diode-connecting the first gate electrode and the first electrode of the driving element DT. At this point, the voltage at the first node n1 is initialized to the pixel driving voltage VDD, and the voltage at the third node n3 is initialized to the initialization voltage Vinit, thereby turning on the driving element DT. Vth' is the threshold voltage of the driving element DT, which is offset by the initialization voltage Vinit applied to the second gate electrode of the driving element DT. During the initialization step INIT, the third switching element T3 is also turned on. Therefore, the light-emitting element EL is turned off due to the initialization voltage Vinit, which is lower than its threshold voltage, being applied to the anode electrode. During the initialization step INIT, the second switching element T2, the sixth switching element T6, and the seventh switching element T7 are turned off.

[0112] Figure 8 It is a diagram Figure 5 The sampling steps of the pixel circuit are shown in the circuit diagram of SMPL.

[0113] Reference Figure 8 During the sampling step SMPL, the first switching element T1, the third switching element T3, and the driving element DT remain in an on state. During the sampling step SMPL, the sixth switching element T6 and the seventh switching element T7 are turned on, so that the reference voltage Vref is applied to the third node n3 and the fifth node n5. At this time, the voltage at the first node n1 changes to Vref + Vth', and the fourth node n4 maintains the initialization voltage Vinit. During the sampling step SMPL, the threshold voltage Vth' of the driving element DT is sampled and stored in the first capacitor C1. During the sampling step SMPL, the second switching element T2 remains in an off state, and the fifth switching element T5 is turned off.

[0114] Figure 9It is a diagram Figure 5 The circuit diagram of the addressing step ADDR of the pixel circuit is shown in FIG.

[0115] Reference Figure 9 During the addressing step ADDR, the first switching element T1, the third switching element T3, the fourth switching element T4, and the driving element DT remain in the on state. During the addressing step ADDR, the voltage of the first node n1 changes to Vref+Vth'+C'(Vdata+Vref), and the fourth node n4 maintains the initialization voltage Vinit. Here, C' is C2 / (C1+C2). During the addressing step ADDR, the second switching element T2 and the fifth switching element T5 remain in the off state, and the sixth switching element T6 and the seventh switching element T7 are turned off.

[0116] Figure 10 It is a diagram Figure 5 The light-emitting steps of the pixel circuit are shown in the circuit diagram of EMIS.

[0117] Reference Figure 10 In the light-emitting step EMIS, the second switching element T2 and the fifth switching element DT are turned on, while the first switching element T1, the third switching element T3, and the fourth switching element T4 are turned off. In the light-emitting step EMIS, the sixth switching element T6 and the seventh switching element T7 remain in the off state. At this time, a current is supplied to the light-emitting element EL based on the gate-source voltage Vgs of the driving element DT, allowing the light-emitting element EL to turn on. In the light-emitting step EMIS, the voltage at the fourth node n4 is the anode voltage Vel of the light-emitting element DT, and the voltage at the second node n2 applied to the first gate electrode of the driving element DT is Vref + Vth' + C' (Vdata - Vref) + Vel.

[0118] In the light emitting step EMIS, the current Ioled flowing through the light emitting element EL is k[(Vref-Vinit)+C'(Vdata-Vref)+(Vth'-Vth)] 2 Here, k is a constant value determined according to the mobility and parasitic capacitance of the driving element DT, and Vth is an initial threshold voltage when Vbs of the driving element DT is zero.

[0119] The objects to be achieved by the present disclosure, means for achieving the objects, and effects of the present disclosure described above do not specify essential features of the claims, and thus the scope of the claims is not limited to the disclosure of the present disclosure.

[0120] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above-mentioned embodiments are exemplary in all aspects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the attached claims, and all technical concepts within their equivalent scope should be understood to fall within the scope of protection of the present disclosure.

Claims

1. A pixel circuit, comprising: a driving element including a first electrode connected to the first node, a first gate electrode connected to the second node, a second electrode connected to the third node, and a second gate electrode connected to the fourth node; a light emitting element including an anode electrode connected to the fourth node and a cathode electrode to which a low-potential power supply voltage is applied, the light emitting element being driven by the current from the driving element; a first switching element connected between the first node and the second node; a second switching element connected between the third node and the fourth node; as well as a third switching element connected to the fourth node and applying a preset voltage to the fourth node. 2 . The pixel circuit according to claim 1 , wherein a threshold voltage of the driving element is shifted to a positive voltage higher than 0 V by a voltage between the second gate electrode and the second electrode.

3. The pixel circuit according to claim 1 , further comprising: a fourth switching element including a first electrode connected to the fifth node, a second electrode to which a data voltage of pixel data is applied, and a gate electrode to which a third scan pulse is applied; a fifth switching element, the fifth switching element including a first electrode to which a pixel driving voltage is applied, a second electrode connected to the first node, and a gate electrode to which a first EM pulse is applied; a sixth switching element including a first electrode to which a reference voltage is applied, a second electrode connected to the third node, and a gate electrode to which a second scan pulse is applied; as well as a seventh switching element including a first electrode connected to the fifth node, a second electrode connected to the third node, and a gate electrode to which the second scan pulse is applied, wherein the first switching element includes a first electrode connected to the first node, a second electrode connected to the second node, and a gate electrode to which a first scan pulse is applied, and The second switching element includes a first electrode connected to the third node, a second electrode connected to the fourth node, and a gate electrode to which a second EM pulse is applied. The third switching element includes a first electrode to which an initialization voltage is applied, a second electrode connected to the fourth node, and a gate electrode to which the first scan pulse is applied. The preset voltage is set as the initialization voltage.

4. The pixel circuit according to claim 3, further comprising: a first capacitor connected between the second node and the fourth node; and A second capacitor is connected between the first node and the fifth node.

5. The pixel circuit according to claim 3 , wherein the driving element and the switching element include an n-channel oxide semiconductor, and Each of the switching elements is turned on in response to a gate-on voltage. 6 . The pixel circuit according to claim 5 , wherein when the initialization voltage is applied to the second gate electrode of the driving element, a threshold voltage of the driving element shifts to a positive voltage higher than 0V.

7. The pixel circuit according to claim 5 , wherein when the pixel driving voltage is VDD, the reference voltage is Vref, the initialization voltage is Vinit, and the low potential power supply voltage is VSS, these voltages are set to VDD>Vref>Vinit>VSS. The data voltage of the pixel data is lower than the pixel driving voltage and higher than the low potential power supply voltage, and Each of the scan pulse and the EM pulse swings between a gate-on voltage higher than the pixel driving voltage and a gate-off voltage lower than the low-potential power supply voltage.

8. The pixel circuit according to claim 7 , wherein the pixel circuit is driven in an initialization step, a sampling step after the initialization step, an addressing step of applying the data voltage after the sampling step, and a light emitting step after the addressing step, The first scanning pulse is generated as a gate-on voltage in the initialization step, the sampling step, and the addressing step, and the first scanning pulse is generated as a gate-off voltage in the light emitting step, The second scanning pulse is generated as a gate-on voltage in the sampling step, and the second scanning pulse is generated as a gate-off voltage in the initialization step, the addressing step, and the light emitting step, The third scanning pulse is generated as a gate-on voltage in the addressing step, and the third scanning pulse is generated as a gate-off voltage in the initialization step, the sampling step, and the light emitting step, The first EM pulse is generated as a gate-on voltage during at least a portion of the initialization step and at least a portion of the light emitting step, and the first EM pulse is generated as a gate-off voltage during the sampling step and the addressing step, and The second EM pulse is generated as a gate-on voltage during at least a portion of the light emitting step, and the second EM pulse is generated as a gate-off voltage during the initialization step, the sampling step, and the addressing step. 9 . The pixel circuit according to claim 1 , wherein the first gate electrode and the second gate electrode overlap each other with a semiconductor active pattern therebetween. 10 . The pixel circuit according to claim 1 , wherein a voltage between the second gate electrode and the second electrode shifts a threshold voltage of the driving element into a senseable range. 11 . The pixel circuit according to claim 10 , wherein a threshold voltage of the driving element is shifted from a voltage of 0 V or less to a positive voltage higher than 0 V.

12. A display device comprising: a display panel, wherein a plurality of data lines, a plurality of gate lines intersecting the data lines, a first power line to which a pixel driving voltage is applied, a second power line to which an initialization voltage is applied, a third power line to which a reference voltage is applied, a fourth power line to which a low-potential power supply voltage is applied, and a plurality of pixel circuits connected to the data lines, the gate lines, and the power lines are provided; a data driver that provides a data voltage of pixel data to the data line; as well as a gate driver that provides a gate signal to the gate line, Each of the pixel circuits comprises: a driving element including a first electrode connected to the first node, a first gate electrode connected to the second node, a second electrode connected to the third node, and a second gate electrode connected to the fourth node; a light emitting element including an anode electrode connected to the fourth node and a cathode electrode to which a low-potential power supply voltage is applied, the light emitting element being driven by the current from the driving element; a first switching element connected between the first node and the second node; a second switching element connected between the third node and the fourth node, and a third switching element connected to the fourth node and applying a preset voltage to the fourth node.

13. The display device according to claim 12, wherein each of the pixel circuits further comprises: a fourth switching element including a first electrode connected to the fifth node, a second electrode to which the data voltage of the pixel data is applied, and a gate electrode to which a third scan pulse is applied; a fifth switching element, the fifth switching element including a first electrode to which the pixel driving voltage is applied, a second electrode connected to the first node, and a gate electrode to which a first EM pulse is applied; a sixth switching element including a first electrode to which the reference voltage is applied, a second electrode connected to the third node, and a gate electrode to which a second scan pulse is applied; a seventh switching element, the seventh switching element including a first electrode connected to the fifth node, a second electrode connected to the third node, and a gate electrode to which a second scan pulse is applied; a first capacitor connected between the second node and the fourth node; and a second capacitor connected between the first node and the fifth node, wherein the first switching element includes a first electrode connected to the first node, a second electrode connected to the second node, and a gate electrode to which a first scan pulse is applied, and The second switching element includes a first electrode connected to the third node, a second electrode connected to the fourth node, and a gate electrode to which a second EM pulse is applied. The third switching element includes a first electrode to which an initialization voltage is applied, a second electrode connected to the fourth node, and a gate electrode to which the first scan pulse is applied. The preset voltage is set as the initialization voltage. 14 . The display device according to claim 13 , wherein the driving element and the switching element include an n-channel oxide semiconductor. 15 . The display device according to claim 14 , wherein when the initialization voltage is applied to the second gate electrode of the driving element, a threshold voltage of the driving element shifts to a positive voltage higher than 0V.

16. The display device according to claim 14 , wherein the pixel circuit is driven in an initialization step, a sampling step after the initialization step, an addressing step of applying the data voltage after the sampling step, and a light emitting step after the addressing step, The first scanning pulse is generated as a gate-on voltage in the initialization step, the sampling step, and the addressing step, and the first scanning pulse is generated as a gate-off voltage in the light emitting step, The second scanning pulse is generated as a gate-on voltage in the sampling step, and the second scanning pulse is generated as a gate-off voltage in the initialization step, the addressing step, and the light emitting step, The third scanning pulse is generated as a gate-on voltage in the addressing step, and the third scanning pulse is generated as a gate-off voltage in the initialization step, the sampling step, and the light emitting step, The first EM pulse is generated as a gate-on voltage during at least a portion of the initialization step and at least a portion of the light emitting step, and the first EM pulse is generated as a gate-off voltage during the sampling step and the addressing step, and The second EM pulse is generated as a gate-on voltage during at least a portion of the light emitting step, and the second EM pulse is generated as a gate-off voltage during the initialization step, the sampling step, and the addressing step, and Each of the switching elements is turned on in response to a gate-on voltage.

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