Pixel circuit and display device including the same

Abstract

Disclosed are a pixel circuit and a display device including the pixel circuit. The pixel circuit includes: a driving element including a first electrode connected to a first node, a first gate electrode connected to a second node, a second electrode connected to a third node, and a second gate electrode to which a preset voltage is applied; a light-emitting element including an anode connected to a fourth node and a cathode to which a low-potential power supply voltage is applied, the light-emitting element being driven by a current from the driving element; a first switching element connected between the first node and the second node; a second switching element connected between the third node and the fourth node; a first capacitor connected to the first gate electrode of the driving element and to which a data voltage of pixel data is applied; and a second capacitor connected to the third node and to which a preset voltage is applied.

Description

Technical Field

[0001] The present disclosure relates to a pixel circuit and a display device including the pixel circuit. Background Art

[0002] Depending on the material of the light-emitting layer, electroluminescent display devices are roughly divided into inorganic light-emitting display devices and organic light-emitting display devices. Active matrix organic light-emitting display devices include organic light-emitting diodes (hereinafter referred to as "OLEDs") that emit light themselves, and have the advantages of fast response speed, high luminous efficiency, brightness and viewing angle. In an organic light-emitting display device, an OLED is formed in each pixel. The organic light-emitting display device not only has a fast response speed, excellent luminous efficiency, brightness and viewing angle, but also has excellent contrast and color reproducibility because it can represent black grayscale in full black.

[0003] The pixel circuit of an electroluminescent display device includes an OLED serving as a light-emitting element and a driver element for driving the OLED. The electrical characteristics of the driver element may change due to degradation of the driver element. In this case, the quality of the image reproduced on the screen is reduced, so it is necessary to compensate for the electrical characteristics of the driver element. Specifically, when the threshold voltage of the driver element shifts, when the shift range exceeds the voltage that can be sensed, it becomes difficult to sense the threshold voltage of the driver element.

[0004] For example, in the case where a driver element is implemented as a transistor including an oxide semiconductor, if the threshold voltage of the transistor is close to 0 V, it is difficult to compensate for a shift in the threshold voltage of the driver element.

[0005] When the driving frequency of the display device increases or the resolution of the display device increases, one horizontal period becomes smaller. In this case, the compensation performance deteriorates due to insufficient time for sensing and sampling the threshold voltage of the driving element, making it difficult to achieve the brightness of the black gray level. Summary of the Invention

[0006] The present disclosure aims to address the above needs and / or problems. The present disclosure provides a pixel circuit capable of accurately sampling the threshold voltage of a driving element, and also provides a display device including the pixel circuit.

[0007] Problems to be solved by the present disclosure are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0008] According to an embodiment of the present disclosure, a pixel circuit includes: a driving element, which includes a first electrode connected to a first node, a first gate electrode connected to a second node, a second electrode connected to a third node, and a second gate electrode to which a preset voltage is applied; a light-emitting element, which includes an anode connected to a fourth node and a cathode to which a low-potential power supply voltage is applied, and the light-emitting element is driven according to a current from the driving element; a first switching element connected between the first node and the second node; a second switching element connected between the third node and the fourth node; a first capacitor connected to the first gate electrode of the driving element and to which a data voltage of pixel data is applied; and a second capacitor connected to the third node and to which the preset voltage is applied.

[0009] A display device according to an embodiment of the present disclosure includes: a display panel, in which a plurality of data lines, a plurality of gate lines crossing the data lines, a first power line to which a pixel driving voltage is applied, a second power line to which an initialization voltage is applied, a third power line to which a reference voltage is applied, a fourth power line to which a low-potential power supply voltage is applied, and a plurality of pixel circuits connected to the data lines, the gate lines, and the power lines; a data driver that provides a data voltage of pixel data to the data lines; and a gate driver that provides a gate signal to the gate lines.

[0010] The present disclosure can shift the threshold voltage of a driving element to a voltage range that can be sensed by applying a preset voltage to the second gate electrode of the driving element in the internal compensation circuit using a diode connection circuit. As a result, by shifting the threshold voltage of the driving element that has shifted to a voltage of 0V or less to a voltage that can be sensed, the present disclosure can sense the threshold voltage of the driving element and compensate for the threshold voltage of the driving element.

[0011] The present disclosure can reduce power consumption, improve the reliability of a display panel, and ensure the reliability of elements constituting a pixel circuit by using an oxide TFT whose threshold voltage is shifted to 0V or less as a driving element of a pixel circuit.

[0012] By separating the sampling step and the addressing step in the pixel circuit to which the internal compensation circuit is applied, the present disclosure can ensure sufficient time required to sample the threshold voltage of the driving element, solve the problem of achieving black brightness and compensation performance degradation, allow high-speed driving of the display device, and improve image quality in high-resolution and high-speed driving display devices.

[0013] The present disclosure can optimize the thickness of the insulating layer, thereby increasing the influence of the voltage causing the threshold voltage of the driving element to shift.

[0014] The present disclosure can achieve flicker-free image quality by allocating anode reset frames in a low-speed driving mode.

[0015] The present disclosure may allocate a reset step before the initialization step to reset the pixel circuit in the previous frame, thereby preventing a change in a voltage applied to the pixel circuit in the current frame.

[0016] The present disclosure can offset the phenomenon that the kickback voltage generated during the cut-off period of the switching element connected to the switching diode in the pixel circuit increases according to the threshold voltage that increases depending on the cumulative driving time of the switching element by changing the gate voltage or the data voltage, thereby reducing the time error of sampling the threshold voltage of the driving element.

[0017] Effects of the present disclosure are not limited to the above-mentioned effects, and other effects that are not mentioned will be clearly understood by those skilled in the art from the following description and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0019] Figure 1A is a block diagram illustrating a display device according to one embodiment of the present disclosure;

[0020] Figure 1B It shows Figure 1A A cross-sectional view of the cross-sectional structure of the display panel shown;

[0021] Figure 2 is a circuit diagram showing a pixel circuit according to one embodiment of the present disclosure;

[0022] Figure 3 is shown for verification Figure 2 FIG. 1 is a diagram showing simulation results of the effect of a threshold voltage shift Vbs of a driving element shown;

[0023] Figure 4 is a cross-sectional view schematically showing a cross-sectional structure of a driving element;

[0024] Figure 5 is a circuit diagram showing a pixel circuit according to another embodiment of the present disclosure;

[0025] Figure 6 is a waveform diagram illustrating a method of driving a pixel circuit according to one embodiment of the present disclosure;

[0026] Figure 7 It shows Figure 5 A circuit diagram showing an initialization step of a pixel circuit;

[0027] Figure 8 It shows Figure 5 A circuit diagram of a sampling step of a pixel circuit shown;

[0028] Figure 9 It shows Figure 5 A circuit diagram of the addressing step of the pixel circuit shown;

[0029] Figure 10 It shows Figure 5 A circuit diagram of the light emitting step of the pixel circuit shown;

[0030] Figure 11 is a graph showing refresh rates in normal drive mode and low-speed drive mode;

[0031] Figure 12 is a waveform diagram showing signals applied to a pixel circuit in a normal drive mode and a low-speed drive mode;

[0032] Figure 13 is a waveform diagram illustrating a method of driving a pixel circuit according to another embodiment of the present disclosure;

[0033] Figure 14 is a circuit diagram showing a reset step of a pixel circuit;

[0034] Figure 15 is a waveform diagram showing a kickback voltage that increases as the cumulative driving time of the sampling switch element increases in the pixel circuit;

[0035] Figures 16 to 18 is a waveform diagram showing an example of a gate voltage and a data voltage that change as the cumulative driving time of a pixel circuit increases; and

[0036] Figure 19 is a circuit diagram illustrating another example of a pixel circuit applicable to the present disclosure. DETAILED DESCRIPTION

[0037] The advantages and features of the present disclosure and the methods for implementing the present disclosure will be more clearly understood from the embodiments described below with reference to the accompanying drawings. However, the present disclosure is not limited to the following embodiments, but can be implemented in various forms. On the contrary, the present embodiments will complete the disclosure of the present disclosure and allow those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is limited only within the scope of the appended claims.

[0038] The shapes, sizes, ratios, angles, numbers, etc. shown in the accompanying drawings for describing the embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout this specification, the same reference numerals generally represent the same elements. In addition, when describing the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0039] As used herein, terms such as "comprising," "including," "having," and "consisting of" are generally intended to allow the addition of other components unless these terms are used with the term "only." Any reference to the singular may include the plural unless expressly stated otherwise.

[0040] Components are interpreted as including ordinary margins of error even if not expressly stated.

[0041] When terms such as “on,” “above,” “below,” and “beside” are used to describe the positional relationship between two components, one or more components may be located between the two components unless the terms are used with the terms “immediately” or “directly.”

[0042] The terms “first”, “second”, etc. may be used to distinguish components from one another, but the function or structure of the components is not limited by the ordinal numbers preceding the components or the names of the components.

[0043] Throughout this disclosure, like reference numerals may refer to substantially like elements.

[0044] The following embodiments may be combined or coupled with each other in part or in whole, and may be linked and operated in technically different ways. The embodiments may be performed independently of each other or in conjunction with each other.

[0045] Each pixel may include multiple sub-pixels with different colors to reproduce the colors of the image on the screen of the display panel. Each sub-pixel includes a transistor that serves as a switching element or driving element. Such a transistor can be implemented as a TFT (thin film transistor).

[0046] The driving circuit of the display device writes pixel data of the input image into the pixels on the display panel. To this end, the driving circuit of the display device may include a data driving circuit configured to provide data signals to the data lines, a gate driving circuit configured to provide gate signals to the gate lines, etc.

[0047] In the display device of the present disclosure, the pixel circuit and the gate driver circuit may include a plurality of transistors. The transistors may be implemented as oxide thin film transistors (oxide TFTs) including oxide semiconductors, low temperature polycrystalline silicon (LTPS) TFTs including low temperature polycrystalline silicon, and the like. In the embodiment, the description is given based on an example in which the transistors of the pixel circuit and the gate driver circuit are implemented as n-channel oxide TFTs, but the present disclosure is not limited thereto.

[0048] Typically, a transistor is a three-electrode component consisting of a gate, a source, and a drain. The source is the electrode that supplies carriers to the transistor. In a transistor, carriers begin to flow from the source. The drain is the electrode through which carriers exit the transistor. In a transistor, carriers flow from the source to the drain. In the case of an n-channel transistor, since the carriers are electrons, the source voltage is a voltage lower than the drain voltage, allowing electrons to flow from the source to the drain. An n-channel transistor has a current flow direction from the drain to the source. In the case of a p-channel transistor (p-channel metal oxide semiconductor (PMOS)), since the carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed depending on the applied voltage. Therefore, the present disclosure is not limited to the source and drain of a transistor. In the following description, a source and a drain of a transistor will be referred to as a first electrode and a second electrode.

[0049] The gate signal swings between a gate-on voltage and a gate-off voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor.

[0050] The transistor is turned on in response to a gate-on voltage and turned off in response to a gate-off voltage. In the case of an n-channel transistor, the gate-on voltage may be a gate high voltage VGH or VEH, and the gate-off voltage may be a gate low voltage VGL or VEL.

[0051] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following embodiments, the display device will be described with emphasis on an organic light emitting display device, but the present disclosure is not limited thereto.

[0052] Reference Figure 1A and Figure 1B , a display device according to an embodiment of the present disclosure includes a display panel 100, a display panel driver for writing pixel data to pixels of the display panel 100, and a power supply 140 for generating power required to drive the pixels and the display panel driver.

[0053] The display panel 100 may be a rectangular display panel having a length along the X-axis direction, a width along the Y-axis direction, and a thickness along the Z-axis direction. The display panel 100 includes a pixel array that displays an input image on a screen. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 crossing the data lines 102, and pixels arranged in a matrix. The display panel 100 may also include power lines commonly connected to the pixels. Figure 5In the embodiment, the power lines may include a first power line VDDL to which a pixel driving voltage VDD is applied, a second power line INL to which an initialization voltage Vinit is applied, and a third power line REFL to which a reference voltage Vref is applied. The display panel 100 may further include a fourth power line to which a low-potential power voltage VSS is applied.

[0054] The cross-sectional structure of the display panel 100 may include a circuit layer 12, a light emitting element layer 14, and an encapsulation layer 16 stacked on a substrate 10. Figure 1B shown.

[0055] Circuit layer 12 may include a TFT array including pixel circuits connected to wiring such as data lines, gate lines, and power lines, a demultiplexer array 112, a gate driver 120, and the like. The wiring and circuit elements of circuit layer 12 may include multiple insulating layers, two or more metal layers separated by insulating layers, and an active layer comprising a semiconductor material. All transistors formed in circuit layer 12 may be implemented as n-channel oxide TFTs.

[0056] The light-emitting element layer 14 may include a light-emitting element EL driven by a pixel circuit. The light-emitting element EL may include a red (R) light-emitting element, a green (G) light-emitting element, and a blue (B) light-emitting element. In another embodiment, the light-emitting element layer 14 may include a white light-emitting element and a color filter. The light-emitting element EL of the light-emitting element layer 14 may be covered by a protective layer including an organic film and a passivation film.

[0057] Encapsulation layer 16 covers light-emitting element layer 14 to seal circuit layer 12 and light-emitting element layer 14. Encapsulation layer 16 may have a multilayer insulation structure in which organic and inorganic films are alternately stacked. The inorganic films block the penetration of moisture and oxygen. The organic films flatten the surface of the inorganic films. When the organic and inorganic films are stacked in multiple layers, the migration path of moisture or oxygen becomes longer compared to a single layer, effectively blocking the penetration of moisture and oxygen that could affect light-emitting element layer 14.

[0058] A touch sensor layer (not shown) may be formed on the encapsulation layer 16, and a polarizer or color filter layer may be provided thereon. The touch sensor layer may include a capacitive touch sensor that senses touch input based on a change in capacitance before and after a touch input. The touch sensor layer may include a metal wiring pattern and an insulating layer that form the capacitance of the touch sensor. The insulating layer may insulate the portion where the metal wiring patterns intersect and may flatten the surface of the touch sensor layer. The polarizer may improve visibility and contrast by converting the polarization of external light reflected by the metal of the touch sensor layer and the circuit layer. The polarizer may be implemented as a polarizer or a circular polarizer in which a linear polarizer and a phase delay film are combined. Cover glass may be attached to the polarizer. The color filter layer may include red, green, and blue color filters. The color filter layer may also include a black matrix pattern. The color filter layer may replace the polarizer by absorbing a portion of the wavelength of light reflected from the circuit layer and the touch sensor layer, and improve the color purity of the image reproduced in the pixel array.

[0059] The pixel array includes a plurality of pixel lines L1 to Ln. Each of the pixel lines L1 to Ln includes a row of pixels arranged along the row direction X in the pixel array of the display panel 100. The pixels arranged in one pixel line share a gate line 103. Subpixels arranged in the column direction Y along the data line direction share the same data line 102. One horizontal period 1H is the time obtained by dividing one frame period by the total number of pixel lines L1 to Ln.

[0060] The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device in which an image is displayed on a screen and an actual background is visible.

[0061] The display panel can be manufactured as a flexible display panel. The flexible display panel can be implemented as an OLED panel using a plastic substrate. The pixel array and light-emitting devices of the plastic OLED panel can be set on an organic film attached to a backplane.

[0062] The organic film can be provided on the backplane of the plastic OLED panel. The pixel circuit and the light-emitting device can be stacked on the organic film, and a touch sensor array can be formed thereon. The backplane blocks moisture from penetrating into the organic film so that the pixel array is not exposed to moisture. The organic film can be a thin polyimide (PI) film substrate. A multilayer buffer film can be formed on the organic film from an insulating material (not shown). The lines of the pixel array can be formed on the organic film to provide power or signals applied to the pixel circuit and the touch sensor array.

[0063] Each pixel 101 can be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel to achieve color. Each pixel can also include a white sub-pixel. Each sub-pixel includes a pixel circuit. Hereinafter, a pixel can be interpreted as having the same meaning as a sub-pixel. Each pixel circuit is connected to a data line, a gate line, and a power line.

[0064] Pixels can be arranged as true color pixels and pentile pixels. By driving two sub-pixels with different colors as one pixel 101 through a preset pixel rendering algorithm, the pentile pixel can achieve higher resolution than a true color pixel. The pixel rendering algorithm can compensate for the insufficient color representation in each pixel with the color of the light emitted from the adjacent pixel.

[0065] A touch sensor may be provided on the display panel 100. Touch input may be sensed using a separate touch sensor or may be sensed by a pixel. The touch sensor may be provided as an on-cell type or an attached type on the display panel screen, or implemented as an in-cell type touch sensor embedded in a pixel array.

[0066] A touch sensor may be provided on the display panel 100. A separate touch sensor may be used to sense touch input, or touch input may be sensed by pixels. The touch sensor may be provided as an on-cell type or an attached type on the display panel screen, or implemented as an in-cell type touch sensor embedded in a pixel array.

[0067] The power supply 140 generates the DC power required to drive the pixel array and display panel driver of the display panel 100 using a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply 140 can adjust the level of the DC input voltage applied from the host system (not shown) to generate DC voltages, such as a gamma reference voltage VGMA, gate-on voltages VGH and VEH, gate-off voltages VGL and VEL, pixel drive voltage VDD, low potential power supply voltage VSS, reference voltage Vref, and initialization voltage Vinit. The gamma reference voltage VGMA is provided to the data driver 110. The gate-on voltages VGH and VEH and the gate-off voltages VGL and VEL are provided to the gate driver 120. The pixel drive voltage VDD, low potential power supply voltage VSS, reference voltage Vref, and initialization voltage Vinit are commonly provided to the pixels. The reference voltage Vref and initialization voltage Vinit can be generated from the data driver 110.

[0068] The display panel driver writes pixel data of an input image to pixels of the display panel 100 under the control of a timing controller (TCON) 130 .

[0069] The display panel driver includes a data driver 110 and a gate driver 120. The display panel driver may further include a demultiplexer array 112 disposed between the data driver 110 and the data lines 102.

[0070] The demultiplexer array 112 sequentially connects the channels of the data driver 110 to the data lines 102 by transmitting the data voltage output from the data driver 110 to the data lines 102 using a plurality of demultiplexers (DEMUX). The demultiplexer array 112 may include a plurality of switching elements disposed on the display panel 100. When the demultiplexer array 112 is disposed between the output terminal of the data driver 110 and the data lines 102, the number of channels of the data driver 110 may be reduced. The demultiplexer array 112 may be omitted.

[0071] The display panel driver may further include a touch sensor driver for driving the touch sensor. The touch sensor driver is configured to: Figure 1A and Figure 1B The data driver and the touch sensor driver may be integrated into one driver integrated circuit (IC). In a mobile device or a wearable device, the timing controller 130, the power supply 140, the data driver 110, etc. may be integrated into one driver IC.

[0072] The display panel driver can operate in a low-speed drive mode under the control of the timing controller 130. By analyzing the input image, the low-speed drive mode can be set to reduce the power consumption of the display device when the input image has not changed in a preset number of frames. In the low-speed drive mode, when a still image is input for a predetermined time or longer, the power consumption of the display panel driver and the display panel 100 can be reduced by reducing the refresh rate of the pixels. The low-speed drive mode is not limited to the case of inputting a still image. For example, when the display device is operating in standby mode, or when no user command or input image is input to the display panel drive circuit for a predetermined time or longer, the display panel drive circuit can operate in the low-speed drive mode.

[0073] The data driver 110 generates data voltages by converting pixel data of an input image received as a digital signal from the timing controller 130 using a digital-to-analog converter (DAC) with a gamma compensation voltage in each frame period. The gamma reference voltage VGMA is divided into gamma compensation voltages for each grayscale level by a voltage divider circuit. The gamma compensation voltage for each grayscale level is supplied to the DAC of the data driver 110. The data voltages are output through an output buffer in each channel of the data driver 110.

[0074] The gate driver 120 can be implemented as a gate-in-panel (GIP) circuit directly formed on the display panel 100 along with the wiring of the TFT array and the pixel array. The GIP circuit can be provided in the bezel (BZ) area of ​​the display panel 100, which is a non-display area, or can be dispersedly provided in the pixel array that reproduces the input image. The gate driver 120 sequentially outputs gate signals to the gate lines 103 under the control of the timing controller 130. The gate driver 120 can sequentially supply the gate signals to the gate lines 103 by shifting the gate signals using a shift register. In an organic light emitting diode display, the gate signals may include scan signals and emission control signals (hereinafter referred to as "EM signals"). The scan signals include scan pulses that swing between a gate-on voltage VGH and a gate-off voltage VGL. The EM signals may include EM pulses that swing between a gate-on voltage VEH and a gate-off voltage VEL.

[0075] The scan pulse is synchronized with the data voltage to select the pixels of the row to be written with data. The EM signal defines the light emission time of the pixel.

[0076] The gate driver 120 may include a first gate driver 121 and a second gate driver 122. The first gate driver 121 outputs a scan pulse in response to a start pulse and a shift clock from the timing controller 130, and shifts the scan pulse according to the shift clock timing. The second gate driver 122 outputs an EM pulse in response to a start pulse and a shift clock from the timing controller 130, and sequentially shifts the EM pulse according to the shift clock.

[0077] The timing controller 130 receives digital video data DATA of an input image and timing signals synchronized therewith from the host system. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock CLK, a data enable signal DE, and the like. Because the vertical and horizontal periods can be determined by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted. The data enable signal DE has a period of one horizontal period (1H).

[0078] The host system may be a television (TV) system, a tablet computer, a notebook computer, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, and a vehicle system. The host system may scale the image signal from the video source to fit the resolution of the display panel 100 and send it to the timing controller 130 along with the timing signal.

[0079] Compared to the normal drive mode, the timing controller 130 reduces the frame rate (or frequency) at which pixel data is written to the pixel in the low-speed drive mode. For example, the data refresh frame for writing pixel data to the pixel in the normal drive mode may occur at a frequency of 60 Hz or higher, such as any one of 60 Hz, 120 Hz, and 144 Hz, while the data refresh frame (DRF) in the low-speed drive mode may occur at a refresh rate lower than that in the normal drive mode. In order to reduce the refresh rate of the pixel in the low-speed drive mode, the timing controller 130 may reduce the frame rate to a frequency between 1 Hz and 30 Hz, thereby reducing the drive frequency of the display panel driver.

[0080] Based on the timing signals Vsync, Hsync, and DE received from the host system, the timing controller 130 generates data timing control signals for controlling the operation timing of the data driver 110, MUX signals MUX1 and MUX2 for controlling the operation timing of the demultiplexer array 112, and gate timing control signals for controlling the operation timing of the gate driver 120. To control the operation timing of the display panel driver, the timing controller 130 synchronizes the data driver 110, the demultiplexer array 112, the touch sensor driver, and the gate driver 120.

[0081] The gate timing control signal output from the timing controller 130 may be input to the gate driver 120 through a level shifter (not shown). The level shifter may receive the gate timing control signal, generate a start signal and a shift clock that swing between the gate-on voltages VGH and VEH and the gate-off voltages VGL and VEL, and provide them to the gate driver 120.

[0082] The timing controller 130 can control the power supply 140 to change the output voltage of the power supply 140 according to the cumulative driving time of the pixel 101. For example, based on the results of measuring the reliability characteristics of the positive bias temperature stress (PBTS) of the transistors constituting the pixel circuit before product shipment, the offset of the threshold voltage Vth according to the cumulative driving time of the pixel can be derived. The timing controller 130 can have a lookup table (LUT) in which the offset of the threshold voltage according to the cumulative driving time of the switching element and the corresponding voltage compensation value are preset. Based on the data stored in the lookup table, the timing controller 130 can provide the power supply 140 with a voltage compensation value for compensating for the offset of the threshold voltage according to the cumulative driving time of the pixel. In this case, the power supply 140 can change at least one of the gamma reference voltage VGMA, the gate-on voltages VGH and VEH, and the gate-off voltages VGL and VEL according to the voltage compensation value from the timing controller 130. The data voltage Vdata output from the data driver 110 can be changed according to the gamma reference voltage VGMA. The voltages of the scan pulse and the EM pulse output from the gate driver 120 may be changed according to the gate-on voltages VGH and VEH and the gate-off voltages VGL and VEL.

[0083] Due to the device characteristic deviation and process deviation caused in the manufacturing process of the display panel 100, there may be differences in the electrical characteristics of the driving elements between pixels, and this difference may increase as the driving time of the pixels passes. In order to compensate for the differences in the electrical characteristics of the driving elements between pixels, an internal compensation technology or an external compensation technology may be applied to the organic light emitting diode display. The internal compensation technology samples the threshold voltage of the driving element of each sub-pixel by using an internal compensation circuit implemented in each pixel circuit, and compensates the gate-source voltage (Vgs) of the driving element by the threshold voltage. The external compensation technology senses the current or voltage of the driving element that changes according to the electrical characteristics of the driving element in real time by using an external compensation circuit. The external compensation technology compensates for the deviation (or change) of the electrical characteristics of the driving element in each pixel in real time by modulating the pixel data (digital data) of the input image with the deviation (or change) of the electrical characteristics of the driving element sensed for each pixel. Using the external compensation technology and / or the internal compensation technology, the display panel driver can drive the pixels. The pixel circuit can be implemented as a circuit to which the internal compensation circuit is applied, such as Figures 5 to 10 The circuit shown.

[0084] Figure 2 is a circuit diagram illustrating a pixel circuit according to one embodiment of the present disclosure.

[0085] Reference Figure 2The pixel circuit includes a light emitting element EL, a driving element DT for driving the light emitting element EL, a first switching element T1 connected between a first gate electrode G1 and a first electrode D of the driving element DT, and a second switching element T2 connected between a second electrode S of the driving element DT and the light emitting element EL. The driving element DT and the switching elements T1 and T2 may be implemented as n-channel oxide TFTs.

[0086] The light-emitting element EL can be implemented as an OLED. The OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), a light-emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When a voltage is applied to the anode and cathode of the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the light-emitting layer (EML) to form excitons, and thus visible light is emitted from the light-emitting layer (EML). The OLED used as the light-emitting element EL can have a series structure in which multiple light-emitting layers are stacked. The OLED of the series structure can improve the brightness and lifespan of the pixel.

[0087] The driver element DT may be a MOSFET having a dual-gate structure including a first gate electrode G1 and a second gate electrode G2. The second gate electrode G2 may be a bulk electrode or a bottom gate electrode. The first gate electrode G1 and the second gate electrode G2 may overlap with each other, with a semiconductor active pattern therebetween. A predetermined voltage, such as an initialization voltage Vinit described later, may be applied to the second gate electrode G2.

[0088] The voltage Vbs between the second gate electrode G2 of the driving element DT and the second electrode of the driving element can shift the threshold voltage of the driving element DT to a desired voltage. The first electrode can be a drain electrode, and the second electrode can be a source electrode. Hereinafter, the voltage between the second gate electrode G2 of the driving element DT and the second electrode of the driving element is abbreviated as "Vbs."

[0089] The first switching element T1 includes a first electrode connected to the first electrode D of the driving element DT, a second electrode connected to the first gate electrode G1 of the driving element DT, and a gate electrode to which a scan pulse is applied. The first switching element T1 is turned on in response to the gate-on voltage VGH of the scan pulse and turned off in response to the gate-off voltage VGL of the scan pulse. When the first switching element T1 is turned on, the driving element DT operates as a diode because the first gate electrode G1 and the first electrode D are connected. When the first switching element T1 is turned off, the first gate electrode G1 of the driving element DT and the first electrode D are separated.

[0090] The second switching element T2 includes a first electrode connected to the second electrode S of the driving element DT, a second electrode connected to the anode of the light-emitting element EL, and a gate electrode to which an EM pulse is applied. The second switching element T2 is turned on in response to a gate-on voltage VEH of the EM pulse and turned off in response to a gate-off voltage VEL of the EM pulse. When the second switching element T2 is turned on, a current path is formed between the driving element DT and the light-emitting element EL, supplying current to the light-emitting element EL. When the second switching element T2 is turned off, the current path between the driving element DT and the light-emitting element EL is cut off.

[0091] The pixel circuit may further include a first capacitor C1 , a second capacitor C2 , a third switching element T3 , and a fourth switching element T4 .

[0092] The first capacitor C1 includes a first electrode connected to the data line and a second electrode connected to the first gate electrode G1 of the driving element DT. The first capacitor C1 can provide a data voltage Vdata of pixel data to the first gate electrode G1 of the driving element DT. The second capacitor C2 includes a first electrode connected to a power line to which an initialization voltage Vinit is applied and a second electrode connected to the second electrode of the driving element DT. The first electrode of the first capacitor C1 is connected to the first electrode of the second capacitor C2.

[0093] The third switching element T3 supplies the initialization voltage Vinit to the first capacitor C1 and the second capacitor C2. The fourth switching element T4 supplies the data voltage Vdata to the first capacitor C1 and the second capacitor C2.

[0094] The first to fourth switching elements T1 to T4 are turned on in response to the gate-on voltage VGH of the scan pulse, and are turned off in response to the gate-off voltage VGL of the scan pulse.

[0095] exist Figure 3 In the figure, the horizontal axis represents the gate-source voltage (Vgs[V]) of the driving element DT, and the vertical axis represents the drain-source current Ids[A] of the driving element DT. When sensing the threshold voltage of the driving element DT, Vbs can cause the threshold voltage of the driving element DT to shift within the sensing range, as shown in FIG. Figure 3 As shown. Therefore, even if the threshold voltage of the driving element DT shifts beyond the range that can be sensed, the threshold voltage of the driving element DT can be accurately sensed. For example, if the threshold voltage of the driving element DT shifts to a voltage of 0 [V] or less, the threshold voltage of the driving element DT cannot be sensed. However, because the threshold voltage of the driving element DT can be shifted to a positive voltage greater than 0V by applying Vbs to the driving element DT, the threshold voltage of the driving element DT can be sensed. The degree of the threshold voltage shift of the driving element DT depends on Vbs, the parasitic capacitance connected to the first gate electrode G1 ( Figure 4 Cgi in) and the parasitic capacitance connected to the second gate electrode G2 ( Figure 4 Cbuf in ), so that the threshold voltage of the driving element can be shifted to the desired voltage.

[0096] When the reference voltage Vref is applied to the first gate electrode G1 of the driving element DT and the initialization voltage Vinit is applied to the second gate electrode G2, the voltage of the first gate electrode G1 may be Figure 2 Vref+Vth in Vref is a reference voltage, and Vth is a threshold voltage of the driving element DT shifted by Vbs. In this case, if Vref>Vinit, the threshold voltage of the driving element DT can be shifted to a positive voltage.

[0097] Figure 4 is a cross-sectional view schematically showing a cross-sectional structure of a driving element DT in the display panel 100 .

[0098] Reference Figure 4 , a first metal pattern may be formed on the substrate of the display panel 100. The first metal pattern may include the second gate electrode G2 of the driving element DT.

[0099] A first insulating layer BUF may be formed on the substrate to cover the first metal pattern. A semiconductor layer may be formed on the first insulating layer BUF. The semiconductor layer includes a semiconductor active pattern ACT of the driving element DT.

[0100] A second insulating layer GI may be formed on the first insulating layer BUF to cover the semiconductor pattern. A second metal pattern may be formed on the second insulating layer GI. The second metal pattern may include a first gate electrode G1 of the driving element DT.

[0101] exist Figure 4 In the figure, "Cgi" is a capacitance formed between the first gate electrode G1 and the semiconductor active pattern ACT in the driving element DT, and "Cbuf" is a capacitance connected between the second gate electrode G2 and the semiconductor active pattern ACT in the driving element DT. In order to increase the effect of Vbs applied to the driving element DT, by setting the thickness tbuf of the first insulating layer BUF to be smaller than the thickness tgi of the second insulating layer GI, the capacitance of Cbuf can be greater than the capacitance of Cgi.

[0102] Figure 5 is a circuit diagram illustrating a pixel circuit according to another embodiment of the present disclosure. Figure 5 The pixel circuit shown includes an internal compensation circuit that samples the threshold voltage of the driving element DT and compensates for variations in the threshold voltage of the driving element DT. Figure 6 is a waveform diagram illustrating a method of driving a pixel circuit according to one embodiment of the present disclosure.

[0103] Reference Figure 5 and Figure 6 The pixel circuit includes a light emitting element EL, a driving element DT, a first capacitor C1, a second capacitor C2, and first to seventh switching elements T1 to T7. The driving element DT and the switching elements T1 to T7 may be implemented as n-channel oxide TFTs.

[0104] In this pixel circuit, DC voltages such as a pixel driving voltage VDD, a low-potential power supply voltage VSS, a reference voltage Vref, and an initialization voltage Vinit, a data voltage Vdata that varies according to the grayscale level of pixel data, scan pulses SC1, SC2, and SC3, and EM pulses EM1 and EM2 are provided. The voltages of the scan pulses SC1, SC2, and SC3 and the EM pulses EM1 and EM2 swing between gate-on voltages VGH and VEH and gate-off voltages VGL and VEL.

[0105] The relationship of the voltages commonly applied to the pixels can be set to VDD>Vref>Vinit>VSS. The data voltage Vdata can be generated as a gamma compensation voltage selected according to the grayscale level of the pixel data from the data driver 110 within a voltage range lower than the pixel driving voltage VDD and higher than the low potential power supply voltage VSS. The initialization voltage Vinit can be set to a voltage equal to or lower than the threshold voltage of the light-emitting element EL. The reference voltage Vref can be set to a voltage higher than the initialization voltage Vinit so that a negative reverse bias is applied to the driving element DT in the sampling step SMPL. The gate-on voltages VGH and VEH can be set to be higher than the pixel driving voltage VDD. The gate-off voltages VGL and VEL can be set to be lower than the low potential power supply voltage VSS.

[0106] The scan pulses SC1, SC2, and SC3 may include a first scan pulse SC1 applied to the first gate line GL1, a second scan pulse SC2 applied to the second gate line GL2, and a third scan pulse SC3 applied to the third gate line GL3. The EM pulses EM1 and EM2 may include a first EM pulse EM1 applied to the fourth gate line GL4 and a second EM pulse EM2 applied to the fifth gate line GL5.

[0107] The driving cycle of the pixel circuit can be divided into: an initialization step INIT, in which the pixel circuit is initialized; a sampling step SMPL, in which the threshold voltage Vth of the driving element DT is sampled; an addressing step ADDR, in which the data voltage Vdata is charged and the pixel data is written; and a light emitting step EMIS, in which the light emitting element EL emits light having a brightness corresponding to the grayscale level of the pixel data. Figure 6, “(N-1)th FR” represents the (N-1)th frame period, and “Nth FR” represents the Nth frame period.

[0108] The first scan pulse SC1 may be a gate-on voltage VGH in the addressing step ADDR. The first scan pulse SC1 may be a gate-off voltage VGL in the initialization step INIT, the sampling step SMPL, and the light-emitting step EMIS. The first scan pulse SC1 may be generated as a pulse having a duration equal to or less than one horizontal period 1H, synchronized with the data voltage Vdata of the pixel data. In the addressing step ADDR, the data voltage Vdata is provided to the pixel circuit via the data line DL in synchronization with the first scan pulse SC1.

[0109] The second scan pulse SC2 may rise to the gate-on voltage VGH before the third scan pulse SC3 and fall to the gate-off voltage VGL before the falling edge of the third scan pulse SC3. The second scan pulse SC2 may be the gate-on voltage VGH in the initialization step INIT and the sampling step SMPL. The second scan pulse SC2 may be the gate-off voltage VGL in the addressing step ADDR and the light-emitting step EMIS.

[0110] The third scan pulse SC3 may be generated as the gate-on voltage VGH during the sampling step SMPL and the addressing step ADDR. During the addressing step ADDR, the gate-on voltage portion of the third scan pulse SC3 may overlap the gate-on voltage portion of the first scan pulse SC1. The third scan pulse SC3 may rise to the gate-on voltage VGH after the rising edge of the second scan pulse SC2 and then fall to the gate-off voltage VGL after the falling edge of the second scan pulse SC2. The third scan pulse SC3 may be the gate-off voltage VGL during the initialization step INIT and the light-emitting step EMIS.

[0111] The first EM pulse EM1 may be generated as the gate-on voltage VGH in the initialization step INIT and as the gate-on voltage VEH during at least a portion of the light-emitting step EMIS. The first EM pulse EM1 may be the gate-off voltage VEL in the sampling step SMPL and the addressing step ADDR. The first EM pulse EM1 may fall to the gate-off voltage VEL after a falling edge of the second EM pulse EM2 and rise to the gate-on voltage VEH before a rising edge of the second EM pulse EM2.

[0112] The second EM pulse EM2 may be generated as the gate-on voltage VEH during at least a portion of the light emitting step EMIS and may be the gate-off voltage VEL in the initialization step INIT, the sampling step SMPL, and the addressing step ADDR.

[0113] The light emitting element EL may be implemented as an OLED. An anode of the light emitting element EL may be connected to the fourth node n4, and a low potential power supply voltage VSS may be applied to a cathode of the light emitting element EL.

[0114] The first capacitor C1 may be connected between the second node n2 and the fifth node n5. The first capacitor C1 stores the threshold voltage Vth of the driving element DT in the sampling step SMPL. In the addressing step ADDR, the data voltage Vdata is transferred to the first gate electrode G1 of the driving element DT through the first capacitor C1.

[0115] The second capacitor C2 is connected between the third node n3 and the fifth node n5. The second capacitor C2 stores the second electrode voltage, ie, the source voltage, of the driving element DT at the start of the light emitting step EMIS and maintains the gate-source voltage Vgs of the driving element during the light emitting step EMIS.

[0116] The driving element DT may be a MOSFET having a dual-gate structure. The driving element DT includes a first gate electrode connected to the second node n2, a second gate electrode connected to the fourth node n4, a first electrode connected to the first node n1, and a second electrode connected to the third node n3. Figure 4 As shown, the first and second gate electrodes of the driving element DT may overlap each other with a semiconductor active pattern therebetween.

[0117] The first switching element T1 includes a first electrode connected to the first node n1, a second electrode connected to the second node n2, and a gate electrode to which the second scan pulse SC2 is applied. The first switching element T1 is turned on during the initialization step INIT and the sampling step SMPL in response to the gate-on voltage VGH of the second scan pulse SC2, connecting the first node n1 and the second node n2. When the first switching element T1 is turned on, the driving element DT operates as a diode because the first gate electrode G1 is connected to the first electrode.

[0118] The second switching element T2 includes a first electrode connected to the third node n3, a second electrode connected to the fourth node n4, and a gate electrode to which the second EM pulse EM2 is applied. In response to the gate-on voltage VEH of the second EM pulse EM2, the second switching element T2 is turned on during at least a portion of the light-emitting step EMIS, thereby forming a current path between the driving element DT and the light-emitting element EL. During the initialization step INIT, the sampling step SMPL, and the addressing step ADDR, in which the second switching element T2 is in the off state, the current path between the driving element DT and the light-emitting element EL is cut off, and thus the light-emitting element EL does not emit light.

[0119] The third switching element T3 includes a first electrode connected to the second power line INL to which the initialization voltage Vinit is applied, a second electrode connected to the fifth node n5, and a gate electrode to which the second scan pulse SC2 is applied. The third switching element T3 is turned on in response to the gate-on voltage VGH of the second scan pulse SC2 during the initialization step INIT and the sampling step SMPL and supplies the initialization voltage Vinit to the fifth node n5. During the light-emitting step EMIS and the addressing step ADDR when the third switching element T3 is turned off, the current path between the second power line INL and the fifth node n5 is cut off.

[0120] The fourth switching element T4 includes a first electrode connected to the data line DL to which the data voltage Vdata is applied, a second electrode connected to the fifth node n5, and a gate electrode to which the first scan pulse SC1 is applied. The fourth switching element T4 is turned on in the address step ADDR in response to the gate-on voltage VGH of the first scan pulse SC1 and supplies the data voltage Vdata to the fifth node n5. During the initialization step INIT, the sampling step SMPL, and the light-emitting step EMIS, when the fourth switching element T4 is turned off, the current path between the data line DL and the fifth node n5 is cut off.

[0121] The fifth switching element T5 includes a first electrode connected to a first power line VDDL to which a pixel driving voltage VDD is applied, a second electrode connected to a first node n1, and a gate electrode to which a first EM pulse EM1 is applied. In response to a gate-on voltage VEH of the first EM pulse EM1, the fifth switching element T5 is turned on during the initialization step INIT and the light-emitting step EMIS and supplies the pixel driving voltage VDD to the first node n1. During the sampling step SMPL and the addressing step ADDR, when the fifth switching element T5 is turned off, the current path between the first power line VDDL and the first node n1 is cut off.

[0122] The sixth switching element T6 includes a first electrode connected to the third node n3, a second electrode connected to the third power line REFL to which the reference voltage Vref is applied, and a gate electrode to which the third scan pulse SC3 is applied. The sixth switching element T6 is turned on in response to the gate-on voltage VGH of the third scan pulse SC3 during the sampling step SMPL and the addressing step ADDR, and supplies the reference voltage Vref to the third node n3. During the initialization step INIT and the light-emitting step EMIS, when the sixth switching element T6 is turned off, the current path between the third power line REFL and the third node n3 is cut off.

[0123] The seventh switching element T7 includes a first electrode connected to the second power line INL to which the initialization voltage Vinit is applied, a second electrode connected to the fourth node n4, and a gate electrode to which the third scan pulse SC3 is applied. The seventh switching element T7 is turned on in response to the gate-on voltage VGH of the third scan pulse SC3 during the sampling step SMPL and the addressing step ADDR and supplies the initialization voltage Vinit to the fourth node n4. During the initialization step INIT and the light-emitting step EMIS when the seventh switching element T7 is turned off, the current path between the second power line INL and the fourth node n4 is cut off.

[0124] In the present disclosure, the sampling step SMPL and the addressing step ADDR can be separated by applying a reference voltage Vref to the third node n3 to sample the threshold voltage Vth of the driving element DT in the sampling step SMPL and applying the data voltage Vdata in the addressing step ADDR. Therefore, according to the present disclosure, by ensuring a sufficiently long time (e.g., two or more horizontal periods) for the sampling step SMPL, the threshold voltage Vth of the driving element DT can be accurately sensed, and thus, a shift in the threshold voltage Vth can be compensated.

[0125] In the following, reference will be made to Figures 7 to 10 A stepping driving method of a pixel circuit is described in detail.

[0126] Figure 7 It shows Figure 5 The circuit diagram of the initialization step INIT of the pixel circuit is shown.

[0127] Reference Figure 7 In the initialization step INIT, the second scan pulse SC2 and the first EM pulse EM1 are generated as gate-on voltages VGH and VEH, while the other gate signals SC1, SC3, and EM2 are gate-off voltages VGL and VEL. In the initialization step INIT, the second, fourth, sixth, and seventh switching elements T2, T4, T6, and T7 are turned off. Therefore, in the initialization step INIT, the first, third, and fifth switching elements T1, T3, and T5, as well as the driving element DT, are turned on. In this case, the first gate electrode and the first electrode of the driving element DT are connected in a diode connection.

[0128] In the initialization step INIT, the voltages of the first and second nodes n1 and n2 are initialized to the pixel drive voltage VDD, and the voltage of the third node n3 is VDD-Vth0. Here, Vth0 is the initial threshold voltage when Vbs is not applied to the driver element DT. The voltage of the fifth node n5 is the initialization voltage Vinit. The voltage of the fourth node n4 is maintained at the initialization voltage Vinit applied in the previous frame.

[0129] Figure 8 It shows Figure 5 The sampling steps of the pixel circuit are shown in the circuit diagram of SMPL.

[0130] Reference Figure 8 In the sampling step SMPL, the third scan pulse SC3 is inverted to the gate-on voltage VGH, while the first EM pulse EM1 is inverted to the gate-off voltage VEL. In the sampling step SMPL, the second scan pulse SC2 maintains the gate-on voltage VGH. In the sampling step SMPL, the second scan pulse SC2 and the third scan pulse SC3 are at the gate-on voltage VGH, while the other gate signals SC1, EM1, and EM2 are at the gate-off voltages VGL and VEL. Therefore, in the sampling step SMPL, the first, third, sixth, and seventh switching elements T1, T3, T6, and T7, as well as the driving element DT, are turned on.

[0131] In the sampling step SMPL, the initialization voltage Vinit is applied to the second gate electrode G2 of the driving element DT through the turned-on third switching element T3, and the reference voltage Vref higher than the initialization voltage Vinit is applied to the second electrode of the driving element DT through the turned-on sixth switching element T6. Therefore, Vbs is applied to the driving element DT, so that the threshold voltage of the driving element DT can be shifted to a positive voltage higher than zero.

[0132] In the sampling step SMPL, the voltages at the first and second nodes n1 and n2 are changed to Vref+Vth0+α. Here, α is β(vref-vinit), and β is Cbuf / Cgi. The voltage at the third node n3 is the reference voltage Vref, and the voltages at the fourth and fifth nodes n4 and n5 are maintained at the initialization voltage Vinit.

[0133] Figure 9 It shows Figure 5 The circuit diagram of the addressing step ADDR of the pixel circuit is shown.

[0134] Reference Figure 9In the addressing step ADDR, a first scan pulse SC1 synchronized with the data voltage Vdata of the pixel data is generated as the gate-on voltage VGH. In the addressing step ADDR, a third scan pulse SC3 maintains the gate-on voltage VGH and then inverts to the gate-off voltage VGL. In the addressing step ADDR, a first EM pulse EM1 maintains the gate-off voltage VEL and then inverts to the gate-on voltage after the falling edge of the first scan pulse SC1. In the addressing step ADDR, a second scan pulse SC2 is inverted to the gate-off voltage VGL. In the addressing step ADDR, the voltages of the first EM pulse EM1 and the second EM pulse EM2 may be the gate-off voltage VEL. Therefore, in the addressing step ADDR, the first, fourth, sixth, and seventh switching elements T1, T4, T6, and T7, as well as the driving element DT, are turned on.

[0135] In the addressing step ADDR, the voltage of the first node n1 is maintained at Vref + Vth0 + α, and the voltage of the second node n2 is changed to Vref + Vth0 + α + C' (Vdata - Vinit). Here, C' can be expressed as C1 / (C1 + Cpar). "Cpar" is the parasitic capacitance connected to the first gate electrode G1 of the driving element DT. When Cpar is 0, C' becomes 1, so the data transfer rate is high. The higher Cpar, the lower the data transfer rate. The voltage of the third node n3 is the reference voltage Vref, and the voltages of the fourth node n4 and the fifth node n5 are maintained at the initialization voltage Vinit.

[0136] Figure 10 It shows Figure 5 The circuit diagram of the pixel circuit showing the light emitting step EMI.

[0137] Reference Figure 10 During the light-emitting step EMIS, the voltage of the scan pulses SC1, SC2, and SC3 is the gate-off voltage VGL. The first EM pulse EM1 and the second EM pulse EM2 are generated as the gate-on voltage VEH during at least a portion of the period during the light-emitting step EMIS. Therefore, during the light-emitting step EMIS, the driving element DT and the second and fifth switching elements T2 and T5 are turned on, while the first, third, fourth, sixth, and seventh switching elements T1, T3, T4, T6, and T7 are turned off. At this time, Vbs is not applied to the driving element DT, and current is supplied to the light-emitting element EL based on the gate-source voltage Vgs of the driving element DT, thereby turning on the light-emitting element EL.

[0138] In the light emitting step EMIS, the current Ioled flowing through the light emitting element EL is k[(Vref-Vinit)+C′(Vdata-Vref)+(Vth0+α-Vth0)] 2Here, k is a constant value determined according to the mobility and parasitic capacitance of the driving element DT. Assuming the condition C′=1, by ignoring the parasitic capacitance of the second node n2, Ioled can be k[(Vdata-Vinit)+α)] 2 .

[0139] During the EMIS, the initialization voltage Vinit applied to the second gate electrode of the driving element DT is substantially the same as the source voltage of the driving element DT. Therefore, during the EMIS, the threshold voltage of the driving element DT is not shifted by the voltage of the second gate electrode of the driving element DT.

[0140] Figure 11 is a graph showing refresh rates in normal drive mode and low-speed drive mode. Figure 12 is a waveform diagram showing signals applied to the pixel circuit in the normal drive mode and the low-speed drive mode. Figure 11 In the figure, “fx” represents the x-th frame period.

[0141] refer to Figure 11 and Figure 12 The frequency of a data refresh frame in which pixel data is written to the pixel circuit is set to be lower in the low-speed driving mode than in the normal driving mode.

[0142] In each frame of the normal drive mode and the data refresh frame of the low-speed drive mode, the driving time of the pixel circuit can be divided into an initialization step INIT, a sampling step SMPL, an addressing step ADDR, and a light-emitting step EMIS. The low-speed drive mode may include one or more anode reset frames (ARFs) allocated after the data refresh frame. In the anode reset frame (ARF), the driving time of the pixel circuit can be divided into a sampling step SMPL and a light-emitting step EMIS without the initialization step INIT. At least one of the anode reset frames (ARFs) may also include an addressing step ADDR.

[0143] Compared to the normal drive mode, the timing controller 130 reduces the frame rate frequency of writing pixel data to the pixel in the low-speed drive mode. For example, in the normal drive mode, the data refresh frame (DRF) for writing pixel data to the pixel may occur at a frequency of 60 Hz or higher, such as any one of 60 Hz, 120 Hz, and 144 Hz, while the data refresh frame (DRF) in the low-speed drive mode may occur at a refresh rate lower than that in the low-speed drive mode.

[0144] When the refresh rate of the low-speed drive mode is 1 Hz, one data refresh frame (DRF) is allocated per second, and the remaining 60 frames can be anode reset frames (ARF). During the anode reset frame (ARF) of the low-speed drive mode, the source driver IC integrated with the data driver 110 does not output the data voltage, and therefore does not generate power consumption. During the anode reset frame (ARF), the reference voltage Vref is applied to the third node n3 of each sub-pixel, thereby resetting the Vgs of the driving element DT stored in the previous data refresh frame (DRF). Therefore, in the low-speed drive mode, the brightness of the sub-pixel is not reduced during the anode reset frame (ARF), so that flicker is not recognized.

[0145] The second scan pulse SC2 is not generated in the anode reset frame (ARF) of the low speed driving mode, the second gate line GL2 maintains the gate-off voltage VGL, and other gate pulses SC1, SC3, EM1, and EM2 may be generated substantially the same as in the normal driving mode.

[0146] Figure 13 is a waveform diagram illustrating a method of driving a pixel circuit according to another embodiment of the present disclosure. Figure 14 is a circuit diagram showing a reset procedure of a pixel circuit.

[0147] refer to Figure 13 and Figure 14 , a reset step RST can be set before the initialization step INIT.

[0148] During the reset step RST, the third scan pulse SC3 is generated as the gate-on voltage VGH, while the other gate signals SC1, SC2, EM1, and EM2 are gate-off voltages VGL and VEL. Therefore, during the reset step RST, the sixth switching element T6 and the seventh switching element T7 are turned on, discharging the residual charge accumulated in the anode of the light-emitting element EL and the charge of the capacitors C1 and C2. As a result, the present disclosure can reset the voltages charged in the capacitors C1 and C2 and the capacitor of the OLED in the previous frame, thereby preventing voltage fluctuations caused by the influence of the previous voltage before sampling begins.

[0149] A holding step HOLD may be provided between the reset step RST and the initialization step INIT. In the holding step HOLD, all gate signals SC1, SC2, SC3, EM1, and EM2 are generated as gate-off voltages so that the main node of the pixel circuit may float.

[0150] In the pixel circuit, the first switching element T1 connects the driving element DT through a diode connection in response to the second scan pulse SC2 in the sampling step SMPL. At this time, the threshold voltage Vth of the driving element DT is sampled at the second node n2.

[0151] When the first switching element T1 is turned off due to the change in gate voltage at the falling edge of the second scan pulse SC2, the voltage of the second node n2 connected to the second gate electrode of the driving element DT is as follows: Figure 15 The flyback voltage is generated as shown. Figure 15 In FIG, 'Vn2' is the voltage of the second node n2, and 'Vn4' is the voltage of the fourth node n4. Variations in the kickback voltage of the voltage Vn2 at the second node may cause a threshold voltage sampling error in the driving element DT. When the threshold voltage of the first switching element T1 changes to a positive direction due to positive bias temperature stress (PBTS) that increases with the cumulative driving time of the first switching element T1, the kickback voltage may increase. Such a change in the kickback voltage may cause a threshold voltage sampling error in the driving element DT, thereby increasing the variation width of the current flowing through the light-emitting element EL during the light-emitting step EMIS.

[0152] like Figures 16 to 18 As shown, the present disclosure adjusts the gate-on voltage VGH or gate-off voltage VGL of at least the second scan pulse SC2 in the gate signal, or adjusts the data voltage Vdata, according to the accumulated driving time of the pixel circuit, thereby offsetting the kickback voltage that increases with the increase in the accumulated driving time. In the same manner as the voltage adjustment method for the second scan pulse SC2, the gate voltages of the other scan pulses SC1 and the EM pulse EM can be changed according to the accumulated driving time of the pixel circuit.

[0153] refer to Figure 16 Under the control of the timing controller 130, the power supply 140 may increase the gate-on voltage VGH as the cumulative driving time of the pixel circuit increases. As a result, as the kickback voltage increases, the voltage Vn2 of the second node may decrease. At this time, the threshold voltage sampling rate of the driving element DT may be increased.

[0154] Reference Figure 17 Under the control of the timing controller 130, when the cumulative driving time of the pixel circuit increases, the power supply 140 may reduce the gate-off voltage VGL. As a result, as the kickback voltage increases, the voltage Vn2 of the second node may decrease.

[0155] The timing controller 130 may change the data voltage Vdata output from the data driver 110 by changing the pixel data value of the input image or by changing the gamma reference voltage VGMA output from the power supply 140. Figure 18 As shown, when the cumulative driving time of the pixel circuit increases, the data voltage Vdata may decrease, thereby offsetting the increase in the kickback voltage. Figures 16 to 18 The embodiment shown also applies to Figure 19 The pixel circuit shown.

[0156] Figure 19 The pixel circuit shown is composed of a light emitting element EL, six transistors DT, T1 to T5, and one capacitor Cst, and a threshold voltage Vth of the driving element DT is sampled using a diode connection circuit in a sampling step SMPL.

[0157] refer to Figure 19 The driving element DT may be a MOSFET having a double-gate structure to which a negative reverse bias may be applied. The driving element DT includes a first gate electrode connected to the second node n2, a second gate electrode connected to the fourth node n4, a first electrode connected to the first node n1, and a second electrode connected to the third node n3.

[0158] The first switching element T1 includes a first electrode connected to the first node n1, a second electrode connected to the second node n2, and a gate electrode to which the second scan pulse SC2 is applied. The second switching element T2 includes a first electrode connected to the third node n3, a second electrode connected to the fourth node n4, and a gate electrode to which the second EM pulse EM2 is applied. The third switching element T3 includes a first electrode to which the initialization voltage Vinit is applied, a second electrode connected to the fourth node n4, and a gate electrode to which the second scan pulse SC2 is applied. The fourth switching element T4 includes a first electrode to which the data voltage Vdata is applied, a second electrode connected to the third node n3, and a gate electrode to which the first scan pulse SC1 is applied. The fifth switching element T5 includes a first electrode to which the pixel driving voltage VDD is applied, a second electrode connected to the first node n1, and a gate electrode to which the first EM pulse EM1 is applied.

[0159] The objects to be achieved by the present disclosure, the means for achieving the objects, and the effects of the present disclosure described above do not indicate the essential features of the claims, and therefore, the scope of the claims is not limited to the disclosure of the present disclosure.

[0160] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above-mentioned embodiments are illustrative in all aspects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the attached claims, and all technical concepts within their equivalent scope should be interpreted as falling within the scope of the present disclosure.

[0161] CROSS-REFERENCE TO RELATED APPLICATIONS

[0162] This application claims priority to and the benefit of Korean Patent Application No. 10-2021-0090018, filed on July 8, 2021, and Korean Patent Application No. 10-2021-0170674, filed on December 2, 2021, the disclosures of which are incorporated herein by reference in their entirety.

Claims

1. A pixel circuit, comprising: a driving element comprising a first electrode connected to the first node, a first gate electrode connected to the second node, a second electrode connected to the third node, and a second gate electrode connected to the fourth node and to which a preset voltage is applied; a light emitting element including an anode connected to the fourth node and a cathode to which a low-potential power supply voltage is applied, the light emitting element being driven by the current from the driving element; a first switching element including a first electrode connected to the first node, a second electrode connected to the second node, and a gate electrode to which a second scan pulse is applied; a second switching element including a first electrode connected to the third node, a second electrode connected to the fourth node, and a gate electrode to which a second EM pulse is applied; a third switching element, the third switching element including a first electrode to which an initialization voltage is applied, a second electrode connected to the fifth node, and a gate electrode to which the second scan pulse is applied; a fourth switching element, the fourth switching element including a first electrode to which the data voltage is applied, a second electrode connected to the fifth node, and a gate electrode to which the first scan pulse is applied; a fifth switching element, the fifth switching element including a first electrode to which a pixel driving voltage is applied, a second electrode connected to the first node, and a gate electrode to which a first EM pulse is applied; a sixth switching element, the sixth switching element including a first electrode to which a reference voltage is applied, a second electrode connected to the third node, and a gate electrode to which a third scan pulse is applied; a seventh switching element, the seventh switching element including a first electrode to which the initialization voltage is applied, a second electrode connected to the fourth node, and a gate electrode to which the third scan pulse is applied; a first capacitor including a first electrode connected to the fifth node and a second electrode connected to the second node; as well as A second capacitor includes a first electrode connected to the fifth node and a second electrode connected to the third node.

2. The pixel circuit according to claim 1, wherein: The threshold voltage of the driving element is shifted to a senseable voltage by the voltage between the second gate electrode and the second electrode.

3. The pixel circuit according to claim 1 , further comprising: a first insulating layer covering the second gate electrode; a semiconductor active pattern of the driving element formed on the first insulating layer; as well as a second insulating layer formed on the first insulating layer to cover the semiconductor active pattern and disposed under the first gate electrode, Wherein, the thickness of the first insulating layer is smaller than the thickness of the second insulating layer.

4. The pixel circuit according to claim 1, wherein: The driving element and the switching element include n-channel oxide semiconductors, and Each of the switching elements is turned on in response to a gate-on voltage of a corresponding gate electrode.

5. The pixel circuit according to claim 4, wherein: The preset voltage is set as the initialization voltage. The pixel circuit according to claim 4 , wherein: When the initialization voltage is applied to the second gate electrode of the driving element, the threshold voltage of the driving element shifts to a voltage that can be sensed.

7. The pixel circuit according to claim 1, wherein: When the pixel driving voltage is VDD, the reference voltage is Vref, the initialization voltage is Vinit, and the low potential power supply voltage is VSS, these voltages are set to VDD>Vref>Vinit>VSS. The data voltage of the pixel data is lower than the pixel driving voltage and higher than the low potential power supply voltage, and Each of the first to third scan pulses and the first to second EM pulses swings between a gate-on voltage higher than the pixel driving voltage and a gate-off voltage lower than the low-potential power supply voltage.

8. The pixel circuit according to claim 4, wherein: The pixel circuit is driven according to an initialization step, a sampling step after the initialization step, an addressing step of applying the data voltage after the sampling step, and a light emitting step after the addressing step, The first scanning pulse is generated as a gate-on voltage in synchronization with the data voltage in the addressing step, and is generated as a gate-off voltage in the initialization step, the sampling step, and the light-emitting step, The second scanning pulse is generated as a gate-on voltage in the initialization step and the sampling step, and is generated as a gate-off voltage in the addressing step and the light-emitting step, The third scanning pulse is generated as a gate-on voltage in the sampling step and the addressing step, and is generated as a gate-off voltage in the initialization step and the light-emitting step, The first EM pulse is generated as a gate-on voltage in the initialization step and the light-emitting step, and is generated as a gate-off voltage in the sampling step and the addressing step, and The second EM pulse is generated as a gate-on voltage in the light emitting step, and is generated as a gate-off voltage in the initialization step, the sampling step, and the addressing step.

9. The pixel circuit according to claim 4, wherein: The frequency of the data refresh frame for writing pixel data into the pixel circuit is set to be lower in the low-speed driving mode than in the normal driving mode, In the data refresh frame of the low-speed driving mode and each frame of the normal driving mode, the driving time of the pixel circuit is divided into an initialization step, a sampling step, an addressing step and a light-emitting step. The low-speed driving mode includes one or more anode reset frames allocated after the data refresh frame, and In the anode reset frame, the driving time of the pixel circuit is divided into a sampling step and a light emitting step.

10. The pixel circuit according to claim 9, wherein: The voltage of the gate line to which the second scan pulse is applied in the anode reset frame is a gate-off voltage.

11. The pixel circuit according to claim 8, wherein: allocating a reset step before said initialization step, and In the resetting step, the third scan pulse is generated as a gate-on voltage, and voltages of the first scan pulse, the second scan pulse, the first EM pulse, and the second EM pulse maintain a gate-off voltage.

12. The pixel circuit according to claim 1, wherein: The scan pulses applied to the first switching element and the second switching element swing between a gate-on voltage and a gate-off voltage, and When the accumulated driving time of the pixel circuit increases, the gate-on voltage of at least the scanning pulse applied to the first switching element among the scanning pulses increases or the gate-off voltage of at least the scanning pulse applied to the first switching element among the scanning pulses decreases.

13. The pixel circuit according to claim 1, wherein: When the accumulated driving time of the pixel circuit increases, the data voltage decreases.

14. The pixel circuit according to claim 8, wherein: In the sampling step, the threshold voltage of the driving element is sampled.

15. The pixel circuit according to claim 9, wherein: In the anode reset frame, the reference voltage is applied to the third node.

16. The pixel circuit according to claim 11, wherein: a holding step is allocated between the initialization step and the reset step, and In the maintaining step, voltages of the first scan pulse, the second scan pulse, the third scan pulse, the first EM pulse, and the second EM pulse maintain a gate-off voltage.

17. A display device, comprising: a display panel, wherein the display panel is provided with a plurality of data lines, a plurality of gate lines crossing the data lines, a first power line to which a pixel driving voltage is applied, a second power line to which an initialization voltage is applied, a third power line to which a reference voltage is applied, a fourth power line to which a low-potential power voltage is applied, and a plurality of pixel circuits connected to the data lines, the gate lines, and the power lines; a data driver for providing a data voltage of pixel data to the data line; as well as a gate driver for providing a gate signal to the gate line; Wherein, each of the pixel circuits includes: a driving element comprising a first electrode connected to the first node, a first gate electrode connected to the second node, a second electrode connected to the third node, and a second gate electrode connected to the fourth node and to which a preset voltage is applied; a light emitting element including an anode connected to the fourth node and a cathode to which a low-potential power supply voltage is applied, the light emitting element being driven by the current from the driving element; a first switching element including a first electrode connected to the first node, a second electrode connected to the second node, and a gate electrode to which a second scan pulse is applied; a second switching element including a first electrode connected to the third node, a second electrode connected to the fourth node, and a gate electrode to which a second EM pulse is applied; a third switching element, the third switching element including a first electrode to which an initialization voltage is applied, a second electrode connected to the fifth node, and a gate electrode to which the second scan pulse is applied; a fourth switching element, the fourth switching element including a first electrode to which the data voltage is applied, a second electrode connected to the fifth node, and a gate electrode to which the first scan pulse is applied; a fifth switching element, the fifth switching element including a first electrode to which a pixel driving voltage is applied, a second electrode connected to the first node, and a gate electrode to which a first EM pulse is applied; a sixth switching element, the sixth switching element including a first electrode to which a reference voltage is applied, a second electrode connected to the third node, and a gate electrode to which a third scan pulse is applied; a seventh switching element, the seventh switching element including a first electrode to which the initialization voltage is applied, a second electrode connected to the fourth node, and a gate electrode to which the third scan pulse is applied; a first capacitor including a first electrode connected to the fifth node and a second electrode connected to the second node; and A second capacitor includes a first electrode connected to the fifth node and a second electrode connected to the third node.

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