Inverter circuit, gate driver and display device using the same

Abstract

Disclosed are an inverter circuit according to an embodiment, a gate driver using the inverter circuit, and a display device. The inverter circuit according to the embodiment includes: a first transistor connected between a high-potential voltage line and a first node; a second transistor having a gate connected to the first node and turned on in response to a voltage at the first node to charge a second control node to a high-potential voltage applied to the high-potential voltage line; a third transistor having a gate connected to the first control node, a first electrode connected to the first node, and a second electrode connected to a second control node; and a fourth transistor having a gate connected to the first control node, a first electrode connected to the second control node, and a second electrode connected to a low-potential voltage line. The third and fourth transistors are turned on in response to a voltage at the first control node to discharge the second control node to a low-potential voltage applied to the low-potential voltage line.

Description

Technical Field

[0001] The present disclosure relates to an inverter circuit, a gate driver using the inverter circuit, and a display device. Background Art

[0002] Display devices include liquid crystal display (LCD) devices, electroluminescent display devices, field emission display (FED) devices, plasma display panels (PDPs), and the like.

[0003] Electroluminescent displays are classified into inorganic and organic light-emitting displays, depending on the material used in their light-emitting layers. Active-matrix organic light-emitting displays use self-luminous elements, such as organic light-emitting diodes (OLEDs), to reproduce input images. Organic light-emitting displays offer the advantages of fast response times, high luminous efficiency, high brightness, and a wide viewing angle.

[0004] Some display devices (e.g., liquid crystal display devices or organic light-emitting display devices) include a display panel including a plurality of sub-pixels, a driver that outputs a drive signal for driving the display panel, a power supply that generates power to be supplied to the display panel or the driver, etc. The driver includes a gate driver that provides a scan signal or a gate signal to the display panel, and a data driver that provides a data signal to the display panel.

[0005] In such a display device, when driving signals (eg, scan signals, EM signals, and data signals) are supplied to a plurality of sub-pixels formed in a display panel, selected sub-pixels transmit light or directly emit light, thereby displaying an image.

[0006] In this case, the gate driver controls the charging and discharging of the Q node and the Qb node to provide a scan signal or a gate signal to the display panel. However, due to the ripple of the Q node, leakage current and malfunction may occur. Summary of the Invention

[0007] The present disclosure is intended to address all of the above-mentioned needs and problems.

[0008] The present disclosure is directed to providing an inverter circuit, a gate driver and a display device using the inverter circuit.

[0009] It should be noted that the objects of the present disclosure are not limited to the above objects, and other objects of the present disclosure will be apparent to those skilled in the art from the following description.

[0010] The inverter circuit of the present disclosure includes: a first transistor, which is connected between a high-potential voltage line and a first node; a second transistor, which has a gate connected to the first node and is turned on according to the voltage of the first node to charge a second control node to a high-potential voltage applied to the high-potential voltage line; a third transistor, which has a gate connected to the first control node, a first electrode connected to the first node, and a second electrode connected to the second control node; and a fourth transistor, which has a gate connected to the first control node, a first electrode connected to the second control node, and a second electrode connected to the low-potential voltage line, wherein the third transistor and the fourth transistor are turned on according to the voltage of the first control node to discharge the second control node to a low-potential voltage applied to the low-potential voltage line. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0012] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0013] Figures 2 to 4 is a circuit diagram showing various pixel circuits applicable to the pixel circuit of the present disclosure;

[0014] Figure 5 is a view schematically illustrating a scan driver according to an embodiment of the present disclosure;

[0015] Figure 6 is a circuit diagram illustrating in detail a scan driver according to an embodiment of the present disclosure;

[0016] Figure 7 It shows Figure 6 The waveform diagram of the voltage of the control node and the input and output signals of the scan driver shown;

[0017] Figure 8A and Figure 8B This is a circuit diagram used to comparatively describe the ripple prevention principle of the inverter;

[0018] Figure 9A and Figure 9B This is a circuit diagram used to comparatively describe the principle of preventing leakage current in inverters.

[0019] Figure 10 is a diagram showing simulation results of an inverter circuit according to an embodiment;

[0020] Figure 11 is a view schematically illustrating an EM driver according to an embodiment of the present disclosure;

[0021] Figure 12 is a circuit diagram illustrating in detail an EM driver according to an embodiment of the present disclosure;

[0022] Figure 13 It shows Figure 12 The waveform diagram of the voltage of the control node and the input and output signals of the EM driver shown;

[0023] Figure 14A and Figure 14B This is a circuit diagram used to comparatively describe the ripple prevention principle of the inverter;

[0024] Figure 15A and Figure 15B is a circuit diagram for comparatively describing the leakage current prevention principle of an inverter; and

[0025] Figure 16 is a diagram showing simulation results of the inverter circuit according to the embodiment. DETAILED DESCRIPTION

[0026] The advantages and features of the present disclosure and the methods for achieving them will be more clearly understood from the embodiments described below with reference to the accompanying drawings. However, the present disclosure is not limited to the following embodiments, but can be implemented in various forms. On the contrary, the present embodiments will complete the disclosure of the present disclosure and enable those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is limited only within the scope of the appended claims.

[0027] The shapes, sizes, ratios, angles, quantities, etc. shown in the drawings used to describe the embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. In this specification, the same reference numerals generally represent the same elements. In addition, when describing the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0028] Terms such as "including," "comprising," "having," and "consisting of" used herein are generally intended to allow the addition of other components unless these terms are used with the term "only." Any reference to the singular may also include the plural unless expressly stated otherwise.

[0029] Even if not explicitly stated, components are interpreted as including ordinary margins of error.

[0030] When terms such as “on,” “above,” “below,” and “near” are used to describe the positional relationship between two components, one or more components may be located between the two components unless these terms are used with the terms “immediately” or “directly.”

[0031] Terms such as “first” and “second” may be used to distinguish components from one another, but the function or structure of the components is not limited by the preceding sequence numbers or names of the components.

[0032] Like reference numerals may represent substantially like elements throughout this disclosure.

[0033] The following embodiments may be combined or combined with each other in part or in whole, and may be linked and operated in technically different ways. These embodiments may be implemented independently of each other or in association with each other.

[0034] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0035] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0036] Reference Figure 1 , a display device according to an embodiment of the present disclosure includes a display panel 100, a display panel driver for writing pixel data to pixels of the display panel 100, and a power supply 140 for generating power required to drive the pixels and the display panel driver.

[0037] The display panel 100 includes a pixel array AA that displays an input image. The pixel array AA includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 102, and pixels arranged in a matrix.

[0038] The pixel array AA includes a plurality of pixel rows L1 to Ln. Each of the pixel rows L1 to Ln includes a row of pixels arranged along the row direction X in the pixel array AA of the display panel 100. The pixels arranged in one pixel row share a gate line 103. Sub-pixels arranged in the column direction Y along the data line direction share the same data line 102. One horizontal period 1H is the time obtained by dividing one frame period by the total number of pixel rows L1 to Ln.

[0039] A touch sensor may be provided on the display panel 100. Touch input may be sensed using a separate touch sensor or may be sensed by a pixel. The touch sensor may be provided as an on-cell type or add-on type on the screen of the display panel, or implemented as an in-cell type touch sensor embedded in the pixel array AA.

[0040] The display panel 100 may be implemented as a flexible display panel. The flexible display panel may be made of a plastic OLED panel. An organic film may be provided on a back panel of the plastic OLED panel, and the pixel array AA may be formed on the organic film.

[0041] The backplane of the plastic OLED panel can be a polyethylene terephthalate (PET) substrate. An organic film is formed on the backplane. The pixel array AA and the touch sensor array can be formed on the organic film. The backplane blocks moisture penetration so that the pixel array AA is not exposed to moisture. The organic film can be a thin polyimide (PI) film substrate. A multilayer buffer film can be formed of an insulating material (not shown) on the organic film. Circuits can be formed on the organic film to provide power or signals applied to the pixel array AA and the touch sensor array.

[0042] To achieve color, each pixel can be divided into a red sub-pixel (hereinafter referred to as an "R sub-pixel"), a green sub-pixel (hereinafter referred to as a "G sub-pixel"), and a blue sub-pixel (hereinafter referred to as a "B sub-pixel"). Each pixel can also include a white sub-pixel. Each sub-pixel 101 includes a pixel circuit. The pixel circuit is connected to a data line 102 and a gate line 103.

[0043] Hereinafter, a pixel may be interpreted as having the same meaning as a sub-pixel.

[0044] The power supply 140 generates the DC power required to drive the pixel array AA and the display panel driving circuit of the display panel 100 using a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply 140 can regulate the DC input voltage from the host system (not shown) to generate DC voltages, such as the gamma reference voltage VGMA, the gate-on voltages VGH and VEH, the gate-off voltages VGL and VEL, the pixel drive voltage EVDD, and the pixel low-potential power supply voltage EVSS. The gamma reference voltage VGMA is provided to the data driver 110. The gate-on voltages VGH and VEH and the gate-off voltages VGL and VEL are provided to the gate driver 120. The pixel drive voltage EVDD and the pixel low-potential power supply voltage EVSS are jointly provided to the pixels.

[0045] The display panel driving circuit writes pixel data (digital data) of an input image into pixels of the display panel 100 under the control of a timing controller (TCON) 130 .

[0046] The display panel driving circuit includes a data driver 110 and a gate driver 120 .

[0047] A demultiplexer (DEMUX) 112 may be provided between the data driver 110 and the data lines 102. The demultiplexer 112 sequentially connects one channel of the data driver 110 to the plurality of data lines 102 and distributes the data voltage output from one channel of the data driver 110 to the data lines 102 in a time-division manner, thereby reducing the number of channels of the data driver 110. The demultiplexer 112 may be omitted. In this case, the output buffer AMP of the data driver 110 is directly connected to the data lines 102.

[0048] The display panel driving circuit may further include a touch sensor driver for driving the touch sensor. Figure 1 In the mobile device, the timing controller 130, the power supply 140, the data driver 110, etc. may be integrated into one driving integrated circuit (IC).

[0049] The data driver 110 generates a data voltage Vdata by converting pixel data of an input image received from the timing controller 130 into a gamma compensation voltage in each frame period using a digital-to-analog converter (DAC). The gamma reference voltage VGMA is divided for each grayscale level by a voltage divider circuit. The gamma compensation voltage divided from the gamma reference voltage VGMA is provided to the DAC of the data driver 110. The data voltage Vdata is output through an output buffer AMP in each channel of the data driver 110.

[0050] In the data driver 110, the output buffer AMP included in one channel can be connected to adjacent data lines 102 through the demultiplexer 112. The demultiplexer 112 can be directly formed on the substrate of the display panel 100 or integrated into one driving IC together with the data driver 110.

[0051] The gate driver 120 may be implemented as a gate-in-panel (GIP) circuit directly formed on the bezel BZ region of the display panel 100 together with the TFT array of the pixel array AA. The gate driver 120 sequentially outputs gate signals to the gate lines 103 under the control of the timing controller 130. The gate driver 120 may sequentially provide the gate signals to the gate lines 103 by shifting the gate signals using a shift register.

[0052] The gate signal may include a scan signal for selecting a pixel row in which data is to be written in synchronization with a data voltage, and an EM signal that defines a light-emitting time of a pixel charged with the data voltage.

[0053] The gate driver 120 may include a scan driver 121 and an EM driver 122 .

[0054] The scan driver 121 outputs a scan signal SCAN in response to a start pulse and a shift clock from the timing controller 130, and shifts the scan signal SCAN according to the shift clock timing. The EM driver 122 outputs an EM signal EM in response to a start pulse and a shift clock from the timing controller 130, and sequentially shifts the EM signal EM according to the shift clock. Thus, the scan signal SCAN and the EM signal EM are sequentially provided to the gate lines 103 of the pixel rows L1 to Ln. In the case of a borderless model, at least some of the transistors and clock wiring that constitute the gate driver 120 can be dispersedly arranged in the pixel array AA.

[0055] The timing controller 130 receives digital video data DATA of an input image and timing signals synchronized with the digital video data DATA from a host system (not shown). The timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock CLK, a data enable signal DE, and the like. Because the vertical and horizontal periods can be determined by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE has a cycle of one horizontal period (1H).

[0056] The host system may be any of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a vehicle system, and a mobile device system.

[0057] The timing controller 130 multiplies the input frame frequency by i and controls the operation timing of the display panel driving circuit at a frame frequency of input frame frequency×i (i is a positive integer greater than 0) Hz. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) scheme and 50 Hz in the Phase Alternation Line (PAL) scheme.

[0058] The display panel drive circuit can operate in a low-speed drive mode. When the input image does not change within a preset number of frames in the analysis of the input image, the low-speed drive mode can be set to reduce the power consumption of the display device. In the low-speed drive mode, when a still image is input for a predetermined time or longer, the power consumption of the display panel drive circuit and the display panel 100 can be reduced by reducing the refresh rate of the pixels. In the low-speed drive mode, the timing controller 130 can reduce the frame rate to a frequency between 1 Hz and 30 Hz to reduce the refresh rate of the pixels. At a frame rate of 60 Hz or lower, flickering may be seen in the displayed image.

[0059] To reduce flicker in the low-speed driving mode, when the frame frequency is reduced in the low-speed driving mode, the timing controller 130 may maintain the high frequency of the EM signal EM and may reduce the frequencies of the scan signal SCAN and the data voltage Vdata. In this case, when entering the low-speed driving mode, the output frequencies of the scan driver 121 and the data driver 110 are reduced under the control of the timing controller 130, but the output frequency of the EM driver 122 remains unchanged.

[0060] Based on the timing signals Vsync, Hsync and DE received from the host system, the timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110, MUX signals MUX1 and MUX2 for controlling the operation timing of the demultiplexer 112, and a gate timing control signal for controlling the operation timing of the gate driver 120.

[0061] The voltage level of the gate timing control signal output from the timing controller 130 can be converted into gate-on voltages VGH and VEH and gate-off voltages VGL and VEL by a level shifter (not shown), and then provided to the gate driver 120. That is, the level shifter converts the low-level voltage of the gate timing control signal into the gate-off voltages VGL and VEL, and converts the high-level voltage of the gate timing control signal into the gate-on voltages VGH and VEH. The gate timing signal includes a start pulse and a shift clock.

[0062] Figures 2 to 4 is a circuit diagram illustrating various pixel circuits applicable to the pixel circuit of the present disclosure.

[0063] Reference Figure 2 The pixel circuit includes a light-emitting element OLED, a driving element DT that supplies current to the light-emitting element OLED, a switching element M01 that connects the data line 40 and the gate (or gate electrode) of the driving element DT in response to a scan signal SCAN, and a capacitor Cst connected to the gate (or gate electrode) of the driving element DT. The driving element DT and the switching element M01 can be implemented using n-channel transistors. However, the present disclosure is not limited thereto. The driving element DT and the switching element M01 can also be implemented using p-channel transistors.

[0064] An organic light emitting diode used as a light emitting element may have a tandem structure in which a plurality of light emitting layers are stacked. An organic light emitting diode having a tandem structure can improve the brightness and lifespan of a pixel.

[0065] A pixel driving voltage EVDD is applied to a first electrode of a driving element DT via a first power line 41. The driving element DT drives the light-emitting element OLED by supplying a current to the light-emitting element OLED according to a gate-source voltage Vgs. When the forward voltage between the anode and cathode is greater than or equal to a threshold voltage, the light-emitting element OLED turns on and emits light.

[0066] The storage capacitor Cst is connected between the first node n1 and the second node n2, and the gate-source voltage Vgs of the driving element DT is charged in the storage capacitor Cst.

[0067] Figure 3 An example of a pixel circuit connected to an external compensation circuit is shown.

[0068] Reference Figure 3 The pixel circuit further includes a second switching element M02 connected between the reference voltage line 43 and the second electrode (or source) of the driving element DT. In this pixel circuit, the driving element DT and the switching elements M01 and M02 can be implemented using n-channel transistors. However, the present disclosure is not limited thereto. The driving element DT and the switching elements M01 and M02 can also be implemented using p-channel transistors.

[0069] The second switching element M02 applies a reference voltage Vref in response to a scan signal SCAN or a separate sensing pulse SENSE. The reference voltage Vref is applied to the pixel circuit through a reference voltage line 43.

[0070] In the sensing mode, the current flowing through the channel of the driving element DT or the voltage between the driving element DT and the light-emitting element OLED is sensed through the reference voltage line 43. The current flowing through the reference voltage line 43 is converted into a voltage by an integrator and converted into digital data by an analog-to-digital converter (ADC). This digital data is sensing data including the threshold voltage or mobility information of the driving element DT. The sensing data is transmitted to the data operation unit. The data operation unit can receive the sensing data from the ADC to compensate for the driving deviation and degradation of the pixel by adding or multiplying the compensation value selected based on the sensing data with the pixel data.

[0071] Reference Figure 4 The pixel circuit includes a light-emitting element OLED, a driving element DT that drives the light-emitting element OLED, a plurality of switching elements M01, M02, and M03 that switch the current path connected to the driving element DT, and a capacitor Cst that stores the gate-source voltage Vgs of the driving element DT. The driving element DT and the switching elements M01, M02, and M03 can be implemented using n-channel transistors. However, the present disclosure is not limited to this. The driving element DT and the switching elements M01, M02, and M03 can also be implemented using p-channel transistors.

[0072] The light-emitting element OLED emits light by a current applied through the channel of the driving element DT according to the gate-source voltage Vgs of the driving element DT that varies with the data voltage Vdata. The light-emitting element OLED can be implemented using an organic light-emitting diode (OLED) including an organic compound layer formed between an anode and a cathode. The organic compound layer may include, but is not limited to, a hole injection layer HIL, a hole transport layer HTL, an emission layer EML, an electron transport layer ETL, an electron injection layer EIL, and the like. The anode of the light-emitting element OLED is connected to the driving element DT via a second node n2, and the cathode of the light-emitting element OLED is connected to a second power line 42 to which a low potential power supply voltage EVSS is applied.

[0073] The first switching element M01 is turned on in response to the gate-on voltage VGH of the scan signal SCAN to supply a data voltage Vdata to the driving element DT connected to the first node n1 by connecting the data line to the first node n1. The first node n1 is connected to the gate of the driving element DT. Therefore, the gate voltage of the driving element DT is the same as the voltage of the first node n1. The first switching element M01 includes a gate connected to the first gate line to which the scan signal SCAN is applied, a first electrode connected to the data line, and a second electrode connected to the first node n1.

[0074] The second switching element M02 is turned on according to the gate-on voltage VGH of the scan signal SCAN to provide the reference voltage Vref to the second node n2. The second switching element M02 has a gate connected to the first gate line to which the scan signal SCAN is applied, a first electrode connected to the reference voltage line 43 to which the reference voltage Vref is applied, and a second electrode connected to the second node n2.

[0075] The third switching element M03 is turned on according to the gate-on voltage VEH of the EM signal EM to supply the pixel driving voltage EVDD to the third node n3. The third switching element M03 includes a gate electrode connected to the second gate line to which the EM signal EM is applied, a first electrode connected to the first power line 41 to which the pixel driving voltage EVDD is supplied, and a second electrode connected to the third node n3.

[0076] The driving element DT drives the light emitting element OLED by supplying a current to the light emitting element OLED according to the gate-source voltage Vgs. The driving element DT includes a gate connected to a first node n1, a first electrode (or drain) connected to a third node n3, and a second electrode (or source) connected to an anode of the light emitting element OLED through a second node n2.

[0077] The storage capacitor Cst is connected between the first node n1 and the second node n2, and the gate-source voltage Vgs of the driving element DT is charged in the storage capacitor Cst.

[0078] Figure 5 is a view schematically illustrating a scan driver according to an embodiment of the present disclosure.

[0079] Reference Figure 5 According to an embodiment, the scan driver 121 includes a plurality of signal transmission units (…, ST(n-2), ST(n-1), ST(n), ST(n+1), ST(n+2), …), which pass through a carry line for transmitting a carry signal and are cascade-connected with respect to the odd-numbered signal transmission units and the even-numbered signal transmission units.

[0080] The timing controller 130 may adjust the width and multiplex output of an output signal of the scan driver using the start pulse Vst input to the scan driver 121 .

[0081] Each of the signal transmission units (..., ST(n-2), ST(n-1), ST(n), ST(n+1), ST(n+2), ...) receives a clock signal CLK and a start pulse or a carry signal output from a preceding odd-numbered signal transmission unit or an even-numbered signal transmission unit. The first signal transmission unit ST(1) starts to be driven according to the start pulse Vst, and the other signal transmission units (..., ST(n-2), ST(n-1), ST(n), ST(n+1), ST(n+2), ...) receive a carry signal (..., Cout(n-2), Cout(n-1), Cout(n), Cout(n+1), Cout(n+2), ...) from the preceding odd-numbered signal transmission unit or the even-numbered signal transmission unit to start being driven.

[0082] Figure 6 1 is a circuit diagram illustrating a scan driver according to an embodiment of the present disclosure in detail. The transistors T1 to T9 constituting the scan driver 121 may be implemented with n-channel oxide thin film transistors (TFTs). Figure 6 The circuit shown is the circuit of the nth (n is a positive integer) signal transmission unit ST(n). Other signal transmission units can be implemented using a circuit substantially the same as that of the nth signal transmission unit ST(n). Figure 7 It shows Figure 6 FIG. 4 is a diagram showing the voltage of the control node of the scan driver and the waveforms of the input and output signals.

[0083] Reference Figure 6 and Figure 7 According to an embodiment, the scan driver 121 may include a first control node (hereinafter referred to as “Q node”), a second control node (hereinafter referred to as “Qb node”), a first circuit unit 61, a second circuit unit 62 and a third circuit unit 63.

[0084] The first circuit unit 61 is used to control the charging and discharging of the Q node Q and the Qb node Qb. The first circuit unit 61 includes a first transistor T1, a first-a transistor T1A, a third transistor T3, a third-a transistor T3A, a third-n transistor T3n, a third-nA transistor T3nA, and a third-q transistor T3q.

[0085] The first transistor T1 is turned on by the N-2 carry signal applied through the N-2 carry signal line C(n-2) and transmits the N-2 carry signal to the Qh node Qh. In the first transistor T1, the gate electrode and the first electrode are commonly connected to the N-2 carry signal line C(n-2), and the second electrode is connected to the Qh node Qh.

[0086] The first-a transistor T1A is turned on by the N-2 th carry signal applied through the N-2 th carry signal line C(n-2), and charges the Q node Q according to the N-2 th carry signal. In the first-a transistor T1A, a gate electrode is connected to the N-2 th carry signal line C(n-2), a first electrode is connected to the second electrode of the first transistor T1, and a second electrode is connected to the Q node Q.

[0087] The third transistor T3 is turned on by the Qb node Qb and discharges the Q node Q to the second low potential voltage of the second low potential voltage line GVSS1 together with the third-a transistor T3A. In the third transistor T3, the gate electrode is connected to the Qb node Qb, the first electrode is connected to the Q node Q, and the second electrode is connected to the first electrode of the third-a transistor T3A.

[0088] The third-a transistor T3A is turned on by the Qb node Qb and discharges the Q node Q to the second low potential voltage of the second low potential voltage line GVSS1 together with the third transistor T3. In the third-a transistor T3A, the gate electrode is connected to the Qb node Qb, the first electrode is connected to the second electrode of the third transistor T3, and the second electrode is connected to the second low potential voltage line GVSS1.

[0089] The third-n transistor T3n is turned on by the N+2th carry signal applied via the N+2th carry signal line C(n+2), and discharges the Q node Q to the second low potential voltage of the second low potential voltage line GVSS1 together with the third-nA transistor T3nA. In the third-n transistor T3n, a gate electrode is connected to the N+2th carry signal line C(n+2), a first electrode is connected to the Q node Q, and a second electrode is connected to the first electrode of the third-nA transistor T3nA.

[0090] The third-nA transistor T3nA is turned on by the N+2th carry signal applied via the N+2th carry signal line C(n+2), and discharges the Q node Q to the second low potential voltage of the second low potential voltage line GVSS1 together with the third-n transistor T3n. In the third-nA transistor T3nA, the gate electrode is connected to the N+2th carry signal line C(n+2), the first electrode is connected to the second electrode of the third-n transistor T3n, and the second electrode is connected to the second low potential voltage line GVSS1.

[0091] The third-q transistor T3q is turned on by the Q node Q and transmits the high potential voltage of the high potential voltage line GVDD to the Qh node Qh. In the third-q transistor T3q, the gate electrode is connected to the Q node Q, the first electrode is connected to the high potential voltage line GVDD, and the second electrode is connected to the Qh node Qh.

[0092] The second circuit unit 62 includes a fourth-a transistor T4A, a fourth-b transistor T4B, a fifth-a transistor T5A, a fifth-b transistor T5B, and a fifth transistor T5.

[0093] The second circuit unit 62 includes an inverter circuit that inverts the voltage of the Q node Q and applies the voltage to the Qb node Qb. The inverter circuit includes a Qb node charging unit and a Qb node discharging unit.

[0094] The Qb node charging unit includes a plurality of transistors T4A and T4B. The Qb node discharging unit includes a plurality of transistors T5A and T5B, and the plurality of transistors T5A and T5B are connected in series. The plurality of transistors T5A and T5B are connected in series between the first node 80 and the second low potential voltage line GVSS1.

[0095] The fourth-a transistor T4A is turned on by the high potential voltage transmitted through the fourth-b transistor T4B, and charges the Qb node Qb to the high potential voltage applied to the high potential voltage line GVDD. The first capacitor Ca is used to form a bootstrap voltage at the gate node of the fourth-a transistor T4A. In the fourth-a transistor T4A, the gate electrode is connected to one end of the first capacitor Ca and the second electrode of the fourth-b transistor T4B, the first electrode is connected to the high potential voltage line GVDD, and the second electrode is connected to the other end of the first capacitor Ca and the Qb node Qb.

[0096] The fourth-b transistor T4B is turned on by the high potential voltage and transmits the high potential voltage applied to the high potential voltage line GVDD to the gate node of the fourth-a transistor T4A. In the fourth-b transistor T4B, the gate and the first electrode are connected to the high potential voltage line GVDD, and the second electrode is connected to the gate electrode of the fourth-a transistor T4A and the first electrode of the fifth-a transistor T5A.

[0097] The fifth-a transistor T5A is turned on by the Q node Q and, together with the fifth-b transistor T5B, discharges the first node 80 to the second low potential voltage applied to the second low potential voltage line GVSS1. In the fifth-a transistor T5A, the gate electrode is connected to the Q node Q, the first electrode is connected to the gate electrode of the fourth-a transistor T4A and the second electrode of the fourth-b transistor T4B, and the second electrode is connected to the Qb node Qb.

[0098] The fifth-b transistor T5B is turned on by the Q node Q and, together with the fifth-a transistor T5A, discharges the first node 80 to the second low potential voltage applied to the second low potential voltage line GVSS1. In the fifth-b transistor T5B, the gate electrode is connected to the Q node Q, the first electrode is connected to the second electrode of the fourth-a transistor T4A, one end of the first capacitor Ca, and the Qb node Qb, and the second electrode is connected to the second low potential voltage line GVSS1.

[0099] The fifth transistor T5 is turned on by the N-2 carry signal of the N-2 carry signal line C(n-2) and discharges the Qb node Qb to the second low potential voltage of the second low potential voltage line GVSS1. In the fifth transistor T5, the gate electrode is connected to the N-2 carry signal line C(n-2), the first electrode is connected to the Qb node Qb, and the second electrode is connected to the second low potential voltage line GVSS1.

[0100] The third circuit unit 63 outputs a scan signal SC_OUT(n) and a carry signal C(n) in response to the potentials of the Q node Q and the Qb node Qb. The third circuit unit 63 includes first buffer transistors T6 and T7 that output the carry signal C(n) and second buffer transistors T8 and T9 that output the scan signal SC_OUT(n).

[0101] The first buffer transistors T6 and T7 are divided into a first pull-up transistor T6 that turns on based on the potential of the Q node Q, and a first pull-down transistor T7 that turns on based on the potential of the Qb node Qb. In the first pull-up transistor T6, the gate electrode is connected to the Q node Q and one end of the second capacitor Cb, the first electrode is connected to the first clock signal line CLK(n), and the second electrode is connected to the first output terminal C(n) and the other end of the second capacitor Cb. In the first pull-down transistor T7, the gate electrode is connected to the Qb node Qb, the first electrode is connected to the first output terminal C(n) and the other end of the second capacitor Cb, and the second electrode is connected to the second low-potential voltage line GVSS1. Based on the first clock signal applied via the first clock signal line CLK(n) and the second low-potential voltage applied via the second low-potential voltage line GVSS1, the first buffer transistors T6 and T7 output a carry signal C(n).

[0102] The second buffer transistors T8 and T9 are divided into a second pull-up transistor T8 that is turned on based on the potential of the Q node Q, and a second pull-down transistor T9 that is turned on based on the potential of the Qb node Qb. The gate electrode of the second pull-up transistor T8 is connected to the Q node Q, the first electrode is connected to the second clock signal line SC_CLK(n), and the second electrode is connected to the second output terminal SC_OUT(n). The gate electrode of the second pull-down transistor T9 is connected to the Qb node Qb, the first electrode is connected to the second output terminal SC_OUT(n), and the second electrode is connected to the first low-potential voltage line GVSS0. Based on the second clock signal applied via the second clock signal line SC_CLK(n) and the first low-potential voltage applied via the first low-potential voltage line GVSS0, the second buffer transistors T8 and T9 output the second scan signal SC_OUT(n). The first low-potential voltage is set higher than the second low-potential voltage.

[0103] A structural advantage of an inverter circuit applied to a scan driver according to an embodiment will be described.

[0104] Figure 8A and Figure 8B This is a circuit diagram used to comparatively describe the ripple prevention principle of the inverter. Figure 9A and Figure 9B This is a circuit diagram for comparatively describing the leakage current prevention principle of an inverter, and Figure 10 is a diagram showing simulation results of the inverter circuit according to the embodiment.

[0105] Refer to the ripple prevention of the inverter. Figure 8AIn an inverter circuit (in which the Qb node discharge unit according to an embodiment is implemented as a structure in which two transistors are connected in series and a low-voltage power supply is connected), when the voltage of the Q node Q is a low voltage and the voltage of the Qb node Qb is a high voltage, since all of the plurality of transistors T5A and T5B connected in series in the Qb node discharge unit are turned off, the Vgs of the fifth transistor T5A becomes -36 V. Therefore, the inverter circuit according to an embodiment can respond to the ripple of the Qb node Qb(n) within 36 V.

[0106] like Figure 8B As shown, the inverter circuit compared with the inverter circuit of the embodiment is an inverter circuit in which two low-voltage power supplies are connected, and when the voltage of the Q node Q is low voltage and the voltage of the Qb node Qb is high voltage, since the plurality of transistors T5A and T5B are turned off in the Qb node discharge unit, the Vgs of the fifth-a transistor T5A becomes -6 V. Therefore, the comparative inverter circuit can also respond to the ripple of the Qb node Qb(n) within 6 V.

[0107] Refer to the section on leakage current prevention. Figure 9A , in the inverter circuit (in which the Qb node discharge unit according to the embodiment is implemented as a structure in which two transistors are connected in series and a low voltage power supply is connected), when the voltage of the Q node Q is a high voltage (24 V) and the voltage of the Qb node Qb is a low voltage (-12 V), since the first node and the Qb node are discharged to the first low potential voltage (-12 V) even when the plurality of transistors T5A and T5B connected in series are turned on, Vgs of the fourth-a transistor T4A is formed to 0 V, thereby reducing leakage current in the first low potential voltage line.

[0108] like Figure 9B As shown, the inverter circuit for comparison with the inverter circuit of the embodiment is an inverter circuit in which two low-voltage power supplies are connected, and when the voltage of the Q node Q is a high voltage (24 V) and the voltage of the Qb node Qb is a low voltage (-12 V), since the plurality of transistors T5A and T5B connected in parallel are turned on, the first node is discharged to the first low potential voltage (-6 V), and the Qb node is discharged to the second low potential voltage (-12 V), so that the Vgs of the fourth-a transistor T4A is formed to 6 V (=-6 V-(-12 V)), thereby generating a leakage current in the second low potential voltage line.

[0109] Therefore, if Figure 10As shown, in the scan driver applying the inverter circuit according to the embodiment, the leakage current is measured as 19.626 mA only in the first low potential voltage line, but in the scan driver applying the inverter circuit for comparison, since the leakage current in the first low potential voltage line is measured as 1.186 mA and the leakage current in the second low potential voltage line is measured as 18.241 mA, the total leakage current is 19.427 mA.

[0110] According to the simulation results, it can be seen that even when a low potential voltage is used, the scan driver to which the inverter circuit according to the embodiment is applied exhibits comparable performance of reducing leakage current while minimizing the influence of the ripple of the Q node.

[0111] Figure 11 is a view schematically illustrating an EM driver according to an embodiment of the present disclosure.

[0112] Reference Figure 11 According to an embodiment, the EM driver 122 includes a plurality of signal processing units (..., ST(n-2), ST(n-1), ST(n), ST(n+1), ST(n+2), ...), which are cascade-connected via a carry line that transmits a carry signal.

[0113] The timing controller 130 may adjust the width and multiple output of the output signal EM_OUT of the EM driver using the start pulse Vst input to the EM driver 122 .

[0114] Each of the signal processing units (..., ST(n-2), ST(n-1), ST(n), ST(n+1), ST(n+2), ...) receives a start pulse or a carry signal (..., C(n-2), C(n-1), C(n), C(n+1), C(n+2), ...) output from the previous signal processing unit, and receives a shift clock EMCLK. The first signal processing unit ST(1) starts to be driven according to the start pulse Vst, and the other signal processing units (..., ST(n-2), ST(n-1), ST(n), ST(n+1), ST(n+2), ...) receive the carry signal (..., C(n-2), C(n-1), C(n), C(n+1), C(n+2), ...) from the previous signal processing unit to start being driven. The shift clock EMCLK may be an N (N is a positive integer greater than or equal to 2) phase clock. For example, the shift clock EMCLK may be as follows Figure 7The two-phase clocks EMCLK1 and EMCLK2 are shown. The phases of the two-phase clocks EMCLK1 and EMCLK2 are opposite to each other. The signal processing units (..., ST(n-2), ST(n-1), ST(n), ST(n+1), ST(n+2), ...) shift the start pulse or the carry signal (..., C(n-2), C(n-1), C(n), C(n+1), C(n+2), ...) from the previous signal processing unit according to the timing of the shift clock to sequentially output EM signals (..., EM_out(n-2), EM_out(n-1), EM_out(n), EM_out(n+1), EM_out(n+2), ...).

[0115] Figure 12 1 is a circuit diagram illustrating in detail an EM driver according to an embodiment of the present disclosure. Transistors T1 to T9 constituting the EM driver 122 can be implemented using n-channel oxide TFTs. However, the present disclosure is not limited thereto. Transistors T1 to T9 can also be implemented using p-channel oxide TFTs or n-channel amorphous silicon TFTs. Figure 12 The circuit shown is the circuit of the nth (n is a positive integer) signal transmission unit ST(n). Other signal transmission units can be implemented using a circuit substantially the same as that of the nth signal transmission unit ST(n). Figure 13 It shows Figure 12 The voltage at the control node of the EM driver and the waveforms of the input and output signals are shown.

[0116] Reference Figure 12 and Figure 13 According to an embodiment, the EM driver 122 may include a first control node (hereinafter referred to as “Q node”), a second control node (hereinafter referred to as “Qb node”), a first circuit unit 71 , a second circuit unit 72 , and a third circuit unit 73 .

[0117] The first circuit unit 71 controls the charging and discharging of the Q node Q and the Qb node Qb(n). When the shift clock EMCLK1 has a voltage greater than or equal to the gate-on voltage VEH, the first circuit unit 71 supplies the voltage of the n-1th carry signal C(n-1) from the n-1th signal processing unit ST(n-1), which is the previous signal processing unit, to the Q node Q(n), thereby charging the Q node Q(n). The first circuit unit 71 includes first to third transistors T1, T2, and T3.

[0118] When the shift clock EMCLK1 is a high voltage VGH2 greater than or equal to the gate-on voltage VEH, the first transistor T1 is turned on to provide the voltage (24V) of the carry signal C(n-1) to the Qh node Qh. The first transistor T1 includes a gate to which the shift clock EMCLK1 is applied, a first electrode connected to the (N-1)th carry signal line C(n-1), and a second electrode connected to the Qh node Qh.

[0119] The high voltage VGH2 of the shift clock EMCLK1 can be set to a voltage lower than the second high potential voltage VGH1. The high voltage VGH1 of the carry signal C(n-1) and the EM signal EM OUT(n) is the same voltage as the second high potential voltage VGH1. When the high voltage VGH2 of the shift clock EMCLK1 is set to be lower than the second high potential voltage VGH1, when the voltage of the Q node Q(n) is increased, the Vgs of the first transistor T1 changes to a negative voltage, and the Q node Q(n) floats, thereby improving the voltage increase of the Q node Q(n).

[0120] When the shift clock EMCLK1 is a voltage VGH2 greater than or equal to the gate-on voltage VEH, the second transistor T2 is turned on to supply the voltage of the Qh node Qh to the Q node Q(n), thereby charging the Q node. The second transistor T2 includes a gate to which the shift clock EMCLK1 is applied, a first electrode connected to the Qh node Qh, and a second electrode connected to the Q node Q(n).

[0121] The first transistor T1 and the second transistor T2 are connected in series. The first transistor T1 and the second transistor T2 are connected in series between the N-1th carry signal line C(n-1) and the Q node Q(n).

[0122] When the Q node Q(n) is charged, the third transistor T3 is turned on to supply a second high potential voltage to the Qh node Qh through the second high potential voltage line GVDD1. The second high potential voltage is supplied to the Qh node Qh through the second high potential voltage line GVDD1. The third transistor T3 includes a gate connected to the Q node Q(n), a first electrode connected to the second high potential voltage line GVDD1, and a second electrode connected to the Qh node Qh.

[0123] The second circuit unit 72 includes an inverter circuit that inverts the voltage of the Q node Q(n) and applies the voltage to the Qb node Qb(n). The inverter circuit of the second circuit unit 72 includes a Qb node charging unit and a Qb node discharging unit.

[0124] The Qb node charging unit includes a plurality of transistors T4A and T4B, and the Qb node discharging unit includes a plurality of transistors T5A and T5B, and the plurality of transistors T5A and T5B are connected in series.

[0125] The Qb node charging unit switches a current path between the second high potential voltage line GVDD1 and the Qb node Qb(n) according to the voltage of the n-1th Qb node Qb(n-1) from the n-1th signal transmission unit ST(n-1).

[0126] When the voltage at the first node 80 is a high voltage greater than or equal to the gate-on voltage VEH, the fourth-a transistor T4A is turned on to charge the Qb node Qb(n) to a high voltage greater than or equal to the gate-on voltage VEH by connecting the second high potential voltage line GVDD1 to the Qb node Qb(n). The fourth-a transistor T4A includes a gate connected to the first node 80, a first electrode connected to the second high potential voltage line GVDD1, and a second electrode connected to the Qb node Qb(n). A first capacitor Ca is connected between the gate and the second electrode of the fourth-a transistor T4A. When the fourth-a transistor T4A is turned on by the first capacitor Ca, the voltage of the first node 80 can be increased.

[0127] When the voltage of the n-1th Qb node Qb(n-1) of the n-1th signal transmission unit ST(n-1) is a high voltage greater than or equal to the gate-on voltage VEH, the fourth-b transistor T4B is turned on to charge the first node 80 to a voltage greater than or equal to the gate-on voltage VEH by supplying the second high potential voltage to the first node 80. The fourth-b transistor T4B includes a gate connected to the n-1th Qb node Qb(n-1) of the n-1th signal transmission unit ST(n-1), a first electrode connected to the second high potential voltage line GVDD1, and a second electrode connected to the first node 80.

[0128] When the voltage of the Q node Q(n) and the voltage of the previous carry signal C(n-1) input from the n-1th signal transmission unit ST(n-1) are high voltages greater than or equal to the gate-on voltage VEH, the Qb node discharge unit is turned on to discharge the Qb node Qb(n).

[0129] When the voltage of the Qh node Qh is a high voltage greater than or equal to the gate-on voltage VEH, the fifth-a transistor T5A is turned on to connect the first node 80 to the Qb node Qb(n). The fifth-a transistor T5A includes a gate connected to the Qh node Qh, a first electrode connected to the first node 80, and a second electrode connected to the Qb node Qb(n).

[0130] When the voltage of the Qh node Qh is a high voltage greater than or equal to the gate-on voltage VEH, the fifth-b transistor T5B is turned on to discharge the voltage of the Qb node Qb(n) to the second low potential voltage by connecting the Qb node Qb(n) to the second low potential voltage line GVSS1. The fifth-b transistor T5B includes a gate connected to the Qh node Qh, a first electrode connected to the Qb node Qb(n), and a second electrode connected to the second low potential voltage line GVSS1.

[0131] The third circuit unit 73 outputs the EM signal EM_OUT(n) and the carry signal C(n) in response to the potentials of the Q node Q and the Qb node Qb. The third circuit unit 73 includes first buffer transistors T6 and T7 that output the carry signal C(n) and second buffer transistors T8 and T9 that output the EM signal EM_OUT(n).

[0132] The first buffer transistors T6 and T7 are divided into a first pull-up transistor T6 that is turned on based on the potential of the Q node Q, and a first pull-down transistor T7 that is turned on based on the potential of the Qb node Qb. The first pull-up transistor T6 has a gate connected to the Q node Q, a first electrode connected to the second high-potential voltage line GVDD1, and a second electrode connected to the first output terminal C(n). The first pull-down transistor T7 has a gate connected to the Qb node Qb, a first electrode connected to the first output terminal C(n), and a second electrode connected to the second low-potential voltage line GVSS1. Based on the second high-potential voltage applied via the second high-potential voltage line GVDD1 and the second low-potential voltage applied via the second low-potential voltage line GVSS1, the first buffer transistors T6 and T7 output a carry signal C(n).

[0133] The second buffer transistors T8 and T9 are divided into a second pull-up transistor T8 that is turned on based on the potential of the Q node Q, and a second pull-down transistor T9 that is turned on based on the potential of the Qb node Qb. The gate of the second pull-up transistor T8 is connected to one end of the second capacitor Cb and the Q node Q, the first electrode is connected to the first high-potential voltage line GVDD0, and the second electrode is connected to the second output terminal EM_OUT(n). The gate of the second pull-down transistor T9 is connected to the Qb node Qb, the first electrode is connected to the other end of the second capacitor Cb and the second output terminal EM_OUT(n), and the second electrode is connected to the first low-potential voltage line GVSS0. The second buffer transistors T8 and T9 output the second EM signal EM_OUT(n) based on the first high-potential voltage applied via the first high-potential voltage line GVDD0 and the first low-potential voltage applied via the first low-potential voltage line GVSS0. The first low-potential voltage is set higher than the second low-potential voltage.

[0134] The structural advantages of the inverter circuit applied to the EM driver according to the embodiment will be described.

[0135] Figure 14A and Figure 14B This is a circuit diagram used to comparatively describe the ripple prevention principle of the inverter. Figure 15A and Figure 15B This is a circuit diagram for comparatively describing the leakage current prevention principle of an inverter, and Figure 16 is a diagram showing simulation results of the inverter circuit according to the embodiment.

[0136] Refer to the ripple prevention of the inverter. Figure 14A In an inverter circuit (in which the Qb node discharge unit according to an embodiment is implemented as a structure in which two transistors are connected in series and a low-voltage power supply is connected), when the voltage of the Qh node Qh is a low voltage and the voltage of the Qb node Qb(n) is a high voltage, since the plurality of transistors T5A and T5B connected in series in the Qb node discharge unit are turned off, the Vgs of the fifth transistor T5A becomes -36 V. Therefore, the inverter circuit according to an embodiment can respond to the ripple of the Qb node Qb(n) within 36 V.

[0137] like Figure 14B As shown, the inverter circuit compared with the inverter circuit of the embodiment is an inverter circuit in which two low-voltage power supplies are connected, and when the voltage of the Qh node Qh is low voltage and the voltage of the Qb node Qb(n) is high voltage, since the plurality of transistors T5A and T5B connected in series in the Qb node discharge unit are turned off, the Vgs of the fifth-a transistor T5A becomes -6 V. Therefore, the inverter circuit according to the first embodiment can also respond to the ripple of the Qb node Qb(n) within the 6 V range.

[0138] Refer to the relevant information on leakage current prevention Figure 15A In the inverter circuit (in which the Qb node discharge unit according to the embodiment is implemented as a structure in which two transistors are connected in series and a low voltage power supply is connected), when the voltage of the Qh node Qh is a high voltage and the voltage of the Qb node Qb(n) is a low voltage, since the first node and the Qb node are discharged to the first low potential voltage even when the plurality of transistors T5A and T5B connected in series are turned on, Vgs of the fourth-a transistor T4A is formed to 0 V, thereby reducing leakage current toward the first low potential voltage line.

[0139] like Figure 15BAs shown, the inverter circuit compared with the inverter circuit of the embodiment is an inverter circuit in which two low-voltage power supplies are connected, and when the voltage of the Qh node Qh is a high voltage and the voltage of the Qb node Qb(n) is a low voltage, since the plurality of transistors T5A and T5B are turned on, the first node 80 is discharged to the first low potential voltage, and the Qb node is discharged to the second low potential voltage, so that the Vgs of the fourth-a transistor T4A is formed to 6 V, thereby generating a leakage current toward the second low potential voltage line.

[0140] Therefore, if Figure 16 As shown, in the EM driver to which the inverter circuit according to the embodiment is applied, a leakage current of 10.509 mA is measured only in the first low-potential voltage line. However, in the EM driver to which the inverter circuit for comparison is applied, the leakage current in the first low-potential voltage line is measured as 0.054 mA, and the leakage current in the second low-potential voltage line is measured as 19.407 mA, so the total leakage current is 19.461 mA.

[0141] From the simulation results, it can be seen that the EM driver to which the inverter circuit according to the embodiment is applied exhibits improved performance of reducing leakage current while minimizing the influence of the ripple of the Q node even when a low potential power supply is used.

[0142] In the present disclosure, since the Qb node charging unit and the Qb node discharging unit of the inverter circuit are composed of multiple transistors, and the Qb node discharging unit is implemented as a structure in which multiple transistors are connected in series, one low-voltage power supply can be applied to prevent failures caused by ripples at the Q node without the need to separately apply multiple low-voltage power supplies.

[0143] In the present disclosure, the influence of ripples when the Q node is at a low voltage can be minimized.

[0144] In the present disclosure, leakage current when the Q node is at a high voltage can be minimized.

[0145] In the present disclosure, since a low-voltage power supply is applied, the manufacturing cost can be reduced.

[0146] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above-mentioned embodiments are illustrative in all aspects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the attached claims, and all technical concepts within their equivalent scope should be interpreted as falling within the scope of the present disclosure.

[0147] CROSS-REFERENCE TO RELATED APPLICATIONS

[0148] This application claims priority to and the benefit of Korean Patent Application No. 10-2021-0089981, filed on Jul. 8, 2021, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An inverter circuit, comprising: a first transistor connected between a high potential voltage line and a first node; a second transistor having a gate connected to the first node and being turned on according to a voltage of the first node to charge a second control node to a high potential voltage applied to the high potential voltage line; a third transistor having a gate connected to the first control node, a first electrode connected to the first node, and a second electrode connected to the second control node; as well as a fourth transistor having a gate connected to the first control node, a first electrode connected to the second control node, and a second electrode connected to a low potential voltage line, wherein the third transistor and the fourth transistor are turned on according to the voltage of the first control node to discharge the second control node to the low potential voltage applied to the low potential voltage line, and The first control node is an output node of the inverter circuit.

2. The inverter circuit according to claim 1, wherein: The third transistor and the fourth transistor have a structure of being connected in series between the first node and the low potential voltage line. 3 . The inverter circuit according to claim 1 , further comprising a capacitor having one end connected to the first node and the other end connected to the second control node.

4. The inverter circuit according to claim 1, wherein: When a high voltage is applied to the first control node, the third transistor and the fourth transistor are turned on to discharge the first node and the second control node to the low potential voltage of the low potential voltage line, and the gate-source voltage of the second transistor is maintained at 0V.

5. The inverter circuit according to claim 1, wherein: When a low voltage is applied to the second control node, The third transistor and the fourth transistor are turned on, and thus the gate-source voltage of the second transistor is 0V.

6. The inverter circuit according to claim 1, wherein: The first transistor has a gate and a first electrode connected to the high potential voltage line and a second electrode connected to the first node, and The third transistor and the fourth transistor have gates directly connected to the first control node.

7. The inverter circuit according to claim 1, wherein: The first transistor has a gate connected to the second control node of the n-1th signal transmission unit preceding the nth signal transmission unit to which the inverter circuit belongs, a first electrode connected to the high potential voltage line, and a second electrode connected to the first node, n being a positive integer greater than 1, and The third transistor and the fourth transistor have gates connected to another control node configured to be connected to the first control node.

8. The inverter circuit according to claim 1, wherein: The first to fourth transistors are implemented by n-channel thin film transistors.

9. A gate driver comprising a plurality of signal transmission units connected in cascade via a carry line, a carry signal of an nth signal transmission unit being applied from other signal transmission units to the carry line, in, n is a positive integer, and the nth signal transmission unit includes: a first circuit unit configured to receive the carry signal from the other signal transmission unit to charge a first control node; a second circuit unit including an inverter circuit configured to discharge a second control node according to a voltage of the first control node; and a third circuit unit configured to output a selection signal based on a first high potential voltage and a first low potential voltage based on potentials of the first control node and the second control node; The inverter circuit comprises: a first transistor connected between a second high-potential voltage line and a first node; a second transistor having a gate connected to the first node and being turned on according to a voltage of the first node to charge the second control node to a second high potential voltage applied to the second high potential voltage line; a third transistor having a gate connected to the first control node, a first electrode connected to the first node, and a second electrode connected to the second control node; and a fourth transistor having a gate connected to the first control node, a first electrode connected to the second control node, and a second electrode connected to a second low-potential voltage line, and The third transistor and the fourth transistor are turned on according to the voltage of the first control node to discharge the second control node to a second low potential voltage applied to the second low potential voltage line.

10. The gate driver according to claim 9, wherein When a high voltage is applied to the first control node, the third transistor and the fourth transistor are turned on to discharge the first node and the second control node to the second low potential voltage of the second low potential voltage line, and the gate-source voltage of the second transistor is maintained at 0V.

11. The gate driver according to claim 9, wherein When a low voltage is applied to the second control node, the third transistor and the fourth transistor are turned on, and thus the gate-source voltage of the second transistor becomes 0V.

12. The gate driver according to claim 9, wherein The first transistor has a gate and a first electrode connected to the second high potential voltage line and a second electrode connected to the first node, and The third transistor and the fourth transistor have gates directly connected to the first control node.

13. The gate driver according to claim 12, wherein: The third circuit unit outputs a scan signal and a carry signal for selecting a pixel row in response to potentials of the first control node and the second control node.

14. The gate driver according to claim 9, wherein The first transistor has a gate connected to the second control node of the (n-1)th signal transmission unit, a first electrode connected to the second high potential voltage line, and a second electrode connected to the first node, and The third transistor and the fourth transistor have gates connected to another control node configured to be connected to the first control node.

15. The gate driver according to claim 14, wherein The third circuit unit outputs an EM signal and a carry signal defining a light emitting time of a pixel in response to the potentials of the first control node and the second control node.

16. The gate driver according to claim 9, wherein The first circuit unit receives an (n-2)th carry signal and an (n+2)th carry signal from the other signal transmission unit to charge the first control node.

17. The gate driver according to claim 9, wherein The first circuit unit receives the (n-1)th carry signal and the clock signal from the other signal transmission unit to charge the first control node.

18. The gate driver according to claim 9, wherein The inverter circuit further includes a capacitor having one end connected to the first node and the other end connected to the second control node.

19. A display device, comprising: a data driver configured to output a data voltage; A gate driver, the gate driver including a signal transmission unit, the signal transmission unit including: a first circuit unit configured to receive a carry signal from other signal transmission units of the gate driver to charge a first control node; a second circuit unit including an inverter circuit configured to discharge a second control node according to a voltage of the first control node; and a third circuit unit configured to output a gate signal based on a first high potential voltage and a first low potential voltage based on potentials of the first control node and the second control node; and a plurality of pixel circuits configured to receive the data voltage and the gate signal to reproduce an input image, Wherein, the inverter circuit includes: a first transistor connected between a second high-potential voltage line and a first node; a second transistor having a gate connected to the first node and being turned on according to a voltage of the first node to charge the second control node to a second high potential voltage applied to the second high potential voltage line; a third transistor having a gate connected to the first control node, a first electrode connected to the first node, and a second electrode connected to the second control node; and a fourth transistor having a gate connected to the first control node, a first electrode connected to the second control node, and a second electrode connected to a second low-potential voltage line, and The third transistor and the fourth transistor are turned on according to the voltage of the first control node to discharge the second control node to a second low potential voltage applied to the second low potential voltage line.

20. The display device according to claim 19, wherein When a high voltage is applied to the first control node, the third transistor and the fourth transistor are turned on, and thereby the first node and the second control node are discharged to the second low potential voltage of the second low potential voltage line, and the gate-source voltage of the second transistor is maintained at 0V.

21. The display device according to claim 19, wherein When a low voltage is applied to the second control node, the third transistor and the fourth transistor are turned on, and thus the gate-source voltage of the second transistor becomes 0V.

22. The display device according to claim 19, wherein The first transistor has a gate and a first electrode connected to the second high potential voltage line and a second electrode connected to the first node, and The third transistor and the fourth transistor have gates directly connected to the first control node.

23. The display device according to claim 19, wherein The first transistor has a gate connected to the second control node of the (n-1)th signal transmission unit, a first electrode connected to the second high potential voltage line, and a second electrode connected to the first node, and The third transistor and the fourth transistor have gates connected to another control node configured to be connected to the first control node.

24. The display device according to claim 19, wherein All transistors in the panel including the data driver, the gate driver, and the pixel circuit are implemented by oxide thin film transistors (TFTs) including an n-channel oxide semiconductor.

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