Gate driver and display panel including the same

Abstract

Disclosed are a gate driver and a display panel including the same. The gate driver includes a plurality of signal transmission units connected in cascade via a carry line, wherein an nth (n is a positive integer) signal transmission unit includes: a first output unit that outputs a first gate signal to a first output node based on the voltages of a first control node for a pull-up output voltage and a second control node for a pull-down output voltage; and a second output unit that outputs a second gate signal in which the phase of the first gate signal is inverted to the second output node, wherein the second output unit may include: a first pull-up transistor that outputs a high potential voltage to the second output node based on the voltage of the second control node of the (n-i)th (i is a positive integer less than n)th signal transmission unit; and a second pull-down transistor that outputs a first low potential voltage to the second output node based on the voltage of the first control node of the (n+j)th (j is a natural number greater than n)th signal transmission unit.

Description

Technical Field

[0001] The present disclosure relates to a gate driver and a display panel including the same. Background Art

[0002] Display devices include liquid crystal display (LCD) devices, electroluminescent display devices, field emission display (FED) devices, plasma display panels (PDPs), and the like.

[0003] Electroluminescent displays are classified into inorganic and organic light-emitting displays, depending on the material of their light-emitting layers. Active-matrix organic light-emitting displays reproduce input images using self-luminous elements, such as organic light-emitting diodes (OLEDs), which emit their own light. Organic light-emitting displays offer advantages such as fast response times, high luminous efficiency, brightness, and viewing angles.

[0004] Some display devices, such as liquid crystal display devices or organic light-emitting display devices, include a display panel including a plurality of sub-pixels; a driver that outputs a drive signal for driving the display panel; and a power supply that generates power to be supplied to the display panel or the driver. The driver includes a gate driver that supplies a scan signal or a gate signal to the display panel, and a data driver that supplies a data signal to the display panel.

[0005] In such a display device, when driving signals such as scan signals, EM signals, and data signals are supplied to a plurality of sub-pixels formed in a display panel, selected sub-pixels transmit light or directly emit light to display an image.

[0006] In this context, display devices sometimes require strobe signals with opposite phases but different pulse widths. However, as the number of required signals increases, the bezel of the display panel becomes wider. Therefore, a method is needed to output various strobe signals with different phases and pulse widths while achieving a narrow bezel. Summary of the Invention

[0007] The present disclosure is intended to address all of the above-mentioned needs and problems.

[0008] The present disclosure provides a gate driver capable of outputting various gate signals having different at least one of phase and pulse width while achieving a narrow bezel, and a display panel including the gate driver.

[0009] It should be noted that the objects of the present disclosure are not limited to the above objects, and other objects of the present disclosure will be apparent to those skilled in the art from the following description.

[0010] The selection driver disclosed in the present invention includes a plurality of signal transmission units cascaded via a carry line, and a carry signal is applied from the previous signal transmission unit to the carry line, wherein the nth (n is a positive integer) signal transmission unit includes: a first output unit, which is configured to output a first selection signal to a first output node according to the voltage of a first control node configured as a pull-up output voltage and a second control node configured as a pull-down output voltage; and a second output unit, which is configured to output a second selection signal in which the phase of the first selection signal is inverted to the second output node, wherein the second output unit includes: a first pull-up transistor, which is configured to output a high potential voltage to the second output node according to the voltage of the second control node of the (ni)th (i is a positive integer less than n) signal transmission unit; and a second pull-down transistor, which is configured to output a first low potential voltage to the second output node according to the voltage of the first control node of the (n+j)th (j is a natural number greater than n) signal transmission unit.

[0011] On the other hand, the display panel of the present disclosure includes: a data driver configured to output a data voltage; a gate driver including a plurality of signal transfer units connected in cascade via a carry line, applying a carry signal from a preceding signal transfer unit to the carry line, wherein the nth signal transfer unit includes: a first output unit configured to output a first gate signal to a first output node according to a voltage of a first control node configured to pull up the output voltage and a voltage of a second control node configured to pull down the output voltage, and a second output unit configured to output a first gate signal to a second output node wherein the phase of the first gate signal is inverted. a second selection signal; and a plurality of pixel circuits configured to reproduce an input image by receiving the data voltage, the first selection signal and the second selection signal, wherein the second output unit includes: a first pull-up transistor configured to output a high potential voltage to the second output node according to the voltage of the second control node of the (ni)th signal transmission unit; and a first pull-down transistor configured to output a first low potential voltage to the second output node according to the voltage of the first control node of the (n+j)th signal transmission unit, wherein n is a positive integer, i is a positive integer less than n, and j is a natural number greater than n.

[0012] According to the present disclosure, an inverted gate signal required to drive a pixel circuit can be output without adding a shift register to a gate driver.

[0013] According to the present disclosure, a single shift register can be used to output an in-phase strobe signal and simultaneously output an inverted strobe signal with simple pulse width adjustment.

[0014] According to the present disclosure, a display panel with a narrow bezel and a shift register provided with a gate driver can be realized by outputting various gate signals with at least one different phase and pulse width through a single shift register without adding a separate shift register for outputting an inverted gate signal to the gate driver.

[0015] The effects of the present invention are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0017] Figure 1 is a diagram illustrating a gate driver according to a first exemplary embodiment of the present disclosure;

[0018] Figure 2 It is an example Figure 1 A circuit diagram of the circuit unit shown;

[0019] Figure 3 It is an example Figure 1 Waveform diagrams of input / output signals and voltages of the control node of the gate driver shown;

[0020] Figure 4 is a diagram schematically illustrating a gate driver according to an exemplary embodiment of the present disclosure;

[0021] Figure 5 is a diagram illustrating a gate driver according to a second exemplary embodiment of the present disclosure;

[0022] Figure 6 It is an example Figure 5 Waveform diagrams of input / output signals and voltages of the control node of the gate driver shown;

[0023] Figure 7 is a diagram illustrating a gate driver according to a third embodiment of the present disclosure;

[0024] Figure 8 It is an example Figure 7 Waveform diagrams of input / output signals and voltages of the control node of the gate driver shown;

[0025] Figure 9 is a diagram illustrating a gate driver according to a fourth embodiment of the present disclosure;

[0026] Figure 10 It is an example Figure 9Waveform diagrams of input / output signals and voltages of the control node of the gate driver shown;

[0027] Figure 11 is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0028] Figure 12 It is an example Figure 11 A diagram showing a cross-sectional structure of a display panel;

[0029] Figure 13 This is an example of an application Figure 11 A diagram of a pixel circuit of a display panel shown; and

[0030] Figure 14 It is an example Figure 13 FIG. 1 is a graph showing the waveforms of the input / output signals and voltages of the control node of the gate driver. FIG. DETAILED DESCRIPTION

[0031] The advantages and features of the present disclosure and the methods for achieving the same will be more clearly understood from the following embodiments described with reference to the accompanying drawings. However, the present disclosure is not limited to the following embodiments and can be implemented in a variety of different forms. Rather, the present embodiments will complete the disclosure and enable those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is limited only within the scope of the appended claims.

[0032] The shapes, sizes, proportions, angles, quantities, etc. illustrated in the accompanying drawings for the purpose of describing the embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout this specification, similar reference numerals generally refer to similar elements. In addition, when describing the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0033] Unless used with the term “only,” terms such as “comprising,” “including,” “having,” and “consisting of” used herein are generally intended to allow for the addition of other components. Any reference to the singular may include the plural unless explicitly mentioned otherwise.

[0034] Even if not explicitly mentioned, components are interpreted as including ordinary error ranges.

[0035] When terms such as “on,” “above,” “lower,” and “next” are used to describe the positional relationship between two components, unless these terms are used with the term “immediately next” or “directly,” one or more components may be located between the two components.

[0036] The terms “first”, “second”, etc. may be used to distinguish components from each other, but the function or structure of the components is not limited by the sequence numbers preceding the components or the names of the components.

[0037] Like reference numerals may refer to substantially like elements throughout this disclosure.

[0038] The following embodiments may be combined or combined with each other in part or in whole, and may be linked and operated in various technical ways. These embodiments may be performed independently or in association with each other.

[0039] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0040] Figure 1 is a diagram illustrating a gate driver according to a first embodiment of the present disclosure, Figure 2 It is an example Figure 1 The circuit diagram of the circuit unit is shown, and Figure 3 It is an example Figure 1 FIG. 1 is a graph showing the waveforms of the input / output signals and voltages of the control node of the gate driver. FIG.

[0041] Reference Figures 1 to 3 The gate driver 120 according to an exemplary embodiment of the present disclosure may include a first control node for pulling up the output voltage (hereinafter referred to as a "Q node"), a second control node for pulling down the output voltage (hereinafter referred to as a "Qb node"), a circuit unit 120-1, a first output unit 120-2 and a second output unit 120-3.

[0042] The circuit unit 120-1 can charge and discharge the Q node Q(n) and the Qb node Qb(n), and output a carry signal C(n) according to the potentials of the Q node Q(n) and the Qb node Qb(n). The circuit unit 120-1 can include a first circuit unit 120-1a, a second circuit unit 120-1b, and a third circuit unit 120-1c.

[0043] The first circuit unit 120-1a controls the charging and discharging of the Q node Q(n) and the Qb node Qb(n). When the shift clock GCLK1 is a high voltage VGH2 equal to or greater than the gate-on voltage VEH, the first circuit unit 120-1a charges the Q node Q(n) by supplying the voltage of the (n-1)th carry signal C(n-1) from the (n-1)th signal processing unit ST(n-1), which is the preceding signal processing unit, to the Q node Q(n). The first circuit unit 120-1a includes first to third transistors T1, T2, and T3.

[0044] The first transistor T1 is turned on when the shift clock GCLK1 is a high voltage VGH2 equal to or greater than the gate-on voltage VEH, and provides the voltage of the carry signal C(n-1) to the Qh node Qh(n). The first transistor T1 includes a gate to which the shift clock GCLK1 is applied, a first electrode connected to the (n-1)th carry signal line 73, and a second electrode connected to the Qh node Qh(n).

[0045] The high voltage VGH2 of the shift clock GCLK1 can be set to a voltage lower than the second high potential voltage VGH1. The high voltage VGH1 of the first selection signal OUT(n) and the carry signal C(n-1) is the same voltage as the second high potential voltage VGH1. When the high voltage VGH2 of the shift clock GCLK1 is set to be lower than the second high potential voltage VGH1, when the threshold voltage Vth of the first transistor T1 changes to the negative polarity -Vth while the Q node Q(n) is charged, the Q node Q(n) is floated, so that the boosting of the Q node Q(n) can be improved.

[0046] The second transistor T2 is turned on when the shift clock GCLK1 has a voltage VGH2 equal to or greater than the gate-on voltage VEH, and charges the Q node by supplying a voltage of the Qh node Qh(n) to the Q node Q(n). The second transistor T2 includes a gate to which the shift clock GCLK1 is applied, a first electrode connected to the Qh node Qh(n), and a second electrode connected to the Q node Q(n).

[0047] The first transistor T1 and the second transistor T2 are connected in series. The first transistor T1 and the second transistor T2 are connected in series between the (n-1)th carry signal line 73 and the Qh node Qh(n).

[0048] The third transistor T3 is turned on when the Q node Q(n) is charged and supplies a second high potential voltage to the Qh node Qh(n) via the second high potential voltage line GVDD1. The second high potential voltage is supplied to the Qh node Qh(n) via the second high potential voltage line GVDD1. The third transistor T3 includes a gate connected to the Q node Q(n), a first electrode connected to the second high potential voltage line GVDD1, and a second electrode connected to the Qh node Qh(n).

[0049] The second circuit unit 120-1b includes an inverter circuit that inverts the voltage of the Q node Q(n) and applies the voltage to the Qb node Qb(n). The inverter circuit of the second circuit unit 120-1b includes a Qb node charging unit and a Qb node discharging unit.

[0050] The Qb node charging unit includes a plurality of transistors T4A and T4B, and the Qb node discharging unit includes a plurality of transistors T5A and T5B, and the plurality of transistors T5A and T5B are connected in parallel.

[0051] The Qb node charging unit switches a current path between the second high potential voltage line GVDD1 and the Qb node Qb(n) according to the voltage of the (n-1)th Qb node Qb(n-1) from the (n-1)th signal transferring unit ST(n-1).

[0052] The 4a-th transistor T4A is turned on when the voltage at the first node 80 is a high voltage equal to or greater than the gate-on voltage VEH, and charges the Qb node Qb(n) to a high voltage equal to or greater than the gate-on voltage VEH by connecting the second high-potential voltage line GVDD1 to the Qb node Qb(n). The 4a-th transistor T4A includes a gate connected to the first node 80, a first electrode connected to the second high-potential voltage line GVDD1, and a second electrode connected to the Qb node Qb(n). A first capacitor C1 is connected between the gate and the second electrode of the 4a-th transistor T4A. When the 4a-th transistor T4A is turned on via the first capacitor C1, the voltage at the first node 80 can be increased.

[0053] The 4b-th transistor T4B is turned on when the voltage of the (n-1)th Qb node Qb(n-1) of the (n-1)th signal transmitting unit ST(n-1) is a high voltage equal to or greater than the gate-on voltage VEH, and charges the first node 80 by supplying the second high potential voltage of the second high potential voltage line GVDD1 to the first node 80. The 4b-th transistor T4B includes a gate connected to the (n-1)th Qb node Qb(n-1) of the (n-1)th signal transmitting unit ST(n-1), a first electrode connected to the second high potential voltage line GVDD1, and a second electrode connected to the first node 80.

[0054] The Qb node discharge unit is turned on when the voltage of the Qh node Qh(n) is a high voltage equal to or greater than the gate-on voltage VEH, and discharges the Qb node Qb(n).

[0055] The 5a-th transistor T5A is turned on when the voltage of the Qh node Qh(n) is a high voltage equal to or greater than the gate-on voltage VEH, and discharges the voltage of the Qb node Qb(n) to the third low potential voltage by connecting the Qb node Qb(n) to the third low potential voltage line GVSS2. The 5a-th transistor T5A includes a gate connected to the Qh node Qh(n), a first electrode connected to the Qb node Qb(n), and a second electrode connected to the third low potential voltage line GVSS2.

[0056] The 5b-th transistor T5B is turned on when the voltage of the Qh node Qh(n) is a high voltage equal to or greater than the gate-on voltage VEH, and connects the first node 80 to the second low-potential voltage line GVSS1. The 5b-th transistor T5B includes a gate connected to the Qh node Qh(n), a first electrode connected to the first node 80, and a second electrode connected to the second low-potential voltage line GVSS1.

[0057] The third circuit unit 120-1c may output a carry signal C(n) in response to the potentials of the Q node Q(n) and the Qb node Qb(n). The third circuit unit 120-1c may include third buffer transistors T6cr and T7cr that output the carry signal C(n). The third buffer transistors T6cr and T7cr may output the carry signal C(n) based on the second high potential voltage applied via the second high potential voltage line GVDD1 and the third low potential voltage applied via the third low potential voltage line GVSS2.

[0058] The first output unit 120-2 may output a first selection signal OUT(n) in response to potentials of the Q node Q(n) and the Qb node Qb(n). The first output unit 120-2 may include first buffer transistors T6 and T7 that output the first selection signal OUT(n).

[0059] The first buffer transistors T6 and T7 can be divided into a first pull-up transistor T6 that is turned on based on the potential of the Q node Q(n) and a first pull-down transistor T7 that is turned on based on the potential of the Qb node Qb(n). In the first pull-up transistor T6, the gate electrode is connected to the Q node Q(n), the first electrode is connected to the high-potential voltage line GVDD0, and the second electrode is connected to the first output terminal 71. In the first pull-down transistor T7, the gate electrode is connected to the Qb node Qb(n), the first electrode is connected to the first output terminal 71, and the second electrode is connected to the first low-potential voltage line GVSS0. The first buffer transistors T6 and T7 can output the first selection signal OUT(n) based on the high-potential voltage applied by the high-potential voltage line GVDD0 and the first low-potential voltage applied by the first low-potential voltage line GVSS0.

[0060] The second output unit 120-3 may output a second strobe signal OUTB(n) in which the phase of the first strobe signal is inverted. The second output unit 120-3 may include second buffer transistors T6b and T7b that output the second strobe signal OUTB(n).

[0061] The second buffer transistors T6b and T7b can be divided into a second pull-up transistor T6b that is turned on based on the potential of the preceding Qb node Qb(ni), and a second pull-down transistor T7b that is turned on based on the potential of the succeeding Q node Q(n+j). In the second pull-up transistor T6b, the gate electrode is connected to the preceding Qb node Qb(ni), the first electrode is connected to the high potential voltage line GVDD0, and the second electrode is connected to the second output terminal 72. In the second pull-down transistor T7b, the gate electrode is connected to the succeeding Q node Q(n+j), the first electrode is connected to the second output terminal 72, and the second electrode is connected to the first low potential voltage line GVSS0.

[0062] In this case, switching elements T8 and T9 for adjusting the pulse width of the second gating signal can be included between the second pull-down transistor T7b and the subsequent Q node Q(n+j). The switching elements T8 and T9 can be divided into a first switching element T8 that is turned on based on the clock signal and a second switching element T9 that is turned on based on the potential of the preceding Qb node Qb(ni). The first switching element T8 includes a gate electrode to which the clock signal is applied, a first electrode connected to the subsequent Q node Q(n+j), and a second electrode connected to the third control node QA. The second switching element T9 includes a gate electrode connected to the preceding Qb node Qb(ni), a first electrode connected to the third control node QA, and a second electrode connected to the third low potential voltage line GVSS2.

[0063] Figure 4 is a diagram schematically illustrating a gate driver according to an exemplary embodiment of the present disclosure.

[0064] Reference Figure 4 , a gate driver according to an exemplary embodiment includes a plurality of signal processing units ST(n-2), ST(n-1), ST(n), ST(n+1), and ST(n+2) cascaded via a carry line through which a carry signal is transmitted.

[0065] Each of the signal processing units ST(n-2), ST(n-1), ST(n), ST(n+1), and ST(n+2) receives a start pulse or a carry signal C(n-2), C(n-1), C(n), C(n+1), and C(n+2) output from a preceding signal processing unit, and receives a shift clock GCLK. The first signal processing unit ST(1) starts to be driven according to the start pulse Vst, and the other signal processing units ST(n-2), ST(n-1), ST(n), ST(n+1), and ST(n+2) start to be driven by receiving the carry signal C(n-2), C(n-1), C(n), C(n+1), and C(n+2) from the preceding signal processing unit. The shift clock GCLK may be an N-phase clock (N is a positive integer equal to or greater than 2). For example, the shift clock GCLK may be a four-phase clock GCLK1, GCLK2, GCLK3, and GCLK4. The four-phase shift clocks GCLK1, GCLK2, GCLK3, and GCLK4 have opposite phases. Signal processing units ST(n-2), ST(n-1), ST(n), ST(n+1), and ST(n+2) can sequentially output first selection signals OUT(n-2), OUT(n-1), OUT(n), OUT(n+1), and OUT(n+2) of the same phase and second selection signals OUTB(n-2), OUTB(n-1), OUTB(n), OUTB(n+1), and OUTB(n+2) of opposite phase by shifting start pulses or carry signals C(n-2), C(n-1), C(n), C(n+1), and C(n+2) from preceding signal processing units according to the timing of the shift clocks.

[0066] In this case, each signal processing unit can output the same-phase first selection signals OUT(n-2), OUT(n-1), OUT(n), OUT(n+1) and OUT(n+2) through the first buffer BUF1 and output the inverted second selection signals OUTB(n-2), OUTB(n-1), OUTB(n), OUTB(n+1) and OUTB(n+2) through the second buffer BUF2.

[0067] Figure 5 is a diagram illustrating a gate driver according to a second embodiment of the present disclosure, and Figure 6 It is an example Figure 5 FIG. 1 is a graph showing the waveforms of the input / output signals and voltages of the control node of the gate driver. FIG.

[0068] Reference Figure 5 and Figure 6, the gate driver according to the second exemplary embodiment of the present disclosure may include a plurality of signal transmitting units, and each signal transmitting unit may include a circuit unit 120 - 1 , a first output unit 120 - 2 , and a second output unit 120 - 3 .

[0069] The circuit unit 120 - 1 may charge and discharge the Q node Q(n) and the Qb node Qb(n), and output a carry signal C(n) according to the potentials of the Q node Q(n) and the Qb node Qb(n).

[0070] The first output unit 120-2 may output a first selection signal OUT(n) in response to the potentials of the Q node Q(n) and the Qb node Qb(n) of the nth (n is a positive integer) signal transfer unit ST(n). The first output unit 120-2 may include first buffer transistors T6 and T7 that output the first selection signal OUT(n).

[0071] The first buffer transistors T6 and T7 can be divided into a first pull-up transistor T6 that is turned on based on the potential of the Q node Q(n) and a first pull-down transistor T7 that is turned on based on the potential of the Qb node Qb(n). In the first pull-up transistor T6, the gate electrode is connected to the Q node Q(n), the first electrode is connected to the high-potential voltage line GVDD0, and the second electrode is connected to the first output terminal 71. In the first pull-down transistor T7, the gate electrode is connected to the Qb node Qb(n), the first electrode is connected to the first output terminal 71, and the second electrode is connected to the first low-potential voltage line GVSS0. The first buffer transistors T6 and T7 can output the first selection signal OUT(n) based on the high-potential voltage applied by the high-potential voltage line GVDD0 and the first low-potential voltage applied by the first low-potential voltage line GVSS0.

[0072] The second output unit 120-3 may output a second selection signal OUTB(n) in which the phase of the first selection signal is inverted in response to the potential of the Qb node Qb(n-1) of the (n-1)th signal transmission unit ST(n-1) and the Q node Q(n+1) of the (n+1)th signal transmission unit ST(n+1). The second output unit 120-3 may include second buffer transistors T6b and T7b that output the second selection signal OUTB(n).

[0073] The second buffer transistors T6b and T7b can be divided into a second pull-up transistor T6b that is turned on based on the potential of the preceding Qb node Qb(n-1) and a second pull-down transistor T7b that is turned on based on the potential of the succeeding Q node Q(n+1). In the second pull-up transistor T6b, the gate electrode is connected to the preceding Qb node Qb(n-1), the first electrode is connected to the high potential voltage line GVDD0, and the second electrode is connected to the second output terminal 72. In the second pull-down transistor T7b, the gate electrode is connected to the succeeding Q node Q(n+1), the first electrode is connected to the second output terminal 72, and the second electrode is connected to the first low potential voltage line GVSS0.

[0074] In this case, switching elements T8 and T9 for adjusting the pulse width of the second gating signal can be included between the second pull-down transistor T7b and the subsequent Q node Q(n+1). The switching elements T8 and T9 can be divided into a first switching element T8 that is turned on based on the clock signal and a second switching element T9 that is turned on based on the preceding Qb node Qb(n-1). The first switching element T8 includes a gate electrode to which the clock signal is applied, a first electrode connected to the subsequent Q node Q(n+j), and a second electrode connected to the third control node QA. The second switching element T9 includes a gate electrode connected to the preceding Qb node Qb(ni), a first electrode connected to the third control node QA, and a second electrode connected to the second low potential voltage line GVSS1.

[0075] In this case, if Figure 6 As shown, the pulse width of the high voltage of the second strobe signal can be formed to be greater than the pulse width of the first strobe signal, and can be formed to be 2H longer than the application section of the low voltage pulse of the first strobe signal. Here, the section of applying the high voltage pulse of the second strobe signal can be formed to be 1H long based on the falling edge of the section of applying the low voltage pulse of the first strobe signal, and can be formed to be 1H long based on the rising edge.

[0076] Figure 7 is a diagram illustrating a gate driver according to a third embodiment of the present disclosure, and Figure 8 It is an example Figure 7 FIG. 1 is a graph showing the waveforms of the input / output signals and voltages of the control node of the gate driver. FIG.

[0077] Reference Figure 7 and Figure 8 , the gate driver according to the third exemplary embodiment of the present disclosure may include a plurality of signal transmitting units, and each signal transmitting unit may include a circuit unit 120 - 1 , a first output unit 120 - 2 , and a second output unit 120 - 3 .

[0078] The circuit unit 120 - 1 may charge and discharge the Q node Q(n) and the Qb node Qb(n), and output a carry signal C(n) according to the potentials of the Q node Q(n) and the Qb node Qb(n).

[0079] The first output unit 120-2 may output a first selection signal OUT(n) in response to the potentials of the Q node Q(n) and the Qb node Qb(n) of the nth signal transfer unit. The first output unit 120-2 may include first buffer transistors T6 and T7 that output the first selection signal OUT(n).

[0080] The first buffer transistors T6 and T7 can be divided into a first pull-up transistor T6 that is turned on based on the potential of the Q node Q(n) and a first pull-down transistor T7 that is turned on based on the potential of the Qb node Qb(n). In the first pull-up transistor T6, the gate electrode is connected to the Q node Q(n), the first electrode is connected to the high-potential voltage line GVDD0, and the second electrode is connected to the first output terminal 71. In the first pull-down transistor T7, the gate electrode is connected to the Qb node Qb(n), the first electrode is connected to the first output terminal 71, and the second electrode is connected to the first low-potential voltage line GVSS0. The first buffer transistors T6 and T7 can output the first selection signal OUT(n) based on the high-potential voltage applied by the high-potential voltage line GVDD0 and the first low-potential voltage applied by the first low-potential voltage line GVSS0.

[0081] The second output unit 120-3 may output a second selection signal OUTB(n) in which the phase of the first selection signal is inverted in response to the potential of the Qb node Qb(n-2) of the (n-2)th signal transmission unit and the Q node Q(n+1) of the (n+1)th signal transmission unit. The second output unit 120-3 may include second buffer transistors T6b and T7b that output the second selection signal OUTB(n).

[0082] The second buffer transistors T6b and T7b can be divided into a second pull-up transistor T6b that is turned on based on the potential of the preceding Qb node Qb(n-2) and a second pull-down transistor T7b that is turned on based on the potential of the succeeding Q node Q(n+1). In the second pull-up transistor T6b, the gate electrode is connected to the preceding Qb node Qb(n-2), the first electrode is connected to the high potential voltage line GVDD0, and the second electrode is connected to the second output terminal 72. In the second pull-down transistor T7b, the gate electrode is connected to the succeeding Q node Q(n+1), the first electrode is connected to the second output terminal 72, and the second electrode is connected to the first low potential voltage line GVSS0.

[0083] In this case, switching elements T8 and T9 for adjusting the pulse width of the second gating signal can be included between the second pull-down transistor T7b and the subsequent Q node Q(n+1). The switching elements T8 and T9 can be divided into a first switching element T8 that is turned on based on the clock signal and a second switching element T9 that is turned on based on the potential of the preceding Qb node Qb(n-2). The first switching element T8 includes a gate electrode to which the clock signal is applied, a first electrode connected to the subsequent Q node Q(n+j), and a second electrode connected to the third control node QA. The second switching element T9 includes a gate electrode connected to the preceding Qb node Qb(ni), a first electrode connected to the third control node QA, and a second electrode connected to the second low potential voltage line GVSS1.

[0084] In this case, if Figure 8 As shown, the pulse width of the high voltage of the second selection signal can be formed to be greater than the pulse width of the first selection signal, and can be formed to be 3H longer than the application section of the low voltage pulse of the first selection signal. Here, the section where the high voltage pulse of the second selection signal is applied can be formed to be 2H long based on the falling edge of the application section of the low voltage pulse of the first selection signal, and can be formed to be 1H long based on the rising edge.

[0085] Figure 9 is a diagram illustrating a gate driver according to a fourth embodiment of the present disclosure, Figure 10 It is an example Figure 9 FIG. 1 is a graph showing the waveforms of the input / output signals and voltages of the control node of the gate driver. FIG.

[0086] Reference Figure 9 and Figure 10 , the gate driver according to the fourth exemplary embodiment of the present disclosure may include a plurality of signal transmitting units, and each signal transmitting unit may include a circuit unit 120 - 1 , a first output unit 120 - 2 , and a second output unit 120 - 3 .

[0087] The circuit unit 120 - 1 may charge and discharge the Q node Q(n) and the Qb node Qb(n), and output a carry signal C(n) according to the potentials of the Q node Q(n) and the Qb node Qb(n).

[0088] The first output unit 120-2 may output a first selection signal OUT(n) in response to the potentials of the Q node Q(n) and the Qb node Qb(n) of the nth signal transfer unit. The first output unit 120-2 may include first buffer transistors T6 and T7 that output the first selection signal OUT(n).

[0089] The first buffer transistors T6 and T7 can be divided into a first pull-up transistor T6 that is turned on based on the potential of the Q node Q(n) and a first pull-down transistor T7 that is turned on based on the potential of the Qb node Qb(n). In the first pull-up transistor T6, the gate electrode is connected to the Q node Q(n), the first electrode is connected to the high-potential voltage line GVDD0, and the second electrode is connected to the first output terminal 71. In the first pull-down transistor T7, the gate electrode is connected to the Qb node Qb(n), the first electrode is connected to the first output terminal 71, and the second electrode is connected to the first low-potential voltage line GVSS0. The first buffer transistors T6 and T7 can output the first selection signal OUT(n) based on the high-potential voltage applied by the high-potential voltage line GVDD0 and the first low-potential voltage applied by the first low-potential voltage line GVSS0.

[0090] The second output unit 120-3 may output a second selection signal OUTB(n) in which the phase of the first selection signal is inverted in response to the potentials of the Qb node Qb(n) of the nth signal transmission unit and the Q node Q(n+1) of the (n+1)th signal transmission unit. The second output unit 120-3 may include second buffer transistors T6b and T7b that output the second selection signal OUTB(n).

[0091] The second buffer transistors T6b and T7b can be divided into a second pull-up transistor T6b that is turned on based on the potential of the Qb node Qb(n) and a second pull-down transistor T7b that is turned on based on the potential of the subsequent Q node Q(n+1). In the second pull-up transistor T6b, the gate electrode is connected to the Qb node Qb(n), the first electrode is connected to the high potential voltage line GVDD0, and the second electrode is connected to the second output terminal 72. In the second pull-down transistor T7b, the gate electrode is connected to the subsequent Q node Q(n+1), the first electrode is connected to the second output terminal 72, and the second electrode is connected to the first low potential voltage line GVSS0.

[0092] In this case, switching elements T8 and T9 for adjusting the pulse width of the second selection signal can be included between the second pull-down transistor T7b and the subsequent Q node Q(n+1). The switching elements T8 and T9 can be divided into a first switching element T8 that is turned on based on the clock signal and a second switching element T9 that is turned on based on the Qb node Qb(n). The first switching element T8 includes a gate electrode to which the clock signal is applied, a first electrode connected to the subsequent Q node Q(n+1), and a second electrode connected to the third control node QA. The second switching element T9 includes a gate electrode connected to the Qb node Qb(n), a first electrode connected to the third control node QA, and a second electrode connected to the second low potential voltage line GVSS1.

[0093] In this case, if Figure 10As shown, the pulse width of the high voltage of the second selection signal can be formed to be greater than the pulse width of the first selection signal, and can be formed to be longer by 1H than the application section of the low voltage pulse of the first selection signal. Here, the application section of the high voltage pulse of the second selection signal can be formed to be longer by 1H based on the rising edge of the application section of the low voltage pulse of the first selection signal.

[0094] In an exemplary embodiment, a second gating signal in which the phase of the first gating signal is reversed may be output. The second gating signal may be formed based on the voltage of the second node of the (ni)th (i is a positive integer less than n) signal transmission unit and the first node of the (n+j)th (j is a positive integer greater than n) signal transmission unit. In this case, the section in which the high voltage pulse of the second gating signal is applied may be formed to be 1H longer or more than the section in which the low voltage pulse of the first gating signal is applied. In addition, the section in which the high voltage pulse of the second gating signal is applied may be formed to be 1H longer or more than at least one of the rising edge and the falling edge of the application section of the low voltage pulse of the first gating signal.

[0095] Figure 11 is a block diagram illustrating a display device according to an embodiment of the present disclosure, and Figure 12 It is an example Figure 11 A diagram showing a cross-sectional structure of a display panel. Figure 13 This is an example of an application Figure 11 FIG. 1 is a diagram of a pixel circuit of a display panel shown in FIG. 1 , and Figure 14 It is an example Figure 13 FIG. 1 is a graph showing the waveforms of the input / output signals and voltages of the control node of the gate driver. FIG.

[0096] Reference Figure 11 The display device according to an embodiment of the present disclosure includes a display panel 100, a display panel driver for writing pixel data into pixels of the display panel 100, and a power supply 140 for generating power required to drive the pixels and the display panel driver.

[0097] The display panel 100 includes a pixel array AA for displaying an input image. The pixel array AA includes a plurality of data lines 102, a plurality of gate lines 103 crossing the data lines 102, and pixels arranged in a matrix.

[0098] The pixel array AA includes a plurality of pixel lines L1 to Ln. Each of the pixel lines L1 to Ln includes a row of pixels arranged along the row direction X in the pixel array AA of the display panel 100. The pixels arranged in one pixel row share a gate line 103. Subpixels arranged in the column direction Y along the data line direction share the same data line 102. One horizontal period 1H is the time obtained by dividing one frame period by the total number of pixel lines L1 to Ln.

[0099] The touch sensor may be provided on the display panel 100. A separate touch sensor may be used to sense touch input, or the touch input may be sensed by pixels. The touch sensor may be provided as an on-box type or an attached type on the screen of the display panel, or implemented as an in-box type touch sensor embedded in the pixel array AA.

[0100] The display panel 100 may be implemented as a flexible display panel. The flexible display panel may be made of a plastic OLED panel. An organic film may be provided on a back panel of the plastic OLED panel, and the pixel array AA may be formed on the organic film.

[0101] The backplane of the plastic OLED may be a polyethylene terephthalate (PET) substrate. An organic film is formed on the backplane. The pixel array AA and the touch sensor array may be formed on the organic film. The backplane blocks moisture infiltration so that the pixel array AA is not exposed to moisture. The organic film may be a thin polyimide (PI) film substrate. A multilayer buffer film may be formed on the organic film from an insulating material (not shown). Lines may be formed on the organic film to provide power or signals applied to the pixel array AA and the touch sensor array.

[0102] To achieve color, each pixel can be divided into a red sub-pixel (hereinafter referred to as "R sub-pixel"), a green sub-pixel (hereinafter referred to as "G sub-pixel"), and a blue sub-pixel (hereinafter referred to as "B sub-pixel"). Each pixel can also include a white sub-pixel. Each sub-pixel 101 includes a pixel circuit. The pixel circuit is connected to a data line 102 and a gate line 103.

[0103] Hereinafter, a pixel may be interpreted as having the same meaning as a sub-pixel.

[0104] like Figure 12 As shown, when viewed from a cross-sectional structure, the display panel 100 may include a circuit layer 12 , a light emitting element layer 14 , and an encapsulation layer 16 stacked on a substrate 10 .

[0105] The circuit layer 12 may include pixel circuits connected to wiring such as data lines, gate lines, and power lines, a gate driver (GIP) connected to the gate lines, a demultiplexer array 112, and circuits (not shown) for automatic probe inspection. The wiring and circuit elements of the circuit layer 12 may include multiple insulating layers, two or more metal layers separated by insulating layers, and an active layer including a semiconductor material. All transistors formed in the circuit layer 12 may be implemented as oxide TFTs having an n-channel oxide semiconductor.

[0106] The light-emitting element layer 14 may include a light-emitting element EL driven by a pixel circuit. The light-emitting element EL may include a red (R) light-emitting element, a green (G) light-emitting element, and a blue (B) light-emitting element. The light-emitting element layer 14 may include a white light-emitting element and a color filter. The light-emitting element EL of the light-emitting element layer 14 may be covered by a protective layer including an organic film and a passivation film.

[0107] The encapsulation layer 16 covers the light-emitting element layer 14 to seal the circuit layer 12 and the light-emitting element layer 14. The encapsulation layer 16 may have a multilayer insulating structure in which organic films and inorganic films are alternately stacked. The inorganic films block the infiltration of moisture and oxygen. The organic films flatten the surface of the inorganic films. When the organic and inorganic films are stacked in multiple layers, the path for moisture or oxygen to move becomes longer compared to a single layer, making it possible to effectively block the infiltration of moisture and oxygen that could affect the light-emitting element layer 14.

[0108] The touch sensor layer may be disposed on the encapsulation layer 16. The touch sensor layer may include a capacitive touch sensor that senses touch input based on a change in capacitance before and after a touch input. The touch sensor layer may include a metal wiring pattern and an insulating layer that form the capacitance of the touch sensor. The capacitance of the touch sensor may be formed between the metal wiring patterns. A polarizing plate may be disposed on the touch sensor layer. The polarizing plate may improve visibility and contrast by converting the polarization of external light reflected by the metal of the touch sensor layer and circuit layer 12. The polarizing plate may be implemented as a polarizing plate in which a linear polarizing plate and a phase delay film are bonded, or as a circular polarizing plate. The cover glass may be adhered to the polarizing plate.

[0109] The display panel 100 may further include a touch sensor layer and a color filter layer stacked on the encapsulation layer 16. The color filter layer may include a red filter, a green filter, and a blue filter as well as a black matrix pattern. The color filter layer may replace the polarizing plate and improve color purity by absorbing some wavelengths of light reflected from the circuit layer and the touch sensor layer. In this embodiment, by applying a color filter layer 20 having a higher transmittance than the polarizing plate to the display panel, the transmittance of the display panel PNL can be improved, and the thickness and flexibility of the display panel PNL can be increased. The cover glass may be adhered to the color filter layer.

[0110] The power supply 140 generates the DC power required to drive the pixel array AA and the display panel driving circuit of the display panel 100 using a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply 140 can adjust the DC input voltage from the host system (not shown) to generate DC voltages such as the gamma reference voltage VGMA, the gate-on voltages VGH and VEH, the gate-off voltages VGL and VEL, the pixel drive voltage EVDD, and the pixel low-potential power supply voltage EVSS. The gamma reference voltage VGMA is provided to the data driver 110. The gate-on voltages VGH and VEH and the gate-off voltages VGL and VEL are provided to the gate driver 120. The pixel drive voltage EVDD and the pixel low-potential power supply voltage EVSS are commonly provided to the pixels.

[0111] The display panel driving circuit writes pixel data (digital data) of an input image into pixels of the display panel 100 under the control of a timing controller (TCON) 130 .

[0112] The display panel driving circuit includes a data driver 110 and a gate driver 120 .

[0113] A demultiplexer (DEMUX) array 112 may be provided between the data driver 110 and the data lines 102. The demultiplexer array 112 sequentially connects one channel of the data driver 110 to the plurality of data lines 102 and distributes the data voltage output by the one channel of the data driver 110 to the plurality of data lines 102 in a time-division manner, thereby reducing the number of channels of the data driver 110. The demultiplexer array 112 may be omitted. In this case, the output buffer AMP of the data driver 110 is directly connected to the data lines 102.

[0114] The display panel driving circuit may further include a touch sensor driver for driving the touch sensor. Figure 11 In a mobile device, the timing controller 130, the power supply 140, the data driver 110, etc. may be integrated into one driving integrated circuit (IC).

[0115] The data driver 110 generates a data voltage Vdata by converting pixel data of an input image received from the timing controller 130 into a gamma compensation voltage in each frame period using a digital-to-analog converter (DAC). The gamma reference voltage VGMA is divided for each grayscale level by a voltage divider circuit. The gamma compensation voltage divided from the gamma reference voltage VGMA is supplied to the DAC of the data driver 110. The data voltage Vdata is outputted in each channel of the data driver 110 through an output buffer AMP.

[0116] In the data driver 110, the output buffer AMP included in one channel may be connected to adjacent data lines 102 through the demultiplexer array 112. The demultiplexer array 112 may be directly formed on the substrate of the display panel 100 or integrated with the data driver 110 in one driving IC.

[0117] The gate driver 120 may be implemented as a gate-in-plane (GIP) circuit directly formed on the bezel BZ region of the display panel 100 together with the TFT array of the pixel array AA. The gate driver 120 sequentially outputs gate signals to the gate lines 103 under the control of the timing controller 130. The gate driver 120 may sequentially provide the gate signals to the gate lines 103 by shifting the gate signals using a shift register.

[0118] The gate signal may include a scan signal for selecting pixels of a row to which data is to be written in synchronization with a data voltage, and an EM signal defining a light emitting time of the pixels charged with the data voltage.

[0119] The gate driver 120 may include a scan driver 121 , an EM driver 122 , and an initialization driver 123 .

[0120] The scan driver 121 outputs a scan signal SCAN in response to a start pulse and a shift clock from the timing controller 130, and shifts the scan signal SCAN according to the shift clock timing. The EM driver 122 outputs an EM signal EM in response to a start pulse and a shift clock from the timing controller 130, and sequentially shifts the EM signal EM according to the shift clock timing. The initialization driver 123 outputs an initialization signal INIT in response to a start pulse and a shift clock from the timing controller 130, and shifts the initialization signal INIT according to the shift clock timing. Thus, the scan signal SCAN, the EM signal EM, and the initialization signal INIT are sequentially provided to the gate lines 103 of the pixel lines L1 to Ln. In the case of a borderless model, at least some of the transistors constituting the gate driver 120 and the clock wiring can be dispersed throughout the pixel array AA.

[0121] The timing controller 130 receives digital video data DATA of an input image and timing signals synchronized therewith from a host system (not shown). The timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock CLK, a data enable signal DE, and the like. Because the vertical and horizontal periods can be determined by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE has a period of one horizontal period (1H).

[0122] The host system may be any one of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a car system, and a mobile device system.

[0123] The timing controller 130 multiplies the input frame frequency by i and controls the operation timing of the display panel driving circuit with a frame frequency of input frame frequency×i (i is a positive integer greater than 0) Hz. The input frame frequency is 60 Hz in the NTSC (National Television Standards Committee) scheme and 50 Hz in the PAL (Phase Alternation Line) scheme.

[0124] Based on the timing signals Vsync, Hsync and DE received from the host system, the timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110, MUX signals MUX1 and MUX2 for controlling the operation timing of the demultiplexer array 112, and a gate timing control signal for controlling the operation timing of the gate driver 120.

[0125] The voltage level of the gate timing control signal output from the timing controller 130 can be converted into gate-on voltages VGH and VEH and gate-off voltages VGL and VEL by a level converter (not shown), and then provided to the gate driver 120. That is, the level converter converts the low-level voltage of the gate timing control signal into the gate-off voltages VGL and VEL, and converts the high-level voltage of the gate timing control signal into the gate-on voltages VGH and VEH. The gate timing signal includes a start pulse and a shift clock.

[0126] Reference Figure 13 and Figure 14 The pixel circuit according to the exemplary embodiment of the present disclosure includes a light-emitting element EL, a driving element DT for supplying current to the light-emitting element EL, a plurality of switching elements such as M01, M02, M03, M04, and M05 for switching a current path connected to the driving element DT, a first capacitor Cst for storing a voltage between a gate and a source of the driving element DT, and a second capacitor C2. The driving element DT and the switching elements M01, M02, M03, M04, and M05 may be implemented as N-channel oxide TFTs.

[0127] The light-emitting element EL emits light according to the current applied through the channel of the driving element DT according to the gate-source voltage Vgs of the driving element DT, and the gate-source voltage Vgs of the driving element DT varies according to the data voltage Vdata. The light-emitting element EL can be implemented as an OLED including an organic compound layer formed between an anode and a cathode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), a light-emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The anode of the light-emitting element EL is connected to the driving element DT through the third node n3, and the cathode of the light-emitting element EL is connected to the second power line 42 to which the low potential power supply voltage EVSS is applied.

[0128] An organic light emitting diode used as a light emitting element may have a tandem structure in which a plurality of light emitting layers are stacked. An organic light emitting diode having a tandem structure can improve the brightness and lifespan of a pixel.

[0129] The driving element DT drives the light emitting element EL by supplying current to the light emitting element EL according to the gate-source voltage Vgs. The driving element DT includes a gate connected to a first node n1, a first electrode (or drain) connected to a first power line, and a second electrode (or source) connected to a second node n2.

[0130] The first switching element M01 is turned on according to the gate-on voltage of the EM signal and connects the second electrode of the driving element DT to the anode of the light-emitting element EL. The first switching element M01 includes a gate connected to the gate line to which the EM signal is applied, a first electrode connected to the second node n2, and a second electrode connected to the third node n3.

[0131] The second switching element M02 is turned on according to the gate-on voltage of the scan signal SCAN and connects the data voltage line to the first node n1 to apply the data voltage. The second switching element M02 includes a gate connected to the gate line to which the scan signal SCAN is applied, a first electrode connected to the data voltage line to which the data voltage is applied, and a second electrode connected to the first node n1.

[0132] The third switching element M03 is turned on according to the gate-on voltage of the sensing signal SENSE and connects the second node n2 to the reference voltage line. The third switching element M03 includes a gate connected to the gate line to which the sensing signal is applied, a first electrode connected to the second node n2, and a second electrode connected to the reference voltage line to which the reference voltage Vref is applied.

[0133] The fourth switching element M04 applies an initialization voltage in response to the first initialization signal INIT1. In this case, the initialization voltage is applied to the first node through the initialization voltage line. The fourth switching element M04 includes a gate to which the first initialization signal INIT1 is applied, a first electrode connected to the initialization voltage line, and a second electrode connected to the first node n1.

[0134] The fifth switching element M05 applies an anode voltage in response to the second initialization signal INIT2. In this case, the anode voltage is applied to the third node through the anode voltage line. The fifth switching element M05 includes a gate to which the second initialization signal INIT2 is applied, a first electrode connected to the third node n3, and a second electrode connected to the anode voltage line.

[0135] The first capacitor Cst is connected between the first node n1 and the third node n3 and charges the gate-source voltage Vgs of the driving element DT.

[0136] The second capacitor C2 is connected between the high potential voltage line and the second node n2.

[0137] A first selection signal and a second selection signal in which the phase of the first selection signal is inverted may be applied to the pixel circuit according to an exemplary embodiment. For example, the EM signal EM is formed as the first selection signal and applied to the gate of the first switching element M01, and the second initialization signal INIT2 is formed as the second selection signal and applied to the gate of the fifth switching element M05.

[0138] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above-mentioned embodiments are exemplary in all aspects and are not intended to limit the present disclosure. The scope of protection of the present disclosure shall be based on the appended claims, and all technical concepts within their equivalent scope shall be interpreted as falling within the scope of protection of the present disclosure.

[0139] CROSS-REFERENCE TO RELATED APPLICATIONS

[0140] This application claims priority to and the benefit of Korean Patent Application No. 10-2021-0090005, filed on July 8, 2021, and Korean Patent Application No. 10-2021-0171605, filed on December 3, 2021, the disclosures of which are incorporated herein by reference in their entirety.

Claims

1. A gate driver comprising a plurality of signal transfer units connected in cascade via a carry line, a carry signal being applied from a preceding signal transfer unit to the carry line, in, The nth signal transmission unit includes: a first output unit configured to output a first gating signal to a first output node according to a voltage of a first control node configured to pull up an output voltage and a voltage of a second control node configured to pull down the output voltage; and a second output unit configured to output a second selection signal to a second output node, Wherein, the second output unit includes: a first pull-up transistor configured to output a high potential voltage to the second output node according to a voltage of a second control node of a (ni)th signal transmitting unit; and a first pull-down transistor configured to output a first low potential voltage to the second output node according to a voltage of a first control node of an (n+j)th signal transmitting unit, Where n is a positive integer, i is a positive integer less than n, and j is a natural number, The section where the high voltage pulse of the second strobe signal is applied is formed to be longer by 1H or more than the section where the low voltage pulse of the first strobe signal is applied.

2. The gate driver according to claim 1, wherein The first output unit includes: a second pull-up transistor configured to output a high potential voltage to the first output node according to a voltage of the first control node of the nth signal transmitting unit; and a second pull-down transistor configured to output a first low-potential voltage to the first output node according to a voltage of a second control node of the nth signal transmitting unit; 3. The gate driver according to claim 1 , further comprising: a first switching element connected between a first node connected to a gate of the first pull-down transistor and the first control node of the (n+j)th signal transmitting unit; as well as A second switching element is connected between the first node and a second low potential voltage and has a gate connected to the second control node of the (ni)th signal transmitting unit.

4. The gate driver according to claim 3, wherein: When a high voltage is applied to the second control node of the (ni)th signal transmitting unit, the first pull-up transistor is turned on, and the second switching element is turned on to turn off the first pull-down transistor.

5. The gate driver according to claim 3, wherein: When a low voltage is applied to the second control node of the (ni)th signal transmitting unit, the first pull-up transistor is turned off, and the second switching element is turned off to turn on the first pull-down transistor.

6. The gate driver according to claim 5, wherein: When a high voltage is applied to the first control node of the (n+j)th signal transmitting unit, the first switching element is turned on, and the second switching element is turned off to turn on the first pull-down transistor.

7. The gate driver according to claim 1, wherein The section where the high voltage pulse of the second strobe signal is applied is formed to be 1H long or more based on at least one of a rising edge and a falling edge of the section where the low voltage pulse of the first strobe signal is applied.

8. The gate driver according to claim 1, wherein The nth signal transmitting unit further includes: a first circuit unit configured to charge the first control node by receiving the carry signal from the previous signal transmitting unit; a second circuit unit, the second circuit unit comprising an inverter circuit configured to discharge the second control node according to the voltage of the first control node; and The third circuit unit is configured to output the carry signal to a third output node according to the voltage of the first control node and the voltage of the second control node.

9. A display panel, comprising: a data driver configured to output a data voltage; a gate driver including a plurality of signal transfer units connected in cascade via a carry line, a carry signal being applied from a preceding signal transfer unit to the carry line, The nth signal transmission unit includes: a first output unit configured to output a first strobe signal to a first output node according to a voltage of a first control node configured to pull up an output voltage and a voltage of a second control node configured to pull down an output voltage, and a second output unit configured to output a second strobe signal to a second output node; and a plurality of pixel circuits configured to reproduce an input image by receiving the data voltage, the first gate signal, and the second gate signal, Wherein, the second output unit includes: a first pull-up transistor configured to output a high potential voltage to the second output node according to a voltage of a second control node of a (ni)th signal transmitting unit; and a first pull-down transistor configured to output a first low potential voltage to the second output node according to a voltage of a first control node of an (n+j)th signal transmitting unit, Where n is a positive integer, i is a positive integer less than n, and j is a natural number, The section where the high voltage pulse of the second strobe signal is applied is formed to be longer by 1H or more than the section where the low voltage pulse of the first strobe signal is applied.

10. The display panel according to claim 9, wherein: The first output unit includes: a second pull-up transistor configured to output a high potential voltage to the first output node according to a voltage of the first control node of the nth signal transmitting unit; and a second pull-down transistor configured to output a first low-potential voltage to the first output node according to a voltage of a second control node of the nth signal transmitting unit; 11. The display panel according to claim 9, further comprising: a first switching element connected between a first node connected to a gate of the first pull-down transistor and the first control node of the (n+j)th signal transmitting unit; as well as A second switching element is connected between the first node and a second low potential voltage and has a gate connected to the second control node of the (ni)th signal transmitting unit.

12. The display panel according to claim 11, wherein: When a high voltage is applied to the second control node of the (ni)th signal transmitting unit, the first pull-up transistor is turned on, and the second switching element is turned on to turn off the first pull-down transistor.

13. The display panel according to claim 11, wherein: When a low voltage is applied to the second control node of the (ni)th signal transmitting unit, the first pull-up transistor is turned off, and the second switching element is turned off to turn on the first pull-down transistor.

14. The display panel according to claim 13, wherein: When a high voltage is applied to the first control node of the (n+j)th signal transmitting unit, the first switching element is turned on, and the second switching element is turned off to turn on the first pull-down transistor.

15. The display panel according to claim 9, wherein: The section where the high voltage pulse of the second strobe signal is applied is formed to be 1H or longer based on at least one of the rising edge and the falling edge of the section where the low voltage pulse of the first strobe signal is applied.

16. The display panel according to claim 9, wherein: The nth signal transmitting unit further includes: a first circuit unit configured to charge the first control node by receiving the carry signal from the previous signal transmitting unit; a second circuit unit, the second circuit unit comprising an inverter circuit configured to discharge the second control node according to the voltage of the first control node; and The third circuit unit is configured to output the carry signal to a third output node according to the voltage of the first control node and the voltage of the second control node.

17. The display panel according to claim 9, wherein: All transistors in the panel including the data driver, the gate driver, and the pixel circuit are implemented using oxide thin film transistors (TFTs) including an n-channel oxide semiconductor.

18. The display panel according to claim 9, wherein: Each pixel circuit includes: Light-emitting element; a driving element configured to provide current to the light emitting element EL; a plurality of switching elements for switching a current path connected to the driving element; a first capacitor for storing a voltage between a gate and a source of the driving element; and Second capacitor.

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