A voltage management circuit for an SRAM type programmable logic device

Abstract

The present application discloses a voltage management circuit for an SRAM-type programmable logic device (PLD), relating to the field of SRAM-type programmable logic devices. This application utilizes the characteristics of SRAM-type programmable logic devices having several fixed operating phases and corresponding flag bits. During the configuration phase, the voltage management circuit provides a wordline driver connected between a wordline circuit and a configuration SRAM with a wordline drive voltage greater than the core logic voltage. This allows the wordline voltage to be raised to a level sufficient to provide the wordline drive voltage to the selected configuration SRAM, improving the write performance of the configuration SRAM without compromising stability and optimizing the performance of the entire SRAM-type programmable logic device. Furthermore, the load during regulation is limited to the selected configuration SRAMs, resulting in a low load, rapid response, and reduced impact on the device's operating frequency.

Description

Technical Field

[0001] The present application relates to the field of SRAM type programmable logic devices, and in particular to a voltage management circuit of an SRAM type programmable logic device. Background Art

[0002] SRAM (Static Random-Access Memory) programmable logic devices (PLDs) are designed based on reconfigurable SRAM memory technology and are widely used in various fields and scenarios. By downloading a data stream to configure the SRAM, wiring switches can be controlled to select different signal paths, thereby implementing programmable logic functions to achieve desired user functions.

[0003] Please refer to Figure 1 The internal circuit structure of a common six-transistor SRAM configuration is shown. PMOS transistor P0 and NMOS transistor N0 form one inverter, while PMOS transistor P1 and NMOS transistor N1 form another inverter. These two inverters are each powered by the power supply voltage SRAM_VDD. The input and output terminals of the two inverters are cross-connected and connected to bit line BL through NMOS transistor N2 and bit line BLN through NMOS transistor N3. The gates of N2 and N3 are connected to word line WL.

[0004] To ensure the performance of SRAM-based programmable logic devices, the configuration SRAM must have excellent writeability and stability. Excellent writeability means that data can be easily written to the configuration SRAM, allowing for smooth refreshing of old data stored there. Excellent stability means that data stored there cannot be overwritten when reading from it, and the SRAM must have strong anti-interference capabilities.

[0005] To optimize the performance of configuration SRAM, it's common to adjust the size of the PMOS or NMOS transistors within the SRAM: reducing the aspect ratio of P1 improves the write performance of the configuration SRAM, while increasing the aspect ratio of N1 improves the stability and anti-interference capabilities of the configuration SRAM. However, the sizes of P0 and P1 within the configuration SRAM are identical, as are the sizes of N0 and N1. Reducing the size of the PMOS transistor and increasing the size of the NMOS transistor in the inverter can cause inverter failure. Therefore, currently, the only way to achieve a balance between write performance and stability is to carefully design the size of the PMOS or NMOS transistors within the configuration SRAM. This can easily lead to some configuration SRAMs (usually those at the end of the bit line) in SRAM-type programmable logic devices failing to write "1" under certain extreme conditions (-55°C to 125°C), ultimately causing the user logic to fail. Summary of the Invention

[0006] In response to the above-mentioned problems and technical requirements, the applicant has proposed a voltage management circuit for an SRAM-type programmable logic device. The technical solution of this application is as follows:

[0007] A voltage management circuit for an SRAM-type programmable logic device. In the SRAM-type programmable logic device, each wordline channel of a wordline circuit is connected to a corresponding plurality of configuration SRAMs via a wordline driver. The voltage management circuit is connected to each wordline driver to provide a wordline drive voltage WL_VDD. The wordline driver is configured to convert the wordline voltage output by the wordline channel to the configuration SRAM into the wordline drive voltage WL_VDD. The method performed by the voltage management circuit includes:

[0008] When the SRAM type programmable logic device is determined to be in the configuration stage based on the initialization flag and the configuration completion flag, a word line drive voltage WL_VDD greater than the core logic voltage VCCINT is provided to each word line driver. The word line driver connected to the selected word line channel converts the word line voltage output by the word line channel into a word line drive voltage WL_VDD and provides it to several currently selected configuration SRAMs.

[0009] A further technical solution is that the voltage management circuit is further connected to all configuration SRAMs to provide a power supply voltage SRAM_VDD for the configuration SRAMs, and the method performed by the voltage management circuit further includes:

[0010] When the SRAM type programmable logic device is determined to be in the clearing stage according to the initialization flag and the configuration completion flag, a power supply voltage SRAM_VDD lower than the core logic voltage VCCINT is provided to all configuration SRAMs, so that all configuration SRAMs complete data clearing through one cycle.

[0011] A further technical solution is that the method performed by the voltage management circuit further includes:

[0012] When it is determined according to the initialization flag and the configuration completion flag that the SRAM type programmable logic device is in the stage of running the user logic function, a power supply voltage SRAM_VDD greater than the core logic voltage VCCINT is provided to all configuration SRAMs.

[0013] A further technical solution is that the method performed by the voltage management circuit further includes:

[0014] When the SRAM type programmable logic device is determined to be in the user logic function running stage according to the initialization flag and the configuration completion flag, the voltage value of the power supply voltage SRAM_VDD provided to all configuration SRAMs is adjusted according to the configuration SRAM voltage control register.

[0015] A further technical solution is that the method performed by the voltage management circuit further includes:

[0016] When it is determined according to the initialization flag and the configuration completion flag that the SRAM type programmable logic device is in the stage of running the user logic function, a word line driving voltage WL_VDD of 0V is provided to all word line drivers.

[0017] A further technical solution is that the voltage management circuit includes a reference voltage module and a high voltage generation module, the reference voltage module generates a reference voltage Vref and provides it to the high voltage generation module;

[0018] A first output terminal of the voltage management circuit is grounded via switch K0. The first output terminal is also connected to the core logic voltage VCCINT via switch K1. The first output terminal is also connected to the output terminal of the high-voltage generation module via switch K2. Only one of switches K0, K1, and K2 is in the closed state at any given time.

[0019] When switch K0 is closed, the voltage management circuit outputs a 0V word line drive voltage WL_VDD through the first output terminal; when switch K1 is closed, the voltage management circuit outputs a word line drive voltage WL_VDD equal to the core logic voltage VCCINT through the first output terminal; when switch K2 is closed, the high-voltage generation module generates a voltage greater than the core logic voltage VCCINT based on the reference voltage and outputs it through the first output terminal as the word line drive voltage WL_VDD.

[0020] A further technical solution is that the voltage management circuit further includes a low voltage generation module, and the reference voltage Vref generated by the reference voltage module is also provided to the low voltage generation module;

[0021] The second output terminal of the voltage management circuit is connected to the output terminal of the high-voltage generation module through switch K3, the second output terminal is connected to the core logic voltage VCCINT through switch K4, and the second output terminal is connected to the output terminal of the low-voltage generation module through switch K5. Only one of switches K3, K4, and K5 is in the closed state at any one time.

[0022] When switch K3 is closed, the high-voltage generation module generates a voltage greater than the core logic voltage VCCINT based on the reference voltage and outputs it through the second output terminal as the power supply voltage SRAM_VDD; when switch K4 is closed, the voltage management circuit outputs a power supply voltage SRAM_VDD equal to the core logic voltage VCCINT through the second output terminal; when switch K5 is closed, the low-voltage generation module generates a voltage less than the core logic voltage VCCINT based on the reference voltage and outputs it through the second output terminal as the power supply voltage SRAM_VDD.

[0023] Its further technical solution is that in the high-voltage generating module, the output end of the voltage regulating unit is connected to the inverting input end of the first operational amplifier, and the voltage regulating unit generates a target voltage Vref_1 of a corresponding voltage value based on the reference voltage Vref generated by the reference voltage module according to the configuration of the SRAM voltage control register. The output end of the first operational amplifier is connected to the input end of the charge pump, and the output end of the charge pump serves as the output end of the high-voltage generating module. The output end of the charge pump is also connected to resistor R6 and resistor R7 in sequence and then grounded, and the common end of resistor R6 and resistor R7 is connected to the non-inverting input end of the first operational amplifier.

[0024] A further technical solution is that the voltage regulating unit includes an input branch and P output branches;

[0025] The input branch includes: the source of PMOS transistor P2 is connected to the core logic voltage VCCINT, the drain of P2 is connected to the source of PMOS transistor P3, and the drain of P3 is grounded through resistor R3; the gate of P2 is connected to the reference voltage Vref, and the gate of P3 obtains 0V voltage. P2, P3 and R3 form an input branch and provide a reference current Iref of Vref / R3;

[0026] P output branches share the series-connected resistors R4 and R5 as output loads, and the on / off of the P output branches is controlled by the configured SRAM voltage control register; the input branch and each conductive output branch respectively form a current mirror, through which the reference current Iref of the input branch is copied to each output branch respectively, and the voltage generated by all output branches on the output load is output as the target voltage Vref_1 = Iref*(R4+R5)*N, where N is the number of conductive output branches among the P output branches.

[0027] A further technical solution is that in the low-voltage generation module, the source of the PMOS transistor P11 is connected to the core logic voltage VCCINT, the drain of P11 is connected to the resistor R8 and the resistor R9 in sequence and then to ground, and the drain of P11 serves as the output end of the low-voltage generation module;

[0028] The non-inverting input terminal of the second operational amplifier is connected to the reference voltage Vref generated by the reference voltage module, the inverting input terminal of the second operational amplifier is connected to the common terminal of the resistor R8 and the resistor R9, the output terminal of the second operational amplifier is connected to the input terminal of the inverter, and the output terminal of the inverter is connected to the gate of P11.

[0029] The beneficial technical effects of this application are:

[0030] (1) This application discloses a voltage management circuit for an SRAM-type programmable logic device. During the configuration phase of the SRAM-type programmable logic device, the voltage management circuit provides a wordline driver between the wordline circuit and the configuration SRAM with a wordline drive voltage WL_VDD greater than the core logic voltage VCCINT, so that the wordline driver connected to the selected wordline channel raises the wordline voltage to WL_VDD and then provides it to the connected configuration SRAM, thereby improving the write performance of the configuration SRAM without affecting the stability and optimizing the performance of the entire SRAM-type programmable logic device. After actual testing, the voltage management circuit and its implementation method can ensure that the configuration SRAM at all locations can be successfully written within the full temperature range (-55°C to 125°C).

[0031] (2) In the process of sequentially selecting the word line channels, it is only necessary to raise the word line voltage of the selected configuration SRAM to WL_VDD each time, without raising the word line voltage of all configuration SRAMs. Therefore, the load is small, the response can be fast, and the impact on the operating frequency is reduced.

[0032] (3) The voltage management circuit can also provide the configuration SRAM with a power supply voltage SRAM_VDD that is less than VCCINT during the clearing phase of the SRAM type programmable logic device, thereby reducing the difficulty of data clearing and enabling data clearing to be completed in one cycle, thereby reducing the time consumption of the clearing phase.

[0033] (4) The voltage management circuit can also provide the configuration SRAM with a power supply voltage SRAM_VDD greater than VCCINT during the user logic function phase of the SRAM-type programmable logic device, thereby accelerating the speed at which the NMOS switch controlled by the configuration SRAM transmits signals, thereby increasing the gate voltage of the transmission NMOS tube controlled by the configuration SRAM, thereby improving the delay and duty cycle of signal transmission. In addition, the SRAM_VDD voltage can be adjusted by configuring the SRAM voltage control register, which not only ensures the quality of signal transmission, but also ensures the reliability of the device under long-term operation.

[0034] (5) The voltage management circuit can also provide 0V WL_VDD to the word line driver when the SRAM type programmable logic device is running the user logic function stage, thereby turning off the word line driver and reducing power consumption.

[0035] (6) SRAM type programmable logic devices have several fixed working stages and corresponding flag bits after power-on. The method for implementing the voltage management circuit utilizes this characteristic of SRAM type programmable logic devices to manage the voltage of the configured SRAM, thereby realizing the required voltage management function in different working stages. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 This is the internal structure diagram of the common six-tube configuration SRAM.

[0037] Figure 2 This is a schematic diagram of the connection between the voltage management circuit of the present application and the circuit configuring SRAM.

[0038] Figure 3 This is a timing diagram of the voltage provided by the voltage management circuit in one embodiment of the present application to configure the SRAM type programmable logic device at different stages.

[0039] Figure 4 This is a diagram showing the relationship between the signal transmission characteristics of the NMOS transistor and the power supply voltage SRAM_VDD for configuring the SRAM.

[0040] Figure 5 is a circuit diagram of a voltage management circuit in one embodiment of the present application.

[0041] Figure 6 yes Figure 5 Control timing diagram of each switch in .

[0042] Figure 7 This is a circuit diagram of a high voltage generating module in one embodiment of the present application.

[0043] Figure 8 This is a circuit diagram of a voltage regulating unit in a high voltage generating module in one embodiment of the present application.

[0044] Figure 9 This is a circuit diagram of a low voltage generating module in one embodiment of the present application.

[0045] Figure 10 yes Figure 5 A circuit diagram of one embodiment of each switch in the circuit diagram is shown. DETAILED DESCRIPTION

[0046] The specific implementation of this application will be further described below with reference to the accompanying drawings.

[0047] The present application discloses a voltage management circuit for an SRAM type programmable logic device, which is used to adjust the voltage involved in configuring the SRAM in the SRAM type programmable logic device. The configuration SRAM in the present application can be used as follows Figure 1In the common six-transistor structure shown or other structures, according to common practice, in an array formed by configuration SRAM, each word line channel of the word line circuit is connected to a row of configuration SRAM to provide a word line voltage WL. Based on this, the present application sets a word line driver I1 between the word line circuit and the configuration SRAM. Each word line channel in the word line circuit is connected to a corresponding number of configuration SRAMs through a word line driver I1. According to common practice, each word line channel is connected to a number of configuration SRAMs in the same row of the array through a word line driver I1, as shown in FIG. Figure 2 shown.

[0048] In a conventional SRAM type programmable logic device, each word line channel of the word line circuit is sequentially selected to select each row of configuration SRAM. When a word line channel is selected, a row of configuration SRAM connected to it is selected. The word line voltage WL generated by the selected word line channel is directly as follows: Figure 1 As shown, the voltage is provided to the currently selected row of configuration SRAMs and connected to the gates of N2 and N3 within the currently selected row. However, in the present application, the voltage management circuit connects to each wordline driver I1 to provide a wordline drive voltage WL_VDD. During the process of sequentially selecting the wordline channels, the wordline driver I1 connected to the selected wordline channel converts the wordline voltage WL output by the connected wordline channel into a wordline drive voltage WL_VDD and provides it to the currently selected plurality of configuration SRAMs, which are then similarly connected to the gates of N2 and N3 within the currently selected row of configuration SRAMs. In one embodiment, the wordline driver I1 can be implemented as a buffer. When the operating voltage of the wordline driver I1 is the wordline drive voltage WL_VDD, the effect of converting the input wordline voltage WL into the wordline drive voltage WL_VDD can be achieved.

[0049] The method executed by the voltage management circuit includes: when it is determined that the SRAM type programmable logic device is in the configuration stage according to the initialization flag bit Initial and the configuration completion flag bit Done, providing a word line drive voltage WL_VDD greater than the core logic voltage VCCINT to each word line driver, and the word line driver connected to the selected word line channel converts the word line voltage output by the word line channel into a word line drive voltage WL_VDD greater than VCCINT and provides it to the currently selected multiple configuration SRAMs.

[0050] After the SRAM type programmable logic device is powered on and reset based on the upper reset signal PWR_RST, it goes through the clearing stage, the configuration stage, and the user logic function running stage in sequence. The initialization flag bit Initial and the configuration completion flag bit Done can be used to identify the three stages of the SRAM type programmable logic device. According to the conventional method, in an example:

[0051] (1) When the initialization flag bit Initial is at a low level and the configuration completion flag bit Done is at a low level, it indicates that the SRAM type programmable logic device is in the clearing stage.

[0052] (2) When the initialization flag bit Initial is at a high level and the configuration completion flag bit Done is at a low level, it indicates that the SRAM type programmable logic device is in the configuration stage. The configuration stage in this application includes the stage of code stream verification.

[0053] (3) When the initialization flag bit Initial is at a high level and the configuration completion flag bit Done is at a high level, it indicates that the SRAM type programmable logic device is in the stage of running the user logic function.

[0054] Therefore, the voltage management circuit can determine the stage of the SRAM type programmable logic device according to the initialization flag bit Initial and the configuration completion flag bit Done, and perform voltage management on the configuration SRAM accordingly.

[0055] During the configuration phase, the wordline drive voltage WL provided to the currently selected configuration SRAM is increased to the wordline drive voltage WL_VDD, thereby improving the drive capability of the wordline. Field testing has confirmed that this ensures that all configuration SRAMs in all locations can correctly write data over the full temperature range (-55°C to 125°C), especially those connected to the end of the bitline. Because this phase is relatively short, the wordline drive voltage WL_VDD can be relatively high. In one embodiment, the wordline drive voltage WL_VDD provided to each selected configuration SRAM during the configuration phase is 1.2*VCCINT, which ensures correct data writing without affecting the reliability of the SRAM-type programmable logic device. This approach of increasing the wordline drive voltage WL_VDD can provide the configuration SRAM with both better write performance and better anti-interference capabilities, which is more effective than adjusting the size of PMOS or NMOS transistors and is easier to implement.

[0056] In another embodiment, the voltage management circuit further connects all configuration SRAMs and provides the configuration SRAM supply voltage SRAM_VDD. Based on this structure, theoretically, by providing the configuration SRAMs with a supply voltage SRAM_VDD that is lower than the core logic voltage VCCINT during the configuration phase, it is possible to ensure that data can be correctly written to all configuration SRAMs within the full temperature range (-55°C to 125°C). However, since the supply voltage SRAM_VDD of all configuration SRAMs is connected, the voltage management circuit experiences a significant load when adjusting the supply voltage SRAM_VDD of all configuration SRAMs in the array, resulting in a long response time and inability to achieve timely adjustment. This can severely impact the operating frequency during the entire period.

[0057] Each word line channel of the word line circuit is connected to several configuration SRAMs through a word line driver I1. Each word line channel is selected in sequence. Therefore, it is only necessary to raise the word line voltage of the selected configuration SRAM to WL_VDD each time, without raising the word line voltage of all configuration SRAMs. Therefore, the load is small and the response time is short. Compared with the method of adjusting the power supply voltage SRAM_VDD, the response time is shorter and the impact on the operating frequency is reduced.

[0058] Please refer to Figure 3 As shown in the timing diagram, the voltage management circuit can maintain the power supply voltage SRAM_VDD provided by the voltage management circuit to each configuration SRAM equal to the core logic voltage VCCINT based on the fact that the voltage management circuit provides the word line drive voltage WL_VDD greater than the core logic voltage VCCINT to each selected configuration SRAM during the configuration phase.

[0059] Based on a structure in which a voltage management circuit is used to provide both a wordline drive voltage WL_VDD to a wordline driver I1 and a supply voltage SRAM_VDD to each configuration SRAM, the voltage management circuit not only adjusts the wordline drive voltage WL_VDD during the configuration phase of the SRAM-type programmable logic device, but also performs a method further comprising: when the SRAM-type programmable logic device is determined to be in a clearing phase based on an initialization flag and a configuration completion flag, providing a supply voltage SRAM_VDD that is less than the core logic voltage VCCINT to all configuration SRAMs. This lower supply voltage SRAM_VDD reduces the difficulty of clearing the configuration SRAMs, thereby enabling data clearing of all configuration SRAMs to be completed in a single cycle. Conventional practices require balancing the needs of three phases simultaneously to determine the value of the SRAM configuration power supply voltage SRAM_VDD. This often results in multiple cycles required to complete the clearing of all SRAM configurations during the clearing phase, resulting in a significant time consumption. However, the present application utilizes a voltage management circuit to adjust the value of the SRAM configuration power supply voltage SRAM_VDD as needed at different phases. By lowering the SRAM configuration power supply voltage SRAM_VDD during the clearing phase, the slow clearing speed issue can be resolved. In one embodiment, the SRAM configuration power supply voltage SRAM_VDD provided to each SRAM configuration during the clearing phase is 0.9*VCCINT.

[0060] During the clearing phase, the word line driving voltage WL_VDD provided by the voltage management circuit to each word line driver I1 may be maintained at the core logic voltage VCCINT.

[0061] In another embodiment, in addition to adjusting the voltage supplied to each configuration SRAM during the reset and configuration phases, the voltage management circuit can also adjust the voltage supplied to each configuration SRAM during the user logic function execution phase. The method performed by the voltage management circuit further includes: when the SRAM-type programmable logic device is determined to be in the user logic function execution phase based on the initialization flag and the configuration completion flag, providing a supply voltage SRAM_VDD greater than the core logic voltage VCCINT to all configuration SRAMs.

[0062] Please refer to Figure 1 The diagram shows the connection between the configuration SRAM and the transmission NMOS transistor N4. During the user logic function phase of the SRAM-type programmable logic device, a "1" written to the configuration SRAM sets the gate of the controlled transmission NMOS transistor N4 to a high level, turning on the transmission NMOS transistor N4. Signal Signal_in can be transmitted through N4 to generate Signal_out, and the SRAM-type FPGA begins operating according to the user logic function. This approach of using a single NMOS transistor to transmit signals results in significant delays when transmitting high-level signals due to the loss of the NMOS transistor's threshold voltage, often failing to meet the requirements for transmitting higher-frequency signals and causing significant imbalance in the signal duty cycle. This embodiment utilizes a voltage management circuit to provide the configuration SRAM with a supply voltage SRAM_VDD greater than the core logic voltage VCCINT during the user logic function phase. This raises the gate voltage of the transmission NMOS transistor N4, used for signal transmission, to SRAM_VDD, which is greater than the core logic voltage VCCINT. This reduces the loss of the threshold voltage when transmitting high-level signals (voltage VCCINT), thereby increasing the operating frequency and improving the signal duty cycle. (See [1] for details.) Figure 4 The relationship between the signal transmission characteristics and SRAM_VDD shown in FIG. 1 is that the larger the supply voltage SRAM_VDD provided to configure the SRAM, the less signal loss occurs when the transmission NMOS transistor N4 transmits a high level, and the closer Signal_out is to Signal_in, thereby increasing the operating frequency and improving the signal duty cycle.

[0063] However, the supply voltage SRAM_VDD cannot be raised too much, otherwise it will easily affect the reliability of the device. Therefore, the supply voltage SRAM_VDD provided by the voltage management circuit during the user logic function operation stage is relatively lower than the word line drive voltage WL_VDD provided by the voltage management circuit during the configuration stage. In one embodiment, the provided supply voltage SRAM_VDD = 1.05*VCCINT ~ 1.15*VCCINT.

[0064] In another embodiment, in order to balance the operating frequency, duty cycle and device reliability, the voltage management circuit adjusts the voltage value of the power supply voltage SRAM_VDD provided to all configured SRAMs according to the configured SRAM voltage control register. That is, during the user logic function operation stage, the power supply voltage SRAM_VDD provided by the voltage management circuit is not fixed, but can be adjusted and configured according to actual measurement results, so as to ensure both the signal transmission quality and the long-term operation reliability of the chip.

[0065] In another embodiment, in addition to providing a supply voltage SRAM_VDD greater than the core logic voltage VCCINT to all configuration SRAMs during the user logic function phase, the voltage management circuit also provides a 0V wordline drive voltage WL_VDD to all wordline drivers. Since the configuration SRAMs do not need to be operated during the user logic function phase, the wordline drive voltage can be turned off, thereby reducing power consumption.

[0066] Based on the logic that the voltage management circuit manages the voltage of the configuration SRAM according to the above method in each of the three phases, during operation, the SRAM-type programmable logic device: before the configuration phase, the configuration SRAM voltage control register is modified according to the WL_VDD and SRAM_VDD required for the configuration phase, so that the voltage provided to the configuration SRAM meets the requirements of the configuration phase. After configuration is completed, before the configuration completion flag bit Done goes high, the configuration SRAM voltage control register is modified according to the WL_VDD and SRAM_VDD required for the user logic function phase, so that the voltage provided to the configuration SRAM meets the requirements of the user logic function phase.

[0067] In one embodiment, the voltage management circuit provides the word line drive voltage WL_VDD and the power supply voltage SRAM_VDD required for configuring the SRAM at the same time, and is controlled according to the above control method in three stages. The circuit structure of the voltage management circuit for realizing the above function is as follows: Figure 5 shown.

[0068] In order to manage the word line drive voltage WL_VDD, the voltage management circuit includes a reference voltage module and a high voltage generation module. The reference voltage module generates a reference voltage Vref and provides it to the high voltage generation module. The first output terminal of the voltage management circuit is grounded through switch K0, and the first output terminal is also connected to the core logic voltage VCCINT through switch K1. The first output terminal is also connected to the output terminal of the high voltage generation module through switch K2. Among the switches K0, K1 and K2, only one is in a closed state at the same time. Based on the control logic provided in this application, switch K1 is closed in the clearing stage, switch K2 is closed in the configuration stage, and switch K0 is closed in the stage of running the user logic function. Please combine Figure 6 The control timing diagram is shown.

[0069] When switch K0 is closed, the voltage management circuit outputs a 0V wordline drive voltage WL_VDD through the first output terminal. When switch K1 is closed, the voltage management circuit outputs a wordline drive voltage WL_VDD equal to the core logic voltage VCCINT through the first output terminal. When switch K2 is closed, the high-voltage generation module generates a voltage greater than the core logic voltage VCCINT based on the reference voltage and outputs it through the first output terminal as the wordline drive voltage WL_VDD.

[0070] In order to manage the power supply voltage SRAM_VDD, the voltage management circuit also requires a reference voltage module and a high voltage generation module, and also includes a low voltage generation module. Figure 3 As shown in the timing diagram, the voltage management circuit needs to use the high-voltage generation module to generate WL_VDD greater than VCCINT during the configuration phase, and needs to generate SRAM_VDD greater than VCCINT during the user logic function running phase. Since these two voltages greater than VCCINT are generated at different stages, the reference voltage module and the high-voltage generation module can be shared to generate SRAM_VDD and WL_VDD.

[0071] The reference voltage Vref generated by the reference voltage module is also provided to the low-voltage generation module. The second output terminal of the voltage management circuit is connected to the output terminal of the high-voltage generation module via switch K3, the second output terminal is connected to the core logic voltage VCCINT via switch K4, and the second output terminal is connected to the output terminal of the low-voltage generation module via switch K5. Among switches K3, K4, and K5, only one is closed at a time. Based on the control logic provided in this application, switch K3 is closed during the user logic function execution phase, switch K4 is closed during the configuration phase, and switch K5 is closed during the reset phase.

[0072] When switch K3 is closed, the high-voltage generation module generates a voltage greater than the core logic voltage VCCINT based on the reference voltage and outputs it via the second output terminal as the supply voltage SRAM_VDD. When switch K4 is closed, the voltage management circuit outputs the supply voltage SRAM_VDD equal to the core logic voltage VCCINT via the second output terminal. When switch K5 is closed, the low-voltage generation module generates a voltage less than the core logic voltage VCCINT based on the reference voltage and outputs it via the second output terminal as the supply voltage SRAM_VDD.

[0073] Please refer to Figure 7 In the high-voltage generation module, the output of the voltage regulation unit is connected to the inverting input of the first operational amplifier I2. The voltage regulation unit generates a target voltage Vref_1 of a corresponding voltage value based on the reference voltage Vref generated by the reference voltage module, according to the configuration of the SRAM voltage control register. The output of the first operational amplifier I2 is connected to the input of a charge pump, which serves as the output of the high-voltage generation module. The output of the charge pump is further connected to resistors R6 and R7 in sequence and then to ground. The common terminal of resistors R6 and R7 is connected to the non-inverting input of the first operational amplifier I2. The voltage generated by the high-voltage generation module, which is greater than the core logic voltage VCCINT, can be expressed as ((R6 + R7) / R7) * Vref_1.

[0074] For the circuit diagram of the voltage regulator unit, please refer to Figure 8 As shown, the voltage regulation unit includes an input branch and P output branches. The input branch includes: the source of PMOS transistor P2 is connected to the core logic voltage VCCINT, the drain of P2 is connected to the source of PMOS transistor P2, and the drain of P3 is grounded through resistor R3; the gate of P2 is connected to the reference voltage Vref, and the gate of P3 receives 0V. P2, P3, and R3 form an input branch and provide a reference current Iref = Vref / R3.

[0075] P output branches share the series resistors R4 and R5 as output loads. Figure 8 For example, in a circuit with 13 output branches, the source of PMOS transistor P4 in the first output branch is connected to VCCINT, the drain of P4 is connected to the source of P5, and the drain of P5 is connected to the series circuit of R4 and R5 and ground. In the second output branch, the source of PMOS transistor P6 is connected to VCCINT, the drain of P6 is connected to the source of P7, and the drain of P7 is connected to the series circuit of R4 and R5 and ground. Similarly, in the last output branch, the source of PMOS transistor P8 is connected to VCCINT, the drain of P8 is connected to the source of P9, and the drain of P9 is connected to the series circuit of R4 and R5 and ground. The connection between the PMOS transistors in each output branch and R4 serves as the output of the voltage regulation unit, which outputs the voltage generated across the output loads R4 and R5 as Vref_1.

[0076] The on / off of the P output branches is controlled by configuring the SRAM voltage control register. In this application, one output branch is turned on by default, for example Figure 8 In the first output branch, the gate of one PMOS transistor P4 is controlled by Vref, and the gate of another PMOS transistor P5 is connected to 0V. The on-off of the P-1 output branches in the remaining P output branches is controlled by configuring the SRAM voltage control register. One implementation method is that the gate of one PMOS transistor in each of the remaining output branches is controlled by Vref, and the gate of the other PMOS transistor is connected to the register signal Reg[0]~Reg[P-2] respectively. Then, by configuring the SRAM voltage control register and configuring the register signal Reg[P-2:0], the on-off of the remaining P-1 output branches can be controlled. The number of output branches is related to the range of voltage regulation and can be configured according to actual needs, for example Figure 8 In the example, the PMOS transistors in the remaining 12 output branches are controlled by register signals Reg[0] to Reg

[11] . When the register signal connected to the PMOS transistor in the output branch is 0V, the output branch is turned on, and at least one register signal from Reg[0] to Reg

[11] is 0V, so that the number of output branches that are turned on in all P output branches is N∈[2,P]. For example Figure 8 In the example, by configuring the SRAM voltage control register, the values ​​of all 12-bit register signals Reg[11:0] are configured from 1111_1111_1110 to 0000_0000_0000, and the number of output branches that are turned on is N∈[2,13].

[0077] The input branch and each active output branch form a current mirror, which copies the input branch's reference current, Iref, to each output branch. The number of copies made by the current mirror is N∈[2,P]. The voltage generated by all output branches at the output load is output as the target voltage, Vref_1 = Iref*(R4+R5)*N, where N is the number of active output branches in the P output branches.

[0078] Please refer to Figure 9In the low-voltage generation module, the source of PMOS transistor P11 is connected to the core logic voltage VCCINT. The drain of P11 is connected to resistors R8 and R9 in sequence and then to ground. The drain of P11 serves as the output of the low-voltage generation module. The non-inverting input of the second operational amplifier I3 is connected to the reference voltage Vref generated by the reference voltage module. The inverting input of the second operational amplifier I3 is connected to the common terminal of resistors R8 and R9. The output of the second operational amplifier I3 is connected to the input of inverter I4, and the output of inverter I4 is connected to the gate of P11. The voltage generated by the low-voltage generation module, which is lower than the core logic voltage VCCINT, can be expressed as ((R8 + R9) / R9) * Vref.

[0079] In one embodiment, Figure 5 Each of the switches K0, K1, K2, K3, K4 and K5 can be configured as follows: Figure 10 The circuit structure shown is implemented such that when the input control signal k=1, the switch is turned on, and POWER_OUT on the output side of the switch is equal to POWER_IN on the input side; when k=0, the switch is turned off.

[0080] The above description is only a preferred embodiment of the present application, and the present application is not limited to the above embodiments. It is understood that other improvements and variations directly derived or imagined by those skilled in the art without departing from the spirit and concept of the present application should be considered to be included in the scope of protection of the present application.

Claims

1. A voltage management circuit for an SRAM type programmable logic device, characterized in that: In the SRAM-type programmable logic device, each word line channel of the word line circuit is connected to a corresponding number of configuration SRAMs via a word line driver, the voltage management circuit is connected to each word line driver to provide a word line drive voltage WL_VDD, and the voltage management circuit is also connected to all configuration SRAMs to provide a power supply voltage SRAM_VDD for the configuration SRAMs; The method performed by the voltage management circuit includes: When it is determined based on the initialization flag and the configuration completion flag that the SRAM type programmable logic device is in the configuration stage, a word line drive voltage WL_VDD greater than the core logic voltage VCCINT is provided to each word line driver, and the word line driver connected to the selected word line channel converts the word line voltage output by the word line channel into the word line drive voltage WL_VDD and provides it to the currently selected multiple configuration SRAMs; when it is determined based on the initialization flag and the configuration completion flag that the SRAM type programmable logic device is in the reset stage, a power supply voltage SRAM_VDD less than the core logic voltage VCCINT is provided to all configuration SRAMs, so that all configuration SRAMs complete data reset in one cycle.

2. The voltage management circuit according to claim 1, wherein: The method performed by the voltage management circuit further includes: When it is determined according to the initialization flag and the configuration completion flag that the SRAM type programmable logic device is in the stage of running the user logic function, a power supply voltage SRAM_VDD greater than the core logic voltage VCCINT is provided to all configuration SRAMs.

3. The voltage management circuit according to claim 2, wherein: The method performed by the voltage management circuit further includes: When it is determined according to the initialization flag and the configuration completion flag that the SRAM type programmable logic device is in the stage of running the user logic function, the voltage value of the power supply voltage SRAM_VDD provided to all configuration SRAMs is adjusted according to the configuration SRAM voltage control register.

4. The voltage management circuit according to claim 1, wherein: The method performed by the voltage management circuit further includes: When it is determined according to the initialization flag and the configuration completion flag that the SRAM type programmable logic device is in the stage of running the user logic function, a word line driving voltage WL_VDD of 0V is provided to all word line drivers.

5. The voltage management circuit according to claim 1, wherein: The voltage management circuit includes a reference voltage module and a high voltage generation module, wherein the reference voltage module generates a reference voltage Vref and provides the reference voltage Vref to the high voltage generation module; The first output terminal of the voltage management circuit is grounded through a switch K0, the first output terminal is further connected to the core logic voltage VCCINT through a switch K1, and the first output terminal is further connected to the output terminal of the high voltage generation module through a switch K2; Among switch K0, switch K1 and switch K2, only one switch is in the closed state at the same time; When switch K0 is closed, the voltage management circuit outputs a word line drive voltage WL_VDD of 0V through the first output terminal; when switch K1 is closed, the voltage management circuit outputs a word line drive voltage WL_VDD equal to the core logic voltage VCCINT through the first output terminal; when switch K2 is closed, the high-voltage generation module generates a voltage greater than the core logic voltage VCCINT based on the reference voltage and outputs it through the first output terminal as the word line drive voltage WL_VDD.

6. The voltage management circuit according to claim 5, wherein: The voltage management circuit further includes a low voltage generating module, and the reference voltage Vref generated by the reference voltage module is also provided to the low voltage generating module; The second output end of the voltage management circuit is connected to the output end of the high voltage generation module through a switch K3, the second output end is connected to the core logic voltage VCCINT through a switch K4, and the second output end is connected to the output end of the low voltage generation module through a switch K5; Among switch K3, switch K4 and switch K5, only one of them is in the closed state at the same time; When the switch K3 is closed, the high-voltage generation module generates a voltage greater than the core logic voltage VCCINT based on the reference voltage and outputs it via the second output terminal as the power supply voltage SRAM_VDD; when the switch K4 is closed, the voltage management circuit outputs a power supply voltage SRAM_VDD equal to the core logic voltage VCCINT via the second output terminal; when the switch K5 is closed, the low-voltage generation module generates a voltage less than the core logic voltage VCCINT based on the reference voltage and outputs it via the second output terminal as the power supply voltage SRAM_VDD.

7. The voltage management circuit according to claim 6, wherein: In the high-voltage generation module, the output end of the voltage regulation unit is connected to the inverting input end of the first operational amplifier. The voltage regulation unit generates a target voltage Vref_1 of a corresponding voltage value based on the reference voltage Vref generated by the reference voltage module according to the configuration of the SRAM voltage control register. The output end of the first operational amplifier is connected to the input end of the charge pump. The output end of the charge pump serves as the output end of the high-voltage generation module. The output end of the charge pump is also connected to resistor R6 and resistor R7 in sequence and then grounded. The common end of the resistor R6 and resistor R7 is connected to the non-inverting input end of the first operational amplifier.

8. The voltage management circuit according to claim 7, wherein: The voltage regulating unit includes an input branch and P output branches; The input branch includes: the source of the PMOS transistor P2 is connected to the core logic voltage VCCINT, the drain of P2 is connected to the source of the PMOS transistor P3, and the drain of P3 is grounded through the resistor R3; the gate of P2 is connected to the reference voltage Vref, and the gate of P3 obtains 0V voltage. P2, P3 and R3 form an input branch and provide a reference current Iref of Vref / R3; P output branches share a resistor R4 and a resistor R5 connected in series as an output load, and the on / off of the P output branches is controlled by a configuration SRAM voltage control register; the input branch and each conductive output branch respectively form a current mirror, through which the reference current Iref of the input branch is copied to each output branch, and the voltage generated by all output branches on the output load is output as the target voltage Vref_1=Iref*(R4+R5)*N, where N is the number of conductive output branches among the P output branches.

9. The voltage management circuit according to claim 6, wherein: In the low-voltage generation module, the source of the PMOS transistor P11 is connected to the core logic voltage VCCINT, the drain of P11 is connected to the resistor R8 and the resistor R9 in sequence and then to ground, and the drain of P11 serves as the output end of the low-voltage generation module; The non-inverting input terminal of the second operational amplifier is connected to the reference voltage Vref generated by the reference voltage module, the inverting input terminal of the second operational amplifier is connected to the common end of resistor R8 and resistor R9, the output terminal of the second operational amplifier is connected to the input terminal of the inverter, and the output terminal of the inverter is connected to the gate of P11.

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