Antifuse memory circuit

Abstract

An embodiment of the present application provides an anti-fuse memory circuit, including: a memory array including a plurality of anti-fuse memory cells; bit lines connected to the anti-fuse memory cells arranged in the extending direction of the bit lines, and the anti-fuse memory cells are electrically connected to the bit lines through first switching transistors; word lines connected to the first switching transistors arranged in the extending direction of the word lines; a second switching transistor for connecting the bit lines to transmission wires; a reading module, with a first input terminal connected to the transmission wires, a second input terminal for receiving a reference voltage, and a sampling input terminal for receiving a sampling signal; a signal generating module for generating the sampling signal according to a pre-charge voltage and a pre-charge signal, wherein the pre-charge signal is used to indicate pre-charging the transmission wires to the pre-charge voltage, and the delay length between the sampling signal and the pre-charge signal is positively correlated with the voltage magnitude of the pre-charge voltage, so as to ensure that when the pre-charge voltage is relatively large, the anti-fuse memory cells have sufficient time to discharge current and ensure the accuracy of the read data.

Description

Technical Field

[0001] This application relates to the field of semiconductor circuit design, and particularly to an anti-fuse memory circuit. Background Art

[0002] An anti-fuse memory can be implemented through an anti-fuse memory cell array. The gate oxide medium of the anti-fuse memory cell will break down after applying a high voltage, and the impedance of the path decreases after breakdown; the information stored in the anti-fuse memory cell can be read by detecting the resistance state of the path after breakdown.

[0003] However, due to certain fluctuations in the internal power supply voltage V DD of the device. For example, the high voltage of V DD may reach 1.4V, while the low voltage may only reach 1.0V. At this time, if the reference voltage remains unchanged, when V DD is at a high voltage, it may cause the anti-fuse memory cell that would originally output a low level to finally read a high level, resulting in a read error. Summary of the Invention

[0004] An embodiment of this application provides an anti-fuse memory circuit, which delays the sampling signal for data reading relative to the pre-charge signal, and the length of the delay is positively correlated with the pre-charge voltage, so as to ensure that when the pre-charge voltage is large, the anti-fuse memory cell has enough time to discharge current, thereby ensuring the accuracy of the read data.

[0005] To solve the above technical problems, an embodiment of this application provides an anti-fuse memory circuit, including: a storage array including a plurality of anti-fuse memory cells, and the anti-fuse memory cells represent 1-bit data stored by whether the gate oxide layer is broken down; bit lines connected to the anti-fuse memory cells arranged in the extending direction of the bit lines, and the anti-fuse memory cells are electrically connected to the bit lines through first switching transistors; word lines connected to the first switching transistors arranged in the extending direction of the word lines, for turning on the selected first switching transistors according to a row selection signal, wherein the extending direction of the bit lines and the extending direction of the word lines are perpendicular to each other; a second switching transistor for connecting the bit lines to a transmission wire; a reading module including a first input terminal, a second input terminal, and a sampling input terminal, the first input terminal is connected to the transmission wire, the second input terminal is used to receive a reference voltage, and the sampling input terminal is used to receive a sampling signal; a signal generation module for generating a sampling signal according to a pre-charge voltage and a pre-charge signal, wherein the pre-charge signal is used to indicate pre-charging the transmission wire to the pre-charge voltage, and the length of the delay between the sampling signal and the pre-charge signal is positively correlated with the magnitude of the pre-charge voltage; when the sampling signal is a valid pulse, the reading module compares the input voltage at the first input terminal with the reference voltage to output the 1-bit data stored in the anti-fuse memory cell.

[0006] Compared with the related art, the sampling signal for data reading no longer uses a fixed signal, but generates a delay signal based on the pre-charge signal. There is a delay between the sampling signal and the pre-charge signal, and the magnitude of the delay is related to the pre-charge voltage. The larger the pre-charge voltage, the longer the time required for the anti-fuse memory cell to discharge the current. At this time, a larger delay is used to ensure that the anti-fuse memory cell has enough time to discharge the current; the smaller the pre-charge voltage, the shorter the time required for the anti-fuse memory cell to discharge the current. At this time, a smaller delay is used to ensure that the anti-fuse memory cell can read data faster. By flexibly setting the magnitude of the delay for generating the sampling signal based on the pre-charge signal, both the accuracy of data reading of the anti-fuse memory and the speed of data reading of the anti-fuse memory are ensured.

[0007] In addition, the reading module includes: a comparator, including a first input terminal, a second input terminal and an output terminal; a latching device, including a sampling input terminal and a data input terminal, and the data input terminal is connected to the output terminal of the comparator; the comparator is used to compare the input voltage of the first input terminal with a reference voltage, and the latching device is used to output 1-bit data stored in the anti-fuse memory cell.

[0008] In addition, the signal generation module includes: a signal delay unit, configured to receive the pre-charge signal and delay the pre-charge signal to output a charge delay signal; a pulse conversion unit, receiving the charge delay signal, generating a pulse signal based on the charge delay signal, and inputting the pulse signal as the sampling signal to the sampling input terminal.

[0009] In addition, the signal delay unit includes: a first current mirror, a second current mirror, a first MOS inverter and a second MOS inverter; the first end of the first current mirror is connected to the pre-charge voltage through an input resistor, and the second end is connected to the first end of the second current mirror; the first end of the second current mirror is connected to the pre-charge voltage through a constant current source, and the second end outputs the driving current of the first MOS inverter: the input terminal of the first MOS inverter is used to receive the pre-charge signal, and the output terminal is connected to the input terminal of the second MOS inverter; the output terminal of the second MOS inverter is used to output the charge delay signal. By using the second end of the first current mirror as a branch of the first end of the second current mirror, it is realized that the larger the pre-charge voltage connected to the first current mirror, the smaller the current at the second end of the second current mirror. And the current at the second end of the second current mirror is used as the driving current of the MOS inverter. The larger the driving current, the smaller the delay of the MOS inverter. On the contrary, the smaller the driving current, the larger the delay of the MOS inverter. Thus, it is realized that the larger the pre-charge voltage, the larger the delay of the generated sampling signal relative to the pre-charge signal.

[0010] In addition, the first MOS inverter includes a first NMOS transistor and a first PMOS transistor. The drain of the first NMOS transistor is connected to the drain of the first PMOS transistor. Among them, the gates of the first NMOS transistor and the first PMOS transistor are used to receive a pre-charge signal. The source of the first PMOS transistor is used to receive a pre-charge voltage. The source of the first NMOS transistor is used to receive the drive current output by the second current mirror. The second MOS inverter includes a second NMOS transistor and a second PMOS transistor. The drain of the second NMOS transistor is connected to the drain of the second PMOS transistor. Among them, the gates of the second NMOS transistor and the second PMOS transistor are connected to the drain of the first NMOS transistor. The source of the second PMOS transistor is used to receive a pre-charge voltage. The source of the second NMOS transistor is grounded.

[0011] In addition, the pulse conversion unit includes an inverter circuit including an odd number of serially connected inverters, and an input terminal for receiving a charge delay signal; an AND gate, one input terminal of which is connected to the output terminal of the inverter circuit, and the other input terminal of which is used to receive the charge delay signal, and is used to generate a pulse signal according to the charge delay signal and the charge delay signal after being delayed by the inverter circuit.

[0012] In addition, the odd number of serially connected inverters are 3 serially connected inverters.

[0013] In addition, the anti-fuse memory circuit further includes a voltage adjustment module including a voltage dividing circuit in which a plurality of resistors are connected in series. One end of the voltage dividing circuit is used to receive a pre-charge voltage, and the other end is grounded, and is used to generate a reference voltage after voltage division of the pre-charge voltage and input it to the second input terminal. By adjusting the reference voltage based on the pre-charge voltage through the voltage adjustment module, the accuracy of data reading of the anti-fuse memory is further ensured.

[0014] In addition, the reference voltage is 60% - 80% of the pre-charge voltage.

[0015] In addition, the gate of the first switching transistor is connected to the word line, and one end of the source or drain is connected to the anti-fuse memory cell, and the other end is connected to the bit line.

[0016] In addition, in the extending direction of the bit line, the bit lines are connected between every two first switching transistors through the same conducting wire. Connecting the bit lines between every two first switching transistors through the same conducting wire enables the structures of every two first switching transistors to share the source or drain during design, thereby reducing the layout area of the anti-fuse memory array or integrating more anti-fuse memory cells under the same area.

[0017] In addition, the gate of the second switching transistor is used to receive a column select signal. One end of the source or drain is connected to the bit line, and the other end is connected to a transmission wire. The column select signal is used to select and conduct the bit line connected to the selected first switching transistor.

[0018] In addition, the antifuse memory circuit further includes: a precharge MOS transistor, one end of the source or drain is used to receive a precharge voltage, the other end is connected to a transmission wire, and the gate is used to receive a precharge signal. The precharge MOS transistor is used to precharge the transmission wire to the precharge voltage according to the precharge signal.

[0019] In addition, the antifuse memory circuit further includes: a third switching transistor, one end of the source or drain is connected to the transmission wire, the other end is grounded, and the gate is used to receive a discharge signal, and is used to discharge the charge in the transmission wire according to the discharge signal. During the data programming stage of the antifuse memory array, the charge in the transmission wire is discharged through the third switching transistor to ensure the accuracy of data programming for the antifuse memory array.

[0020] In addition, the antifuse memory circuit further includes: a voltage stabilizing capacitor, one side electrode plate is connected to the transmission wire, and the other side electrode plate is grounded, and is used to stabilize the voltage of the transmission wire. Description of the Drawings

[0021] Figure 1 Schematic diagram of the circuit structure of the antifuse memory circuit provided by the embodiment of the present application;

[0022] Figure 2 Schematic diagram of the structure of the signal generation module provided by the embodiment of the present application;

[0023] Figure 3 Schematic diagram of the circuit structure of the signal delay unit provided by the embodiment of the present application;

[0024] Figure 4 Schematic diagram of the circuit structure of the pulse conversion unit provided by the embodiment of the present application;

[0025] Figure 5 Schematic diagram of the principle of generating a sampling signal by the pulse conversion unit provided by the embodiment of the present application;

[0026] Figure 6 Timing diagram of the antifuse memory circuit based on the signal generation module at different precharge voltages during the readout stage provided by the embodiment of the present application;

[0027] Figure 7 Schematic diagram of the circuit structure of the voltage adjustment module provided by the embodiment of the present application;

[0028] Figure 8 Timing diagram of the antifuse memory circuit based on the voltage adjustment module at different precharge voltages during the readout stage provided by the embodiment of the present application. Detailed Embodiments

[0029] The antifuse memory is implemented through an antifuse memory array. The antifuse memory array includes multiple antifuse memory cells. The gate oxide dielectric of the antifuse memory cell will break down after applying a high voltage. After breakdown, the impedance of the path decreases. Therefore, the information stored in the antifuse memory cell can be read by detecting the resistance state of the path after breakdown.

[0030] Specifically, in the readout stage, when the antifuse memory cell is broken down, the path impedance decreases. When this antifuse memory cell is activated by the bit line and the word line, it can quickly discharge the charge after precharging the transmission line, so that the data readout is at a low level. In addition, when the antifuse memory cell is not broken down, the path impedance is extremely large. When this antifuse memory cell is activated by the bit line and the word line, the discharge speed of the charge after precharging the transmission line is slow, so that the data readout is at a high level.

[0031] Therefore, when programming data in the antifuse memory, the antifuse memory cell that breaks down under the application of a high voltage is characterized as storing data "0", and the antifuse memory cell that is not applied with a high voltage is characterized as storing data "1".

[0032] However, due to a certain fluctuation in the internal power supply voltage V DD For example, the high voltage of V DD may reach 1.4V, while the low voltage may only reach 1.0V. And the internal power supply voltage V DD is used as the precharging voltage during data readout. At this time, if the reference voltage for data readout remains unchanged, it may cause that when V DD is at a high voltage, the antifuse memory cell that would originally output a low level finally reads a high level, resulting in a readout error.

[0033] To solve the above problems, an embodiment of the present application provides an anti-fuse memory circuit, including: a memory array including a plurality of anti-fuse memory cells, where the anti-fuse memory cells characterize the stored 1-bit data by whether the gate oxide layer is broken down; bit lines connected to the anti-fuse memory cells arranged in the extending direction of the bit lines, and the anti-fuse memory cells are electrically connected to the bit lines through first switching transistors; word lines connected to the first switching transistors arranged in the extending direction of the word lines, for turning on the selected first switching transistors according to a row selection signal, where the extending direction of the word lines and the extending direction of the bit lines are perpendicular to each other; a second switching transistor for connecting the bit lines to transmission wires; a reading module including a first input terminal, a second input terminal, and a sampling input terminal, where the first input terminal is connected to the transmission wires, the second input terminal is used to receive a reference voltage, and the sampling input terminal is used to receive a sampling signal; a signal generating module for generating a sampling signal according to a pre-charge voltage and a pre-charge signal, where the pre-charge signal is used to indicate pre-charging the transmission wires to the pre-charge voltage, and the delay between the sampling signal and the pre-charge signal is positively correlated with the magnitude of the pre-charge voltage; when the sampling signal is a valid pulse, the reading module compares the input voltage at the first input terminal with the reference voltage to output the 1-bit data stored in the anti-fuse memory cell.

[0034] Those of ordinary skill in the art can understand that in various embodiments of the present application, many technical details are proposed to help readers better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0035] Figure 1 is a schematic circuit diagram of the anti-fuse memory circuit provided in this embodiment, Figure 2 is a schematic structure diagram of the signal generating module provided in this embodiment, Figure 3 is a schematic circuit diagram of the signal delay unit provided in this embodiment, Figure 4 is a schematic circuit diagram of the pulse conversion unit provided in this embodiment, Figure 5 is a schematic diagram of the principle for the pulse conversion unit provided in this embodiment to generate a sampling signal, Figure 6 is a timing diagram of the anti-fuse memory circuit based on the signal generating module at different pre-charge voltages during the readout stage provided in this embodiment, Figure 7 is a schematic circuit diagram of the voltage adjustment module provided in this embodiment; Figure 8 is a timing diagram of the anti-fuse memory circuit based on the voltage adjustment module at different pre-charge voltages during the readout stage provided in this embodiment. The following further describes the anti-fuse memory circuit provided in this embodiment in detail with reference to the accompanying drawings, as follows:

[0036] Refer to Figure 1 , the anti-fuse memory circuit includes:

[0037] A storage array includes a plurality of antifuse storage cells FsBln01…FsBln0x, FsBln11…FsBln1x, FsBln21…FsBln2x, FsBln31…FsBln3x. The antifuse storage cells characterize the 1-bit data stored by whether the gate oxide layer is broken down.

[0038] It should be noted that, taking the antifuse storage cell characterized by "FsBln01" as an example, where "0" characterizes the 0th word line to which the antifuse storage cell is connected, and "1" characterizes the 1st bit line to which the antifuse storage cell is connected; taking the antifuse storage cell characterized by "FsBln2x" as an example, where "2" characterizes the 2nd word line to which the antifuse storage cell is connected, and "x" characterizes the xth bit line to which the antifuse storage cell is connected; in addition, in the description of this embodiment, if there is no digital suffix after the label of FsBln, it indicates that no specific antifuse storage cell is specified.

[0039] The bit line BL is connected to the antifuse storage cells FsBln arranged in the extending direction of the bit line BL. The antifuse storage cells FsBln are connected to the bit line BL through the first switching transistors 1Add. Specifically, the first switching transistors 1Add include: 1Add01…1Add0x, 1Add11…1Add1x, 1Add21…1Add2x, 1Add31…1Add3x.

[0040] It should be noted that, taking the first switching transistor characterized by "1Add01" as an example, where "01" characterizes the connection with the antifuse storage cell "FsBln01", that is, the first switching transistor 1Add01 serves as the switching transistor of the antifuse storage cell FsBln01; taking the first switching transistor characterized by "1Add2x" as an example, where "2x" characterizes the connection with the antifuse storage cell "FsBln2x", that is, the first switching transistor 1Add2x serves as the switching transistor of the antifuse storage cell FsBln2x; in addition, in the description of this embodiment, if there is no digital suffix after the label of 1Add, it indicates that no specific first switching transistor is specified.

[0041] The word line WL is connected to the first switching transistors 1Add arranged in the extending direction of the word line WL, and is used to turn on the selected first switching transistors 1Add according to the row selection signal. Among them, the extending direction of the bit line BL and the extending direction of the word line WL are perpendicular to each other; it should be noted that the row selection signal is the word line selection signal, which is used to select a target word line WL among many word lines WL and turn on the first switching transistors 1Add connected to the target word line WL.

[0042] Specifically, the gate of the first switching transistor 1Add is connected to the bit line BL, one end of the source or drain is connected to the antifuse storage cell FsBln, and the other end is connected to the bit line BL.

[0043] In this embodiment, in the extending direction of the bit line BL, two adjacent first switching transistors 1Add are connected to the bit line BL through the same conductive wire. Connecting the two adjacent first switching transistors 1Add to the bit line through the same conductive wire enables the source or drain of two adjacent first switching transistors 1Add to be shared during design, thereby reducing the layout area of the antifuse memory array or integrating more antifuse memory cells under the same area.

[0044] The second switching transistor 2Add is used to connect the bit line BL to the transmission wire 100.

[0045] The gate of the second switching transistor 2Add is used to receive the column strobe signal. One end of the source or drain is connected to the bit line BL, and the other end is connected to the transmission wire 100. The column strobe signal is used to select and conduct the bit line BL connected to the selected second switching transistor 2Add; it should be noted that the column strobe signal is the bit line strobe signal, which is used to select a target bit line BL from among a plurality of bit lines BL and conduct the second switching transistor 2Add connected to the target bit line BL.

[0046] Specifically, the second switching transistor 2Add includes: 2Add0…2Addx.

[0047] Taking the second switching transistor characterized by "2Add0" as an example, where "0" represents the connection to the first bit line, and the first bit line is connected to the antifuse memory cell "FsBlnz1" through the first switching transistor "1Addz1", where z is any integer from 0 to x; taking the second switching transistor characterized by "2Addx" as an example, where "x" represents the connection to the (x + 1)-th bit line, and the (x + 1)-th bit line is connected to the antifuse memory cell "FsBlnzx" through the first switching transistor "1Addzx", where z is any integer from 0 to x; in addition, in the description of this embodiment, if there is no numerical suffix after the label of 2Add, it indicates that a specific second switching transistor is not specified.

[0048] The reading module 102 includes a first input terminal +, a second input terminal -, and a sampling input terminal C. The first input terminal + is connected to the transmission wire 100, and the second input terminal - is used to receive the reference voltage V TRIP , and the sampling input terminal C is used to receive the sampling signal CLK.

[0049] The signal generation module 101 is used to generate the sampling signal CLK according to the precharge voltage V DD , and the precharge signal PRE. The precharge signal PRE is used to indicate precharging the transmission wire 100 to the precharge voltage V DD , and the delay between the sampling signal CLK and the precharge signal PRE is positively correlated with the voltage magnitude of the precharge voltage V DD .

[0050] In this embodiment, it further includes: a pre-charge MOS transistor, one end of the source or drain is used to receive a pre-charge voltage V DD , the other end is connected to a transmission wire 100, and the gate is used to receive a pre-charge signal PRE. The pre-charge MOS transistor is used to pre-charge the transmission wire 100 to the pre-charge voltage V DD .

[0051] When the sampling signal CLK is a valid pulse, the readout module 102 compares the input voltage V at the first input terminal + with a reference voltage V TRIP , so as to output 1-bit data stored in the selected anti-fuse memory cell FsBln

[0052] The working principle of the anti-fuse memory circuit provided in this embodiment will be described in detail below by taking the anti-fuse memory cells FsBln01 and FsBln11 as examples, specifically as follows:

[0053] In the data programming stage, a high voltage is applied to the anti-fuse memory cell FsBln01 to cause the gate oxide medium of the anti-fuse memory cell FsBln01 to break down. A low voltage or no voltage is applied to the anti-fuse memory cell FsBln11, and the gate oxide medium of the anti-fuse memory cell FsBln11 is not broken down.

[0054] In this embodiment, the anti-fuse memory circuit further includes: a third switching transistor 3Add, one end of the source or drain is connected to the transmission wire 100, the other end is grounded, and the gate is used to receive a discharge signal, and is used to discharge the charge in the transmission wire 100 according to the discharge signal.

[0055] Specifically, during the process of applying a high voltage to the anti-fuse memory cell FsBln01, the first switching transistor 1Add01, the second switching transistor 2Add1, and the third switching transistor 3Add are turned on, and the charge in the transmission wire 100 is discharged through the third switching transistor 3Add to ensure the accuracy of data programming for the anti-fuse memory cell FsBln01.

[0056] The read module 102 includes: a comparator 112, including a first input terminal +, a second input terminal -, and an output terminal. A latch device 122, including a sampling input terminal C and a data input terminal D, and the data input terminal D is connected to the output terminal of the comparator; the comparator 112 is used to compare the input voltage V at the first input terminal + with a reference voltage V TRIP , and the latch device 122 is used to output 1-bit data stored in the anti-fuse memory cell.

[0057] In the data readout stage, the third switching transistor 3Add is turned off, and the pre-charge MOS transistor receives the pre-charge signal PRE to conduct the source and drain. At this time, the transmission wire 100 is connected to the pre-charge voltage V DDconnected and thus pre-charged to a pre-charge voltage V DD .

[0058] When reading the data stored in the anti-fuse memory cell FsBln01, the gate oxide medium of the anti-fuse memory cell FsBln01 breaks down, and the impedance is very small. When the first switching transistor 1Add01 and the second switching transistor 2Add1 are turned on, the charge on the transmission wire 100 is discharged through the anti-fuse memory cell FsBln01, thereby quickly pulling down the input voltage V at the first input terminal +, making the input voltage V input at the first input terminal + less than the reference voltage V TRIP . When the sampling signal CLK is an effective pulse, at this time the reading module 102 outputs a low level, corresponding to the stored data "0".

[0059] When reading the data stored in the anti-fuse memory cell FsBln11, the gate oxide medium of the anti-fuse memory cell FsBln11 does not break down, and the impedance is extremely large. When the first switching transistor 1Add11 and the second switching transistor 2Add1 are turned on, the charge on the transmission wire 100 is discharged through the anti-fuse memory cell FsBln11 slowly, and cannot quickly pull down the input voltage V at the first input terminal +, making the input voltage V input at the first input terminal + still greater than the reference voltage V when the sampling signal CLK is an effective pulse TRIP . At this time, the reading module 102 outputs a high level, corresponding to the stored data "1".

[0060] It should be noted that in this embodiment, the first input terminal is used as the positive-phase input terminal of the comparator, and the second input terminal is used as the negative-phase input terminal of the comparator, which is only used to illustrate the anti-fuse memory circuit provided in this embodiment. In other embodiments, the second input terminal can receive the transmission wire, and the first input terminal receives the reference voltage. At this time, the gate oxide medium of the anti-fuse memory cell breaks down, and during the reading process, the reading module 102 outputs a high level corresponding to the stored data "0"; the gate oxide medium of the anti-fuse memory cell does not break down, and during the reading process, the reading module 102 outputs a low level corresponding to the stored data "1"; in addition, in this embodiment, the latching device 122 is described by taking a D flip-flop as an example, which is only used to illustrate the anti-fuse memory circuit provided in this embodiment. In other embodiments, the latching device can also be a latch.

[0061] In this embodiment, the sampling signal for data reading no longer uses a fixed signal, but a delay signal generated based on the pre-charge signal. There is a delay between the sampling signal and the pre-charge signal, and the magnitude of the delay is related to the pre-charge voltage. The larger the pre-charge voltage, the longer the time required for the anti-fuse memory cell to discharge the current. At this time, a larger delay is used to ensure that the anti-fuse memory cell has enough time to discharge the current; the smaller the pre-charge voltage, the shorter the time required for the anti-fuse memory cell to discharge the current. At this time, a smaller delay is used to ensure that the anti-fuse memory cell can read data faster.

[0062] Specifically, referring to Figure 2 , the signal generation module 101 includes: a signal delay unit 111, configured to receive the pre-charge signal PRE and delay the pre-charge signal to output a charge delay signal PRE_delay. A pulse conversion unit 121 receives the charge delay signal PRE_delay, generates a pulse signal based on the charge delay signal PRE_delay, and uses the pulse signal as the sampling signal CLK to input to the sampling input terminal C (refer to Figure 1 ).

[0063] Specifically, referring to Figure 3 , the signal delay unit 111 includes: a first current mirror 201, a second current mirror 202, a first MOS inverter 203, and a second inverter 204.

[0064] The first end of the first current mirror 201 is connected to the pre-charge voltage V through the input resistor R DD , and the second end is connected to the first end of the second current mirror 202.

[0065] The first stage of the second current mirror 202 is connected to the pre-charge voltage V through a constant current source DD , and the second end outputs the drive current of the first MOS inverter 203.

[0066] The input terminal of the first MOS inverter 203 is used to receive the pre-charge signal PRE, and the output terminal is connected to the input terminal of the second MOS inverter 204.

[0067] Specifically, the first MOS inverter 203 includes: a first NMOS transistor and a first PMOS transistor. The drain of the first NMOS transistor and the drain of the first PMOS transistor are connected and used as the output terminal of the first MOS inverter. Among them, the gates of the first NMOS transistor and the first PMOS transistor are used to receive the pre-charge signal PRE, the source of the first PMOS transistor is used to receive the pre-charge voltage V DD , and the source of the first NMOS transistor is used to receive the drive current output by the second current mirror 202.

[0068] The output terminal of the second MOS inverter 204 is used to output the charge delay signal PRE_delay.

[0069] Specifically, the second MOS inverter 204 includes: a second NMOS transistor and a second PMOS transistor. The drains of the second NMOS transistor and the second PMOS transistor are connected and serve as the output terminal of the second MOS inverter. Among them, the gates of the second NMOS transistor and the second PMOS transistor are connected to the drain of the first NMOS transistor, and the source of the second PMOS transistor is used to receive the pre-charge voltage V DD , and the source of the second NMOS transistor is grounded.

[0070] Due to the function of the current mirror, the input current at the first end is equal to the input current at the second end. For the first current mirror: the current I1 at the first end = (V DD - V DS ) / R, and the current I2 at the second end = I1. For the second current mirror: the current I3 at the first end = I - I1, and the current I4 at the second end = I3 = I - (V DD - V DS ) / R. Among them, the current I generated by the constant current source is a fixed value, the source-drain voltage V DS of the MOS transistor is equal to the gate-drain voltage V GS , which is a fixed value, and the resistor R is a fixed value. Thus, it can be known that the drive current I4 of the first MOS inverter 203 is negatively correlated with V DD , that is, the larger V DD is, the smaller I4 is; the smaller V DD is, the larger I4 is.

[0071] For a MOS inverter, the larger the drive current is, the smaller the delay of signal inversion is, and the smaller the drive current is, the larger the delay of signal inversion is. Thus, it can be known that the delay of the charge delay signal PRE_delay generated after delaying the pre-charge signal PRE by the first MOS inverter 203 and the second MOS inverter 204 is positively correlated with the pre-charge voltage V DD , that is, the larger V DD is, the larger the delay of the charge delay signal PRE_delay relative to the pre-charge signal PRE is; the smaller V DD is, the smaller the delay of the charge delay signal PRE_delay relative to the pre-charge signal PRE is.

[0072] Referring to Figure 4 , the pulse conversion unit 121 includes:

[0073] An inverting circuit 205, including an odd number of cascaded inverters, and the input terminal is used to receive the charge delay signal PRE_delay.

[0074] The AND gate 206 has one input terminal connected to the output terminal of the inverter circuit 205, and the other input terminal is used to receive the charge delay signal PRE_delay, and is used to generate a pulse signal, that is, the sampling signal CLK, according to the charge delay signal PRE_delay and the charge delay signal PRE_delay2 after being delayed by the inverter circuit 205.

[0075] The AND gate 206 in the figure is formed by a NAND gate and an inverter. The reason is that the logic gates usually integrated in the chip are NAND gates. In other embodiments, a logic gate structure of an AND gate can also be directly used to replace Figure 4 the connection structure of the NAND gate and the inverter shown in

[0076] In this embodiment, the number of serially connected odd-stage inverters is 3 inverters. It should be noted that in other embodiments, the number of serially connected odd-stage inverters is 1 inverter, or 5 inverters, etc.

[0077] Reference Figure 5 , the signal delay unit 111 delays the precharge signal PRE to generate the charge delay signal PRE_delay. The odd number of inverters in the pulse conversion unit 121 invert and slightly delay the charge delay signal PRE_delay to obtain the signal PRE_delay2, and the square wave part of the charge delay signal PRE_delay and the signal PRE_delay2 are staggered. At this time, after passing through the AND gate 206, the parts with the same height of the staggered square waves generate a pulse, that is, the sampling signal CLK.

[0078] Reference Figure 6 , when the precharge voltage V DD is normal, the sampling signal generated according to the precharge signal PRE is CLK2; when the precharge voltage V DD is a high voltage, the sampling signal generated according to the precharge signal PRE is CLK3, that is, the effective pulse of the sampling signal is shifted backward to ensure that the antifuse storage unit FsBln has enough time to discharge the charge on the transmission wire 100 after precharging to a higher voltage; when the precharge voltage V DD is a low voltage, the sampling signal generated according to the precharge signal PRE is CLK1, that is, the effective pulse of the sampling signal is shifted forward to ensure that the antifuse storage unit FsBln can read data faster.

[0079] In another example, reference Figure 7 , the antifuse storage unit further includes: a voltage adjustment module, including a voltage dividing circuit in which a plurality of resistors are connected in series. One end of the voltage dividing circuit is used to receive the precharge voltage V DD , and the other end is grounded, and is used to generate a reference voltage V DD after voltage division of the precharge voltage V TRIP and input it to the second input terminal-.

[0080] In this embodiment, the multiple series voltage dividing resistors are respectively R1, R2, R3, R4, and R5, where (R3 + R4 + R5) / (R1 + R2 + R3 + R4 + R5) = 60% - 80%, thereby ensuring that the generated reference voltage V TRIP is 60% - 80% of the pre-charge voltage V DD . In other embodiments, those skilled in the art can set the percentage between the reference voltage V TRIP and the pre-charge voltage V TRIP according to the specifically required reference voltage V DD .

[0081] The voltage adjustment module adjusts the reference voltage V DD based on the pre-charge voltage V TRIP , further ensuring the accuracy of the anti-fuse memory data reading.

[0082] In other embodiments, only by using the voltage adjustment module and discarding the signal generation module, the accuracy of the anti-fuse memory data reading can also be ensured. Refer to Figure 8 . When there is a voltage adjustment module, the generated reference voltage V TRIP fluctuates with the pre-charge voltage V DD . When the pre-charge voltage V DD increases, the reference voltage V TRIP also increases, thereby ensuring that when the effective pulse of the sampling signal CLK arrives, the anti-fuse memory cell FsBln has enough time to discharge the charge on the transmission wire 100, so that the voltage on the transmission wire 100 drops to the reference voltage V TRIP . When the pre-charge voltage V DD decreases, the reference voltage V TRIP also decreases, thereby ensuring that when the effective pulse of the sampling signal CLK arrives, the anti-fuse memory cell FsBln has enough time to discharge the charge on the transmission wire 100, so that the voltage on the transmission wire 100 drops to the reference voltage V TRIP .

[0083] Continue to refer to Figure 1 . In this embodiment, the anti-fuse memory circuit further includes: a voltage stabilizing capacitor Cap, one side electrode plate is connected to the transmission wire 100, and the other side electrode plate is grounded, which is used to stabilize the voltage of the transmission wire 100 and prevent the voltage of the transmission wire 100 from jumping.

[0084] Compared with the related art, the sampling signal for data reading no longer uses a fixed signal, but a delay signal generated based on a pre-charge signal. There is a delay between the sampling signal and the pre-charge signal, and the magnitude of the delay is related to the pre-charge voltage. The larger the pre-charge voltage, the longer the time required for the anti-fuse memory cell to discharge the current. At this time, a larger delay is used to ensure that the anti-fuse memory cell has enough time to discharge the current; the smaller the pre-charge voltage, the shorter the time required for the anti-fuse memory cell to discharge the current. At this time, a smaller delay is used to ensure that the anti-fuse memory cell can read data faster. By flexibly setting the magnitude of the delay of the sampling signal generated based on the pre-charge signal, both the accuracy of data reading of the anti-fuse memory and the speed of data reading of the anti-fuse memory are ensured.

[0085] It is worth mentioning that each unit involved in this embodiment is a logic unit. In practical applications, a logic unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, to highlight the innovative part of this application, units that are not closely related to solving the technical problems proposed in this application are not introduced in this embodiment, but this does not mean that there are no other units in this embodiment.

[0086] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing this application. In practical applications, various changes can be made in form and details without departing from the spirit and scope of this application.

Claims

1. An anti-fuse memory circuit, characterized in that, Comprising: A storage array, including a plurality of antifuse storage cells, where the antifuse storage cells characterize the stored 1-bit data by whether the gate oxide layer is broken down; Bit lines, connecting the antifuse storage cells arranged in the extending direction of the bit lines, and the antifuse storage cells are electrically connected to the bit lines through first switching transistors; Word lines, connecting the first switching transistors arranged in the extending direction of the word lines, for turning on the selected first switching transistors according to a row selection signal, where the extending direction of the bit lines and the extending direction of the word lines are perpendicular to each other; Second switching transistors, for connecting the bit lines to transmission conductors; A reading module, including a first input terminal, a second input terminal, and a sampling input terminal, where the first input terminal is connected to the transmission conductor, the second input terminal is used to receive a reference voltage, and the sampling input terminal is used to receive a sampling signal; A signal generation module, for generating the sampling signal according to a pre-charge voltage and a pre-charge signal, where the pre-charge signal is used to indicate pre-charging the transmission conductor to the pre-charge voltage, and the delay length between the sampling signal and the pre-charge signal is positively correlated with the voltage magnitude of the pre-charge voltage; When the sampling signal is a valid pulse, the reading module compares the input voltage at the first input terminal with the reference voltage to output the 1-bit data stored in the antifuse storage cell.

2. The anti-fuse memory circuit according to claim 1, wherein The reading module includes: A comparator, including the first input terminal, the second input terminal, and an output terminal; A latch device, including the sampling input terminal and a data input terminal, and the data input terminal is connected to the output terminal of the comparator; The comparator is used to compare the input voltage at the first input terminal with the reference voltage, and the latch device is used to output the 1-bit data stored in the antifuse storage cell.

3. The anti-fuse memory circuit according to claim 2, wherein The signal generation module includes: A signal delay unit, for receiving the pre-charge signal and delaying the pre-charge signal to output a charge delay signal; A pulse conversion unit, receiving the charge delay signal, generating a pulse signal based on the charge delay signal, and inputting the pulse signal as the sampling signal to the sampling input terminal.

4. The anti-fuse memory circuit according to claim 3, characterized in that, The signal delay unit includes: a first current mirror, a second current mirror, a first MOS inverter, and a second MOS inverter; The first end of the first current mirror is connected to the pre-charge voltage through an input resistor, and the second end is connected to the first end of the second current mirror; The first end of the second current mirror is connected to the pre-charge voltage through a constant current source, and the second end outputs the drive current of the first MOS inverter; The input terminal of the first MOS inverter is used to receive the pre-charge signal, and the output terminal is connected to the input terminal of the second MOS inverter; The output terminal of the second MOS inverter is used to output the charge delay signal.

5. The anti-fuse memory circuit according to claim 4, wherein Comprising: The first MOS inverter includes: a first NMOS transistor and a first PMOS transistor. The drains of the first NMOS transistor and the first PMOS transistor are connected. Among them, the gates of the first NMOS transistor and the first PMOS transistor are used to receive the pre-charge signal. The source of the first PMOS transistor is used to receive the pre-charge voltage. The source of the first NMOS transistor is used to receive the drive current output by the second current mirror. The second MOS inverter includes: a second NMOS transistor and a second PMOS transistor. The drains of the second NMOS transistor and the second PMOS transistor are connected. Among them, the gates of the second NMOS transistor and the second PMOS transistor are connected to the drain of the first NMOS transistor. The source of the second PMOS transistor is used to receive the pre-charge voltage. The source of the second NMOS transistor is grounded.

6. The anti-fuse memory circuit according to claim 3, wherein The pulse conversion unit includes: An inverter circuit, including an odd number of cascaded inverters, and the input terminal is used to receive the charge delay signal. An AND gate, one input terminal is connected to the output terminal of the inverter circuit, and the other input terminal is used to receive the charge delay signal, and is used to generate the pulse signal according to the charge delay signal and the charge delay signal after being delayed by the inverter circuit.

7. The anti-fuse memory circuit according to claim 6, wherein The cascaded odd number of inverters are 3 cascaded inverters.

8. The antifuse memory circuit according to claim 1, wherein It further includes: A voltage adjustment module, including a voltage dividing circuit in which a plurality of resistors are connected in series. One end of the voltage dividing circuit is used to receive the pre-charge voltage, and the other end is grounded, and is used to generate the reference voltage after voltage division of the pre-charge voltage and input it to the second input terminal.

9. The anti-fuse memory circuit according to claim 8, wherein The reference voltage is 60% - 80% of the pre-charge voltage.

10. The anti-fuse memory circuit according to claim 1, wherein The gate of the first switching transistor is connected to the word line, and one end of the source or drain is connected to the anti-fuse storage unit, and the other end is connected to the bit line.

11. The anti-fuse memory circuit according to claim 10, wherein In the extending direction of the bit line, two adjacent first switching transistors are connected to the bit line through the same conductive wire.

12. The anti-fuse memory circuit according to claim 1, characterized in that, The gate of the second switching transistor is used to receive the column select signal. One end of the source or drain is connected to the bit line, and the other end is connected to the transmission wire. The column select signal is used to selectively conduct the bit line connected to the selected first switching transistor.

13. The anti-fuse memory circuit according to claim 1, wherein It further includes: A pre-charge MOS transistor, one end of the source or drain is used to receive the pre-charge voltage, the other end is connected to the transmission wire, and the gate is used to receive the pre-charge signal. The pre-charge MOS transistor is used to pre-charge the transmission wire to the pre-charge voltage according to the pre-charge signal.

14. The anti-fuse memory circuit according to claim 1, wherein It further includes: a third switching transistor, one end of the source or drain is connected to the transmission wire, the other end is grounded, and the gate is used to receive the discharge signal, and is used to discharge the charge in the transmission wire according to the discharge signal.

15. The anti-fuse memory circuit according to claim 1, wherein, It further includes: A voltage stabilizing capacitor, one side electrode plate is connected to the transmission wire, and the other side electrode plate is grounded, and is used to stabilize the voltage of the transmission wire.

Images