Method for manufacturing a fe-dsos wafer and fe-dsos device

Abstract

The application discloses a preparation method of FE-DSOI wafers and FE-DSOI devices, and the method comprises the following steps: providing a plurality of original wafers; preparing a bottom wafer by using the original wafers; depositing ferroelectric material on the surface of the bottom wafer to obtain a bottom wafer containing ferroelectric material; performing thermal oxidation treatment on the original wafers to obtain a top wafer; and performing bonding and layer transfer treatment on the top wafer and the bottom wafer containing ferroelectric material, so as to obtain FE-DSOI wafers containing ferroelectric material and double buried oxide silicon. By using the application, the technical problems that the conventional DSOI does not have back gate regulation capability and cannot inhibit threshold voltage drift when no back gate voltage is continuously applied in the prior art can be solved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for preparing a silicon-on-insulator (FE-DSOI) wafer containing ferroelectric materials and an FE-DSOI device. Background Technology

[0002] Double silicon on insulator (DSOI) has independent back-gate regulation capability, which can suppress threshold voltage drift caused by total dose irradiation. For example, the threshold voltage Vt of an N-channel device under irradiation conditions... th Decrease.

[0003] However, in practice, it has been found that the back-gate regulation capability of DSOI is limited, requiring a continuous external back-gate bias voltage or the design of a back-bias circuit to achieve back-gate regulation. In other words, traditional DSOI requires a continuously applied back-gate (bias) voltage to suppress threshold voltage drift; without a back-gate voltage, the DSOI lacks back-gate regulation capability and cannot suppress threshold voltage drift. Therefore, traditional DSOI back-gate regulation has significant limitations. Thus, it is necessary to design a DSOI wafer or device structure that can achieve back-gate regulation capability without the need for a continuously applied back-gate voltage. Summary of the Invention

[0004] This application provides a method for fabricating a silicon-on-a-chip (FE-DSOI) wafer containing ferroelectric materials and an FE-DSOI device, which solves the technical problem in the prior art that traditional DSOIs do not have back-gate regulation capability and cannot suppress threshold voltage drift when a back-gate voltage is not continuously applied.

[0005] On one hand, this application provides a method for preparing a silicon-on-a-metal (FE-DSOI) wafer containing ferroelectric materials through one embodiment of the application, the method comprising:

[0006] Provides multiple original wafers;

[0007] The underlying wafer is prepared using the original wafer;

[0008] Ferroelectric material is deposited on the surface of the bottom wafer to obtain a bottom wafer containing ferroelectric material;

[0009] The original wafer is subjected to thermal oxidation to obtain the top layer wafer;

[0010] The top wafer and the bottom wafer containing ferroelectric material are bonded and layer transferred to obtain a silicon-on-insulator (FE-DSOI) wafer containing ferroelectric material.

[0011] Optionally, the step of preparing the underlying wafer using the original wafer includes:

[0012] The original wafer is subjected to thermal oxidation and hydrogen implantation to obtain a processed wafer;

[0013] The processed wafer is flipped over and bonded to the original wafer to obtain a merged wafer;

[0014] The excess upper-layer wafer on the merged wafer is cut using the Smartcut process to obtain the cut-remaining wafer;

[0015] The original wafer is bonded to the surface of the cut remaining wafer to obtain a multilayer wafer;

[0016] The multilayer wafer is subjected to top silicon oxidation treatment to obtain the treated bottom wafer.

[0017] Optionally, the thermal oxidation treatment of the original wafer to obtain the top layer wafer includes:

[0018] The original wafer is subjected to thermal oxidation treatment to obtain a thermally oxidized wafer;

[0019] The thermally oxidized wafer is subjected to hydrogen implantation to obtain the top layer wafer.

[0020] Optionally, the bonding and layer transfer process performed on the top wafer and the bottom wafer containing the ferroelectric material to obtain a silicon-on-insulator (FE-DSOI) wafer containing the ferroelectric material includes:

[0021] After flipping the top wafer, it is bonded to the top ferroelectric material in the bottom wafer containing ferroelectric material to obtain a bonded wafer.

[0022] The excess upper layer wafer on the bonding wafer is cut or transferred using a Smartcut process to produce a silicon-on-insulator (FE-DSOI) wafer containing ferroelectric materials.

[0023] Optionally, the ferroelectric material-containing double buried oxide silicon-on-insulator (FE-DSOI) wafer comprises, from bottom to top: a silicon substrate, a first buried oxide layer (BOX1), a back gate, a second buried oxide layer (BOX2), ferroelectric material HZO, and silicon-on-insulator (SOI). The silicon substrate is the original wafer, the silicon-on-insulator (SOI) is the top layer wafer after bonding and layer transfer processing, and the first and second buried oxide layers are intermediate wafers prepared from the original wafer.

[0024] Optionally, the method further includes:

[0025] Ferroelectric back-biased silicon-on-insulator (FE-DSOI) devices were fabricated on the ferroelectric material-containing double buried oxygen insulator silicon-on-insulator wafer.

[0026] Optionally, the ferroelectric material possesses remanent polarization characteristics, and the method further includes:

[0027] By utilizing the residual polarization characteristics of the ferroelectric material, back-gate modulation is performed on the FE-DSOI device to suppress the threshold voltage drift of the FE-DSOI device.

[0028] On the other hand, through one embodiment of this application, a ferroelectric back-biased silicon-on-insulator (FE-DSOI) device is provided. The FE-DSOI device is fabricated on a silicon-on-insulator (FE-DSOI) wafer containing ferroelectric material using a preset device fabrication process. The FE-DSOI wafer is fabricated using the fabrication method for silicon-on-insulator (FE-DSOI) wafer containing ferroelectric material as described above.

[0029] Optionally, the FE-DSOI device has residual polarization characteristics, and these residual polarization characteristics are independent of the back gate voltage applied to the FE-DSOI device and the preset total dose irradiation.

[0030] Optionally, the FE-DSOI device supports back-gate modulation using the residual polarization characteristics of the ferroelectric material to suppress threshold voltage drift of the FE-DSOI device.

[0031] One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages: This application provides multiple raw wafers, and uses the raw wafers to prepare a bottom wafer; ferroelectric material is deposited on the surface of the bottom wafer to obtain a bottom wafer containing ferroelectric material; the raw wafers are subjected to thermal oxidation treatment to obtain a top wafer; the top wafer and the bottom wafer containing ferroelectric material are bonded and layer transferred to obtain a silicon-on-insulator (FE-DSOI) wafer containing ferroelectric material. Optionally, an FE-DSOI device (also known as a metal-oxide-semiconductor field-effect transistor) can be prepared based on this FE-DSOI wafer. This utilizes the residual polarization characteristics of ferroelectric materials to continue providing back-gate regulation capability even when the back-gate voltage or ambient electric field is disconnected, effectively suppressing the threshold voltage drift problem of the device. This solves the problem in the prior art that traditional DSOI devices require a continuous back-gate voltage to perform back-gate regulation and adjust the threshold voltage. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic flowchart of a method for fabricating an FE-DSOI wafer provided in an embodiment of this application.

[0034] Figure 2 This is a schematic diagram of an FE-DSOI wafer fabrication process provided in an embodiment of this application.

[0035] Figure 3 This is a schematic diagram of the structure of an FE-DSOI device provided in an embodiment of this application.

[0036] Figure 4 This is a schematic diagram of a simulation scenario of the hysteresis characteristics of a ferroelectric material provided in an embodiment of this application.

[0037] Figure 5 This is a schematic diagram of the hysteresis characteristic curve of a ferroelectric material provided in an embodiment of this application.

[0038] Figure 6 This is a schematic diagram of the structure of a conventional DSOI device provided in an embodiment of this application.

[0039] Figure 7 This application provides embodiments of the current transfer characteristics (I) of a conventional DSOI device and an FE-DSOI device. d -V g (Illustrated diagram of the fitted curve)

[0040] Figure 8 This is a schematic diagram comparing the back gate adjustment capabilities of a traditional DSOI device and an FE-DSOI device, provided in an embodiment of this application.

[0041] Figure 9 This is a schematic diagram of a simulation setting scenario corresponding to the back gate adjustment capability of an FE-DSOI device provided in the embodiments of this application.

[0042] Figure 10 This application provides an embodiment of the current transfer characteristics (I) of an FE-DSOI device under a specific back gate voltage pulse. d -V g (Curve diagram)

[0043] Figure 11This application provides an embodiment of the current transfer characteristics (I) of an FE-DSOI device under different back-gate voltage pulse durations. d -V g (Curve diagram)

[0044] Figure 12 This is a schematic diagram of the residual polarization characteristic curves of an FE-DSOI device under different back gate voltage pulse durations, provided in an embodiment of this application. Detailed Implementation

[0045] In the process of filing this application, the applicant discovered that as early as 2011, HZO (hafnium zirconium oxide), specifically a HfO2-ZrO2 solid solution, a ferroelectric material, emerged. This ferroelectric material, with good compatibility with silicon (Si) processes, solved a series of problems associated with traditional perovskite iron materials. Ferroelectric materials are widely used in ferroelectric-gate field-effect transistors (FeFETs). FeFETs utilize the unique electrical properties of ferroelectric materials, allowing them to remain on even after the gate voltage is removed. Leveraging this characteristic, future computers using FeFETs can retain their state before power-off, due to the remanent polarization capability of ferroelectric materials. Ferroelectric materials are a class of materials with spontaneous polarization, which can flip under an applied electric field. Even after the applied electric field disappears, a portion of the spontaneous polarization remains, known as remanent polarization. Therefore, FeFETs can remain on even after the gate voltage is removed.

[0046] To address the technical challenge of traditional DSOI devices lacking back-gate regulation capability when no back-gate voltage is continuously applied, inspired by the gate control characteristics of FeFETs, a layer of ferroelectric material (such as HZO) can be introduced into the middle of the buried oxide layer BOX1 of the DSOI. Based on the principle of DSOI devices, the threshold voltage can be adjusted by applying a back-gate voltage to the back gate. Due to the introduction of HZO ferroelectric material, a voltage pulse can be applied to the back gate; because the HZO ferroelectric material becomes polarized under the pulse and retains residual polarization when no voltage is applied, the back gate still maintains regulation capability even without a back-gate voltage.

[0047] To achieve the above objectives, this application, based on existing DSOI processes and a technology-aided design (TCAD) simulation platform, compares the back-gate regulation capability of existing DSOI with that of DSOI incorporating HZO ferroelectric materials. Furthermore, the simulation-based method verifies the feasibility of maintaining the back-gate regulation mechanism using the residual polarization characteristics of the ferroelectric material. Based on an example of existing HZO and Si process compatibility, the fabrication process of silicon-on-feed (FE-DSOI) wafers containing ferroelectric materials on a double buried oxide insulator is illustrated, enabling the fabrication of FE-DSOI devices (i.e., MOS devices) on the fabricated wafers.

[0048] This application provides a method for fabricating a silicon-on-a-chip (FE-DSOI) wafer containing ferroelectric materials and an FE-DSOI device, which solves the technical problem in the prior art that traditional DSOIs do not have back-gate regulation capability and cannot suppress threshold voltage drift when a back-gate voltage is not continuously applied.

[0049] The technical solution of this application embodiment is to solve the above-mentioned technical problems. The overall idea is as follows: providing multiple raw wafers; performing multi-process processing on the raw wafers to obtain a bottom wafer; depositing a layer of ferroelectric material on the surface of the bottom wafer to obtain a bottom wafer containing ferroelectric material; performing thermal oxidation treatment on one of the raw wafers to obtain a top wafer; performing bonding and layer transfer treatment on the top wafer and the bottom wafer containing ferroelectric material to obtain a silicon-on-insulator (FE-DSOI) wafer containing ferroelectric material.

[0050] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0051] First, it should be clarified that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0052] Please see Figure 1 This is a schematic flowchart illustrating a method for fabricating an FE-DSOI wafer according to an embodiment of this application. Figure 1 The method shown includes the following implementation steps:

[0053] S101 provides multiple raw wafers.

[0054] S102. A bottom layer wafer is prepared using the original wafer. Specifically, a portion of the original wafer can be processed using a multi-process method to obtain the bottom layer wafer.

[0055] In one specific embodiment, please refer to Figure 2 A schematic diagram of a process flow for FE-DSOI wafer fabrication is shown. Figure 2 In this application, a raw wafer 201 (e.g., a silicon wafer) is first thermally oxidized, and then hydrogen is implanted to obtain a processed wafer 202. The processed wafer 202 is then flipped and bonded to another raw wafer 201 to obtain a merged wafer 203. Excess upper-layer wafers on the merged wafer 203 are removed using a Smartcut process (i.e., the merged wafer 203 is diced or layer-transferred) to obtain a diced wafer 204. A layer of raw wafer 201 is then bonded or grown on the surface of the diced wafer 204 to obtain a multilayer wafer 205. Finally, a top-layer silicon oxidation process is performed on the multilayer wafer 205 to obtain a processed bottom-layer wafer 206.

[0056] S103. Deposit one or more layers of ferroelectric material on the surface of the bottom wafer to obtain a bottom wafer containing ferroelectric material.

[0057] S104. Perform thermal oxidation treatment on the original wafer to obtain a top layer wafer.

[0058] Optionally, this application can use magnetron sputtering technology to deposit a layer of ferroelectric material (HZO) on the silicon oxide (SiO2) surface of the bottom wafer 206 to obtain a bottom wafer 207 containing ferroelectric material. Then, another original wafer 201 (silicon wafer) is used to perform the same thermal oxidation treatment, and optionally, hydrogen implantation treatment can be performed, whereby hydrogen implantation is for subsequent layer transfer processing, thereby obtaining a top wafer 208.

[0059] S105. The top wafer and the bottom wafer containing ferroelectric material are bonded and transferred to obtain a silicon-on-insulator (FE-DSOI) wafer containing ferroelectric material.

[0060] Finally, as Figure 2 As shown, this application allows for the flipping of the top wafer 208, followed by bonding the silicon oxide (SiO2) of the top wafer 207 to the top HZO of the bottom wafer 207 containing ferroelectric material HZO, resulting in a bonded wafer 209. Further, a Smartcut process is used to cut away the excess upper wafer on the bonded wafer 209, thus fabricating a DSOI wafer 210 incorporating ferroelectric HZO material, i.e., a ferroelectric double buried oxide insulator-on-silicon (FE-DSOI) wafer 210.

[0061] Alternatively, this application can also fabricate FE-DSOI devices on the FE-DSOI wafer 210. Specifically, this application can use a preset device fabrication process to fabricate devices on the FE-DSOI wafer to obtain ferroelectric back-biased double buried oxide insulator-on-silicon FE-DSOI devices. The device fabrication process used for FE-DSOI device fabrication can be referenced from the existing MOS device fabrication process, and will not be detailed in this application.

[0062] Further optional, such as Figure 2 A schematic cross-sectional view of the FE-DSOI wafer is also shown, which can be simply referred to as a cross-sectional view of the FE-DSOI wafer. Figure 2 The layers shown in the cross-sectional view, from bottom to top, are: silicon substrate (Sub), second buried oxide layer BOX2, back gate, first buried oxide layer BOX1, and ferroelectric material HZO and silicon-on-insulator (SOI) added to the first buried oxide layer BOX1.

[0063] Please see also Figure 3 This is a schematic diagram of the structure of an FE-DSOI device fabricated on an FE-DSOI wafer, provided in an embodiment of this application. Figure 3 The FE-DSOI device shown includes: a silicon substrate (Sub) 301, a second buried oxide layer BOX 2 302, a back gate 303, a first buried oxide layer BOX 1 304, a ferroelectric material HZO 305 incorporated into the first buried oxide layer BOX 1, silicon-on-insulator SOI 306, a gate dielectric 307, and a gate electrode 308. Figure 3 The silicon substrate (Sub) 301, the second buried oxide layer BOX2 302, the back gate 303, the first buried oxide layer BOX1 304, the ferroelectric material HZO 305 added to the first buried oxide layer BOX1, and the silicon-on-insulator (SOI) 306 involved are all related to Figure 2 The layer structure corresponding to the FE-DSOI wafer cross-section shown is not described in detail here.

[0064] The following describes embodiments of this application that compare the back-gate control capability of existing DSOI processes with that of DSOI processes incorporating ferroelectric material HZO, based on existing DSOI technology and a TCAD simulation platform, and verify the feasibility of using simulation methods to maintain back-gate control capability using ferroelectric remanent polarization characteristics. Please refer to... Figure 4 and Figure 5 This paper presents a simulation of the hysteresis curve of the ferroelectric material HZO and a schematic diagram of the hysteresis characteristic curve obtained from the simulation. Figure 4 The diagram shows a simulation of the ferroelectric material HZO. Using a simulation method with parameters set to the hysteresis characteristics of HZO, a preset scanning voltage (e.g., (0V, 4V, -4V, 4V)) is applied to the medium to obtain results. Figure 5The hysteresis characteristic curve is shown below. Figure 5 The hysteresis phenomenon of HZO can be observed on the curve shown, and this hysteresis phenomenon can then be used for subsequent simulations.

[0065] Please see Figure 6 This is a schematic diagram of the structure of a conventional DSOI device provided in an embodiment of this application. Figure 6 The DSOI device shown includes a silicon substrate (Sub) 601, a second buried oxide layer BOX2 602, a back gate 603, a first buried oxide layer BOX1 604, silicon-on-insulator (SOI) 605, a gate dielectric 606, and a gate electrode 607. For example... Figure 6 The provided DSOI device is fabricated using the following layer parameters: gate dielectric t ox = 4.5nm, top silicon length L tot =1μm, gate length L g =0.2μm, top silicon thickness t soi1 =0.8μm, BOX1 thickness t BOX1 =0.16μm, BOX2 thickness t BOX2 =0.15μm, back gate thickness t soi2 =0.08μm.

[0066] based on Figure 6 The conventional DSOI device structure shown in this application introduces ferroelectric material into the BOX1 layer, that is, a portion of the BOX1 layer is replaced with HZO ferroelectric material, thereby obtaining the structure shown in the traditional application. Figure 3 The FE-DSOI device shown is fabricated using the following parameters: gate dielectric t ox = 4.5nm, top silicon length L tot =1μm, gate length L g =0.2μm, top silicon thickness t soi1 =0.8μm, HZO thickness t FE =0.1μm, total thickness t of BOX1 BOX1 =0.069μm (including the thickness of the two BOX1 portions separated by HZO), BOX2 thickness t BOX2 =0.15μm, back gate thickness t soi2 =0.08μm.

[0067] against Figure 3 and Figure 6 For the DSOI and FE-DSOI devices shown respectively, in TCAD simulation, by adjusting the thickness of the BOX1 layer and the ferroelectric material, the I of the FE-DSOI device with introduced ferroelectric material is... d -V g Characteristics (current transfer characteristics) compared to traditional DSOI devices d -V gThe characteristics are fitted to obtain, as follows Figure 7 The traditional DSOI device and the FE-DSOI device shown have I d -V g Characteristic fitting curve. The horizontal axis in the figure represents the device gate voltage V. g The vertical axis represents the device gate current I. d To compare the effect of the FE-DSOI device structure on back-gate modulation without considering ferroelectric remanent polarization, this application uses TACD simulations to obtain... Figure 7 The DSOI device and the FE-DSOI device shown have I d -V g The characteristic fitting curves, as shown in the figure, reveal the differences in Ig between the DSOI device and the FE-DSOI device before and after total dose irradiation. d -V g The characteristic curves are not affected by whether or not ferroelectric HZO material is added.

[0068] Please see Figure 8 This is a comparative schematic diagram of the back-gate adjustment capabilities of DSOI and FE-DSOI devices provided in an embodiment of this application. Figure 8 As shown, curves 1 and 2 illustrate the I values ​​of the DSOI device before and after total dose irradiation. d -V g Characteristic curves Figure 3 and Figure 4 This shows the I of the FE-DSOI device before and after total dose irradiation. d -V g Characteristic curve. Specifically, in TCAD, the total dose is set to 2.8e within a preset duration (e.g., 1-11 seconds). 8 The total dose irradiation environment; during irradiation, a back gate voltage of -5V is simultaneously applied to the back gate of both the DSOI device and the FE-DSOI device. In this embodiment, the device drain voltage is set to 0.9V, and a scanning voltage from -1V to 6V is applied to the front gate (gate). Measurements are obtained as follows. Figure 7 The I shown d -V g Characteristic curves. For example... Figure 7 The curves shown can be used to compare the back-gate tuning capabilities of the two devices. With essentially the same device size, the FE-DSOI device, which incorporates the ferroelectric material HZO, exhibits stronger back-gate tuning capabilities than the conventional DSOI device.

[0069] This application aims to verify whether the remanent polarization characteristics of the ferroelectric material HZO affect the back gate modulation of devices. This application establishes a simulation scheme, which is the core of this application. Specifically, as follows... Figure 9This is a schematic diagram of a simulation setting scenario for the back gate adjustment capability of an FE-DSOI device provided in an embodiment of this application. Figure 9 In the example, back-gate voltage pulses with amplitudes of (-100V, -200V, -300V, -400V, -500V) are applied for preset durations (0-1 second). To analyze the effect of pulse duration on residual polarization, pulse widths are set to 1s, 0.5s, and 0.1s; that is... Figure 9 The simulation scheme for the unique back-gate modulation of DSOI with ferroelectric materials introduced in BOX1 is presented. A -5V pulse voltage with a duration of 1s is applied to the back gate of the FD-DSOI device before irradiation. To consider the impact of pulse hold time on the simulation results, pulse widths of 0.5s and 1s are subsequently set, and the pulse waveforms are shown below. Figure 9 As shown on the far left. Further, the total dose is set to 2.8e during seconds 1-11. 8 The total dose irradiation environment; during the 0-11 second irradiation period, the back gate bias voltage was set on the FE-DSOI device, and the drain voltage was 0.9V; the front gate was scanned from -1V to 6V to obtain the I of the FE-DSOI device. d -V g Characteristic curve. The measurement results I d -V g The characteristic curves were compared with the back-gate modulation capability curves of FE-DSOI devices to obtain... Figure 10 The figure shows I when different back gate voltage pulses are applied to the FE-DSOI device. d -V g Characteristic curves.

[0070] like Figure 10 In the diagram, curve 1 represents the I value after applying a 200V back-gate voltage pulse following irradiation. d -V g Characteristic curves. Curve 2 shows the I value after irradiation with a -100V back-gate voltage pulse. d -V g Characteristic curves. Curve 3 shows the I value after irradiation when a 0V back-gate voltage pulse is applied. d -V g Characteristic curves. Curve 4 shows the I value after irradiation with a -300V back-gate voltage pulse. d -V g Characteristic curves. Curve 5 shows the I value before irradiation when a 0V back-gate voltage pulse is applied. d -V g Characteristic curves. Curve 6 shows the I value after irradiation with a -400V back-gate voltage pulse. d -V g Characteristic curves. Curve 7 shows the I value after irradiation with a -500V back-gate voltage pulse. d -V gCharacteristic curves.

[0071] From the above Figure 10 It can be seen that although no back-gate voltage is continuously applied, the FE-DSOI device still retains a certain back-gate regulation capability under the influence of the remnant polarization of the ferroelectric material. This indicates that the remnant polarization is effective in back-gate regulation, and the back-gate regulation effect (capability) and intensity differ for different pulse amplitudes. As shown in the figure, the threshold voltage still decreases under pulse amplitudes of 100V and 200V; however, when the pulse amplitude reaches 300V, the threshold voltage increases significantly on the basis of irradiation. In other words, when the pulse voltage reaches -300V, the remnant polarization characteristics (effect) of the ferroelectric HZO material caused by the back-gate pulse can increase the threshold voltage of the device.

[0072] Additionally, please see Figure 11 and Figure 12 The diagrams illustrating the effects of different pulse durations on the ferroelectric remanent polarization characteristics and back-gate regulation capability are shown respectively. Figure 11 I corresponding to FE-DSOI device under different pulse times d -V g Characteristic curves Figure 12 The graph shows the residual polarization characteristics of the FE-DSOI device under different pulse times, with time on the x-axis and polarization value on the y-axis. For example... Figure 12 As shown, curve 1 represents the remanent polarization characteristic change curve corresponding to a pulse time of 1.0s, curve 2 represents the remanent polarization characteristic change curve corresponding to a pulse time of 0.5s, and curve 3 represents the remanent polarization characteristic change curve corresponding to a pulse time of 0.1s. Combined with... Figure 11 and Figure 12 It can be seen that the longer the pulse duration, the stronger the residual polarization characteristics of the device, which is reflected in its I. d -V g The stronger the back gate adjustment capability, the less the residual polarization characteristics will be affected by factors such as irradiation and device operating bias.

[0073] This application's embodiments replace some of the silicon oxide in the BOX1 layer of the DSOI with the ferroelectric material HZO, enhancing the DSOI's back-gate regulation / control capability. Utilizing the remnant polarization characteristics of the ferroelectric material, the DSOI device can maintain its threshold voltage regulation capability even without a continuous back bias voltage. This solves the problem that traditional DSOI devices require a continuously applied back-gate voltage to regulate the threshold voltage. The solution in this application can apply a back-gate voltage pulse to the back gate of the FE-DSOI device, or place the FE-DSOI device in a short-duration strong electric field pulse. After the back-gate voltage or ambient electric field returns to zero, due to the remnant polarization characteristics of the ferroelectric material in BOX1, the FE-DSOI device can continuously maintain its back-gate regulation threshold voltage capability. Eliminating the need for a continuously applied back bias voltage also effectively reduces the limitations associated with the back bias voltage, while simultaneously reducing the power consumption caused by continuous back-gate bias. Furthermore, compared to back bias circuits, ferroelectric materials have stronger radiation resistance, thus not increasing the risk of additional radiation damage.

[0074] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the invention.

[0075] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A method for preparing a silicon-on-metal (FE-DSOI) wafer containing ferroelectric materials and buried oxide insulators, characterized in that, The method includes: Provide multiple original wafers, including at least a first original wafer, a second original wafer, a third original wafer, and a fourth original wafer; The process of preparing a bottom layer wafer using the first original wafer includes: thermally oxidizing and hydrogen-implanting the first original wafer to obtain a processed wafer; flipping the processed wafer and bonding it to the second original wafer to obtain a merged wafer; using a Smartcut process to cut the excess upper layer wafer on the merged wafer to obtain a cut-off wafer; bonding the third original wafer to the surface of the cut-off wafer to obtain a multilayer wafer; and performing a top-layer silicon oxidation process on the multilayer wafer to obtain the processed bottom layer wafer. Ferroelectric material is deposited on the surface of the bottom wafer to obtain a bottom wafer containing ferroelectric material; The fourth original wafer is subjected to thermal oxidation treatment to obtain the top layer wafer; The top wafer and the bottom wafer containing ferroelectric material are bonded and layer transferred to obtain a silicon-on-insulator (FE-DSOI) wafer containing ferroelectric material.

2. The method according to claim 1, characterized in that, The process of thermally oxidizing the fourth original wafer to obtain the top layer wafer includes: The fourth original wafer is subjected to thermal oxidation treatment to obtain a thermally oxidized wafer; The thermally oxidized wafer is subjected to hydrogen implantation to obtain the top layer wafer.

3. The method according to claim 1, characterized in that, The process of bonding and layer transfer between the top wafer and the bottom wafer containing the ferroelectric material to obtain a silicon-on-insulator (FE-DSOI) wafer containing the ferroelectric material includes: After flipping the top wafer, it is bonded to the top ferroelectric material in the bottom wafer containing ferroelectric material to obtain a bonded wafer. The excess upper layer wafer on the bonding wafer is cut or transferred using a Smartcut process to produce a silicon-on-insulator (FE-DSOI) wafer containing ferroelectric materials.

4. The method according to any one of claims 1-3, characterized in that, The ferroelectric material-containing double buried oxide silicon-on-insulator (FE-DSOI) wafer comprises, from bottom to top: a silicon substrate, a second buried oxide layer (BOX2), a back gate, a first portion of a first buried oxide layer (BOX1), ferroelectric material HZO, a second portion of the first buried oxide layer (BOX1), and silicon-on-insulator (SOI). The silicon substrate is the second original wafer. The second buried oxide layer (BOX2) is the silicon oxide and silicon oxide portion remaining on the second original wafer after thermal oxidation, hydrogen implantation, inversion bonding, and peeling. The back gate is the remaining portion of the first original wafer after thermal oxidation, hydrogen implantation, inversion bonding, and peeling. The silicon oxide on the wafer and the silicon portion in the silicon; the first part of the first buried oxide layer BOX1 is silicon oxide obtained by high-temperature thermal oxidation bonding of the third original wafer; the ferroelectric material HZO is a layer of ferroelectric material deposited on the first part of the first buried oxide layer BOX1; the second part of the first buried oxide layer BOX1 is the silicon oxide on the ferroelectric material and the silicon oxide portion in the silicon remaining after the fourth original wafer is thermally oxidized, hydrogen-implanted, inverted and bonded on the ferroelectric material, and peeled off; the silicon-on-insulator (SOI) is the silicon oxide on the ferroelectric material and the silicon portion in the silicon remaining after the fourth original wafer is thermally oxidized, hydrogen-implanted, inverted and bonded on the ferroelectric material, and peeled off.

5. The method according to claim 4, characterized in that, The method further includes: Ferroelectric back-biased silicon-on-insulator (FE-DSOI) devices were fabricated on the ferroelectric material-containing double buried oxygen insulator silicon-on-insulator wafer.

6. The method according to claim 5, characterized in that, The ferroelectric material possesses remanent polarization characteristics, and the method further includes: By utilizing the residual polarization characteristics of the ferroelectric material, back-gate modulation is performed on the FE-DSOI device to suppress the threshold voltage drift of the FE-DSOI device.

7. A ferroelectric back-biased double buried oxide insulator silicon-on-insulator (FE-DSOI) device, characterized in that, The FE-DSOI device is a device fabricated on a silicon FE-DSOI wafer containing ferroelectric material on a double buried oxygen insulator using a preset device fabrication process. The FE-DSOI wafer is fabricated using the fabrication method of the silicon FE-DSOI wafer containing ferroelectric material on a double buried oxygen insulator as described in any one of claims 1-6.

8. The FE-DSOI device according to claim 7, characterized in that, The FE-DSOI device has residual polarization characteristics, and these residual polarization characteristics are independent of the back gate voltage applied to the FE-DSOI device and the preset total dose irradiation.

9. The FE-DSOI device according to claim 7 or 8, characterized in that, The FE-DSOI device supports back-gate modulation using the residual polarization characteristics of the ferroelectric material to suppress threshold voltage drift of the FE-DSOI device.

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