Method of forming a semiconductor structure
By removing part of the second dielectric layer to protect the conductive layer before removing the hard mask layer, the aspect ratio of the opening is reduced, which solves the problems of difficulty in filling the conductive material layer and void defects in the prior art and improves the performance of the semiconductor structure.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Filing Date
- 2021-07-08
- Publication Date
- 2026-05-22
AI Technical Summary
In the prior art, as device feature size shrinks, the hard mask layer increases the opening depth, resulting in a larger opening aspect ratio. This increases the difficulty of filling the conductive material layer and the probability of void defects, affecting the performance of the semiconductor structure.
Before removing the hard mask layer, the second dielectric layer, which is a portion of the thickness of the top part of the first conductive layer, is removed first. The remaining part of the second dielectric layer protects the conductive layer, reducing the probability of damage during the removal of the hard mask layer. After removing the hard mask layer, the opening depth is reduced, the aspect ratio is lowered, and the formation of void defects is reduced.
By reducing the aspect ratio of the aperture, the difficulty of filling the conductive layer is reduced, the probability of void defects is decreased, and the performance of the semiconductor structure is improved.
Smart Images
Figure CN115602608B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology
[0002] With the continuous development of integrated circuit manufacturing technology, people have increasingly higher requirements for the integration level and performance of integrated circuits. In order to improve integration level and reduce costs, the critical dimensions of components are constantly shrinking, and the circuit density inside integrated circuits is increasing. This development makes it impossible for the wafer surface to provide enough area to fabricate the required interconnects.
[0003] To meet the interconnect requirements of reduced critical dimensions, current interconnect structures are used to connect different metal layers or between metal layers and the substrate. Interconnect structures include interconnect lines and contact holes formed within contact openings. The contact holes connect to semiconductor devices, and the interconnect lines connect the contact holes to form a circuit. Contact holes within a transistor structure include gate contact holes located on the surface of the gate structure for connecting the gate structure to external circuitry, and source / drain contact holes located on the surfaces of the source / drain doped layers for connecting the source / drain doped layers to external circuitry. Summary of the Invention
[0004] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which is beneficial to further improve the performance of the semiconductor structure.
[0005] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first dielectric layer and a first conductive layer located within the first dielectric layer, a second dielectric layer formed on top of the substrate, a hard mask layer formed on top of the second dielectric layer at a side of the first conductive layer, the mask layer exposing the second dielectric layer located on top of the first conductive layer; using the mask layer as a mask, removing a portion of the thickness of the second dielectric layer at the top of the first conductive layer to form a first opening in the second dielectric layer; using the remaining second dielectric layer at the bottom of the first opening as a mask to remove the hard mask layer; after removing the hard mask layer, removing the remaining second dielectric layer at the bottom of the first opening to form a second opening exposing the top surface of the first conductive layer in the remaining thickness of the second dielectric layer, the top of the second opening being connected to the bottom of the first opening; and forming a second conductive layer in the first opening and the second opening.
[0006] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:
[0007] This invention provides a method for forming a semiconductor structure. Before removing the hard mask layer, a second dielectric layer with a portion of its thickness at the top of the first conductive layer is removed, leaving the remaining portion of the second dielectric layer on top of the first conductive layer. During the removal of the hard mask layer, the remaining second dielectric layer at the top of the first conductive layer can protect the first conductive layer, thereby reducing the probability of damage to the first conductive layer. Furthermore, after removing the hard mask layer, the remaining second dielectric layer at the top of the first conductive layer is removed, forming a second conductive layer in the first opening and the second opening. Because the hard mask layer is removed, the total depth of the first and second openings is reduced, thereby reducing the aspect ratio of the first and second openings. Consequently, the difficulty of filling the second conductive layer in the first and second openings is reduced, thereby reducing the probability of void defects in the second conductive layer formed in the first and second openings, and thus improving the performance of the semiconductor structure. Attached Figure Description
[0008] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.
[0009] Figures 5 to 10 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation
[0010] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of a semiconductor structure needs further improvement, using a specific semiconductor structure formation method as an example.
[0011] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.
[0012] refer to Figure 1 A substrate is provided, the substrate including a first dielectric layer 10 and a first conductive layer 13 located in the first dielectric layer 10, a second dielectric layer 11 is formed on the top of the substrate, and a hard mask layer 12 is formed on the top of the second dielectric layer 11 on the side of the first conductive layer 13, the mask layer 12 exposing the second dielectric layer 11 located on top of the first conductive layer 13.
[0013] refer to Figure 2 Using the hard mask layer as a mask, the second dielectric layer 11 on top of the first conductive layer 13 is etched away to form an opening 16 that penetrates the hard mask layer 12 and the second dielectric layer 11, and the opening 16 exposes the top surface of the first conductive layer 13.
[0014] refer to Figure 3 A conductive material layer 17 is formed in the opening, and the conductive material layer 17 also covers the top of the hard mask layer 12.
[0015] refer to Figure 4 Using the top of the hard mask layer 12 as the stopping position, the conductive material layer 17 is planarized to form a second conductive layer 18 in the opening 16.
[0016] Research has revealed that after forming the opening 16 penetrating the second dielectric layer 11, the opening 16 exposes the top surface of the first conductive layer 13. Since removing the hard mask layer 12 requires an etching solution containing H2O2, this solution can easily damage the exposed top surface of the first conductive layer 13. Therefore, in the semiconductor structure formation process, the hard mask layer 12 on top of the second dielectric layer 11 needs to be retained before forming the conductive material layer 17 in the opening. However, as device feature sizes decrease, the hard mask layer 12 on top of the second dielectric layer 11 increases the total depth of the opening 16, consequently increasing the aspect ratio of the opening 16. This increases the difficulty of filling the conductive material layer 17 into the opening 16, and consequently, increases the probability of void defects in the second conductive layer 18 formed in the opening 16, thus affecting the performance of the semiconductor structure.
[0017] To address the technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first dielectric layer and a first conductive layer located within the first dielectric layer, a second dielectric layer formed on top of the substrate, a hard mask layer formed on top of the second dielectric layer at a side of the first conductive layer, the mask layer exposing the second dielectric layer located on top of the first conductive layer; using the mask layer as a mask, removing a portion of the thickness of the second dielectric layer at the top of the first conductive layer to form a first opening in the second dielectric layer; using the remaining second dielectric layer at the bottom of the first opening as a mask, removing the hard mask layer; after removing the hard mask layer, removing the remaining second dielectric layer at the bottom of the first opening to form a second opening exposing the top surface of the first conductive layer in the remaining thickness of the second dielectric layer, the top of the second opening being connected to the bottom of the first opening; and forming a second conductive layer in the first opening and the second opening.
[0018] In this embodiment of the invention, before removing the hard mask layer, a portion of the second dielectric layer at the top of the first conductive layer is removed, leaving the remaining second dielectric layer on top of the first conductive layer. During the removal of the hard mask layer, the remaining second dielectric layer on top of the first conductive layer can protect the first conductive layer, thereby reducing the probability of damage to the first conductive layer. Furthermore, after removing the hard mask layer, the remaining second dielectric layer on top of the first conductive layer is removed, forming a second conductive layer in the first and second openings. Because the hard mask layer is removed, the total depth of the first and second openings is reduced, thereby reducing the aspect ratio of the first and second openings. Consequently, the difficulty of filling the second conductive layer in the first and second openings is reduced, thus reducing the probability of void defects in the second conductive layer formed in the first and second openings, and thereby improving the performance of the semiconductor structure.
[0019] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0020] Figures 5 to 10 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.
[0021] refer to Figure 5 A substrate is provided, the substrate including a first dielectric layer 100 and a first conductive layer 103 located in the first dielectric layer 100, a second dielectric layer 101 is formed on the top of the substrate, and a hard mask layer 102 is formed on the top of the second dielectric layer 101 on the side of the first conductive layer 100, the mask layer 102 exposing the second dielectric layer 101 located on top of the first conductive layer 103.
[0022] The substrate is used to provide a process platform for subsequent process manufacturing.
[0023] Depending on the actual manufacturing process, the substrate includes a substrate and functional structures formed on the substrate. For example, the functional structures may include semiconductor devices such as MOS field-effect transistors and resistor structures. The MOS field-effect transistor typically includes a gate structure and source / drain doped regions located on both sides of the gate structure. The gate structure may be a polysilicon gate structure or a metal gate structure.
[0024] In this embodiment, the substrate includes a first dielectric layer 100 and a first conductive layer 103 located in the first dielectric layer 100.
[0025] The first dielectric layer 100 is used to achieve electrical isolation between the first conductive layers 103.
[0026] The first dielectric layer 100 is made of an insulating material, and the material of the first dielectric layer 100 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.
[0027] As an example, the material of the first dielectric layer 100 is silicon oxide.
[0028] In this embodiment, the first conductive layer 103 is a bottom source / drain plug, used for electrical connection with the source / drain doped region in the substrate. In other embodiments, the first conductive layer may also be a metal gate structure, a gate plug, or a top source / drain plug, etc. The top source / drain plug is formed on top of the bottom source / drain plug, and the gate plug is used for electrical connection with the gate structure.
[0029] In this embodiment, the first conductive layer 103 is made of tungsten. Using tungsten improves electrical performance. Specifically, tungsten has low resistivity, which helps improve signal delay in the subsequent RC circuit, increasing the chip's processing speed. It also helps reduce the resistance of the first conductive layer 103, thereby reducing power consumption. In other embodiments, the first conductive layer may also be made of cobalt or ruthenium.
[0030] The second dielectric layer 101 is used to achieve electrical isolation between the subsequently formed second conductive layers.
[0031] The material of the second dielectric layer 101 is an insulating material, and the material of the second dielectric layer 101 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.
[0032] As an example, the material of the second dielectric layer 101 is silicon nitride.
[0033] It should be noted that the thickness of the second dielectric layer 101 should not be too large or too small. If the thickness of the second dielectric layer 101 is too large, the total depth of the first and second openings subsequently formed in the second dielectric layer 101 will be too large, resulting in an excessively large aspect ratio of the first and second openings. This increases the probability of void defects in the second conductive layer subsequently formed in the first and second openings, thereby affecting the performance of the semiconductor structure. If the thickness of the second dielectric layer 101 is too small, the effective height of the second conductive layer subsequently formed in the second dielectric layer 101 will not meet the process requirements, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the second dielectric layer 101 is 500 nanometers to 2000 nanometers.
[0034] The hard mask layer 102 is used as an etching mask for subsequent etching of the second dielectric layer 101 to form the first opening.
[0035] When the second dielectric layer 101 is subsequently etched, the etching rate of the hard mask layer 102 is less than the etching rate of the second dielectric layer 101. Specifically, the material of the hard mask layer 102 includes one or more of titanium nitride, titanium oxide, silicon nitride, and silicon oxide.
[0036] As an example, the material of the hard mask layer 102 is titanium nitride.
[0037] refer to Figure 6 Using the hard mask layer 102 as a mask, a portion of the thickness of the second dielectric layer 101 at the top of the first conductive layer 103 is removed, and a first opening 105 is formed in the second dielectric layer 101.
[0038] The first opening 105 provides space for the subsequent formation of the second conductive layer.
[0039] It should be noted that after removing a portion of the thickness of the second dielectric layer 101 from the top of the first conductive layer 103, the remaining portion of the second dielectric layer 101 is located on top of the first conductive layer 103. The remaining portion of the second dielectric layer 101 protects the top of the first conductive layer 103, reducing the probability of damage to the first conductive layer 103 during the subsequent removal of the hard mask layer 102.
[0040] In this embodiment, the step of forming the first opening 105 includes: using the hard mask layer 102 as a mask, removing a portion of the thickness of the second dielectric layer 101 at the top of the first conductive layer 103.
[0041] In this embodiment, the process of removing a portion of the thickness of the second dielectric layer 101 at the top of the first conductive layer 103 includes a dry etching process.
[0042] The dry etching process includes anisotropic dry etching, which possesses the characteristics of anisotropic etching. That is, the longitudinal etching rate is greater than the transverse etching rate, which can achieve higher pattern conversion accuracy, thereby ensuring the morphology and pattern quality of the sidewall of the first opening 105.
[0043] It should be noted that the thickness of the remaining second dielectric layer 101 at the bottom of the first opening 105 should not be too large or too small. If the thickness of the remaining second dielectric layer 101 at the bottom of the first opening 105 is too large, it will increase the difficulty of forming the second opening during the subsequent removal of the remaining second dielectric layer 101 on top of the first conductive layer 103, easily leading to poor pattern quality of the formed second opening, thus affecting the conductivity of the subsequently formed second conductive layer. Moreover, it may lead to excessive etching of the second dielectric layer 101 outside the first opening 105, thus affecting the total depth of the first and second openings, resulting in the effective height of the second conductive layer formed in the second dielectric layer 101 not meeting the process requirements. If the thickness of the remaining second dielectric layer 101 at the bottom of the first opening 105 is too small, it will reduce the protection effect on the first conductive layer 103 during the subsequent removal of the hard mask layer 102, thus affecting the performance of the semiconductor device. Therefore, in this embodiment, the thickness of the remaining second dielectric layer 101 at the bottom of the first opening 105 is 80 angstroms to 200 angstroms.
[0044] refer to Figure 7 Using the remaining second dielectric layer 101 at the bottom of the first opening 105 as a mask, the hard mask layer 102 is removed.
[0045] Specifically, removing the hard mask layer 102 reduces the total depth of the first opening 105 and the subsequently formed second opening, thereby reducing the aspect ratio of the first opening 105 and the second opening. Consequently, it reduces the difficulty of filling the second conductive layer in the first opening 105 and the second opening, thereby reducing the probability of void defects in the second conductive layer formed in the first opening 105 and the second opening, and thus improving the performance of the semiconductor structure.
[0046] In this embodiment, the process for removing the hard mask layer 102 includes a wet etching process.
[0047] The wet etching process is characterized by its simple operation and high efficiency. Moreover, the wet etching process has isotropic etching characteristics, which can completely remove the hard mask layer 102.
[0048] In this embodiment, the solution used in the wet etching process includes H2O2.
[0049] H2O2 etching solution readily reacts chemically with the mask layer 102, and features low process cost and simple operation, and can completely remove the hard mask layer 102 on top of the second dielectric layer 101.
[0050] H2O2 etching solution can easily react chemically with tungsten metal, thereby damaging the first conductive layer 103. Therefore, in this embodiment, during the process of removing the hard mask layer 102 using an H2O2-containing etching solution, the second dielectric layer 101 located on top of the first conductive layer 103 can protect the first conductive layer 103.
[0051] It should be noted that the concentration percentage of the H2O2 solution should not be too high. If the concentration percentage of the H2O2 solution is too high, it can easily damage the second dielectric layer 101, thereby affecting the effective height of the subsequently formed second conductive layer. Therefore, in this embodiment, the concentration percentage of the H2O2 solution is less than 50%.
[0052] refer to Figure 8 After removing the hard mask layer 102, the remaining second dielectric layer 101 at the bottom of the first opening 105 is removed, and a second opening 106 is formed in the remaining thickness of the second dielectric layer 101, exposing the top surface of the first conductive layer 103. The top of the second opening 106 is connected to the bottom of the first opening 105.
[0053] The second opening 106 provides space for the subsequent formation of the second conductive layer.
[0054] In this embodiment, the step of removing the remaining second dielectric layer 101 at the bottom of the first opening 105 includes: performing maskless etching on the remaining second dielectric layer 101 at the bottom of the first opening 105 and the second dielectric layer 101 outside the first opening 105 to expose the top surface of the first conductive layer 103.
[0055] It should be noted that the use of maskless etching reduces the number of process steps and lowers the process cost. At the same time, it also reduces the total depth of the first opening 105 and the second opening 106, thereby reducing the aspect ratio of the first opening 105 and the second opening 106.
[0056] In this embodiment, the process of removing the remaining second dielectric layer 101 at the bottom of the first opening 105 includes a dry etching process.
[0057] The dry etching process includes plasma dry etching.
[0058] Specifically, during the formation of the second opening, plasma is directly used to physically react with the remaining second dielectric layer 101 at the bottom of the first opening 105, thereby achieving the process effect of removing the remaining second dielectric layer 101.
[0059] In this embodiment, the etching gas in the plasma dry etching process includes one or more of CF4, CHF3, CH2F2 and CH3F.
[0060] Continue to refer to Figure 8 After the second opening 106 is formed, the second dielectric layer 101 and the first conductive layer 103 exposed by the first opening 105 and the second opening 106 are cleaned.
[0061] Because a dry etching process is used in the steps of forming the first opening 105 and the second opening 106, this dry etching process easily forms residues on the surfaces of the remaining second dielectric layer 101 and the first conductive layer 103, which in turn affects the conductivity of the second conductive layer subsequently formed in the first opening 105 and the second opening 106. Therefore, before forming the second conductive layer in the first opening 105 and the second opening 106, the residues exposed on the surfaces of the second dielectric layer 101 and the first conductive layer 103 in the first opening 105 and the second opening 106 are cleaned to remove the residues, thereby improving the formation quality of the second conductive layer in the first opening 105 and the second opening 106, as well as the conductivity of the second conductive layer.
[0062] In this embodiment, the process of surface cleaning the second dielectric layer 101 and the first conductive layer 103 exposed by the first opening 105 and the second opening 106 includes a wet cleaning process.
[0063] The wet cleaning process can remove impurities and has the advantages of low process cost and simple operation.
[0064] In this embodiment, the wet cleaning process uses one or more solutions selected from hydrofluoric acid, SC1 solution, and SPM solution. SC1 solution refers to a mixed solution of NH4OH, H2O2, and H2O, while SPM solution refers to a mixed solution of H2SO4 and H2O2.
[0065] The hydrofluoric acid, SC-1 solution, and SPM solution can remove different types of impurities, such as oxides, metal ions, or organic matter.
[0066] refer to Figures 9 to 10 A second conductive layer 108 is formed in the first opening 105 and the second opening 106.
[0067] The second conductive layer 108 is electrically connected to the first conductive layer 103. The second conductive layer 108 is used to realize the electrical connection between the first conductive layer 103 and external circuits or other interconnection structures.
[0068] In this embodiment, the second conductive layer 108 is specifically a top source / drain plug. In other embodiments, the second conductive layer may also be a gate plug, etc.
[0069] In this embodiment, the step of forming a second conductive layer 108 in the first opening 105 and the second opening 106 includes: as follows Figure 9 As shown, a conductive material layer 107 is formed in the first opening 105 and the second opening 106, and the second conductive material layer 107 also covers the top of the second dielectric layer 101; as Figure 10 As shown, the conductive material layer 107 is planarized with the top of the second dielectric layer 101 as the stopping position, and the remaining conductive material layer 107 in the first opening 105 and the second opening 106 serves as the second conductive layer 108.
[0070] In this embodiment, an electroplating process is used to form a conductive material layer 107 in the first opening 105 and the second opening 106. In other embodiments, depending on the material of the second conductive layer, the process for forming the conductive material layer can also be atomic layer deposition (ALD) or metal-organic chemical vapor deposition (MOCVD).
[0071] In this embodiment, the conductive material layer 107 is ground using a chemical mechanical polishing process, which helps to improve the flatness of the top surface of the second conductive layer 108.
[0072] In this embodiment, the second conductive layer 108 is made of copper. Copper has low resistivity, which helps to improve the signal delay of the subsequent RC circuit and increase the processing speed of the chip. It also helps to reduce the resistance of the second conductive layer 108, thereby reducing power consumption. In other embodiments, the second conductive layer may also be made of cobalt or ruthenium.
[0073] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first dielectric layer and a first conductive layer located in the first dielectric layer, a second dielectric layer is formed on top of the substrate, and a hard mask layer is formed on top of the second dielectric layer on the side of the first conductive layer, the hard mask layer exposing the second dielectric layer located on top of the first conductive layer. Using the hard mask layer as a mask, a portion of the thickness of the second dielectric layer on top of the first conductive layer is removed, forming a first opening in the second dielectric layer; Using the remaining second dielectric layer at the bottom of the first opening as a mask, the hard mask layer is removed; After removing the hard mask layer, the remaining second dielectric layer at the bottom of the first opening is removed, and a second opening is formed in the remaining thickness of the second dielectric layer, exposing the top surface of the first conductive layer. The top of the second opening and the bottom of the first opening are connected. A second conductive layer is formed in the first opening and the second opening.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of removing the remaining second dielectric layer at the bottom of the first opening includes: performing maskless etching on the remaining second dielectric layer at the bottom of the first opening and the second dielectric layer outside the first opening to expose the top surface of the first conductive layer.
3. The method for forming a semiconductor structure as described in claim 1 or 2, characterized in that, In the step of providing the substrate, the thickness of the second dielectric layer is 500 nanometers to 2000 nanometers.
4. The method for forming a semiconductor structure as described in claim 1 or 2, characterized in that, In the step of forming the first opening in the second dielectric layer, the thickness of the remaining second dielectric layer at the bottom of the first opening is 80 angstroms to 200 angstroms.
5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for removing the hard mask layer includes a wet etching process.
6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The wet etching process uses a solution including H2O2.
7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The concentration percentage of the H2O2 solution is less than 50%.
8. The method for forming a semiconductor structure as described in claim 1 or 2, characterized in that, In the step of forming the second opening, the process of removing the remaining second dielectric layer at the bottom of the first opening includes a dry etching process.
9. The method for forming a semiconductor structure as described in claim 1, characterized in that, After the second opening is formed, and before the second conductive layer is formed in the first and second openings, the method further includes cleaning the second dielectric layer and the first conductive layer exposed in the first and second openings.
10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The cleaning process includes a wet cleaning process.
11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The wet cleaning process uses one or more of the following solutions: hydrofluoric acid, SC1 solution, and SPM solution.
12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming a second conductive layer in the first opening and the second opening includes: forming a conductive material layer in the first opening and the second opening, the conductive material layer further covering the top of the second dielectric layer; planarizing the conductive material layer with the top of the second dielectric layer as the stopping position, and the remaining conductive material layer in the first opening and the second opening serving as the second conductive layer.
13. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process of removing a portion of the thickness of the second dielectric layer from the top of the first conductive layer includes a dry etching process.
14. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the substrate, the material of the first conductive layer includes one or more of tungsten, cobalt, and ruthenium.
15. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming a second conductive layer in the first opening and the second opening, the material of the second conductive layer includes one or more of copper, tungsten and ruthenium.