Clock synchronization circuit, chip and electronic device

Abstract

The application provides a clock synchronization circuit, a chip and an electronic device, the clock synchronization circuit comprises: a first phase-locked loop circuit, a second phase-locked loop circuit and a first frequency divider; a first end of the first phase-locked loop circuit is connected with an input end; second ends of the first phase-locked loop circuit are respectively connected with a first end of the second phase-locked loop circuit and a first output end; a second end of the second phase-locked loop circuit is connected with a first end of the first frequency divider; and a second end of the first frequency divider is connected with a second output end. The clock synchronization circuit provided by the application comprises: a first phase-locked loop circuit, a second phase-locked loop circuit and a first frequency divider, can realize simultaneous output of standard Ethernet and wireless communication system homologous clock, and simplifies a clock scheme and reduces device cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication technology, in particular to a clock synchronization circuit, a chip and an electronic device. BACKGROUND

[0002] At present, since the standard Ethernet adopts a network cable (Power over Ethernet, POE) transmission mode to more easily simultaneously realize data transmission and power supply to a remote unit, and has a cost and easy construction advantage compared with an optical fiber transmission system, the standard Ethernet transmission is more used in short distance wireless communication system transmission, so the optical fiber communication system and the Ethernet communication system exist simultaneously in the wireless communication system.

[0003] The standard Ethernet transmission rate is usually 10 Mb / s, 100 Mb / s, 1000 Mb / s, and 10000 Mb / s, and the reference clock required by the standard Ethernet communication system is an integer multiple of 25 MHz; and the baseband clock rate of the wireless communication base station system is an integer multiple of 3.84 MHz, in order to meet the frequency error requirement of the wireless communication base station system, the 3.84 MHz integer multiple clock provided for the baseband processing of the expansion unit and the remote unit must be the same as the 25 MHz clock of the standard Ethernet transmission system.

[0004] In the prior art, a general double-loop phase-locked loop chip is selected, two clock signal of 25 MHz and 122.88 MHz cannot be obtained at the same time through integer frequency division of a second voltage controlled oscillator (VCO), and two sets of clock scheme are usually cascaded to realize, which has a high cost. SUMMARY

[0005] In view of the problems in the prior art, the present application provides a clock synchronization circuit, a chip and an electronic device, which realize the simultaneous output of the clock signals of the standard Ethernet and the wireless communication system with the same source, and reduce the device cost.

[0006] The present application provides a clock synchronization circuit, comprising: a first phase-locked loop circuit, a second phase-locked loop circuit and a first frequency divider;

[0007] A first end of the first phase-locked loop circuit is connected with an input end;

[0008] A second end of the first phase-locked loop circuit is connected with a first end and a first output end of the second phase-locked loop circuit respectively;

[0009] A second end of the second phase-locked loop circuit is connected with a first end of the first frequency divider;

[0010] A second end of the first frequency divider is connected with a second output end.

[0011] In some embodiments, the first phase-locked loop circuit comprises: a first voltage-controlled oscillator, a first phase detector, a second frequency divider, and a third frequency divider;

[0012] A first end of the second frequency divider is connected to a second end of the first voltage-controlled oscillator;

[0013] A second end of the second frequency divider is connected to a first end of the first phase detector;

[0014] A first end of the third frequency divider is connected to the input end;

[0015] A second end of the third frequency divider is connected to the first end of the first phase detector;

[0016] A second end of the first phase detector is connected to a first end of the first voltage-controlled oscillator;

[0017] A second end of the first voltage-controlled oscillator is connected to the first output end.

[0018] In some embodiments, the second phase-locked loop circuit comprises: a second voltage-controlled oscillator, a second phase detector, a fourth frequency divider, and a fifth frequency divider;

[0019] A first end of the fourth frequency divider is connected to a second end of the first voltage-controlled oscillator;

[0020] A second end of the fourth frequency divider is connected to a first end of the second phase detector;

[0021] A first end of the fifth frequency divider is connected to a second end of the second voltage-controlled oscillator;

[0022] A second end of the fifth frequency divider is connected to the first end of the second phase detector;

[0023] A second end of the second phase detector is connected to a first end of the second voltage-controlled oscillator.

[0024] In some embodiments, a second end of the second voltage-controlled oscillator is connected to a first end of the first frequency divider.

[0025] In some embodiments, the first voltage-controlled oscillator is a voltage-controlled crystal oscillator.

[0026] In some embodiments, the number of the first frequency dividers is plural.

[0027] In some embodiments, the reference clock frequency input by the input end is recovered from transmission data of a network cable.

[0028] In some embodiments, the reference clock frequency input by the input end is recovered from transmission data of an optical fiber.

[0029] The application further provides a chip comprising any of the clock synchronization circuits.

[0030] The application further provides an electronic device comprising any of the chips.

[0031] The clock synchronization circuit, the chip, the electronic device and the clock synchronization method provided by the application realize the output of standard Ethernet clock 25MHz and wireless communication system clock 122.88MHz homologous clock through the reasonable design of the access unit, the expansion unit and the remote unit clock scheme, the use of single analog PLL, the same clock planning frequency of logic code as the traditional clock scheme and hardware architecture, greatly reducing the logic code development workload, and the low cost of analog PLL, thereby simplifying the hardware circuit and reducing the equipment cost. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the application or prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0033] Figure 1 is one of the structural schematic diagrams of the clock synchronization circuit provided by the embodiment of the application;

[0034] Figure 2 is a structural schematic diagram of a wireless communication system in the prior art;

[0035] Figure 3 is the second structural schematic diagram of the clock synchronization circuit provided by the embodiment of the application;

[0036] Figure 4 is the third structural schematic diagram of the clock synchronization circuit provided by the embodiment of the application. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical scheme and advantages of the application more clear, the technical scheme in the application will be described clearly and completely in the following with reference to the drawings in the application. Obviously, the described embodiments are some embodiments of the application, not all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor belong to the protection scope of the application.

[0038] Figure 1 is one of the structural schematic diagrams of the clock synchronization circuit provided by the embodiment of the application, and reference is made to Figure 1The clock synchronization circuit provided by the embodiment of the present application can comprise a first phase-locked loop circuit, a second phase-locked loop circuit and a first frequency divider.

[0039] The first end of the first phase-locked loop circuit is connected with an input end.

[0040] The second end of the first phase-locked loop circuit is respectively connected with the first end of the second phase-locked loop circuit and a first output end.

[0041] The second end of the second phase-locked loop circuit is connected with the first end of the first frequency divider.

[0042] The second end of the first frequency divider is connected with a second output end.

[0043] Optionally, the clock synchronization circuit provided by the embodiment of the present application comprises a first phase-locked loop circuit 110, a second phase-locked loop circuit 120 and a first frequency divider 130.

[0044] The connection relationship is as follows:

[0045] The first end of the first phase-locked loop circuit 110 is connected with an input end.

[0046] The second end of the first phase-locked loop circuit 110 is respectively connected with the first end of the second phase-locked loop circuit 120 and a first output end.

[0047] The second end of the second phase-locked loop circuit 120 is connected with the first end of the first frequency divider 130.

[0048] The second end of the first frequency divider 130 is connected with a second output end.

[0049] It should be noted that the clock synchronization circuit provided by the embodiment of the present application is applied to a wireless communication small base station system adopting standard Ethernet transmission, and realizes the clock synchronization of an extension unit and a remote unit with a host baseband unit.

[0050] Optionally, in the wireless communication small base station system, the host unit and the extension unit usually adopt an optical fiber connection mode, which is convenient for long-distance transmission, and the extension unit recovers the clock from the data transmitted in the optical fiber, thereby realizing the clock synchronization of the host unit and the extension unit.

[0051] The remote unit and the extension unit adopt a POE transmission mode, and the remote unit recovers the clock from the standard Ethernet data transmitted by the extension unit, thereby realizing the clock synchronization of the whole wireless communication small base station system.

[0052] Figure 2 is a structural schematic diagram of a wireless communication system in the prior art, like Figure 2As shown, the extension unit is connected with the access unit through optical fiber, the remote unit is connected with the extension unit through network cable, and the extension unit and the remote unit both have baseband processing and Ethernet transmission, and both need two types of clock sources, i.e., the wireless communication system clock 122.88MHz and the standard Ethernet clock 25MHz.

[0053] The extension unit recovers the clock from the optical fiber, and the remote unit recovers the clock from the network cable, and the clock of the wireless communication system 122.88MHz and the clock of the standard Ethernet system 25MHz must be the same source, so that the clock of the entire system is synchronized with the clock of the baseband unit.

[0054] Optionally, the phase-locked loop (PLL) is a negative feedback control system that uses a phase-synchronized voltage to tune a voltage-controlled oscillator to generate a target frequency. The frequency and phase of the loop internal oscillation signal are controlled by the external input reference signal, and the output signal frequency is automatically tracked to the input signal frequency. It is a method for stabilizing the frequency in radio transmission, mainly including a VCO and a phase-locked loop integrated circuit (PLL IC). The voltage-controlled oscillator gives a signal, part of which is used as output, and the other part is compared in phase with the local oscillator signal generated by the PLL IC. In order to keep the frequency unchanged, the phase difference must not change. If the phase difference changes, the voltage at the voltage output end of the PLL IC changes to control the VCO until the phase difference is restored, achieving the purpose of phase locking. The closed-loop electronic circuit can make the frequency and phase of the controlled oscillator maintain a certain relationship with the input signal.

[0055] (1) Optionally, when the clock synchronization circuit provided by the embodiment of the application is applied to the extension unit, the input of the clock synchronization circuit is a reference clock frequency, the frequency of the reference clock is recovered from the data transmitted by the optical fiber, and the frequency of the reference clock is an integer multiple of 3.84MHz, for example, it can be 153.6MHz.

[0056] The frequency 153.6MHz of the reference clock is input into the first phase-locked loop circuit 110, and a first clock frequency output by the first phase-locked loop circuit is obtained. The first clock frequency is synchronized with the frequency of the reference clock, i.e., synchronized with the clock frequency of the wireless communication system.

[0057] The first clock frequency also simultaneously serves as the input of the second phase-locked loop circuit 120. The first clock frequency is input into the second phase-locked loop circuit 120, and a second clock frequency output by the second phase-locked loop circuit is obtained. The second clock frequency is divided by the first frequency divider 130, and a third clock frequency is output. The third clock frequency is synchronized with the clock frequency of the standard Ethernet system.

[0058] The wireless communication system clock 122.88MHz and the standard Ethernet clock 25MHz homologous clock are obtained in the extension unit by the above method, so that the extension unit is synchronized with the baseband unit clock.

[0059] (2) Optionally, when the clock synchronization circuit provided by the embodiment of the application is applied to the remote unit, the input of the clock synchronization circuit is a reference clock frequency, the frequency of the reference clock is recovered from the data transmitted from the network cable, and the frequency of the reference clock is an integer multiple of 25MHz, for example, can be 25MHz.

[0060] The 25MHz is input into the first phase-locked loop circuit 110, and the first clock frequency output by the first phase-locked loop circuit is obtained, and the first clock frequency is synchronized with the frequency of the reference clock, that is, synchronized with the clock frequency of the standard Ethernet system.

[0061] The first clock frequency also simultaneously serves as the input of the second phase-locked loop circuit 120, the first clock frequency is input into the second phase-locked loop circuit 120, and the second clock frequency output by the second phase-locked loop circuit is obtained.

[0062] The second clock frequency is divided by the first frequency divider 130, and the third clock frequency is output. The third clock frequency is synchronized with the clock frequency of the wireless communication system.

[0063] The wireless communication system clock 122.88MHz and the standard Ethernet clock 25MHz homologous clock are obtained in the remote unit by the above method, so that the remote unit is synchronized with the extension unit clock.

[0064] The clock synchronization circuit provided by the embodiment of the application is reasonably designed through the clock schemes of the access unit, the extension unit and the remote unit, a single analog PLL is adopted, the standard Ethernet clock 25MHz and the wireless communication system clock 122.88MHz homologous clock are output, the clock planning frequency of the logic code is the same as that of the traditional clock scheme and the hardware architecture, the development workload of the logic code is greatly reduced, and the analog PLL is low in cost, so that the hardware circuit is simplified and the equipment cost is reduced.

[0065] In some embodiments, the first phase-locked loop circuit comprises: a first voltage-controlled oscillator, a first phase detector, a second frequency divider and a third frequency divider;

[0066] The first end of the second frequency divider is connected with the second end of the first voltage-controlled oscillator;

[0067] The second end of the second frequency divider is connected with the first end of the first phase detector;

[0068] The first end of the third frequency divider is connected with the input end;

[0069] The second end of the third frequency divider is connected with the first end of the first phase detector;

[0070] The second end of the first phase detector is connected with the first end of the first voltage controlled oscillator;

[0071] The second end of the first voltage controlled oscillator is connected with the first output end.

[0072] Optionally, the first phase-locked loop circuit can comprise a first voltage controlled oscillator, a first phase detector, a second frequency divider and a third frequency divider.

[0073] The connection relationship is as follows:

[0074] The first end of the second frequency divider is connected with the second end of the first voltage controlled oscillator;

[0075] The second end of the second frequency divider is connected with the first end of the first phase detector;

[0076] The first end of the third frequency divider is connected with the input end;

[0077] The second end of the third frequency divider is connected with the first end of the first phase detector;

[0078] The second end of the first phase detector is connected with the first end of the first voltage controlled oscillator;

[0079] The second end of the first voltage controlled oscillator is connected with the first output end.

[0080] The clock synchronization circuit provided by the embodiment of the application realizes the synchronization of the expansion unit and the wireless system, or the synchronization of the remote unit and the standard Ethernet system, by inputting the reference clock frequency into the first phase-locked loop circuit and outputting the first clock frequency which is synchronized with the reference clock frequency.

[0081] In some embodiments, the second phase-locked loop circuit comprises a second voltage controlled oscillator, a second phase detector, a fourth frequency divider and a fifth frequency divider;

[0082] The first end of the fourth frequency divider is connected with the second end of the first voltage controlled oscillator;

[0083] The second end of the fourth frequency divider is connected with the first end of the second phase detector;

[0084] The first end of the fifth frequency divider is connected with the second end of the second voltage controlled oscillator;

[0085] The second end of the fifth frequency divider is connected with the first end of the second phase detector;

[0086] The second end of the second phase detector is connected with the first end of the second voltage controlled oscillator.

[0087] Optionally, the second phase-locked loop circuit can comprise a second voltage-controlled oscillator, a second phase detector, a fourth frequency divider and a fifth frequency divider.

[0088] The connection relationship is as follows:

[0089] The first end of the fourth frequency divider is connected with the second end of the first voltage-controlled oscillator.

[0090] The second end of the fourth frequency divider is connected with the first end of the second phase detector.

[0091] The first end of the fifth frequency divider is connected with the second end of the second voltage-controlled oscillator.

[0092] The second end of the fifth frequency divider is connected with the first end of the second phase detector.

[0093] The second end of the second phase detector is connected with the first end of the second voltage-controlled oscillator.

[0094] Further, the second end of the second voltage-controlled oscillator is connected with the first end of the first frequency divider.

[0095] The clock synchronization circuit provided by the embodiment of the application can realize synchronization of an expansion unit and a standard Ethernet system or synchronization of a remote unit and a wireless system by inputting the first clock frequency output by the first phase-locked loop circuit into the second phase-locked loop circuit to obtain the second clock frequency, and performing frequency division processing on the second clock frequency by the first frequency divider to output the third clock frequency.

[0096] The clock synchronization circuit provided by the application will be described in detail below in combination with Figure 3 , Figure 4 and specific embodiments.

[0097] Figure 3 is a structural schematic diagram of the clock synchronization circuit provided by the embodiment of the application, and reference is made to Figure 3 for detailed description of a method for synchronizing two types of clocks, i.e., an expansion unit wireless communication system clock 122.88MHz and a standard Ethernet clock 25MHz.

[0098] As shown in Figure 3 , D1 is a second frequency divider, R1 is a third frequency divider, VCXO is a first voltage-controlled oscillator, D1, R1, VCXO and a first phase detector together constitute a first phase-locked loop circuit.

[0099] R2 is a fourth frequency divider, D2 is a fifth frequency divider, VCO is a second voltage-controlled oscillator, D2, R2, VCO and a second phase detector together constitute a second phase-locked loop circuit.

[0100] D is a first frequency divider, and the number of the first frequency dividers can be multiple.

[0101] The connection relationship of each circuit and each device is shown in the figure and will not be described here.

[0102] The first stage voltage controlled crystal oscillator (VCXO) of the extended unit phase-locked loop chip adopts 122.88MHz, and the phase discrimination is performed with the recovered 153.6MHz of the optical fiber, so that the 122.88MHz VCXO is synchronized with the recovered clock.

[0103] The 122.88MHz is output through the first stage clock output pin of the phase-locked loop chip, or is output through the second stage phase-locked loop bypass function from the second stage clock output pin, and is provided for the baseband processing part.

[0104] The algorithm implementation process will be described in detail below:

[0105] Supposing that the input reference clock is CLK_Ref_In, the first stage reference frequency division is R1, the first stage VCXO, the first stage VCXO reference frequency division is D1, the second stage reference clock is the VCXO output of the first stage, the second stage reference frequency division is R2, the second stage VCO, and the second stage VCO reference frequency division is D2, according to the working principle of the phase-locked loop, the following formulae need to be met:

[0106]

[0107] In order to realize the method of simultaneously outputting the wireless communication system clock and the standard Ethernet clock, the VCXO needs to be taken as the input of the second stage PLL, and the following formulae need to be met:

[0108]

[0109] The reference clock CLK_Ref_In recovered from the baseband in the wireless communication system is 153.6MHz, the VCXO is 122.88MHz, the common divisor calculated by formula (1) is 1.28MHz by selecting R1=120 and D1=96.

[0110] The VCXO is 122.88MHz, the VCO is 3000MHz, the common divisor calculated by formula (2) is 0.96MHz by selecting R2=128 and D2=96, and the 25MHz clock is obtained by setting the VCO clock output frequency divider coefficient to 120, and is provided for the Ethernet device.

[0111] The wireless communication system clock 122.88MHz and the standard Ethernet clock 25MHz are obtained in the extended unit by the above method, so that the clock of the extended unit is synchronized with the baseband unit.

[0112] By changing the frequency of the VCXO to 30.72MHz, 61.44MHz, other clock frequencies acceptable to the baseband processing section can be obtained.

[0113] By setting the VCO clock output divider to 60, 24, clock frequencies of 50MHz and 125MHz acceptable to Ethernet devices are obtained, respectively.

[0114] Figure 4 is a third structural diagram of the clock synchronization circuit provided by the embodiment of the present application, referring to Figure 4 , a method of synchronizing the 122.88MHz clock of the remote unit wireless communication system and the 25MHz standard Ethernet clock is described in detail.

[0115] As shown in Figure 4 , D1 is a second frequency divider, R1 is a third frequency divider, VCXO is a first voltage-controlled oscillator, D1, R1, VCXO and a first phase detector together form a first phase-locked loop circuit.

[0116] R2 is a fourth frequency divider, D2 is a fifth frequency divider, VCO is a second voltage-controlled oscillator, D2, R2, VCO and a second phase detector together form a second phase-locked loop circuit.

[0117] D is a first frequency divider, and the number of the first frequency dividers can be multiple.

[0118] The connection relationship of each circuit and each device is shown in the figure, and will not be described here.

[0119] The Ethernet device recovers a 25MHz clock from the standard network cable data, the first-stage VCXO frequency of the phase-locked loop chip adopts 25MHz, and the 25MHz frequency recovered by the Ethernet device is used for phase detection, so that the 25MHz VCXO is synchronized with the recovered clock.

[0120] The 25MHz clock is output through the first-stage clock output pin of the phase-locked loop chip, or is output through the second-stage phase-locked loop bypass function from the second-stage clock output pin, and is provided for the Ethernet device.

[0121] The algorithm implementation process will be described in detail below:

[0122] The reference clock CLK_Ref_In recovered from the baseband in the wireless communication system is 25MHz, and the VCXO is 25MHz, and by selecting R1=25, D1=25, the greatest common divisor calculated by formula (1) is 1MHz.

[0123] VCXO=25MHz, VCO=3072MHz, by selecting R2=25, D2=3072, the common divisor calculated by formula (2) is 1MHz, by setting the VCO clock output divider coefficient to 100, a 30.72MHz clock is obtained, which is provided to the Ethernet device.

[0124] The wireless communication system clock 122.88MHz and the standard Ethernet clock 25MHz homologous clock are obtained at the remote unit in the above manner, so that the remote unit is clock-synchronized with the expansion unit.

[0125] Other clock frequencies acceptable by the Ethernet chip are obtained by replacing the VCXO frequency with 50MHz, 125MHz or 156.25MHz.

[0126] The clock frequencies acceptable by the baseband processing part are obtained by setting the second-stage clock output divider to 160, 100 and 50, respectively, to obtain 19.2MHz, 30.72MHz and 61.44MHz.

[0127] It should be noted that, Figure 3 and Figure 4 Only one embodiment is provided, and the wireless communication system clock 19.2MHz, 30.72MHz and 61.44MHz and the standard Ethernet clock 25MHz, 50HMz, 125MHz can be output by changing the VCXO frequency or changing the frequency division coefficient in the above description.

[0128] The clock synchronization circuit provided by the embodiment of the application is reasonably designed by accessing the clock schemes of the unit, the expansion unit and the remote unit, and adopts a single analog PLL to realize output of the standard Ethernet clock 25MHz (or an integer multiple of 25MHz) and the wireless communication system clock 122.88MHz (or an integer multiple of 3.84MHz) homologous clock, and has the following beneficial effects:

[0129] 1. Like the traditional clock scheme and the hardware architecture, the clock planning frequency of the logic code is the same, which greatly reduces the development workload of the logic code.

[0130] 2. The analog PLL is low in cost and can overcome the disadvantages of the digital PLL, such as fractional frequency division spur and influence on the phase noise index.

[0131] The application further provides a chip comprising the clock synchronization circuit of the above embodiment.

[0132] The application further provides an electronic device comprising the chip of the above embodiment.

[0133] The apparatus embodiments described above are merely illustrative, wherein the units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed on multiple network units. Part or all of the modules can be selected to achieve the purposes of the embodiments according to actual needs. Those skilled in the art can understand and implement without creative labor.

[0134] The terms "first", "second", etc. in the embodiments of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second" are generally a class, and do not limit the number of objects, for example, the first object can be one or more.

[0135] From the above description of the embodiments, those skilled in the art can clearly understand that the embodiments can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware. Based on such understanding, the above technical solutions, essentially or in the sense of contribution to the prior art, can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods described in each embodiment or some parts of the embodiments.

[0136] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A clock synchronization circuit, characterized in that, include: The first phase-locked loop circuit, the second phase-locked loop circuit, and the first frequency divider; The first terminal of the first phase-locked loop circuit is connected to the input terminal; The input terminal is used to receive a reference clock frequency; The second terminal of the first phase-locked loop circuit is connected to the first terminal and the first output terminal of the second phase-locked loop circuit, respectively; the first output terminal is used to output the first clock frequency; The second terminal of the second phase-locked loop circuit is connected to the first terminal of the first frequency divider; The second terminal of the first frequency divider is connected to the second output terminal; the second output terminal is used to output the third clock frequency; Wherein, when the reference clock frequency is an integer multiple of 3.84MHz, the first clock frequency is synchronized with the clock frequency of the wireless communication system (122.88MHz), and the third clock frequency is synchronized with the clock frequency of the standard Ethernet system (25MHz); or, when the reference clock frequency is an integer multiple of 25MHz, the first clock frequency is synchronized with the clock frequency of the standard Ethernet system (25MHz), and the third clock frequency is synchronized with the clock frequency of the wireless communication system (122.88MHz).

2. The clock synchronization circuit according to claim 1, characterized in that, The first phase-locked loop circuit includes: a first voltage-controlled oscillator, a first phase detector, a second frequency divider, and a third frequency divider; The first terminal of the second frequency divider is connected to the second terminal of the first voltage-controlled oscillator; The second terminal of the second frequency divider is connected to the first terminal of the first phase detector; The first terminal of the third frequency divider is connected to the input terminal; The second terminal of the third frequency divider is connected to the first terminal of the first phase detector; The second terminal of the first phase detector is connected to the first terminal of the first voltage-controlled oscillator; The second terminal of the first voltage-controlled oscillator is connected to the first output terminal.

3. The clock synchronization circuit according to claim 2, characterized in that, The second phase-locked loop circuit includes: a second voltage-controlled oscillator, a second phase detector, a fourth frequency divider, and a fifth frequency divider; The first terminal of the fourth frequency divider is connected to the second terminal of the first voltage-controlled oscillator. The second terminal of the fourth frequency divider is connected to the first terminal of the second phase detector; The first terminal of the fifth frequency divider is connected to the second terminal of the second voltage-controlled oscillator; The second terminal of the fifth frequency divider is connected to the first terminal of the second phase detector; The second terminal of the second phase detector is connected to the first terminal of the second voltage-controlled oscillator.

4. The clock synchronization circuit according to claim 3, characterized in that, The second terminal of the second voltage-controlled oscillator is connected to the first terminal of the first frequency divider.

5. The clock synchronization circuit according to any one of claims 2 to 4, characterized in that, The first voltage-controlled oscillator is a voltage-controlled crystal oscillator.

6. The clock synchronization circuit according to any one of claims 1 to 4, characterized in that, There are multiple first frequency dividers.

7. The clock synchronization circuit according to any one of claims 1 to 4, characterized in that, The reference clock frequency input at the input terminal is recovered from the data transmitted via the network cable.

8. The clock synchronization circuit according to any one of claims 1 to 4, characterized in that, The reference clock frequency input to the input terminal is recovered from the transmitted data in the optical fiber.

9. A chip, characterized in that, Includes the clock synchronization circuit according to any one of claims 1 to 8.

10. An electronic device, characterized in that, Includes the chip described in claim 9.

Images