Digital resolver decoder with hardware filter and rectifier

Abstract

Embodiments of the present disclosure generally relate to digital resolver decoders with hardware filters and rectifiers. A resolver decoder circuit includes a first filter circuit configured to compute a first weighted sum of first digital signals over a predetermined time period, where the first digital signals include first digital samples of a first analog signal from a sine winding of a resolver; a second filter circuit configured to compute a second weighted sum of second digital signals over the predetermined time period, where the second digital signals include second digital samples of a second analog signal from a cosine winding of the resolver, where the first and second analog signals are configured to be induced by a sinusoidal signal applied to an input winding of the resolver; and a rectifier configured to generate a first output and a second output by adjusting a first sign of the first weighted sum and adjusting a second sign of the second weighted sum, respectively.

Description

Technical Field

[0001] This invention relates generally to a resolver decoder, and more particularly to a digital resolver decoder having hardware filters and hardware rectifiers. Background Technology

[0002] Traction motor control is crucial for electric vehicle (EV) applications. Axis rotation angle measurement plays a key role in traction motor control. The rotation angle of the motor axis (also known as the motor shaft) is typically measured using a resolver.

[0003] A resolver (also known as a motor resolver) is an electromagnetic sensor used in various position and speed feedback applications, such as servo motor feedback applications. A resolver is a special type of rotating transformer consisting of a cylindrical rotor and a stator. The rotor is attached to the motor shaft and rotates with it. A resolver typically has a primary winding and two secondary windings. The primary winding can be the rotor winding on the rotor, and the secondary windings can be the two stator windings on the stator. The two secondary windings are mechanically arranged such that their physical relationship is offset by a 90° angle.

[0004] A resolver is used to generate an output signal indicating the angular position of the motor shaft relative to a reference point within the space of one full rotation of the motor shaft or within the corresponding angular displacement space from 0° to 360°. To generate the output signal, a rotor excitation signal (e.g., a sine wave signal) is applied to the primary winding. The physical relationship of the secondary windings produces a mathematical / electrical relationship such that the first output signal at the primary winding in the secondary winding is generated by… The amplitude-modulated sine wave signal, and the second output signal at the second secondary winding in the secondary winding is generated by... A sinusoidal signal undergoing amplitude modulation, wherein It refers to the angular position of the motor shaft (also known as the angle of the motor shaft). The output signal of the resolver is then decoded by the resolver decoder to obtain the angle. The estimation. There is a need in this field to provide angles with lower hardware costs and / or lower computing power requirements. The accurate estimation of the resolver decoder. Summary of the Invention

[0005] In some embodiments, a resolver decoder circuit includes: a first filter circuit configured to calculate a first weighted sum of a first digital signal over a predetermined time period, wherein the first digital signal includes a first digital sample of a first analog signal from a first primary winding of the resolver; a second filter circuit configured to calculate a second weighted sum of a second digital signal over the predetermined time period, wherein the second digital signal includes a second digital sample of a second analog signal from a second secondary winding of the resolver, wherein the first analog signal and the second analog signal are configured to be induced by a sinusoidal signal applied to an input winding of the resolver; and a rectifier configured to generate a first output and a second output by adjusting a first sign of the first weighted sum and adjusting a second sign of the second weighted sum, respectively.

[0006] In some embodiments, a processor having an integrated resolver decoder circuit includes: an analog-to-digital converter (ADC) circuit configured to: generate a first digital sample by converting a first analog signal from a sinusoidal winding of a resolver, and generate a second digital sample by converting a second analog signal from a cosine winding of a resolver, the first and second analog signals being generated by exciting an input winding of the resolver with a sinusoidal signal; a first tapped delay line (TDL) filter coupled to the ADC circuit and configured to calculate a first weighted sum of the first digital samples over a predetermined time period; a second TDL filter coupled to the ADC circuit and configured to calculate a second weighted sum of the second digital samples over a predetermined time period; a rectifier configured to generate a first output and a second output by adjusting a first sign of the first weighted sum and a second sign of the second weighted sum, respectively; and a central processing unit coupled to the rectifier.

[0007] In some embodiments, a method of operating a resolver decoder circuit includes: converting a first analog signal from a sinusoidal winding of a resolver into a first data sample; converting a second analog signal from a cosine winding of a resolver into a second data sample; calculating a first weighted sum of the first data samples over a predetermined time period; calculating a second weighted sum of the second data samples over the predetermined time period; adjusting a first sign of the first weighted sum and a second sign of the second weighted sum based on the position of the predetermined time period within the period of the sinusoidal signal; after the adjustment, dividing the first weighted sum by the second weighted sum to obtain a value; and determining the arctangent of the value to obtain an angle. Attached Figure Description

[0008] Details of one or more embodiments of the present invention are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of the invention will become apparent from the description, the drawings, and the claims. In the drawings, the same reference numerals generally denote the same components in various views and are generally not restated for the sake of brevity. For a more complete understanding of the invention, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 A block diagram of a motor system in one embodiment is shown;

[0010] Figure 2 The primary and secondary windings of a rotary transformer in one embodiment are shown.

[0011] Figure 3 The input and output signals of a rotary transformer in one embodiment are shown;

[0012] Figure 4 A block diagram of a resolver decoder in one embodiment is shown;

[0013] Figure 5 A schematic diagram of a digital filter in a resolver decoder is shown in one embodiment;

[0014] Figure 6 A strategy for allocating filter tap coefficients in one embodiment is shown;

[0015] Figure 7A and 7B A strategy for allocating filter tap coefficients is shown in another embodiment;

[0016] Figure 8 A strategy for allocating filter tap coefficients is shown in yet another embodiment; and

[0017] Figure 9 A flowchart of a method for operating a resolver decoder circuit is shown in some embodiments. Detailed Implementation

[0018] The manufacture and use of the presently preferred embodiments are discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific environments. The specific embodiments discussed are merely illustrative of specific ways of making and using the invention and do not limit the scope of the invention.

[0019] The present invention will be described in a specific context with respect to exemplary embodiments, namely, a digital resolver decoder having hardware filters and hardware rectifiers.

[0020] Figure 1A block diagram of a motor system 100 in one embodiment is shown. Note that, for simplicity, not all features of the motor system 100 are shown.

[0021] refer to Figure 1 The motor control system 101 includes a motor 101, which may be, for example, a three-phase motor. The motor 101 is driven by a power stage 121, which may include drive circuitry providing drive voltage to the motor 101. For example, the power stage 121 may include three parallel drive circuits, each for driving one phase of the three phases of the motor 101. Each of the drive circuits may have its corresponding power switch (e.g., a high-voltage side power switch and a low-voltage side power switch). The power stage 121 is controlled by a central processing unit (CPU) 109. The CPU 109 has a memory module 108 (e.g., non-volatile memory). The memory module 108 may store computer programs (e.g., computer code) for motor control algorithms. Furthermore, the memory module 108 may store various parameters related to, for example, system settings or filter coefficients of filter circuitry 115.

[0022] like Figure 1 As shown, the rotor of the rotary transformer 103 is coupled to the motor shaft, causing the rotor to rotate together with the motor shaft. The two secondary windings of the rotary transformer 103 provide two output signals 104A and 104B, which can be used to determine the angle of the motor shaft. Figure 2 and 3 Details regarding the rotary transformer 103 and output signals 104A and 104B are shown.

[0023] For reference only Figure 2 , Figure 2 The primary winding 131 of the rotary transformer 103 and its two secondary windings are shown, wherein the secondary windings include a primary winding 133 and a secondary winding 135. The primary winding 131 may be a rotor winding, and the secondary windings 133 / 135 may be two stator windings. The two secondary windings 133 / 135 are mechanically arranged such that their coils are offset by a 90° angle.

[0024] Rotary transformer 103 is driven by excitation voltage V in The primary winding 131 is excited or stimulated to generate an output signal at the secondary windings 133 / 135, with an excitation voltage V. in It is V in =A*Sin(ω) c t) represents a sinusoidal signal, where ω c V is the angular frequency of the sinusoidal signal, and A is the amplitude of the sinusoidal signal. inA voltage is induced at each point in the secondary windings 133 / 135. The output voltage at the secondary windings 133 / 135 is a sinusoidal signal V. in The amplitude-modulated version, in which the sine wave signal V in The amplitude is determined by the angle of the motor shaft. Sine and cosine modulation. For example, the voltage V across the terminals of the primary winding 133. sin and the voltage V across the terminals of the secondary winding 135 cos It can be expressed by the following formula:

[0025]

[0026]

[0027] Where K is the transfer ratio of the rotary transformer 103. For a given rotary transformer 103, the transfer ratio K is a constant. This is because the output voltage V of the primary winding 133... sin Depend on Amplitude modulation is performed, therefore the primary winding 133 is also referred to as the sine winding of the resolver 103. Similarly, the secondary winding 135 is also referred to as the cosine winding of the resolver 103. In the example shown, the output voltage V sin yes Figure 1 The output signal is 104A, and the output voltage is V. cos yes Figure 1 The output signal is 104B.

[0028] Note the angle of the motor shaft. It is actually a time-varying signal and can be represented by the following formula: Where ω m It is the angular frequency of the motor shaft. However, the sinusoidal signal V in angular frequency ω c It was chosen to be an angular frequency ω much higher than that of the motor shaft. m (For example, ω) c >>ω m And therefore, in the period T of the sinusoidal signal (T=2π / ω) c During this period, the angle of the motor shaft changes very little and can be considered constant. As will be discussed in more detail below, the signal processing of the resolver decoder 130 processes the output voltage V within one period T (also called a cycle) of the sinusoidal signal. sin and V cos The digital samples. Therefore, for the purposes of signal processing performed by the resolver decoder 130, the angle of the motor shaft can be considered a constant (e.g., constant within each cycle T), and is expressed as a constant angle in the equation below. To simplify the analysis.

[0029] Figure 3 The input signal V of the resolver 103 in one embodiment is shown. in and output signal V sin and V cos .also, Figure 3 The modulated input signal V is further illustrated. in Amplitude of motor shaft angle Figure 3 The three sub-graphs at the top show the signal V respectively. in V sin and V cos . Figure 3 The bottom subplot shows the axis angle. The x-axis of the subplot is aligned and represents time, while the y-axis represents the signal value. Figure 3 Curve 301 in the figure shows the modulated sine wave signal V. sin The envelope follows a slowly changing modulation signal. The shape. Similarly, Figure 3 Curve 303 in the figure shows the modulated sine wave signal V. cos The envelope follows a slowly changing modulation signal. The shape.

[0030] Refer again Figure 1 Excitation voltage V in Generated by excitation circuit 105, which may be or include a low-pass filter. Excitation circuit 105 accepts a pulse width modulation (PWM) signal generated by PWM circuit 107 as input. PWM circuit 107 (also referred to as a PWM peripheral device) is controlled by CPU 109 and generates a PWM pulse sequence, which is processed (e.g., filtered) by excitation circuit 105 into a sine wave signal V. in .

[0031] Still referencing Figure 1The output signals 104A and 104B from the resolver 103 are processed by a buffer circuit 119. The buffer circuit 119 performs signal conditioning functions, such as modifying / removing the offset (e.g., DC level) of the output signals 104A and 104B, and / or voltage conversion. For example, the voltages of the output signals 104A and 104B may have amplitudes between approximately 17V and approximately 20V. The buffer circuit 119 converts (e.g., scales) the amplitudes of the output signals 104A and 104B to a voltage range compatible with the analog-to-digital converter (ADC) circuit 117, such as between approximately 3V and approximately 5V. The outputs of the buffer circuit 119 are signals 106A and 106B, which may be scaled versions of signals 104A and 104B, respectively. In other words, signal 106A is signal 104A processed by the buffer circuit 119, and signal 106B is signal 104B processed by the buffer circuit 119.

[0032] The output of buffer circuit 119 is sent to resolver decoder 130 (also known as digital resolver decoder or resolver decoder circuit). Based on digital samples of signals 106A and 106B, resolver decoder 130 generates the angle of the motor shaft. Estimated angle like Figure 1 As shown, the resolver decoder 130 includes an analog-to-digital converter (ADC) circuit 117, a filter circuit 115, a hardware rectifier 113, and an angle calculation circuit 111. The ADC circuit 117 converts signals 106A and 106B into digital samples. The filter circuit 115 calculates a first weighted sum of the digital samples of signal 106A over a predetermined time period (e.g., duration T / 2), and calculates a second weighted sum of the digital samples of signal 106B over a predetermined time period (e.g., duration T / 2), wherein the predetermined time period is within the range of the sinusoidal signal sin(ω). c The hardware rectifier 113 adjusts the signs of the first and second weighted sums based on whether the predetermined time period falls within the first or second half of the period T of the sine wave signal. The output of the hardware rectifier 113 is sent to the angle calculation circuit 111 to obtain the angle. Angle of the motor shaft The estimate. The following will refer to... Figure 4 , Figure 5 , Figure 6 Let's discuss more details.

[0033] In some embodiments, the angle calculation circuit 111 is omitted in the resolver decoder 130, and the function of the angle calculation circuit 111 is performed by the CPU 109. In other words, instead of using dedicated hardware (e.g., the angle calculation circuit 111) to calculate the estimated angle... CPU 109 calculates and estimates angle

[0034] In some embodiments, the resolver decoder 130, CPU 109, memory module 108, PWM circuit 107 (if formed), and other peripheral modules of CPU 109 are integrated onto the same semiconductor substrate as a single semiconductor device 150, which may be referred to as processor 150, microcontroller 150 with integrated resolver decoder, or simply microcontroller 150. Compared to solutions where the resolver decoder 130 is implemented in a dedicated semiconductor device (e.g., an application-specific integrated circuit (ASIC)) and the CPU 109 is implemented in another device, the disclosed microcontroller 150 has the advantage of higher integration density (and therefore lower cost) for the motor control system 100. Compared to software solutions where the CPU 109 implements some or all of the functionality of the resolver decoder 130, the disclosed architecture of microcontroller 150 offloads computationally intensive tasks (e.g., the task of calculating the output of filter circuit 115) to hardware circuitry, thus allowing the CPU 109 to reserve more computational resources for other system tasks. As a result, the real-time performance of the motor control system 100 is improved.

[0035] Figure 4 A block diagram of a resolver decoder 130 in one embodiment is shown. Figure 4 The rotary transformer decoder 130 shows a difference compared to Figure 1 More details, and can be used as Figure 1 The rotary transformer decoder 130.

[0036] like Figure 4 As shown, signal 106A (for example, corresponding to V) sin (signal) and 106B (e.g., corresponding to V) cos The signal 106A and 106B are sent to ADC circuit 117 for conversion into digital samples. ADC circuit 117 may include two analog-to-digital converters 118A and 118B, or two input channels 118A and 118B, to synchronously convert signals 106A and 106B. For example, the same sampling clock signal 120 may be used to drive the circuitry (e.g., 118A and 118B) for converting signals 106A and 106B, such that signals 106A and 106B are sampled at the same time. Therefore, digital sample pairs of signals 106A and 106B are sent to filter circuit 115, where two digital samples in each pair are sampled at the same time.

[0037] The filter circuit 115 has two finite impulse response (FIR) filters, 115A and 115B. Digital samples of signal 106A are sent to FIR filter 115A, and digital samples of signal 106B are sent to FIR filter 115B. Details of FIR filters 115A and 115B are provided in... Figure 5 As shown in the image.

[0038] For reference only Figure 5 , Figure 5 A schematic diagram of FIR filters 115A and 115B is shown. (As shown...) Figure 5 As shown, the FIR filter 115A has a tapped delay line (TDL) with multiple delay elements 401, which can be implemented as multiple memory elements connected in series, such as flip-flops. The input of the TDL of the FIR filter 115A is x(n), which is a digital sample of the signal 106A. The TDL has multiple taps, and each tap has a corresponding coefficient 403 (denoted as a). k (k = 0, 1, 2, ..., m), this coefficient is used to scale (e.g., multiply) the value at the tap. In other words, each coefficient 403 represents a value with a corresponding scaling factor a. k The multiplier. The FIR filter 115A also has multiple adders 405, which sum all the scaling values ​​to generate the output of the FIR filter 115A. Therefore, the FIR filter 115A calculates a weighted sum of the digital samples at the input of TDL and in the delay element 401. The FIR filter 115B has the same structure as the FIR filter 115A, but is used to process the input data y(n), which is a digital sample of the signal 106B. Furthermore, the filter coefficients 403 of the FIR filter 115B are represented as b. k k = 0, 1, 2, ..., m, which can be independent of the coefficients a of the FIR filter 115A. k To select. The outputs of FIR filters 115A and 115B are given by the following formula:

[0039]

[0040]

[0041] In the illustrated embodiment, the sampling frequency f of the ADC circuit 117 is... s Selected as the sinusoidal signal sin(ω) c The frequency f of t) c Several orders of magnitude higher (e.g., 10 times, 20 times, 100 times or more), where f c =ω c In the example embodiment, f(2π) s with f cThe ratio between them is chosen to be 2N, where N is a positive integer (e.g., N≥10), such as 10, 20, or 100. This means that for a sinusoidal signal Sin(ω... c For each period T of t), 2N digital samples are generated for signal 106A and 2N digital samples are generated for signal 106B. Furthermore, the number of taps m+1 of the FIR filters 115A / 115B is chosen such that the duration covered by the TDL of each FIR filter is equal to or less than half of period T, or equivalently, m≤N.

[0042] In some embodiments, filter coefficient a k and b k The value is selected as 1, so that FIR filters 115A and 115B can be easily calculated over time mT. s The sum of all numerical samples in the range, where T s =1 / f s This is the sampling period of the ADC circuit 117. The earliest digital sample in the TDL of the FIR filter 115A (or 115B) (e.g., the digital sample stored in the rightmost delay element 401 of the TDL) corresponds to the signal 106A (or 106B) in the sinusoidal signal sin(ω). c When sampling at the beginning of the period T (e.g., t = 0) of the sine wave signal, the output of the FIR filter 115A (or 115B) is the sum of digital samples set within the first half of the period T of the sine wave signal. Specifically, when m = N, the digital samples stored in the tapped delay lines of the FIR filter 115A (or 115B) exactly cover the first half of the period T of the sine wave signal. This is because the sampling frequency f... s Much higher than the sinusoidal signal sin(ω) c The frequency f of t) c The outputs of FIR filters 115A and 115B in equations (3) and (4) respectively provide approximate values ​​for the following integrals:

[0043]

[0044]

[0045] For similar reasons, when the oldest digital sample stored in the tapped delay line of FIR filter 115A (or 115B) corresponds to signal 106A (or 106B) in the sinusoidal signal sin(ω c When a sample is taken at the midpoint of the period T (e.g., t = T / 2) of t), the outputs of filters 115A and 115B in equations (3) and (4) provide approximations of the following integral values:

[0046]

[0047]

[0048] Note that, for simplicity, the integral values ​​in equations (5) and (6) (and (7) and (8)) omit the positive scaling factor, which is determined by, for example, the positive values ​​A and K in equations (1) and (2), and the scaling factor of buffer circuit 119. As will be discussed below, the positive scaling factor in the integral values ​​in equations (5) and (6) or (7) and (8) will not change the result of the angle calculation performed later.

[0049] Think back, in Figure 1 In the middle, the excitation circuit 105 is used to generate a sinusoidal signal sin(ω). c The PWM pulse of t) is generated under the control of CPU 109. Therefore, CPU 109 knows the sine wave signal sin(ωt). c The timing of t), such as the sinusoidal signal sin(ω) c The starting point (e.g., t = 0), midpoint (e.g., t = T / 2), or ending point (e.g., t = T) of the period T of the amplitude-modulated sine wave signal. Additionally, the time delay introduced by the resolver 103, buffer circuit 119, and ADC circuit 117 is a fixed value and is known or can be measured, for example, through a calibration process. Therefore, the CPU 109 (or PWM circuit 107) knows the timing information of the digital samples (also called data samples) fed into the FIR filters 115A / 115B, such as which digital sample corresponds to the starting point, midpoint, or ending point within the period T of the amplitude-modulated sine wave signal. For example, the digital samples x(n) and y(n) at the input of the FIR filters 115A / 115B corresponding to the starting point of the period T of the amplitude-modulated sine wave signal can be identified by counting a predetermined number of clock cycles (corresponding to a predetermined time delay) from the known starting point of the sine wave signal at the output of the excitation circuit 105.

[0050] Figure 1 A control signal path 123 from the PWM circuit 107 to the hardware rectifier 113 is shown. In some embodiments, the control signal path 123 is used to send timing information of data samples, such as pulses, indicating that the current data samples x(n) and y(n) at the inputs of the FIR filters 115A / 115B are samples corresponding to the midpoint of the period T, or equivalently, samples corresponding to angle π within a 2π period of a sinusoidal signal. Timing such as the pulses discussed above is used to indicate that the current output of the FIR filters 115A / 115B corresponds to an integral value between angle 0 and π (e.g., equations (5) and (6)), or an integral value between angle π and 2π (e.g., equations (7) and (8)). Although Figure 1The timing information is shown to be sent from the PWM circuit 107 to the hardware rectifier 113, but the timing information can also be sent from the CPU 109 to the hardware rectifier 113.

[0051] Note the integral value V in equations (5) and (6). sin and V cos They provided by Scaling and A scaled-down version, It has a positive value because Angles between 0 and π have positive values. Similarly, the integral value V in equations (7) and (8) has a positive value. sin and V cos They provided by Scaling and A scaled-down version, It has negative values ​​because Angles between π and 2π have negative values. The negative proportionality factor in the integrals of equations (7) and (8) may lead to... and To calculate the estimated axis angle Errors may occur. Therefore, in some embodiments, the integral values ​​of equations (7) and (8) are adjusted (e.g., corrected) by multiplying by a value of -1 or equivalently by changing (or reversing) the signs of the integral values ​​of equations (7) and (8).

[0052] Refer again Figure 4 When the output of the FIR filter 115A / 115B corresponds to the integral value of equations (7) and (8), or equivalently, when the data sample stored in the tap delay line of the FIR filter 115A / 115B is a data sample in the latter half of the period T of the amplitude-modulated sine wave signal (e.g., between the angle π and 2π), the hardware rectifier 113 corrects the output of the FIR filter 115A / 115B by multiplying by a value of -1, for example, using multipliers 601 (e.g., 601A and 601B). Conversely, when the output of the FIR filter 115A / 115B corresponds to the integral values ​​of equations (5) and (6), or equivalently, when the data sample stored in the tap delay line of the FIR filter 115A / 115B is a data sample in the first half of the period T of the amplitude-modulated sine wave signal (e.g., between the angle 0 and π), the hardware rectifier 113 passes the output of the FIR filter 115A / 115B, for example, by multiplying it by the value 1.

[0053] The symbol table 603 of the hardware rectifier 113 tracks the sign of the output of the FIR filters 115 / 117. In other words, the symbol table 603 determines whether the multiplication value is 1 or -1 for multiplication with the output of the FIR filters 115A / 115B. As described above, the control signal path 123 sends timing information of the data samples, or equivalently, timing information about whether the output of the FIR filters 115A / 115B corresponds to equations (5) and (6) or to equations (7) and (8). For example, the control signal path 123 may send a so-called "zero-crossing pulse" every half period T, which indicates whether the current output of the FIR filters 115A / 115B corresponds to equations (5) and (6) or to equations (7) and (8). In some embodiments, the symbol table 603 starts with the multiplication value 1 and toggles the multiplication value between 1 and -1 each time a zero-crossing pulse is received. Therefore, in the illustrated embodiment, the hardware rectifier 113 multiplies the output of the FIR filters 115A / 115B by a value of 1 or -1 every half-cycle T, such that the output of the hardware rectifier 113 is always scaled by a proportional factor. and The value of .

[0054] Still referencing Figure 4 The output of hardware rectifier 113 is sent to angle calculation circuit 111, which performs arctangent function and post-processing to calculate the angle. Estimated angle Specifically, the angle calculation circuit 111 calculates the first angle α using the following formula.

[0055]

[0056] In some embodiments, as a low-cost solution, the arctangent function is implemented as a lookup table (LUT), where the computation... The value of the arctangent function is used as the index of the LUT to calculate the value of the arctangent function. Note that the angle α calculated by the arctangent function is between -π / 2 and π / 2, while the angle of the motor shaft... Between 0 and 2π. Post-processing is performed based on the angle. Quadrant calculation to estimate angle angle The quadrants are composed of and The sign is determined. For example, if based on and Symbols, angles In the first quadrant, then If angle In the second quadrant, then If angle In the third quadrant, then If angle In the fourth quadrant, then Then estimate the angle The signal is sent to CPU 109. CPU 109 can determine the drive voltage of motor 101 based on the motor control algorithm, so that motor 101 is controlled in a closed-loop control mode.

[0057] Those skilled in the art will readily understand that the CPU 109 can generate a continuous sinusoidal signal over multiple time periods during the operation of the motor 101. The above processing is repeated for each period T of the sinusoidal signal (which generates an estimated angle for each half-cycle of the sinusoidal signal). This allows the CPU 109 to obtain the motor shaft angle at twice the period of the sine wave signal. The updated estimate.

[0058] The disclosed FIR filters 115A / 115B integrate (e.g., add) the amplitude-modulated sine wave signal over the first or second half of the period T of the sine wave signal, which has the effect of improving... and The calculated values ​​(e.g., signal-to-noise ratio (SNR)) of the scaled version have advantages in quality. This is because, in a practical system, the output voltage V of the resolver 103... sin and V cos The presence of noise (e.g., random noise) degrades the quality of the output voltage. Integral operations (see equations (5) and (6), or (7) and (8)) average the random noise, thereby reducing the noise power without affecting the value being calculated. and This has an adverse effect. Compared to the method of directly using each pair of digital samples from ADC circuit 117 to calculate the arctangent, the disclosed processing provides an estimated angle. Significantly improved accuracy.

[0059] In the above discussion, the coefficients of FIR filters 115A / 115B were set to a value of 1 for simplicity. However, the coefficients of FIR filters 115A / 115B can be chosen to different values ​​to improve performance. For example, digital samples corresponding to angles close to 0, π, and 2π of a sine wave signal have smaller amplitudes, and due to random noise in the system, the quality of these digital samples (e.g., lower SNR) is lower than that of digital samples corresponding to angles close to π / 2 or 3π / 2. Therefore, it may be advantageous to assign smaller weights (e.g., filter coefficients with smaller values) to digital samples with lower quality (e.g., close to the zero-crossing positions of a sine wave signal) and higher weights to digital samples with higher quality (e.g., close to the maximum position of a sine wave signal). Figure 6 The weighting strategy for improving the output quality of FIR filters 115A and 115B is shown.

[0060] refer to Figure 6 The tap coefficients of the FIR filter 115A (or 115B) (see example...) Figure 6 a1, a2, ..., a k The amplitude of the tap coefficient is chosen to be equal to or proportional to the value of the sinusoidal signal at the position corresponding to the position of the filter tap. For example, the amplitude of the tap coefficient follows the envelope of the sinusoidal signal (e.g., the envelope at half the period T).

[0061] Figure 7A and 7B Another strategy for allocating tap coefficients to the FIR filter 115AA (or 115B) is shown. Figure 7A and 7B In the example, the tap coefficients do not follow the envelope of the sinusoidal signal, but the tap coefficients are still large for digital samples of the resolver output signal with a large amplitude, and small for digital samples of the resolver output signal with a small amplitude. For example, the tap coefficients can be calculated by convolving vector A with itself, where the values ​​in vector A follow the envelope of the sinusoidal signal (e.g., in half of the period T). Figure 7A Example vector A = [0.309 0.588 0.809 0.951 1.000 0.951 0.809 0.588 0.309]. The tap coefficients, represented by vector B, are the convolution of vector A with itself (e.g., B = A * A). For the example vector A above, the corresponding tap coefficients are B = [0.019 0.073 0.169 0.308 0.478 0.660 0.828 0.951 1.000 0.951 0.828 0.660 0.478 0.308 0.169 0.073 0.019]. Figure 7B The tap coefficient B was plotted. From Figure 7B As can be seen, the convolution of this vector A has a bell shape, which highlights (e.g., amplifies) the central portion and attenuates (e.g., reduces) the tail portion (e.g., the portion at the edge of the bell). This further improves the output quality of FIR filters 115A and 115B.

[0062] Figure 8 Another tap coefficient allocation strategy is shown. Figure 8 In the middle, only the filter taps corresponding to the positions around the peak of the sine wave signal (see...) Figure 8In the calculation, the central region (Δα) around the peak of the sinusoidal signal is assigned a non-zero value, and the filter taps outside the central region (e.g., near the zero-crossing position) are assigned a zero value. In other words, only digital samples with high SNR are used in the calculation.

[0063] Although the integrals in equations (5) and (6) (or (7) and (8)) cover the entire first half or the entire second half of the period T of the sinusoidal signal, those skilled in the art will readily understand that these are merely non-limiting examples. The integration range, or equivalently, the span of the tapped delay line in the FIR filter 115A / 115B, need not cover the entire first half or the entire second half of the period T of the sinusoidal signal. Instead, the tapped delay line in the FIR filter 115A / 115B may cover only a portion of the first half or the second half of the period T of the sinusoidal signal.

[0064] Figure 9 A flowchart of a method 1000 for operating a resolver decoder circuit according to some embodiments is shown. It should be understood that... Figure 9 The illustrated embodiments are merely examples of many possible embodiments. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, additions, removals, replacements, rearrangements, and repetitions may be made. Figure 9 The various steps shown.

[0065] refer to Figure 9 In box 1010, a first analog signal from the sinusoidal winding of the resolver is converted into a first data sample. In box 1020, a second analog signal from the cosine winding of the resolver is converted into a second data sample. In box 1030, a first weighted sum of the first data samples over a predetermined time period is calculated. In box 1040, a second weighted sum of the second data samples over the predetermined time period is calculated. In box 1050, the first sign of the first weighted sum and the second sign of the second weighted sum are adjusted based on the position of the predetermined time period within the period of the sine wave signal. In box 1060, after this adjustment, the first weighted sum is divided by the second weighted sum to obtain a value. In box 1070, the arctangent of this value is determined to obtain the angle.

[0066] The disclosed embodiments can achieve advantages. For example, filter circuit 115 calculates a weighted sum of the output signals from resolver 103 to obtain... and A scaled version. The averaging effect of filter circuit 115 reduces noise in the output of filter circuit 115, thereby improving the estimation of the motor shaft angle. Furthermore, filter coefficients can be assigned to follow the amplitude of the sine wave signal, thus assigning higher weights to the resolver output signal with a larger amplitude. This also improves the accuracy of the motor shaft angle estimation. By performing an integration operation over a duration of half a period T of the sine wave signal, the sign of the output of the integration operation can be easily adjusted by hardware rectifier 113. Compared to integration over the entire period T (where each data sample in the latter half of period T needs to be multiplied by -1), the disclosed structure allows the use of a low-complexity hardware rectifier 113. The disclosed resolver decoder 130 provides a low-cost hardware solution that can be integrated with CPU 109. The hardware resolver decoder 130 performs computationally intensive operations such as FIR filtering, which offload these tasks from CPU 109, thereby improving the real-time performance of the motor control system.

[0067] Exemplary embodiments of the invention are summarized herein. Other embodiments may also be understood from the full contents of the specification and the claims set forth herein.

[0068] Example 1. In one embodiment, a resolver decoder circuit includes: a first filter circuit configured to calculate a first weighted sum of a first digital signal over a predetermined time period, wherein the first digital signal includes a first digital sample of a first analog signal from a first primary winding of a resolver; a second filter circuit configured to calculate a second weighted sum of a second digital signal over the predetermined time period, wherein the second digital signal includes a second digital sample of a second analog signal from a second secondary winding of the resolver, wherein the first analog signal and the second analog signal are configured to be induced by a sinusoidal signal applied to an input winding of the resolver; and a rectifier configured to generate a first output and a second output by adjusting a first sign of the first weighted sum and adjusting a second sign of the second weighted sum, respectively.

[0069] Example 2. The resolver decoder circuit according to Example 1, wherein the rectifier has an input terminal configured to receive a control signal indicating whether the predetermined time period corresponds to the first half or the second half of the period of the sine wave signal.

[0070] Example 3. The resolver decoder circuit according to Example 2, wherein the rectifier is configured to: reverse the first sign of the first weighted sum and the second sign of the second weighted sum when the control signal indicates that the predetermined time period corresponds to the latter half of the period of the sine wave signal; and keep the first sign of the first weighted sum and the second sign of the second weighted sum unchanged when the predetermined time period corresponds to the first half of the period of the sine wave signal.

[0071] Example 4. The resolver decoder circuit according to Example 1 further includes an analog-to-digital converter (ADC) circuit, wherein the ADC circuit is configured to sample the first analog signal and the second analog signal using the same sampling clock signal.

[0072] Example 5. The resolver decoder circuit according to Example 1 further includes an angle calculation circuit, wherein the angle calculation circuit is configured to: calculate the ratio between the first output of the rectifier and the second output of the rectifier; and determine a first angle by performing an arctangent function on the ratio.

[0073] Example 6. A rotary transformer decoder circuit according to Example 5, wherein the first stage winding of the rotary transformer is a sine winding and the second stage winding of the rotary transformer is a cosine winding.

[0074] Example 7. The rotary transformer decoding circuit according to Example 5, wherein the angle calculation circuit is further configured to: determine the quadrant of the angle indicated by the first analog signal and the second analog signal based on the signs of the first output and the second output of the rectifier; and determine the angle indicated by the first analog signal and the second analog signal by adjusting the first angle based on the determined quadrant.

[0075] Example 8. A resolver decoder circuit according to Example 1, wherein each of the first filter circuit and the second filter circuit includes: an input terminal; an output terminal; a tapped delay line (TDL) coupled to the input terminal and having taps, wherein each tap of the TDL has a corresponding weighting factor; and a plurality of adders configured to generate a weighted sum of digital values ​​at the taps of the TDL at the output terminal.

[0076] Example 9. The resolver decoder circuit according to Example 8, wherein the weighting factors of the TDL are equal.

[0077] Example 10. A resolver decoder circuit according to Example 8, wherein the weighting factors of the TDL are different.

[0078] Example 11. A resolver decoder circuit according to Example 10, wherein the magnitude of the weighting factor of the TDL follows the envelope of the sinusoidal signal.

[0079] Example 12. In one embodiment, a processor having an integrated resolver decoder circuit, the processor comprising: an analog-to-digital converter (ADC) circuit configured to: generate a first digital sample by converting a first analog signal from a sinusoidal winding of a resolver, and generate a second digital sample by converting a second analog signal from a cosine winding of the resolver, the first analog signal and the second analog signal being generated by exciting an input winding of the resolver with a sinusoidal signal; a first tapped delay line (TDL) filter coupled to the ADC circuit and configured to compute a first weighted sum of the first digital samples over a predetermined time period; a second TDL filter coupled to the ADC circuit and configured to compute a second weighted sum of the second digital samples over the predetermined time period; a rectifier configured to generate a first output and a second output by respectively adjusting a first sign of the first weighted sum and a second sign of the second weighted sum; and a central processing unit (CPU) coupled to the rectifier.

[0080] Example 13. The processor according to Example 12, wherein the rectifier is configured to adjust the first sign of the first weighted sum and the second sign of the second weighted sum in such a way that: if the sine wave signal has a negative value during the predetermined time period, the first sign of the first weighted sum and the second sign of the second weighted sum are reversed; and if the sine wave signal has a positive value during the predetermined time period, the first sign of the first weighted sum and the second sign of the second weighted sum are kept unchanged.

[0081] Example 14. The processor according to Example 12, wherein the ADC circuitry is configured to synchronously generate the first digital sample and the second digital sample.

[0082] Example 15. The processor according to Example 12, wherein the first TDL filter has a first weighting factor for scaling the first digital sample at a first moment within the predetermined time period, wherein at least some of the first weighting factors are proportional to the amplitude of the sine wave signal at the first moment within the predetermined time period.

[0083] Example 16. A processor according to Example 12, wherein the CPU is configured to: determine a quadrant of an angle indicated by the first analog signal and the second analog signal based on the first output and the second output of the rectifier; divide the first output of the rectifier by the second output of the rectifier to obtain a first value; perform an arctangent function on the first value to obtain a first angle; and adjust the first angle based on the determined quadrant to obtain an estimate of the angle indicated by the first analog signal and the second analog signal.

[0084] Example 17. A processor according to Example 16, wherein the CPU is configured to use a lookup table to execute the arctangent function.

[0085] Example 18. In one embodiment, a method of operating a resolver decoder circuit, the method comprising: converting a first analog signal from a sinusoidal winding of a resolver into a first data sample; converting a second analog signal from a cosine winding of the resolver into a second data sample; calculating a first weighted sum of the first data samples over a predetermined time period; calculating a second weighted sum of the second data samples over the predetermined time period; adjusting a first sign of the first weighted sum and a second sign of the second weighted sum based on the position of the predetermined time period within the period of the sinusoidal signal; after the adjustment, dividing the first weighted sum by the second weighted sum to obtain a value; and determining the arctangent of the value to obtain an angle.

[0086] Example 19. The method according to Example 18, wherein adjusting the first sign of the first weighted sum and the second sign of the second weighted sum comprises: reversing the first sign of the first weighted sum and the second sign of the second weighted sum when the predetermined time period is in the latter half of the period of the sine wave signal; and keeping the first sign of the first weighted sum and the second sign of the second weighted sum unchanged when the predetermined time period is in the first half of the period of the sine wave signal.

[0087] Example 20. The method according to Example 18, wherein the first analog signal and the second analog signal are synchronously converted into digital samples using an analog-to-digital converter circuit.

[0088] Although the invention has been described with reference to illustrative embodiments, this specification is not intended to be limiting. Referring to this specification, those skilled in the art will clearly understand various modifications and combinations of the illustrative embodiments and other embodiments of the invention. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A rotary transformer decoder circuit, comprising: A first filter circuit is configured to calculate a first weighted sum of a first digital signal over a predetermined time period, wherein the first digital signal includes a first digital sample of a first analog signal from the first winding of a rotary transformer. A second filter circuit is configured to calculate a second weighted sum of a second digital signal over the predetermined time period, wherein the second digital signal includes a second digital sample of a second analog signal from the second stage winding of the rotary transformer, wherein the first analog signal and the second analog signal are configured to be induced by a sinusoidal signal applied to the input winding of the rotary transformer. as well as The rectifier is configured to generate a first output and a second output by respectively adjusting the first sign of the first weighted sum and adjusting the second sign of the second weighted sum. Each of the first filter circuit and the second filter circuit includes: Input terminals; Output terminals; A tapped delay line TDL, coupled to the input terminal and having taps, wherein each tap of the TDL has a corresponding weighting factor; and Multiple adders are configured to generate a weighted sum of the digital values ​​at the taps of the TDL at the output terminal.

2. The rotary transformer decoder circuit of claim 1, wherein the rectifier has an input terminal configured to receive a control signal indicating whether the predetermined time period corresponds to the first half of the period of the sine wave signal or the second half of the period of the sine wave signal.

3. The rotary transformer decoder circuit according to claim 2, wherein the rectifier is configured as follows: When the control signal indicates that the predetermined time period corresponds to the latter half of the period of the sine wave signal, the first sign of the first weighted sum and the second sign of the second weighted sum are reversed; and When the predetermined time period corresponds to the first half of the period of the sine wave signal, the first sign of the first weighted sum and the second sign of the second weighted sum remain unchanged.

4. The resolver decoder circuit of claim 1 further includes an analog-to-digital converter (ADC) circuit, wherein the ADC circuit is configured to sample the first analog signal and the second analog signal using the same sampling clock signal.

5. The rotary transformer decoder circuit according to claim 1, further comprising an angle calculation circuit, wherein the angle calculation circuit is configured to: Calculate the ratio between the first output of the rectifier and the second output of the rectifier; and The first angle is determined by applying the arctangent function to the ratio.

6. The rotary transformer decoder circuit according to claim 5, wherein the first stage winding of the rotary transformer is a sine winding, and the second stage winding of the rotary transformer is a cosine winding.

7. The rotary transformer decoder circuit according to claim 5, wherein the angle calculation circuit is further configured to: Based on the signs of the first and second outputs of the rectifier, determine the quadrant of the angle indicated by the first and second analog signals; and The angle indicated by the first analog signal and the second analog signal is determined by adjusting the first angle based on the determined quadrant.

8. The rotary transformer decoder circuit according to claim 1, wherein the weighting factors of the TDL are equal.

9. The rotary transformer decoder circuit according to claim 1, wherein the weighting factors of the TDL are different.

10. The rotary transformer decoder circuit of claim 9, wherein the magnitude of the weighting factor of the TDL follows the envelope of the sinusoidal signal.

11. A processor having an integrated resolver decoder circuit, the processor comprising: The analog-to-digital converter (ADC) circuit is configured as follows: The first digital sample is generated by converting the first analog signal from the sinusoidal winding of the resolver. A second digital sample is generated by converting a second analog signal from the cosine winding of the rotary transformer, wherein the first analog signal and the second analog signal are generated by exciting the input winding of the rotary transformer with a sine wave signal; A first tap delay line (TDL) filter is coupled to the ADC circuit and configured to calculate a first weighted sum of the first digital samples over a predetermined time period; A second TDL filter is coupled to the ADC circuit and configured to calculate a second weighted sum of the second digital samples over the predetermined time period; The rectifier is configured to generate a first output and a second output by respectively adjusting the first sign of the first weighted sum and the second sign of the second weighted sum; as well as The central processing unit (CPU) is coupled to the rectifier.

12. The processor of claim 11, wherein the rectifier is configured to adjust the first sign of the first weighted sum and the second sign of the second weighted sum in such a way that: If the sinusoidal signal has a negative value during the predetermined time period, then the first sign of the first weighted sum and the second sign of the second weighted sum are reversed; and If the sinusoidal signal has a positive value during the predetermined time period, then the first sign of the first weighted sum and the second sign of the second weighted sum remain unchanged.

13. The processor of claim 11, wherein the ADC circuitry is configured to synchronously generate the first digital sample and the second digital sample.

14. The processor of claim 11, wherein the first TDL filter has a first weighting factor for scaling the first digital sample at a first moment within the predetermined time period, wherein at least some of the first weighting factors are proportional to the amplitude of the sine wave signal at the first moment within the predetermined time period.

15. The processor of claim 11, wherein the CPU is configured to: Based on the first output and the second output of the rectifier, determine the quadrant of the angle indicated by the first analog signal and the second analog signal; Divide the first output of the rectifier by the second output of the rectifier to obtain a first value; Apply the arctangent function to the first value to obtain the first angle; and The first angle is adjusted based on the determined quadrant to obtain an estimate of the angle indicated by the first analog signal and the second analog signal.

16. The processor of claim 15, wherein the CPU is configured to use a lookup table to execute the arctangent function.

17. A method of operating a resolver decoder circuit, the method comprising: The first analog signal from the sinusoidal winding of the rotary transformer is converted into a first data sample; The second analog signal from the cosine winding of the rotary transformer is converted into a second data sample; Calculate the first weighted sum of the first data sample over the predetermined time period; Calculate the second weighted sum of the second data sample over the predetermined time period; Based on the position of the predetermined time period within the period of the sine wave signal, adjust the first sign of the first weighted sum and the second sign of the second weighted sum; After the adjustment, the first weighted sum is divided by the second weighted sum to obtain the value; as well as Determine the arctangent of the value to obtain the angle.

18. The method of claim 17, wherein adjusting the first sign of the first weighted sum and the second sign of the second weighted sum comprises: When the predetermined time period is within the latter half of the period of the sine wave signal, the first sign of the first weighted sum and the second sign of the second weighted sum are reversed; as well as When the predetermined time period is within the first half of the period of the sine wave signal, the first sign of the first weighted sum and the second sign of the second weighted sum remain unchanged.

19. The method of claim 17, wherein the first analog signal and the second analog signal are synchronously converted into digital samples using an analog-to-digital converter circuit.

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