Storage controller, storage control method, solid state disk, and storage system

Abstract

A storage controller, a storage control method, a solid state disk and a storage system, the storage controller comprising: a processor, and a first interface and a memory respectively coupled to the processor. The first interface is configured to receive a data write instruction, the data write instruction being used to request to write target data to a first logical address. The processor is configured to read a hot spot attribute corresponding to the first logical address from the memory, and when the hot spot attribute indicates that the first logical address is a hot spot address, the processor is further configured to store the target data to a first region of the memory. The first region is used to store data instead of a storage space corresponding to the hot spot address in a flash memory controlled by the storage controller. The storage controller can avoid that some small LBA regions are frequently written, so as to ensure that the service life of the solid state disk is not affected, without the participation of the host side, and the host side does not need to be adapted, so that the coupling degree of the host and the solid state disk can be greatly reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage, in particular to a storage controller, a storage control method, a solid state disk and a storage system. BACKGROUND

[0002] The current storage system can adopt the forms of distributed storage, network-attached storage (NAS), storage area network (SAN) and the like. Among them, the solid state disk (SSD) is applied to the above various storage systems due to the advantages of high bandwidth, low latency and high throughput. In the storage system, the host can access the SSD through the logical block address (LBA) of the flash memory of the SSD. In the process of the host writing data into the flash memory of the SSD, there may be a case that a very small LBA region occupies a very high write proportion. Exemplarily, when a certain database application running on the host side writes data to the SSD, only a block of LBA region of about 16MB occupies about 30% of the total write data amount of the SSD. The life of the SSD is related to the total write number of the LBA. When the total write number of the LBA of the SSD reaches the preset upper limit, the SSD cannot be continuously written, thereby affecting the life of the SSD. Therefore, how to avoid the influence of the LBA total write number of the SSD caused by the fact that some very small LBA region occupies a very high write proportion, and then affect the life of the SSD, is an urgent problem to be solved.

[0003] In the prior art, a data writing method participated by the host is proposed. In the method, the host specifies the namespace corresponding to the LBA region occupying a high write proportion, the SSD extends the namespace function, and for the data needing to be written to a specific namespace, the SSD writes the data into a specific storage medium, such as Dynamic Random Access Memory (DRAM), Magnetic Random Access Memory (MRAM) or Phase change memory (PCM), instead of directly writing into the flash memory, and only when the SSD is powered off, the data in the above specific storage medium is written into the flash memory, thereby avoiding that some very small LBA region is frequently written.

[0004] However, using the method of the prior art, if different hosts need to access the SSD, they all need to be adapted to avoid that some very small LBA region is frequently written when writing data to the SSD, resulting in that the coupling degree of the host and the SSD is too high. SUMMARY

[0005] Embodiments of the present application provide a storage controller, a storage control method, a solid state disk and a storage system, which are used to solve the problem that the existing technology needs host-side adaptation to avoid the problem of too high coupling degree between the host and the SSD caused by frequent writing to the extremely small LBA region.

[0006] In a first aspect, embodiments of the present application provide a storage controller, which comprises a processor and a first interface and a memory coupled to the processor respectively. The first interface is configured to receive a data write instruction, the data write instruction being used to request writing target data to a first logical address. The processor is configured to read a hot spot attribute corresponding to the first logical address from the memory, and in the case that the hot spot attribute indicates that the first logical address is a hot spot address, the processor is further configured to store the target data to a first region of the memory. The first region is used to store data in the storage space corresponding to the hot spot address in the flash memory controlled by the storage controller.

[0007] In the above storage controller, the processor can pre-identify whether each logical address of the flash memory is a hot spot address, and when the processor receives the data write instruction for the hot spot address, the target data to be written to the hot spot address is written to the first region, and the first region is used to store data in the storage space corresponding to the hot spot address in the flash memory controlled by the storage controller. Therefore, the frequent data access to the hot spot address can be performed in the first region, and will not be performed in the flash memory, so that the rapid growth of the total number of SSD writes caused by the frequent access to the extremely small LBA region as the hot spot address can be avoided, and the service life of the SSD is ensured. The above processing process is identified and processed by the SSD based on the access history information of the logical address, and does not need the participation of the host side. Therefore, while avoiding the frequent writing to some extremely small LBA region to ensure the service life of the SSD, the participation of the host side is not needed, and the host side does not need to be adapted, so that the coupling degree between the host and the SSD can be greatly reduced.

[0008] As a possible implementation manner, the processor is configured to read cache state information of the first logical address from the memory, and write the target data to the first region according to the cache state information. The cache state information is used to indicate whether the data of the first logical address already exists in the first region.

[0009] Since the cache state information can accurately indicate whether the data of the first logical address already exists in the first region, writing the target data to the first region based on the cache state information can ensure the correctness of data writing.

[0010] In the possible implementation manner, in a case where the cache status information indicates that the data of the first logical address already exists in the first region, the processor replaces the data of the first logical address already stored in the first region with the target data.

[0011] When the cache status information of the first logical address indicates that the data of the first logical address already exists in the first region, it indicates that the data of the first logical address has existed in the first region before, and thus the replacement operation is performed on the existed data, that is, the target data is written into a position where the data of the first logical address written before is stored in the first region, to cover the data written before, so as to ensure correct writing of the data.

[0012] In the possible implementation manner, in another case where the cache status information indicates that the data of the first logical address does not exist in the first region, the processor writes the target data into the first region, and updates the cache status information of the first logical address to information indicating that the data of the first logical address already exists in the first region.

[0013] If the cache status information of the first logical address indicates that the data of the first logical address does not exist in the first region, it indicates that the data of the first logical address has not been stored in the first region, and thus the target data can be directly written into the first region as the data of the first logical address, so as to ensure correct writing of the data. In addition, after the target data is written into the first region, the cache status information of the first logical address is updated to information indicating that the data of the first logical address already exists in the first region, which indicates that the data of the first logical address has existed in the first region, and thus when the host writes data into the first logical address next time, the controller of the SSD can perform the replacement processing based on the information indicating that the data of the first logical address already exists in the first region, so as to further ensure correct writing of the data.

[0014] As a possible implementation manner, the processor is further configured to update the hot spot attribute of each logical address according to the access history information of each logical address, and write the hot spot attribute of each logical address into the memory.

[0015] As a possible implementation manner, the processor can update the hot spot attribute of each logical address according to the access history information of each logical address and the capacity of the first region.

[0016] The capacity of the first region can be small, and thus determining which logical addresses are hot spot addresses based on the access history information of each logical address and the capacity of the first region can ensure that the number of selected hot spot addresses matches the capacity of the first region. In addition, selecting the hot spot addresses based on the capacity of the first region can make the selection of the hot spot addresses more effective.

[0017] As a possible implementation manner, the processor can count the access history information of each logical address in the solid state disk to obtain the write times of each logical address, and then obtain the hot spot addresses in each logical address according to the write times of each logical address and the capacity of the first area. Further, the hot spot attribute of each logical address is updated according to the hot spot addresses in each logical address.

[0018] The hot spot addresses in each logical address are obtained by using the write times and the capacity of the first area, so that the accuracy of the identified hot spot addresses is higher.

[0019] As a possible implementation manner, if the difference between the number of logical addresses with write times greater than 0 and the capacity of the first area is greater than or equal to a first preset threshold, the processor selects a target logical address as a hot spot address, the target logical address is a logical address with write times greater than or equal to a first preset number, or the target logical address is a preset number of logical addresses with the largest write times after sorting the logical addresses with write times greater than 0 according to the write times.

[0020] If the difference between the number of logical addresses with write times greater than 0 and the capacity of the first area is greater than or equal to a first preset threshold, it indicates that the number of logical addresses with write times greater than 0 is much larger than the capacity of the first area. When this condition is met, the selected hot spot addresses have better effect and can be better matched with the capacity of the first area. When this condition is met, the controller can select the target logical address as a hot spot address.

[0021] As a possible implementation manner, if the difference between the number of logical addresses with write times greater than 0 and the capacity of the first area is greater than or equal to a first preset threshold, the processor selects a target logical address as a hot spot address, the target logical address is a logical address with write times greater than or equal to a first preset number, or the target logical address is a preset number of logical addresses with the largest write times after sorting the logical addresses with write times greater than 0 according to the write times. If the ratio of the sum of the write data amounts of the selected hot spot addresses to the total write data amount of the solid state disk in the statistical period of the access history information is greater than or equal to a second preset threshold, the processor selects the selected hot spot addresses as hot spot addresses.

[0022] This manner can confirm the authenticity of the selected hot spot addresses, thereby further improving the accuracy of the finally determined hot spot addresses.

[0023] In the above possible implementation manner, after obtaining the selected hot spot addresses, if the access times of a first selected hot spot address is greater than a second preset number, the processor selects the first selected hot spot address as a hot spot address, and the first selected hot spot address is any address in the selected hot spot addresses.

[0024] As a possible implementation manner, the processor can update the hot property of each logical address according to the hot address set of the first period and the hot address set of the second period, the first period being a statistical period of the access history information, and the second period being a period before the first period.

[0025] Since the hot address set of the first period and the hot address set of the second period respectively store the hot addresses in the respective periods, based on the two hot address sets, the change of the hot addresses from the second period to the first period can be known, and accordingly the hot property of each logical address can be accurately updated.

[0026] In the possible implementation manner, if the first address belongs to the hot address set of the second period and does not belong to the hot address set of the first period, the processor updates the hot property of the first address as a mark for identifying a non-hot address, the first address being any address in the logical addresses.

[0027] In the possible implementation manner, the processor can also write the data of the first address in the first region into the second region and delete the data of the first address from the first region, and the data stored in the second region is written into the flash memory of the solid state disk according to a preset frequency in a powered-on state of the solid state disk.

[0028] Since the first address no longer belongs to the hot address, the access frequency of the first address is reduced, and therefore, writing the data of the first address into the flash memory via the second region makes the data of the first address no longer occupy the resources of the first region, and meanwhile, does not cause the rapid increase of the total write amount of the flash memory.

[0029] In the possible implementation manner, if the first address belongs to the hot address set of the first period and does not belong to the hot address set of the second period, the processor updates the hot property of the first address as a mark for identifying a hot address.

[0030] In the possible implementation manner, the processor can also update the cache state information of the first address as information indicating that the first region does not store the data of the first logical address.

[0031] When the first address is a hot address, the update frequency of the data of the first address is relatively fast, and therefore, only updating the cache state information of the first address as the information indicating that the first region does not store the data of the first logical address without performing data movement can directly write the data into the first region when the host next sends a write instruction for the first address. Therefore, this manner has low processing complexity, and meanwhile, does not affect the data access of the first address.

[0032] In the possible implementation manner, the processor can also write the data of the first address in the second area into the first area, delete the data of the first address from the second area, and update the cache state information of the first address to information indicating that the data of the first logical address already exists in the first area.

[0033] The data of the first address stored in the second area is the data of the first address needed to be written last time, writing the data of the first address into the first area, i.e., performing data migration, and updating the cache state information of the first address to information indicating that the data of the first logical address already exists in the first area, can ensure that when the host needs to read the data of the first address before the next data write for the first address, the data of the first address can be quickly read from the first area.

[0034] As a possible implementation manner, the processor can sample and count the access history information of each logical address in the solid state disk to obtain the write times of each logical address.

[0035] As a possible implementation manner, if the first logical address is not a hot address, the processor can write the target data into the second area.

[0036] In a second aspect, an embodiment of the present application provides a storage control method, the method being applied to a storage controller, the storage controller comprising a storage, and the method comprising: receiving a data write instruction, the data write instruction being used to request writing target data to a first logical address; reading a hot attribute of the first logical address from the storage; and if the hot attribute indicates that the first logical address is a hot address, storing the target data to a first area of the storage. The first area is used to replace a storage space corresponding to the hot address in a flash memory to cache data to be written to the hot address.

[0037] As a possible implementation manner, the storing of the target data to the first area of the storage comprises:

[0038] reading cache state information of the first logical address from the storage; and according to the cache state information, writing the target data to the first area. The cache state information is used to indicate whether the data of the first logical address already exists in the first area.

[0039] As a possible implementation manner, the writing of the target data to the first area according to the cache state information comprises:

[0040] if the cache state information indicates that the data of the first logical address already exists in the first area, replacing the data of the first logical address already stored in the first area with the target data.

[0041] As a possible implementation manner, the writing of the target data into the first region according to the cache state information comprises:

[0042] If the cache state information indicates that the data of the first logical address does not exist in the first region, the target data is written into the first region, and the cache state information of the first logical address is updated as information indicating that the data of the first logical address has existed in the first region.

[0043] As a possible implementation manner, the method further comprises:

[0044] According to the access history information of each logical address, the hotspot attribute of each logical address is updated, and the hotspot attribute of each logical address is written into the memory.

[0045] As a possible implementation manner, the updating of the hotspot attribute of each logical address according to the access history information of each logical address comprises:

[0046] According to the access history information of each logical address and the capacity of the first region, the hotspot attribute of each logical address is updated.

[0047] As a possible implementation manner, the updating of the hotspot attribute of each logical address according to the access history information of each logical address and the capacity of the first region comprises:

[0048] The access history information of each logical address is counted to obtain the write times of each logical address, the hotspot address in each logical address is obtained according to the write times of each logical address and the capacity of the first region, and the hotspot attribute of each logical address is updated according to the hotspot address in each logical address.

[0049] As a possible implementation manner, the obtaining of the hotspot address in each logical address according to the write times of each logical address and the capacity of the first region comprises:

[0050] If a difference between the number of logical addresses with write times greater than 0 and the capacity of the first region is greater than or equal to a first preset threshold, a target logical address is selected as the hotspot address, the target logical address is a logical address with a write time greater than or equal to a first preset number, or the target logical address is a preset number of logical addresses with the largest write times after the logical addresses with the write times greater than 0 are sorted according to the write times.

[0051] As a possible implementation manner, the obtaining of the hotspot address in each logical address according to the write times of each logical address and the capacity of the first region comprises:

[0052] If a difference between a number of logical addresses with a write-in times greater than 0 and a capacity of the first area is greater than or equal to a first preset threshold, a target logical address is selected as a candidate hot spot address, the target logical address is a logical address with a write-in time greater than or equal to a first preset number of times, or the target logical address is a preset number of logical addresses with a maximum write-in time in a write-in time sequence of a majority of logical addresses with a write-in time greater than 0; if a ratio of a sum of write-in data amounts of the candidate hot spot addresses to a total write-in data amount in a statistical period of the access history information is greater than or equal to a second preset threshold, the candidate hot spot addresses are taken as the hot spot addresses.

[0053] As a possible implementation manner, the method further includes:

[0054] If the first candidate hot spot address access times is greater than a second preset number of times, the first candidate hot spot address is taken as a hot spot address, the first candidate hot spot address is any address in the candidate hot spot addresses.

[0055] As a possible implementation manner, the method further includes:

[0056] According to a hot spot address set of a first period and a hot spot address set of a second period, the hot spot attribute of each logical address is updated, the first period is a statistical period of the access history information, and the second period is a previous period of the first period.

[0057] As a possible implementation manner, the method further includes:

[0058] If the first address belongs to the hot spot address set of the second period and does not belong to the hot spot address set of the first period, the hot spot attribute of the first address is updated to an attribute used for identifying a non-hot spot address, the first address is any address in the logical addresses.

[0059] As a possible implementation manner, the method further includes:

[0060] Data of the first address in the first area is written into a second area, and the data of the first address is deleted from the first area, the second area is used for buffering data to be written into a non-hot spot address.

[0061] As a possible implementation manner, the method further includes:

[0062] If the first address belongs to the hot address set of the first period and does not belong to the hot address set of the second period, the hot attribute of the first address is updated to an attribute for identifying a hot address.

[0063] As a possible implementation, the method further includes:

[0064] The cache state information of the first address is updated to information indicating that the data of the first logical address does not exist in the first region.

[0065] As a possible implementation, the method further includes:

[0066] The data of the first address in the second region is written into the first region, and the data of the first address is deleted from the second region; the cache state information of the first address is updated to information indicating that the data of the first logical address does not exist in the first region.

[0067] As a possible implementation, the access history information of each logical address is counted to obtain the write times of each logical address, including:

[0068] The access history information of each logical address is sampled and counted to obtain the write times of each logical address.

[0069] As a possible implementation, the processor is further configured to:

[0070] When the hot attribute indicates that the first logical address is not a hot address, the target data is stored to a second region of the memory.

[0071] In a third aspect, an embodiment of the present application provides a solid state disk, including a flash memory and a storage controller of the first aspect, the storage controller performing data access on the flash memory through a second interface.

[0072] In a fourth aspect, an embodiment of the present application provides a storage system, including the solid state disk of the third aspect and a host, the solid state disk and the host performing communication based on a first interface of the solid state disk and a host interface of the host.

[0073] In a fifth aspect, an embodiment of the present application provides a computer readable storage medium, the computer readable storage medium storing computer instructions, when the computer instructions are executed, causing the computer to execute the method of the second aspect. BRIEF DESCRIPTION OF DRAWINGS

[0074] Figure 1 A schematic diagram of data access of a traditional database system;

[0075] Figure 2 This is an exemplary system architecture diagram according to an embodiment of this application;

[0076] Figure 3 An interactive flowchart of the storage control method provided in the embodiments of this application;

[0077] Figure 4 This is another exemplary system architecture diagram according to an embodiment of this application;

[0078] Figure 5 This is a flowchart illustrating the storage control method provided in an embodiment of this application. Detailed Implementation

[0079] Figure 1 This is a diagram illustrating data access in a traditional database system, such as... Figure 1 As shown, a shared tablespace, independent of the table files, is set up in the flash memory of this database system; this can be called a double write buffer (DWB). When writing data to the SSD's flash memory, the data to be written is first written to the DWB. After the database system confirms that the data has been successfully written to the DWB, the data is then written to the corresponding data page of the table file. This method can prevent data page corruption in the event of an operating system restart or power failure. Specifically, the DWB and the data pages of the table file are written to different locations on the disk at different times; therefore, the DWB and data pages will not be corrupted simultaneously. Therefore, in the event of an operating system restart or power failure, if the DWB is corrupted, the corrupted data in the DWB can be discarded, while the old data is saved in the data page; if the data page is corrupted, the data page can be recovered using the data saved in the DWB.

[0080] In the storage space of the aforementioned database system, the DWB occupies only a tiny LBA region, approximately 16MB in size. Due to the DWB, this tiny LBA region is frequently written to. Statistics show that this 16MB LBA region accounts for about 30% of the total data written to the storage space. This extremely high write percentage of the tiny LBA region causes a rapid increase in the total number of LBA writes to the SSD, thus significantly impacting the SSD's lifespan.

[0081] To solve the above problems, in a possible design, a host specifies a namespace corresponding to an LBA region with a high write ratio to the SSD in a host-involved manner. For data that needs to be written to the namespace corresponding to the LBA region with a high write ratio, the SSD does not directly write the data to the flash memory, but writes the data to a storage medium such as DRAM, MRAM, or PCM. Only when the SSD is powered off, the data in the storage medium is written to the flash memory, so as to avoid that some small LBA regions are frequently written. Since this design needs the host to specify the namespace corresponding to the LBA region with a high write ratio, before a certain host needs to access the SSD, an adaptation process needs to be performed to support the function of specifying the namespace to the SSD, which causes the high coupling between the host and the SSD.

[0082] In view of the problem of the high coupling between the host and the SSD caused by the host-involved design to avoid that some small LBA regions are frequently written, embodiments of the present application determine whether a logical address is a hot address based on access history information of the logical address from the SSD side, and cache data that needs to be written to the hot address, so as to avoid that some small LBA regions are frequently written while ensuring the service life of the SSD is not affected, without the involvement of the host side, and without the adaptation of the host side, thereby greatly reducing the coupling between the host and the SSD.

[0083] Figure 2 For an exemplary system architecture diagram of embodiments of the present application, as shown in Figure 2 Embodiments of the present application relate to a host and an SSD. A communication connection is established between the host and the SSD, which can be a wired connection or a wireless connection, and embodiments of the present application do not make specific limitations.

[0084] In embodiments of the present application, the host can also be referred to as a client, and the user can read data from the SSD via the host or write data to the SSD. For example, the client software of a certain database system is installed on the host, and the database of the database system is stored in the SSD. The user inputs data to be written to the database on the interface of the client software and instructs to write. The host generates a data write instruction based on the instruction of the user, and sends the data write instruction to the SSD. As shown in Figure 2 For example, the host can send the data write instruction to the first interface on the storage device through the host interface on the host.

[0085] Referring to Figure 2 The SSD can at least include a storage controller and a flash memory. The storage controller can include a processor, and a first interface and a memory coupled to the processor, respectively. In addition, a second interface can also be included.

[0086] The flash memory can be composed of a plurality of flash memory chips. Each flash memory chip includes a plurality of blocks, and each block includes a plurality of pages. When data is written into the flash memory, the data can be written in page units. The storage controller writes data into and reads data from the flash memory through the second interface.

[0087] The first interface of the storage controller is connected to the host side and is configured to receive a data access instruction from the host side. In the embodiments of the present application, the data access instruction can be a data write instruction. The first interface is configured to receive the data write instruction. The processor can be a central processing unit (CPU). The memory can include a volatile memory such as a DRAM, an MRAM, or a PCM, or the memory can also include a non-volatile memory. The processor can receive the data write instruction or other information such as a logical address of a data block from the host through the first interface. The processor can also execute the received data write instruction, for example, write a data block carried in the data write instruction into the flash memory or the memory described above, or read a data block from the flash memory or the memory described above.

[0088] As described above, the first interface of the storage controller can receive a data write instruction from the host side network card. In the embodiments of the present application, the first interface can send the data write instruction to the processor of the storage controller after receiving the data write instruction, and the processor can execute the data write based on the scheme of the embodiments of the present application. Alternatively, the first interface can also send the data write instruction to another processing module in the storage controller after receiving the data write instruction, and the processing module can execute the data write based on the scheme of the embodiments of the present application. Alternatively, the processor and the other processing module can also cooperate to complete the data write. For ease of description, the embodiments of the present application are described below by taking the processor of the storage controller as an example.

[0089] Figure 3 The interaction flowchart of the storage control method provided in the embodiments of the present application is shown in FIG. 3. The interaction process between the host and the SSD includes the following steps. Figure 3

[0090] S301: The host generates a data write instruction.

[0091] As shown in the foregoing examples, in the application scenario of a certain database system, the host side can install a client software of the database system, and the database of the database system is stored in the SSD. When a user needs to write data into the database, the user can input the data to be written and instruct to write on the interface of the client software. The host generates a data write instruction based on the user's instruction.

[0092] ​S302, the host sends a data write instruction to the first interface of the storage controller of the SSD through a host interface on the host.

[0093] Correspondingly, the first interface of the storage controller of the SSD receives the data write instruction from the host interface of the host.

[0094] S303, the processor of the storage controller parses the data write instruction.

[0095] After the first interface receives the data write instruction, the processor reads the data write instruction through the first interface and parses the data write instruction.

[0096] In the embodiment of the application, the above-mentioned data write instruction is used to request to write target data to the first logical address. For example, the above-mentioned data write instruction includes the above-mentioned first logical address and the above-mentioned target data. Therefore, the processor can obtain the above-mentioned first logical address and the target data by parsing the data write instruction.

[0097] It should be understood that the first logical address involved in the embodiment of the application refers to a logical address. Alternatively, the first logical address can refer to LBA.

[0098] As described above, the LBA refers to a logical block address of the flash memory of the SSD, and the host accesses the SSD using the LBA. Inside the SSD, the physical address of the actual data storage is a physical page number (PPN). The PPN is used to indicate a space position of the flash memory. After the data is written into the SSD, the LBA of the data can remain fixed, and the host uses the fixed LBA to access the data of the SSD, while the PPN of the data can change. The LBA and the PPN can be mapped through an FTL table. For example, the host first writes a certain data A into the flash memory of the SSD, the processor of the storage controller allocates an LBA 100 for the data A, and allocates a PPN 100 for the data A. Correspondingly, the processor records the mapping relationship of LBA 100->PPN 100 in the FTL table. When the host needs to read the data in LBA 100, the host provides the address LBA 100 to the SSD, and the processor reads the data A from the PPN 100 based on the mapping relationship of LBA 100->PPN 100 and returns the data A to the host. When the host needs to modify the data A in LBA 100 to data B, the host sends a data write request to the SSD, which can carry the address LBA 100 and the data B. The processor can write the data B into another PPN 420 different from the PPN 100, and correspondingly, the processor modifies the mapping relationship of LBA 100->PPN 100 in the FTL table to the mapping relationship of LBA 100->PPN 420. In this example, the LBA 100 presented to the host by the SSD remains unchanged, and the host always uses the LBA 100 to write or read data, while when the data in the LBA 100 is updated, the actual PPN where the updated data is written changes compared with the PPN where the data before the update is written.

[0099] The embodiment of the present application mainly relates to the processing procedure when the processor writes data into the LBA, and in the specific implementation process, the processor further writes the data into the actual PPN based on the LBA and the mapping relationship of the LBA and the PPN in the FTL table. The processing procedure can refer to the description in the above example, and will not be described again.

[0100] In S304, the processor of the storage controller reads the hot spot attribute of the first logical address from the memory, and determines whether the first logical address is a hot spot address according to the hot spot attribute of the first logical address.

[0101] In the embodiment of the present application, each logical address in the SSD has a hot spot attribute, and the hot spot attribute of each logical address can be obtained based on the access history information of each logical address.

[0102] The logical address in the SSD can refer to a logical address in the flash memory of the SSD. Taking the logical address as an LBA for example, in the embodiments of the present application, each LBA corresponds to a hotspot attribute. The hotspot attribute is used to identify whether an LBA is a hotspot address, so that the processor can determine whether the logical address of the data write instruction is a hotspot address according to the hotspot attribute. It should be understood that when a logical address is a hotspot address, it indicates that the data on the logical address is hotspot data. The following embodiments of the present application are explained and described from the perspective of the hotspot address.

[0103] As an example, the hotspot attribute of the first logical address can be recorded in the FTL table described above. The FTL table is stored in the memory described above. The FTL table records the mapping relationship between each LBA and PPN in the flash memory of the SSD, and the embodiments of the present application can add a hotspot attribute to each LBA in the FTL table on this basis. In an example, the hotspot attribute can be represented by a bit. When the value of the bit is 1, it indicates that the LBA is a hotspot address; when the bit is 0, it indicates that the LBA is not a hotspot address, i.e., a non-hotspot address. When the processor reads the hotspot attribute of the first logical address from the memory, it can find the hotspot attribute of the first logical address in the FTL table stored in the memory.

[0104] Alternatively, the hotspot attribute of each logical address in the SSD can be obtained based on the access history information of each logical address. For example, the access history information of the logical address can include access time, access type (write or read), etc. Based on the access history information of the logical address, the processor can know whether the logical address is frequently accessed, and then identify whether the logical address is a hotspot address.

[0105] The processor can generate the hotspot attribute of each logical address based on the access history information of each logical address in the SSD within a preset time period after the SSD is powered on, and the hotspot attribute can be used as the initial hotspot attribute of each logical address. The access frequency of each logical address can be different at different times, so the processor can also periodically update the hotspot attribute of each logical address according to a certain period. The process of generating the initial hotspot attribute and updating the hotspot attribute by the processor will be described in detail in the following embodiments.

[0106] It should be understood that in the embodiments of the present application, the process of data writing involved in steps S301-S305 and the process of generating the initial hotspot attribute and updating the hotspot attribute described above can be executed independently. When step S304 is executed, the hotspot attribute of the logical address used is the currently recorded hotspot attribute of the logical address in the FTL table.

[0107] S305. If the aforementioned hotspot attribute indicates that the first logical address is a hotspot address, then the aforementioned target data is written into the first region of the memory. This first region is used to store data in place of the storage space corresponding to the hotspot address in the flash memory controlled by the storage controller.

[0108] For example, when the SSD is powered on, the data stored in the first area is not written to the flash memory of the SSD, but only to the first area. The data in the first area is written to the flash memory only when the SSD is powered off.

[0109] Figure 4 This is another exemplary system architecture diagram of an embodiment of this application, such as... Figure 4 As shown above, in the above Figure 2 Based on this, the memory can include: a first region, a second region, and a third region. The third region is used to store the FTL table. When the SSD is powered on, as long as it remains powered on, data in the first region will not be written to the SSD's flash memory. However, data in the second region is continuously written to the flash memory in a specific manner. For example, when the data in the second region reaches a preset percentage of the total storage capacity of the second region, the data in the second region is written to the flash memory once. Additionally, the region storing the FTL table can be used to store the aforementioned FTL table.

[0110] Once the processor identifies the first logical address as a hotspot address, it writes the target data indicated by the aforementioned data write instruction into the first region. Since the data stored in the first region is used to replace the storage space in the flash memory controlled by the storage controller corresponding to the hotspot address, once the data for a given logical address is stored in the first region, subsequent data writes and reads for that logical address can all be performed within the first region. For example, when it is necessary to modify the data at that logical address, the modified data can be written into the first region to replace the original data. Through this process, frequent data access to hotspot addresses can all be performed in the first region. Only under certain conditions, such as when the SSD loses power, will the processor store the data in the first region in the SSD's flash memory. This avoids the rapid increase in the total number of writes to the SSD caused by frequent accesses to the extremely small LBA region of the hotspot address, thus ensuring that the SSD's lifespan is not affected.

[0111] In another scenario, once the processor identifies that the first logical address is not a hotspot address, it writes the aforementioned target data into the second region.

[0112] When the first logical address is not a hot address, it indicates that the first logical address will not be frequently accessed, and thus the target data can be written into the second region. When the second region satisfies the aforementioned write condition, the processor writes the data in the second region into the flash memory. Since the first logical address will not be frequently accessed, the data of the first logical address will not cause the rapid increase of the total number of SSD writes after being written into the flash memory.

[0113] S306, the processor sends response information to the host interface of the host through the first interface.

[0114] The response information can be used to indicate that the writing is successful.

[0115] Correspondingly, the host can output response information indicating that the writing is successful to the user based on the above-mentioned response information.

[0116] In this embodiment, the processor can pre-identify whether each logical address of the flash memory is a hot address. When the processor receives a data write instruction for a hot address, the target data to be written to the hot address is written into the first region. The first region is used to replace the storage space corresponding to the hot address in the flash memory controlled by the storage controller to store data. Therefore, frequent data access to the hot address can be performed in the first region, and will not be performed in the flash memory. Therefore, the rapid increase of the total number of SSD writes caused by frequent access to the extremely small LBA region as the hot address can be avoided, and the life of the SSD is not affected. The above-mentioned processing process is processed by the SSD, and does not require the participation of the host side. Therefore, while avoiding the frequent writing of some extremely small LBA regions to ensure the life of the SSD is not affected, the host side does not need to participate, and the host side does not need to be adapted. Therefore, the coupling degree of the host and the SSD can be greatly reduced.

[0117] As described above, the hot attribute of the logical address can be obtained based on the access history information of the logical address. Since the access history information of the logical address can reflect whether the logical address is frequently accessed, the processor can accurately identify whether the logical address is a hot address based on the access history information of the logical address.

[0118] When the processor needs to write the above-mentioned target data to the first logical address as a hot address, there can be the following two cases for a hot address:

[0119] The first case is that the data of the hot address already exists in the first region.

[0120] For example, the host has pre-written data for the hot address. When the host writes data for the hot address again, the first region has already stored the write data of the hot address in the previous time.

[0121] The second case is that there is no data of the hot spot address in the first area.

[0122] For example, a certain logical address is determined as a hot spot address through a period of statistics. At the beginning of the next period, the host performs data writing for the hot spot address. At this time, since the hot spot address is a new hot spot address, the data of the hot spot address has not been stored in the first area.

[0123] For the above two cases, as an optional embodiment, a cache state information corresponding to each hot spot address can be provided to indicate whether the data of the hot spot address has existed in the first area. For the convenience of description, the cache state indicating that the data of a certain hot spot address has existed in the first area is referred to as a cached state, and the cache state indicating that the data of a certain hot spot address has not existed in the first area is referred to as a to-be-cached state. That is, for the first logical address as a hot spot address, if the cache state information indicates that the data of the first logical address has existed in the first area, the following embodiment is referred to as a cached state. If the cache state information indicates that the data of the first logical address has not existed in the first area, the following embodiment is referred to as a to-be-cached state.

[0124] As an example, the processor can allocate a bit for each hot spot address in the aforementioned FTL table to record the cache state information of the hot spot address.

[0125] Correspondingly, in the step S304, when the processor identifies that the first logical address is a hot spot address and writes the target data into the first area, the cache state information of the first logical address can be read from the memory, and the target data is written into the first area according to the cache state information of the first logical address. Since the cache state information can accurately indicate whether the data of the first logical address has existed in the first area, the target data is written into the first area based on the cache state information, which can ensure the correctness of data writing.

[0126] It should be understood that the first logical address belongs to a hot spot address, and therefore the cache state information of the first logical address includes a cached state and a to-be-cached state. The first logical address is in the cached state, which indicates that the data of the first logical address has been cached to the first area, i.e., the data of the first logical address has existed in the first area. It should be understood that the data of the first logical address refers to the data written into the first logical address before the host indicates the target data. In addition, the first logical address is in the to-be-cached state, which indicates that the data of the first logical address has not been cached to the first area, i.e., the data of the first logical address has not existed in the first area.

[0127] In an example, the processor can record in the FTL table a mapping relationship between the LBA as a hot address and a storage location of the data of the LBA in the first area, and based on the mapping relationship, the data write and read for the LBA can be correctly performed.

[0128] The following describes two cases of writing target data to the first logical address in different cache state information.

[0129] In a first case, if the cache state information of the first logical address is the cached state, the processor can replace the data of the first logical address in the first area with the target data.

[0130] When the cache state information of the first logical address is the cached state, it indicates that the data of the first logical address written last time already exists in the first area, and thus the replacement operation is performed on the existing data, i.e., the target data is written to the storage location of the data written last time of the first logical address in the first area to overwrite the data written last time, thereby ensuring correct data writing.

[0131] For example, the processor learns from the FTL table in the storage that the first logical address is a hot address, and the cache state information of the first logical address is the cached state, and then the processor learns the storage location of the data of the first logical address in the first area based on the mapping relationship between the first logical address and the storage address in the FTL table, and further writes the target data to the storage location, thereby completing the replacement operation.

[0132] In a second case, if the cache state information of the first logical address is the uncached state, the processor can write the target data as the data of the first logical address to the first area, and update the cache state information of the first logical address to the information indicating that the data of the first logical address already exists in the first area, i.e., to the cached state.

[0133] If the cache state information of the first logical address is the uncached state, it indicates that the data of the first logical address has not been stored in the first area, and thus the target data can be directly written as the data of the first logical address to the first area, thereby ensuring correct data writing. In addition, after the target data is written to the first area, the cache state information of the first logical address is updated to the cached state, indicating that the data of the first logical address already exists in the first area, and thus when the host writes data to the first logical address next time, the processor can perform the above replacement processing based on the cached state, thereby further ensuring correct data writing.

[0134] For example, the processor learns from the FTL table that the first logical address is a hot address, and the cache state information of the first logical address is in the to-be-cached state, and then the processor first allocates a storage address for the first logical address in the first area, records the mapping relationship between the first logical address and the allocated storage address in the FTL table, and then writes the target data into the storage address, thereby completing the data write operation. Then, the processor modifies the cache state information of the first logical address in the FTL table to the cached state.

[0135] The above embodiment illustrates the processing procedure when data is written for the first logical address. Based on the above processing procedure, when data is read for the first logical address, the following processing procedure can be performed accordingly.

[0136] Optionally, for data read for a non-hot address, the data corresponding to the LBA indicated by the host on the PPN can be read from the flash memory of the SSD based on the mapping relationship between the LBA and the PPN recorded in the FTL table, and the data is returned to the host.

[0137] For data read for a hot address, the following processing can be performed:

[0138] If the cache state information of the hot address is in the cached state, the processor can read the data of the hot address from the first area and return the data of the hot address to the host.

[0139] For example, the processor learns from the FTL table that the address to be read is a hot address, and the cache state information is in the cached state, and then the processor can learn the storage location of the data of the address to be read in the first area based on the mapping relationship between the address to be read and the storage address in the first area recorded in the FTL table, and then read the data from the storage location and return the data to the host.

[0140] Taking the first logical address as an example, after the host sends a data access request for reading the data of the first logical address, if the first logical address is a hot address and the cache state information of the first logical address is in the cached state, the processor of the SSD can read the data of the first logical address from the first area and return the data of the first logical address to the host.

[0141] If the cache state information of the hot address is in the to-be-cached state, it indicates that the data of the hot address is not saved in the first area, and in this case, the processor can read the data of the hot address from the flash memory of the SSD and return the data to the host. Optionally, the processor can also write the data of the hot address in the flash memory into the first area, and modify the cache state information of the hot address to the cached state.

[0142] For example, the processor learns from the FTL table that the address to be read is a hot address, and the cache state information is a to-be-cached state, and then the processor can read the data of the hot address from the flash memory and return it to the host. In addition, the processor can also write the data of the hot address in the flash memory into the first area, record the mapping relationship between the hot address and the storage address in the first area in the FTL table, and then modify the cache state information of the first logical address in the FTL table to a cached state.

[0143] For example, the processor learns from the FTL table that the address to be read is a hot address, and the cache state information is a to-be-cached state, and then the processor can read the data of the hot address from the flash memory and return it to the host. In addition, the processor can also write the data of the hot address in the flash memory into the first area, record the mapping relationship between the hot address and the storage address in the first area in the FTL table, and then modify the cache state information of the first logical address in the FTL table to a cached state.

[0144] Through the above-mentioned processing of the embodiments, the data of the hot address can be saved in the first area. As described above, the first area can be a volatile memory such as DRAM, MRAM or PCM, and therefore, when the SSD is powered off, the processor can write the data of each hot address stored in the first area into the flash memory of the SSD.

[0145] For example, when the SSD is powered off, the processor reads the data of each hot address from the first area based on the mapping relationship between the LBA of each hot address and the storage address in the first area recorded in the FTL table, and the mapping relationship between the LBA and the PPN, and writes the data of each hot address into the corresponding PPN.

[0146] The above embodiments illustrate the process of the processor writing data based on the hot properties of the first logical address after the host sends a data write instruction to the SSD. As described above, the processor can periodically and independently execute the process of obtaining the hot properties of each logical address. The following embodiments illustrate the process of the processor periodically obtaining the hot properties.

[0147] As described in the above-mentioned step S304, the processor can generate the hot properties of each logical address based on the access history information of each logical address in the SSD within a predetermined time period after the SSD is powered on, and the hot properties can be used as the initial hot properties of each logical address. The access frequency of each logical address can be different at different times, and therefore, the processor can periodically update the hot properties of each logical address at a certain period.

[0148] The processor generates the initial hot spot attribute and the subsequent periodic update hot spot attribute, and the processing manner of determining whether a certain logical address is a hot spot is the same, and the difference is only that the periodic update hot spot attribute can involve the update of the hot spot attribute and the migration of data. For the convenience of description, the following embodiments describe the process of updating the hot spot attribute in a period, and the corresponding explanation of the difference scheme of generating the initial hot spot attribute.

[0149] In the first optional embodiment, the processor can update the hot spot attribute of each logical address in the SSD based on the access history information of each logical address.

[0150] For example, the processor can select, based on the statistics of the access history information of each logical address, the logical address with a write-in number greater than or equal to a preset number in the current period as a hot spot address, or select the logical address with a write-in number in the current period as a hot spot address, and then update the hot spot attribute of the logical address which changes from a hot spot address to a non-hot spot address in the current period, and update the hot spot attribute of the logical address which changes from a non-hot spot address to a hot spot address in the current period. The selection and update manner is the same as that in the second optional embodiment described below, and can be referred to the description below.

[0151] It is worth noting that if the initial hot spot attribute is generated based on only the access history information of each logical address, the hot spot attribute of each hot spot address can be modified to a mark for identifying the hot spot address after the hot spot address is selected.

[0152] In the second optional embodiment, the processor can update the hot spot attribute of each logical address in the SSD based on the access history information of each logical address and the capacity of the first area.

[0153] The capacity of the first area can refer to the number of logical addresses whose data can be stored in the first area. For example, the capacity of the first area is 1000, which means that the first area can store data of 1000 LBAs.

[0154] The capacity of the first area can be a preset value, which can be determined by the design of the SSD. In the specific implementation process, the capacity of the first area can be small, and therefore, the processor determines which logical addresses are hot spot addresses based on the access history information of each logical address and the capacity of the first area, so as to ensure that the number of selected hot spot addresses matches the capacity of the first area. In addition, the selection of the hot spot address based on the capacity of the first area can also make the selection of the hot spot address more effective.

[0155] Figure 5 The flowchart of the storage control method provided by the embodiments of the present application is shown in the following figure: Figure 5As shown, one optional way for the processor to update the hotspot attribute of each logical address based on the access history information of each logical address in the SSD and the capacity of the first area includes:

[0156] S501, count the access history information of each logical address in the solid state disk to obtain the write times of each logical address.

[0157] It should be understood that counting the access history information of each logical address in the solid state disk means counting the access history information of each logical address in the current period. Obtaining the write times of each logical address means obtaining the write times of each logical address in the current period.

[0158] As described above, the access history information of the logical address may include, for example, access time, access type (write or read), etc.

[0159] When counting the access history information of the logical address, the access history information can be sampled and counted.

[0160] Since the statistical processing of the access history information may occupy a large amount of processing resources of the storage controller of the SSD, the embodiments of the present application reduce the occupation of processing resources by sampling and counting the access history information. At the same time, since the data access frequency of the SSD can remain stable, sampling and counting will not affect the accuracy of the statistical results.

[0161] Optionally, the above sampling and counting can be sampling and counting according to time, or sampling and counting according to data volume. For example, the processor can count every 10w data access operations in the current period.

[0162] For example, the access history information of the logical address can include FTL journal, data access log, or LBA update history information temporarily stored in the cache, etc.

[0163] The sampling and counting of the access history information can be performed in any of the following ways.

[0164] In the first way, the sampling and counting can be based on the data access log in the current period.

[0165] In one cycle, the processor can record the time of the data access and the access type (such as write or read) of the data access in the data access log each time the data access is performed. Therefore, when the cycle ends, the data access log records information of all data accesses in the cycle. Based on the data access log, the processor can use a sampling method according to time or data volume to statistically sample the access history information in the cycle, and can obtain the write times of each logical address in the cycle. It should be understood that if the access information of a certain logical address is not included in the statistical sampling result, the write times of the logical address can be determined as 0.

[0166] In the second mode, real-time online sampling can be performed in the cycle.

[0167] In this mode, the processor monitors the data access operation in real time, performs sampling each time the duration or the number of data accesses reaches a certain number, and when the cycle ends, the results of each sampling are counted to obtain the write times of each logical address in the cycle.

[0168] S502, obtain the hot spot address in each logical address according to the write times of each logical address and the capacity of the first area.

[0169] Optionally, any of the following modes can be used.

[0170] In the first mode, the write times of each logical address and the capacity of the first area are used to determine whether the number of logical addresses with write times greater than 0 minus the capacity of the first area is greater than or equal to a first preset threshold value. If yes, the target logical address can be selected as the hot spot address. The target logical address refers to a logical address with a write time greater than or equal to a first preset number, or the target logical address refers to a preset number of logical addresses with the largest write times after sorting the write times of the logical addresses with write times greater than 0.

[0171] The first preset threshold value can be a number with a large order of magnitude. Correspondingly, if the number of logical addresses with write times greater than 0 minus the capacity of the first area is greater than or equal to the first preset threshold value, it indicates that the number of logical addresses with write times greater than 0 is much larger than the capacity of the first area. When this condition is met, the effect of the selected hot spot address is better, and the hot spot address can be better matched with the capacity of the first area. When this condition is met, the processor can select the target logical address as the hot spot address.

[0172] As described above, the target logical address can refer to a logical address with a write time greater than or equal to a first preset number.

[0173] For example, the first preset number is 200, and if the write number of a certain logical address is greater than or equal to 200, the logical address is considered as a target logical address, i.e., a hot address.

[0174] The first preset number can be set according to the capacity of the first region, so that the selected hot addresses match the capacity of the first region.

[0175] Alternatively, the target logical address can also refer to a preset number of logical addresses with the largest write number after sorting the logical addresses with a write number greater than 0 according to the write number.

[0176] For example, the logical addresses with a write number greater than 0 are sorted in the following order (the numbers in the brackets represent the write number of the logical address)

[0177] Address 1 (100), Address 2 (99), Address 3 (98), Address 4 (97), Address 5 (97), Address 6 (96), Address 7 (96), Address 8 (96), Address 9 (96), Address 10 (94)…

[0178] Suppose the preset number is 6, then addresses 1-6 can be selected as target logical addresses, i.e., hot addresses.

[0179] The preset number can be set according to the capacity of the first region, so that the selected hot addresses match the capacity of the first region.

[0180] For example, suppose the first region can provide 8MB of space to store data of hot addresses, and the data length corresponding to a single LBA is 4KB, then the preset number can be set to 8MB / 4KB=2K.

[0181] Alternatively, the preset number can also be set according to actual business conditions, so that the data of as few logical addresses as possible is cached, but the effect of caching all the data (such as the aforementioned 2K) is obtained.

[0182] For example, the total write data amount of the top 1K data can reach 80% of the data amount corresponding to the hottest 2K data, then the 1K data can be selected for caching.

[0183] In this way, after the target logical address is selected, the target logical address is directly selected as a hot address. In the following second way, the target logical address is determined in the same way as this way, the target logical address is selected as a candidate hot address, and the hot address is further obtained.

[0184] In the second mode, the number of logical addresses with write times greater than 0 is reduced by the capacity of the first region, and if the difference is greater than or equal to a first preset threshold, the target logical address can be selected as a candidate hot address. The meaning of the target logical address and the selection method are the same as in the first mode described above, and reference can be made to the foregoing description, which will not be repeated here.

[0185] When the target logical address is selected as a candidate hot address, any of the following operations can be performed. In some scenarios, the selected target logical address can be distorted. Therefore, by any of the following methods, the authenticity of the target logical address can be confirmed, thereby further improving the accuracy of the finally determined hot address.

[0186] In the first mode, if the sum of the write data amounts of each candidate hot address is greater than a second preset threshold compared to the total write data amount of the solid state disk in the statistical period of the access history information, the candidate hot address is selected as a hot address.

[0187] For example, assuming that the second preset threshold is 10%, and the number of candidate hot addresses is 2K, if the sum of the write data amounts of the 2K addresses is greater than or equal to 10% of the total write data amount of the SSD in the current period, the candidate hot addresses can be confirmed as hot addresses.

[0188] In the second mode, if the access times of the first candidate hot address are greater than a second preset number, the first candidate hot address is selected as a hot address. The first candidate hot address is any of the candidate hot addresses.

[0189] S503, updating the hot attribute of each logical address according to the hot address in each logical address.

[0190] The processor can establish a hot address set for each period to record the hot addresses in the period. Optionally, in each period, the processor obtains the hot addresses through the foregoing steps S501-S502, and records the hot addresses in the hot address set of the current period. Optionally, in the implementation process, the hot address sets of the current period and the previous period can be maintained in real time, and when entering the next period of the current period, the hot address set of the previous period of the current period can be deleted to reduce the resource occupation of the SSD.

[0191] In a specific period, the processor updates the hot property based on the hot address set of the current period and the hot address set of the previous period. Optionally, the processor can update the hot property of each logical address according to the hot address set of the first period and the hot address set of the second period. The first period is the statistical period of the access history information, and the second period is the previous period of the first period.

[0192] Since the hot address set of the first period and the hot address set of the second period respectively store the hot addresses in their respective periods, based on the two hot address sets, the change of the hot addresses from the second period to the first period can be known, and accordingly the hot property of each logical address can be accurately updated.

[0193] For the first period and the second period, the hot addresses of the respective periods can be obtained based on the foregoing steps S501-S502.

[0194] For any address (hereinafter referred to as the first address) of each access of the SSD, in the first period and the second period, the change of the first address can include the following cases:

[0195] The first case: the first address belongs to the hot address set of the first period and also belongs to the hot address set of the second period.

[0196] In this case, it indicates that the first address belongs to the hot address in the first period and the second period, and therefore, the hot property of the first address does not need to be updated.

[0197] The second case: the first address does not belong to the hot address set of the first period and also does not belong to the hot address set of the second period.

[0198] In this case, it indicates that the first address does not belong to the hot address in the first period and the second period, and therefore, the hot property of the first address does not need to be updated.

[0199] The third case: the first address belongs to the hot address set of the second period and does not belong to the hot address set of the first period.

[0200] In this case, it indicates that the first address belongs to the hot address in the second period and does not belong to the hot address in the first period. Accordingly, the hot property of the first address can be updated to the mark for identifying the non-hot address.

[0201] After the hot property of the first address is updated to the mark for identifying the non-hot address, when the host sends a write instruction for the first address again, the data to be written to the first address is no longer stored in the first area, but stored in the second area, and then written to the flash memory.

[0202] As an optional implementation, after updating the hotspot attribute of the first address to the mark used for identifying the non-hotspot address, the data of the first address in the first region can be written into the second region, and the data of the first address in the first region is deleted. Wherein, the data stored in the second region is written into the flash memory of the solid state disk according to a preset frequency in the powered-on state.

[0203] Since the first address no longer belongs to the hotspot address, the access frequency of the first address is reduced, and therefore, the data of the first address is written into the flash memory via the second region, so that the data of the first address no longer occupies the resources of the first region, and at the same time, the total write amount of the flash memory is not rapidly increased.

[0204] The fourth: the first address belongs to the hotspot address set of the first period, and does not belong to the hotspot address set of the second period.

[0205] In this case, it is indicated that the first address does not belong to the hotspot address in the second period, and belongs to the hotspot address in the first period. Correspondingly, the hotspot attribute of the first address can be updated to the mark used for identifying the hotspot address.

[0206] After updating the hotspot attribute of the first address to the mark used for identifying the hotspot address, when the host sends the access instruction for the first address again, the host controller acquires or writes the data of the first address in the first region.

[0207] After updating the hotspot attribute of the first address to the mark used for identifying the hotspot address, the following two ways can be executed:

[0208] The first way is to update the cache state information of the first address to the to-be-cached state.

[0209] In this way, only the cache state information of the first address is updated to the to-be-cached state, which indicates that the data of the first address has not been written into the first region, and the data movement is not performed.

[0210] When the first address is a hotspot address, the update frequency of the data of the first address is fast, and therefore, only the cache state information of the first address is updated to the to-be-cached state without performing the data movement, and when the host sends the write instruction for the first address next time, the data can be directly written into the first region. Therefore, the processing complexity of this way is low, and at the same time, the data access of the first address is not affected.

[0211] The second way is to write the data of the first address in the second region into the first region, delete the data of the first address in the second region, and update the cache state information of the first address to the cached state.

[0212] The data stored in the first address in the second region is the data needed to be written in the first address last time, the data is written in the first region, i.e. data moving is performed, and the cache state information of the first address is updated to the cached state, so that before the next data write in the first address, when the host needs to read the data in the first address, the data in the first address can be quickly read from the first region.

[0213] It should be noted that for the above-mentioned scenario of generating initial hot spot attributes after the SSD is powered on, the above-mentioned steps S501-S502 also need to be performed. After S502 is performed, for this scenario, the fourth processing mode in step S503 can be used, i.e. the hot spot attributes of each hot spot address obtained in step S502 are updated to the mark for identifying the hot spot address. And the cache state information of each hot spot address can be updated in the manner described in the fourth processing mode. It should be understood that after the SSD is powered on, the hot spot attributes of each logical address of the SSD are initialized to the mark for identifying the non-hot spot address.

[0214] The embodiment of the present application further provides a solid state disk, and a structure diagram of the solid state disk can be seen from the above-mentioned Figure 3 and Figure 4 . Referring to Figure 4 , the solid state disk of the embodiment of the present application comprises a storage controller and a flash memory, wherein the memory of the storage controller comprises a first region in addition to a second region and a region for saving an FTL table. The processor of the storage controller can complete data writing in the flash memory, the first region and the second region according to the method in the above-mentioned method embodiment, and the specific implementation process will not be described here.

[0215] In the embodiments described above, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated. The computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions can be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be transmitted from one website site, computer, storage node or data center to another website site, computer, storage node or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode. The computer readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a storage node, data center, etc. integrated with one or more available media. The available media can be magnetic media (for example, floppy disk, hard disk, magnetic tape), optical media (for example, DVD), or semiconductor media (for example, solid state disk (SSD)) and the like.

[0216] It should be understood that in the embodiments of the present application, the terms "first", "second" and the like are only used to refer to the objects, and do not represent the order of the corresponding objects.

[0217] Those skilled in the art can realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0218] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system, device and unit described above can refer to the corresponding process in the foregoing method embodiments, which will not be described here.

[0219] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other manners. For example, the described device embodiments are merely schematic. The division of the units is merely logical function division. There can be other division manners in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0220] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0221] In addition, each functional unit in the various embodiments of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit.

[0222] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application can be embodied in the form of a software product in essence or the part of the technical solutions that make contributions to the prior art or the part of the technical solutions. The computer software product is stored in a storage medium, and includes a plurality of instructions for causing a computer device (which can be a personal computer, a storage node, or a network device, etc.) to execute all or part of the steps of the method described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0223] The above is merely specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A storage controller, comprising: include: A processor, and a first interface and a memory respectively coupled to the processor; The first interface is used to receive a data write instruction, which is used to request writing target data to a first logical address; The processor is configured to read hotspot attributes corresponding to the first logical address from the memory, wherein the hotspot attributes are obtained based on historical access information of the first logical address; When the hotspot attribute indicates that the first logical address is a hotspot address, the processor is further configured to store the target data in a first region of the memory; wherein, the first region is used to replace the storage space in the flash memory controlled by the memory controller corresponding to the hotspot address to store data, and the capacity of the first region refers to the number of logical addresses that can store data; The processor is used for: The access history information of each logical address is statistically analyzed to obtain the number of writes to each logical address; Based on the number of writes to each logical address and the capacity of the first region, the hotspot addresses in each logical address are obtained; Update the hotspot attribute of each logical address based on the hotspot addresses in each logical address; Write the hotspot attributes of each logical address into the memory respectively; The processor is also used for: If the difference between the number of logical addresses with a write count greater than 0 and the capacity of the first region is greater than or equal to a first preset threshold, then a target logical address is selected as the hotspot address. The target logical address is a logical address with a write count greater than or equal to a first preset number, or the target logical address is a logical address with the largest preset number of write counts after sorting the logical addresses with a write count greater than 0 according to the write count. The write count is obtained by statistically analyzing the above access history information.

2. The storage controller of claim 1, wherein, The processor is used for: The cache status information of the first logical address is read from the memory, and the target data is written into the first region according to the cache status information. The cache status information is used to indicate whether the data of the first logical address already exists in the first region.

3. The storage controller of claim 2, wherein, The processor is used for: If the cache status information indicates that the data at the first logical address already exists in the first region, then the data at the first logical address already stored in the first region will be replaced with the target data.

4. The storage controller of claim 2 or 3, wherein, The processor is used for: If the cache status information indicates that the data at the first logical address does not exist in the first region, then the target data is written into the first region, and the cache status information of the first logical address is updated to indicate that the data at the first logical address already exists in the first region.

5. The storage controller of claim 1, wherein, The processor is used for: If the difference between the number of logical addresses with a write count greater than 0 and the capacity of the first region is greater than or equal to a first preset threshold, then a target logical address is selected as a candidate hotspot address. The target logical address is a logical address with a write count greater than or equal to a first preset number, or the target logical address is a logical address with the largest number of write counts after sorting a majority of logical addresses with a write count greater than 0 according to the write count. If a ratio of a sum of write data amounts of the candidate hot spot addresses to a total write data amount in a statistical period of the access history information is greater than or equal to a second preset threshold, the candidate hot spot address is taken as the hot spot address.

6. The storage controller of claim 5, wherein, The processor is further configured to: If the first candidate hot spot address access times are greater than a second preset number of times, the first candidate hot spot address is taken as a hot spot address, the first candidate hot spot address being any one of the candidate hot spot addresses.

7. The storage controller of claim 5 or 6, wherein, The processor is configured to: According to a hot spot address set of a first period and a hot spot address set of a second period, update a hot spot attribute of each logical address, the first period being a statistical period of the access history information, and the second period being a previous period of the first period.

8. The storage controller of claim 7, wherein, The processor is configured to: If the first address belongs to the hot spot address set of the second period and does not belong to the hot spot address set of the first period, update the hot spot attribute of the first address to an attribute used for identifying a non-hot spot address, the first address being any one of the logical addresses.

9. The storage controller of claim 8, wherein, The processor is further configured to: Write data of the first address in the first region to a second region, and delete the data of the first address from the first region, the second region being used for caching data to be written to a non-hot spot address.

10. The storage controller of any of claims 7-9, wherein, The processor is configured to: If the first address belongs to the hot spot address set of the first period and does not belong to the hot spot address set of the second period, update the hot spot attribute of the first address to an attribute used for identifying a hot spot address.

11. The storage controller of claim 10, wherein, The processor is further configured to: Update the cache state information of the first address to information indicating that the first logical address does not exist in the first region.

12. The storage controller of claim 10, wherein, The processor is further configured to: Write data of the first address in a second region to the first region, and delete the data of the first address from the second region; Update the cache state information of the first address to information indicating that the first logical address already exists in the first region.

13. The storage controller of any of claims 5-12, wherein, The processor is configured to: Sample and count the access history information of the logical addresses to obtain write times of the logical addresses.

14. The storage controller of any of claims 1-12, wherein, The processor is further configured to: When the hot spot attribute indicates that the first logical address is not a hot spot address, store the target data to a second region of the memory.

15. A storage control method characterized by comprising: The method is applied to a storage controller, the storage controller including a memory, and the method includes: Receiving a data write instruction, the data write instruction being used for requesting to write target data to a first logical address; Reading a hot spot attribute of the first logical address from the memory, the hot spot attribute being obtained based on historical access information of the first logical address; if the hot spot attribute indicates that the first logical address is a hot spot address, storing the target data to a first region of the memory, the hot spot address being a logical address with a write-in frequency greater than or equal to a first preset frequency, or a preset number of logical addresses with the largest write-in frequency after sorting the logical addresses with a write-in frequency greater than 0 according to the write-in frequency, the write-in frequency being obtained by counting the access history information, and the capacity of the first region being a number of logical addresses capable of storing data; the first region is used to replace a storage space corresponding to the hot spot address in the flash memory to cache data to be written to the hot spot address; the method further comprises: counting the access history information of each logical address to obtain a write-in frequency of each logical address; obtaining a hot spot address in each logical address according to the write-in frequency of each logical address and the capacity of the first region; updating the hot spot attribute of each logical address according to the hot spot address in each logical address; writing the hot spot attribute of each logical address into the memory.

16. The method of claim 15, wherein, the storing of the target data to the first region of the memory comprises: reading cache state information of the first logical address from the memory; writing the target data into the first region according to the cache state information, the cache state information being used to indicate whether the first logical address data already exists in the first region.

17. The method of claim 16, wherein, the writing of the target data into the first region according to the cache state information comprises: if the cache state information indicates that the first logical address data already exists in the first region, replacing the first logical address data already stored in the first region with the target data.

18. The method according to claim 16 or 17, characterized in that, the writing of the target data into the first region according to the cache state information comprises: if the cache state information indicates that the first logical address data does not exist in the first region, writing the target data into the first region and updating the cache state information of the first logical address to information indicating that the first logical address data already exists in the first region.

19. The method of claim 15, wherein, the updating of the hot spot attribute of each logical address according to the hot spot address in each logical address comprises: updating the hot spot attribute of each logical address according to a first period hot spot address set and a second period hot spot address set, the first period being a counting period of the access history information, and the second period being a previous period of the first period.

20. A solid state drive, comprising: comprises: a flash memory and a storage controller according to any one of claims 1-14, the storage controller performing data access on the flash memory through a second interface.

21. A storage system, characterized by a solid state disk according to claim 20 and a host, the solid state disk and the host communicating based on a first interface of the solid state disk and a host interface of the host.

22. A computer-readable storage medium, characterized in that, The computer storage medium stores computer instructions, when the computer instructions are executed by the processor, the processor executes the method in any one of claims 15-19.

23. A computer program product, characterised in that, The computer storage medium stores computer instructions, when the computer instructions are executed by the processor, the processor executes the method in any one of claims 15-19.

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