Address mapping method of storage chip and storage chip

Abstract

The invention provides an address mapping method of a storage chip and the storage chip. The method comprises the following steps: acquiring original addresses of a plurality of storage units; determining a target distance from each storage unit to the driver; according to the target distance, the original address is divided into a plurality of address areas, and each address area has area information; according to the region information, sorting the plurality of address regions, and re-assigning an original address in each sorted address region to obtain a first target address and an address mapping relationship, the address mapping relationship representing a mapping relationship between the first target address and the original address, the first target addresses in each address area are continuous, and the first target addresses in two adjacent address areas are continuous. On the basis of the technical scheme, address testing can be completed more conveniently; the first target addresses in the same address area are continuous, and the storage controller does not need to additionally develop mapping logic, so that the use complexity of a user is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of phase change memory, and in particular to an address mapping method of a storage chip and a storage chip. BACKGROUND

[0002] The storage chip calculates the address of the storage unit sent by the storage controller, calculates the target distance from the driver, and dynamically adjusts the voltage or current according to the target distance. When the address of the storage unit is sequentially increased, the adjacent addresses are divided into the same "position", and a position distribution map in the storage chip can be obtained.

[0003] When the address sent by the storage controller is fixed, different physical stacking modes will result in different target distances from the driver, and thus the position distribution map of the entire storage chip will also be different. When the number of positions is very large, the position distribution map will be irregular, and the addresses of two adjacent "positions" will be discontinuous, which is not conducive to the rapid development of address testing by testers. SUMMARY

[0004] Embodiments of the present application provide an address mapping method of a storage chip and a storage chip to solve the technical problem that the addresses of two adjacent positions in the storage chip are discontinuous.

[0005] To achieve the above-mentioned purpose, according to a first aspect of the present application, an address mapping method of a storage chip is provided, the storage chip comprising a plurality of stacked storage arrays and a driver electrically connected to the storage arrays, each of the storage arrays comprising a plurality of storage units, the method comprising:

[0006] obtaining original addresses of the plurality of storage units;

[0007] determining a target distance of each of the storage units to the driver;

[0008] dividing the original addresses into a plurality of address regions according to the target distances, each of the address regions having region information;

[0009] sorting the plurality of address regions according to the region information, and reassigning the original addresses in each of the sorted address regions to obtain first target addresses and an address mapping relationship, the address mapping relationship representing a mapping relationship between the first target addresses and the original addresses, the first target addresses in each of the address regions being continuous, and the first target addresses in two adjacent address regions being continuous.

[0010] In some embodiments, after obtaining the first target addresses and the address mapping relationship, the method further comprises:

[0011] receiving a first to-be-processed address, a first instruction and a second instruction;

[0012] in a case where the second instruction is a mapping instruction, determining a second to-be-processed address corresponding to the first to-be-processed address according to the first to-be-processed address and the address mapping relationship;

[0013] executing the first instruction to process a storage unit corresponding to the second to-be-processed address.

[0014] In some embodiments, the first instruction includes any one of a set operation, a reset operation, and a read operation.

[0015] In some embodiments, after determining the second to-be-processed address corresponding to the first to-be-processed address according to the first to-be-processed address and the address mapping relationship, the method further includes:

[0016] positionally compensating the second to-be-processed address;

[0017] executing the first instruction to process a storage unit corresponding to the positionally compensated second to-be-processed address.

[0018] In some embodiments, the method further includes, in a case where the second instruction is a rejection mapping instruction, executing the first instruction to process a storage unit corresponding to the first to-be-processed address.

[0019] In some embodiments, the driver includes a word line driver and a bit line driver.

[0020] determining target distances of a plurality of the storage units to the driver includes:

[0021] determining a first distance of each of the storage units to the word line driver;

[0022] determining a second distance of each of the storage units to the bit line driver;

[0023] determining the target distance according to the first distance and the second distance.

[0024] In some embodiments, dividing the original address into a plurality of address regions according to the target distance includes:

[0025] determining a value range of the target distance;

[0026] dividing the value range into a plurality of subintervals and determining original addresses included in each of the subintervals;

[0027] The multiple original addresses in the same sub-interval are divided into an address region, and region information of the address region is obtained according to the interval attribute value of the sub-interval.

[0028] According to a second aspect of the present application, a memory chip is provided, comprising:

[0029] A plurality of stacked memory arrays, the memory arrays comprising a plurality of memory cells;

[0030] A driver configured to drive the memory arrays;

[0031] An address mapping module configured to:

[0032] Obtain original addresses of the plurality of memory cells;

[0033] Determine a target distance of each of the memory cells to the driver;

[0034] According to the target distances, divide the original addresses into a plurality of address regions, each of the address regions having region information;

[0035] According to the region information, sort the plurality of address regions, and reassign the original addresses in each of the sorted address regions to obtain first target addresses and an address mapping relationship, the address mapping relationship representing a mapping relationship between the first target addresses and the original addresses, the first target addresses in each of the address regions being continuous, and the first target addresses in adjacent two of the address regions being continuous.

[0036] In some embodiments, the memory chip further comprises:

[0037] A memory controller electrically connected to the address mapping module and configured to receive a first to-be-processed address and a first instruction;

[0038] A judging module electrically connected to the address mapping module, the processing module, and the memory controller, and configured to receive a second instruction;

[0039] The address mapping module is further configured to, in a case where the second instruction is a mapping instruction, determine a second to-be-processed address corresponding to the first to-be-processed address according to the first to-be-processed address and the address mapping relationship.

[0040] The memory chip further comprises a processing module electrically connected to the address mapping module and the memory arrays, and configured to execute the first instruction and process a memory cell corresponding to the second to-be-processed address.

[0041] In some embodiments, the processing module is further configured to execute the first instruction to process the storage unit corresponding to the first to-be-processed address in a case where the second instruction is a reject mapping instruction.

[0042] The technical solution of the present application can achieve the following beneficial effects: the address mapping method of the storage chip provided by the embodiments of the present application can obtain continuously distributed address regions, the first target address in each address region is continuous, and the first target addresses in two adjacent address regions are continuous, thereby making it more convenient to complete address testing; for the storage controller, the first target addresses in the same address region are continuous, and the storage controller does not need to develop mapping logic additionally, thereby reducing the logic of the storage controller and the use complexity of the user.

[0043] Other features and advantages of the present application will be described in detail in the following specific implementation part. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0045] In order to more completely understand the present application and its beneficial effects, the following will be described in conjunction with the drawings, wherein the same reference numerals in the following description represent the same parts.

[0046] Figure 1 A structural schematic diagram of a storage array is provided for an embodiment;

[0047] Figure 2 A flowchart of an address mapping method of a storage chip is provided for an embodiment of the present application;

[0048] Figure 3 A flowchart of an address mapping method of a storage chip is provided for an embodiment of the present application;

[0049] Figure 4 A flowchart of an address mapping method of a storage chip is provided for an embodiment of the present application;

[0050] Figure 5 A structural schematic diagram of a storage chip is provided for an embodiment of the present application;

[0051] Figure 6 A schematic diagram of an address region before mapping is provided for an embodiment of the present application;

[0052] Figure 7A mapping-after address region diagram provided by an embodiment of the present application. DETAILED DESCRIPTION

[0053] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person skilled in the art without creative work fall within the scope of protection of the present application.

[0054] In the description of the present application, the terms "first", "second" are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0055] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0056] The use of "adapted for" or "configured for" in the present application means open and inclusive language that does not exclude devices adapted for or configured for performing additional tasks or steps. In addition, the use of "based on" means open and inclusive, because the process, step, calculation or other action "based on" one or more stated conditions or values can be based on additional conditions or values beyond those stated in practice.

[0057] In the present application, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation described as "exemplary" in the present application is not necessarily to be construed as preferred or advantageous over other implementations. The following description is presented to enable any person skilled in the art to make and use the present application. In the following description, for the purposes of explanation, details are set forth in order to provide a thorough understanding of the present application. It should be apparent to one skilled in the art that the present application can be practiced without the specific details presented below. In other instances, well-known structures and processes are not elaborated in order not to obscure the description of the present application with unnecessary details. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

[0058] Reference Figure 1 As shown, the storage array is composed of a plurality of array-arranged storage units, the storage array and the driver are electrically connected, and the driver includes a word line driver and a bit line driver.

[0059] The plurality of arrayed memory cells are electrically connected by a plurality of bit lines (a first bit line BL1, a second bit line BL2, a third bit line BL3, and a fourth bit line BL4) and a bit line driver, and are electrically connected by a plurality of word lines (a first word line WL1, a second word line WL2, a third word line WL3, and a fourth word line WL4) and a word line driver. The driver provides voltage and current for the memory cells. The distance from each memory cell to the driver is referred to as a target distance, which is determined by the distance from the memory cell to the word line driver and the distance from the memory cell to the bit line driver.

[0060] With the increasing area capacity of a memory chip, in the existing memory chip, due to factors such as capacity / density / volume, the memory array is arranged in a stacked manner or even a stacked zigzag manner to form a memory chip, which further includes a memory controller. Based on the above different physical position arrangement manners, the positions of the drivers are also different, thereby causing the target distances from the memory cells to the drivers to be different with different arrangement manners. In order to better operate (for example, set operation, reset operation, read operation) different memory cells, it is usually necessary to dynamically adjust the voltage or current value provided by the driver according to the target distance.

[0061] The memory controller inside the memory chip calculates the address of the memory cell sent by the memory controller, calculates the target distance from the driver, and dynamically adjusts the voltage or current according to the target distance. When the address sequence of the memory cell is increased, the adjacent addresses are divided into the same "position", and a position distribution map inside the memory chip can be obtained. The test personnel of the memory chip manufacturer and the memory controller manufacturer can perform memory chip testing and board-level debugging through the position distribution map.

[0062] When the address (sent in the format of row and column addresses) sent by the memory controller is fixed, different physical stacking manners cause different target distances from the driver, and thereby the position distribution map of the entire memory chip is also different. When the number of position divisions is very large, the position distribution map is irregular, and the addresses of two adjacent "positions" are discontinuous. For a test engineer, the calculation is complicated when testing the same position compensation. For a memory controller, if it wants to access the address of a specific position, it also needs to perform complex address operation and then provide the calculation result to the memory chip, which increases the complexity of the memory controller and reduces the running efficiency of the memory controller and the entire memory system.

[0063] To solve the technical problem that the addresses of two adjacent "positions" are discontinuous, the embodiments of the present application provide a memory chip address mapping method and a memory chip to overcome the above problems.

[0064] In one aspect, the embodiment of the present application provides an address mapping method of a memory chip, which can be executed by the memory chip. The memory chip comprises a plurality of stacked memory arrays and a driver electrically connected to the memory arrays, each of the memory arrays comprising a plurality of memory cells. As shown in the figure, the address mapping method of the memory chip comprises the following steps: Figure 2

[0065] S101: obtaining original addresses of a plurality of memory cells;

[0066] S102: determining a target distance of each memory cell to the driver;

[0067] S103: dividing the original addresses into a plurality of address regions according to the target distance, each of the address regions having region information;

[0068] S104: sorting the plurality of address regions according to the region information, and reassigning the original addresses in each of the sorted address regions to obtain first target addresses and an address mapping relationship, the address mapping relationship representing a mapping relationship between the first target addresses and the original addresses, the first target addresses in each of the address regions being continuous, and the first target addresses in adjacent two of the address regions being continuous.

[0069] The address mapping method of the memory chip provided by the embodiment of the present application will be described in detail below.

[0070] S101: obtaining original addresses of a plurality of memory cells;

[0071] In some embodiments, each of the memory cells has a unique original address, and the embodiment sets 896 memory cells in total, and the original addresses of the 896 memory cells are 0, 1, 2, 3, …, 895 respectively.

[0072] S102: determining a target distance of each memory cell to the driver;

[0073] In some embodiments, the driver comprises a word line driver and a bit line driver.

[0074] Determining the target distance of the plurality of memory cells to the driver specifically comprises:

[0075] S1: determining a first distance of each memory cell to the word line driver;

[0076] S2: determining a second distance of each memory cell to the bit line driver;

[0077] S2: determining the target distance according to the first distance and the second distance.

[0078] ​In some embodiments, corresponding weights can be set for the first distance and the second distance, and the first distance and the second distance can be summed up with weighting to obtain the target distance.

[0079] In some embodiments, the first distance and the second distance can also be summed up to obtain the target distance.

[0080] Based on the above embodiments, the target distance of each storage unit is calculated respectively.

[0081] S103: According to the target distance, the original address is divided into a plurality of address regions, and each address region has region information.

[0082] In some embodiments, according to the target distance, the original address is divided into a plurality of address regions, and each address region has region information.

[0083] S1: Determine the value range of the target distance;

[0084] S2: Divide the value range into a plurality of subintervals, and determine the original address included in each subinterval;

[0085] S3: Divide a plurality of original addresses in the same subinterval into an address region; and according to the interval attribute value of the subinterval, obtain the region information of the address region.

[0086] In some embodiments, the value range of the target region is interval [A, B], and the interval [A, B] is divided into a plurality of subintervals at equal intervals. This embodiment takes dividing into 3 subintervals as an example, and the 3 subintervals are [A, (2xA+B) / 3], ((2xA+B) / 3, (2xB+A) / 3] and ((2xB+A) / 3, B]. The original address included in each subinterval is determined. A plurality of original addresses in [A, (2xA+B) / 3] are divided into an address region, a plurality of original addresses in ((2xA+B) / 3, (2xB+A) / 3] are divided into an address region, and a plurality of original addresses in ((2xB+A) / 3, B] are divided into an address region, thereby obtaining 3 different address regions.

[0087] Of course, it should be noted that the value range can also be divided into a plurality of subintervals in the form of unequal intervals, and the length of each subinterval is not the same. The application does not limit the way of dividing the subintervals.

[0088] In some embodiments, the address region has region information, and the region information indicates the degree of distance from the driver.

[0089] Further, the interval attribute value of the subinterval includes: the left endpoint value of the interval, the right endpoint value of the interval, and the midpoint value of the interval.

[0090] The left end point values of the three sub-intervals can be selected as the interval attribute values, which are A, (2*A+B) / 3 and (2*B+A) / 3 respectively. The ascending order of A, (2*A+B) / 3 and (2*B+A) / 3 is A, (2*A+B) / 3 and (2*B+A) / 3. The ascending order of the interval attribute values is determined as the region information corresponding to the region address. The ascending order of A is 1, and the region information of the address region corresponding to [A, (2*A+B) / 3] is equal to 1 (the address region corresponding to it is represented as address region 1). The ascending order of (2*A+B) / 3 is 2, and the region information of the address region corresponding to ((2*A+B) / 3, (2*B+A) / 3] is equal to 2 (the address region corresponding to it is represented as address region 2). The ascending order of (2*B+A) / 3 is 3, and the region information of the address region corresponding to ((2*B+A) / 3, B] is equal to 3 (the address region corresponding to it is represented as address region 3).

[0091] The address region 1 represents a block of region closest to the driver, the address region 3 represents a block of region farthest from the driver, and the address region 2 is between the address region 1 and the address region 3 in terms of distance from the driver.

[0092] In some embodiments, the continuous original addresses located in the same address region are grouped.

[0093] Referring to Figure 3 As shown in the figure, the storage units with original addresses equal to 0-127 belong to the address region 1, the storage units with original addresses equal to 128-255 belong to the address region 2, the storage units with original addresses equal to 256-511 belong to the address region 3, the storage units with original addresses equal to 512-639 belong to the address region 2, the storage units with original addresses equal to 640-767 belong to the address region 1, and the storage units with original addresses equal to 768-895 belong to the address region 3.

[0094] S104: According to the region information, the plurality of address regions are sorted, and the original addresses in each sorted address region are revalued to obtain the first target addresses and the address mapping relationship. The address mapping relationship represents the mapping relationship between the first target addresses and the original addresses. The first target addresses in each address region are continuous, and the first target addresses in adjacent two address regions are continuous.

[0095] In some embodiments, the plurality of address regions are sorted in ascending order according to the region information. Referring to Figure 3As shown, the address regions after sorting are obtained in ascending order according to the region address 1, the region address 2, and the region address 3 (i.e., the sorting is performed according to the target distance from the driver in the order from near to far). If two groups of continuous original addresses belong to the same address region, for example, the storage units with the original addresses equal to 0-127 belong to the address region 1, and the storage units with the original addresses equal to 640-767 also belong to the address region 1, the size of the end point values in the two groups of original addresses is compared. Since the left end point value 0 in the first group of original addresses is smaller than the left end point value 640 in the second group of original addresses, the address region 1 corresponding to the storage units with the original addresses equal to 0-127 is placed in front of the address region 1 corresponding to the storage units with the original addresses equal to 640-767. Similarly, it can be determined that the address region 2 corresponding to the storage units with the original addresses equal to 128-255 is placed in front of the address region 2 corresponding to the storage units with the original addresses equal to 512-639, and the address region 3 corresponding to the storage units with the original addresses equal to 256-511 is placed in front of the address region 3 corresponding to the storage units with the original addresses equal to 768-895.

[0096] Referring to Figure 3 As shown, the original addresses in each address region after sorting are re-assigned, 0-127 is re-assigned as 0-127, 640-767 is re-assigned as 128-255, 128-255 is re-assigned as 256-511, 512-639 is re-assigned as 512-639, 256-511 is re-assigned as 640-767, and 768-895 is re-assigned as 768-895. The result after re-assignment is taken as the first target address. Based on this, the mapping process is completed, and the mapping relationship between the original addresses before re-assignment and the new addresses (the first target addresses) after re-assignment is saved as the address mapping relationship.

[0097] Referring to Figure 4 As shown, after re-assignment (mapping), the first target addresses and the address mapping relationship are obtained. The address mapping relationship represents the mapping relationship between the first target addresses and the original addresses. The first target addresses in each address region are continuous, and the first target addresses in adjacent two address regions are continuous.

[0098] In some embodiments, Figure 6The 13 address regions before reassignment are represented, and the region information of the 13 address regions is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, and 12 respectively. The horizontal coordinate (row address) range occupied by the 13 address regions is 0-8192, and the vertical coordinate (column address) range occupied by the 13 address regions is 0-8192. The percentage of the address region corresponding to the region information 0 in the total address region is equal to 0.00%, the percentage of the address region corresponding to the region information 1 in the total address region is equal to 3.14%, the percentage of the address region corresponding to the region information 2 in the total address region is equal to 12.52%, the percentage of the address region corresponding to the region information 3 in the total address region is equal to 15.61%, the percentage of the address region corresponding to the region information 4 in the total address region is equal to 9.36%, the percentage of the address region corresponding to the region information 5 in the total address region is equal to 9.39%, the percentage of the address region corresponding to the region information 6 in the total address region is equal to 9.36%, the percentage of the address region corresponding to the region information 7 in the total address region is equal to 9.39%, the percentage of the address region corresponding to the region information 8 in the total address region is equal to 15.64%, the percentage of the address region corresponding to the region information 9 in the total address region is equal to 12.48%, the percentage of the address region corresponding to the region information 10 in the total address region is equal to 3.11%, the percentage of the address region corresponding to the region information 11 in the total address region is equal to 0.00%, and the percentage of the address region corresponding to the region information 12 in the total address region is equal to 0.00%. Figure 6 The distribution of the middle address regions is disordered and irregular, Figure 7 The 13 address regions after reassignment are represented. Figure 6 The 13 address regions after reassignment are represented. Figure 7In the embodiment, the percentage of the address region corresponding to the region information 0 in the total address region is equal to 0.00%, the percentage of the address region corresponding to the region information 1 in the total address region is equal to 3.14%, the percentage of the address region corresponding to the region information 2 in the total address region is equal to 12.52%, the percentage of the address region corresponding to the region information 3 in the total address region is equal to 15.61%, the percentage of the address region corresponding to the region information 4 in the total address region is equal to 9.36%, the percentage of the address region corresponding to the region information 5 in the total address region is equal to 9.39%, the percentage of the address region corresponding to the region information 6 in the total address region is equal to 9.36%, the percentage of the address region corresponding to the region information 7 in the total address region is equal to 9.39%, the percentage of the address region corresponding to the region information 8 in the total address region is equal to 15.64%, the percentage of the address region corresponding to the region information 9 in the total address region is equal to 12.48%, the percentage of the address region corresponding to the region information 10 in the total address region is equal to 3.11%, the percentage of the address region corresponding to the region information 11 in the total address region is equal to 0.00%, and the percentage of the address region corresponding to the region information 12 in the total address region is equal to 0.00%. Figure 7 The distribution of the address regions presents continuity of the addresses, and neither the test engineer nor the storage controller needs to care about the mapping logic inside the storage chip. For the user, the first target addresses that the user sees are continuous and regular.

[0099] Based on the above embodiment, the continuously distributed address regions can be obtained, the first target addresses in each address region are continuous, and the first target addresses in adjacent two address regions are continuous, so that the address test can be more conveniently completed. For the storage controller, the first target addresses in the same address region are continuous, and the storage controller does not need to additionally develop mapping logic, thereby reducing the logic of the storage controller and the use complexity of the user. It should be noted that the address mapping relationship in the embodiment of the application is stored inside the storage chip.

[0100] In some embodiments, after the first target address is obtained, the original address before mapping can also be reserved, and it is determined according to the selection of the user whether to process the original address before mapping or the address after mapping.

[0101] In some embodiments, after the first target address and the address mapping relationship are obtained, the method further includes:

[0102] S1: receiving a first to-be-processed address, a first instruction and a second instruction;

[0103] S2: in the case that the second instruction is a mapping instruction, determining a second to-be-processed address corresponding to the first to-be-processed address according to the first to-be-processed address and the address mapping relationship;

[0104] S3: execute the first instruction to process the storage unit corresponding to the second to-be-processed address.

[0105] In some embodiments, the first instruction includes any one of a set operation, a reset operation, and a read operation.

[0106] The set operation is to change the phase change material of the storage unit from amorphous state (high resistance) to crystalline state (low resistance), and the corresponding storage logic is changed from 0 to 1.

[0107] The reset operation is to change the phase change material of the storage unit from crystalline state (low resistance) to amorphous state (high resistance), and the corresponding storage logic is changed from 1 to 0.

[0108] The read operation is to measure the resistance value of the current storage unit without changing the state of the phase change material, to determine whether it is in crystalline state (low resistance) or amorphous state (high resistance), and then read out whether it is "0" or "1".

[0109] In some embodiments, referring to Figure 4 As shown, the first to-be-processed address, the first instruction, and the second instruction are accepted by the user input. For example, the first to-be-processed address is "256-511", and in the case that the second instruction is a mapping instruction, the original address having a mapping relationship with the first to-be-processed address is determined as the second to-be-processed address according to the address mapping relationship. In the case that the first to-be-processed address is "256-511", the second to-be-processed address is "128-255". Finally, the first instruction is executed to process the storage unit corresponding to the second to-be-processed address. The user perceives the processing address as "256-511", but actually the storage unit corresponding to "128-255" is processed.

[0110] In some embodiments, after the second to-be-processed address corresponding to the first to-be-processed address is determined according to the first to-be-processed address and the address mapping relationship, the method further includes:

[0111] S1: position compensation is performed on the second to-be-processed address;

[0112] S2: the first instruction is executed to process the storage unit corresponding to the second to-be-processed address after the position compensation.

[0113] In some embodiments, in a storage array, an "address" is just a logical row / column number seen from the storage controller side. When really falling into the storage chip, due to the decoder threshold drift caused by process-temperature-aging, word line / bit line RC delay difference, etc., the "best pulse parameters" corresponding to the same "address" at different times, different temperatures, and different wear stages will change. "Position compensation" is to map these changes to the fine-tuning amount of the "address", so that subsequent operations can still fall in the center of the process window, reducing the bit error rate or write delay. The methods of position compensation include: static lookup table (SLT), temperature-voltage double parameter linear interpolation (LIC), adaptive real-time closed loop (ACL), endurance-aware compensation based on endurance history (EAC), and machine learning prediction (MLC).

[0114] In some embodiments, after receiving the first to-be-processed address, the first instruction, and the second instruction, in the case that the second instruction is a rejection mapping instruction, the first instruction is executed to process the storage unit corresponding to the first to-be-processed address. If the second instruction is a rejection mapping instruction, it means that the user does not need to map using the address mapping relationship, and at this time, the storage unit corresponding to the first to-be-processed address is directly processed.

[0115] In some embodiments, after receiving the first to-be-processed address, the first instruction, and the second instruction, in the case that the second instruction is a rejection mapping instruction, the first to-be-processed address can also be position compensated, and the first instruction is executed to process the storage unit corresponding to the position compensated first to-be-processed address.

[0116] Referring to Figure 5 The embodiments of the present application provide a storage chip, comprising:

[0117] A plurality of stacked storage arrays 10, the storage array 10 comprising a plurality of storage units;

[0118] A driver 20 configured to drive the storage array 10;

[0119] An address mapping module 30 configured to:

[0120] Obtain the original addresses of the plurality of storage units;

[0121] Determine the target distance of each storage unit to the driver 20;

[0122] According to the target distance, the original address is divided into a plurality of address regions, each address region has region information;

[0123] According to the region information, the plurality of address regions are sorted, and the original address in each sorted address region is revalued to obtain a first target address and an address mapping relationship, the address mapping relationship representing a mapping relationship between the first target address and the original address, the first target address in each address region being continuous, and the first target addresses in adjacent two address regions being continuous.

[0124] In some embodiments, referring to Figure 5 As shown in the figure, the memory chip 70 further comprises:

[0125] The memory controller 40 and the address mapping module 30 are electrically connected and configured to receive the first to-be-processed address and the first instruction;

[0126] The judgment module 50 is electrically connected with the address mapping module 30, the processing module 60 and the memory controller 40 respectively and is configured to receive the second instruction;

[0127] The address mapping module 30 is further configured to, in the case that the second instruction is a mapping instruction, determine the second to-be-processed address corresponding to the first to-be-processed address according to the first to-be-processed address and the address mapping relationship;

[0128] The memory chip 70 further comprises the processing module 60 electrically connected with the address mapping module 30 and the memory array 10 respectively and configured to execute the first instruction and process the storage unit corresponding to the second to-be-processed address.

[0129] In some embodiments, the processing module 60 is further configured to, in the case that the second instruction is a rejection mapping instruction, execute the first instruction and process the storage unit corresponding to the first to-be-processed address.

[0130] In some embodiments, the judgment module 50 is a mode register (Mode Register), and a user can select whether to map the first to-be-processed address to the second target address through the address mapping relationship through the mode register.

[0131] In some embodiments, the processing module 60 comprises a content-addressable memory (Content-Addressable Memory, CAM), which can receive the second to-be-processed address (or the first to-be-processed address) and search the memory chip 70 to find the storage unit corresponding to the second to-be-processed address (or the first to-be-processed address).

[0132] In some embodiments, the memory chip 70 further comprises a position compensation module configured to perform position compensation on the second to-be-processed address in the case that the second instruction is a mapping instruction; and perform position compensation on the first to-be-processed address in the case that the second instruction is a rejection mapping instruction.

[0133] Correspondingly, the processing module 60 is configured to execute the first instruction to process the storage unit corresponding to the position-compensated second to-be-processed address in the case that the second instruction is a mapping instruction; and execute the first instruction to process the storage unit corresponding to the position-compensated first to-be-processed address in the case that the second instruction is a rejection mapping instruction.

[0134] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0135] The above describes in detail a memory chip address mapping method and a memory chip provided by the embodiments of the present application. The present application applies specific examples to describe the principles and implementation manners of the present application. The above embodiment descriptions are only used to help understand the method of the present application and its core idea. Meanwhile, for those skilled in the art, the specific implementation manners and application ranges can be changed according to the idea of the present application. In summary, the content of the present description should not be understood as a limitation of the present application.

Claims

1. A method of address mapping for a memory chip, the method comprising: The memory chip includes a plurality of stacked memory arrays and a driver electrically connected with the memory arrays, each of the memory arrays includes a plurality of memory cells, and the method includes: obtaining original addresses of the plurality of memory cells; determining target distances from each of the memory cells to the driver; dividing the original addresses into a plurality of address regions according to the target distances, each of the address regions having region information; sorting the plurality of address regions according to the region information, and reassigning the original addresses in each of the sorted address regions to obtain first target addresses and an address mapping relationship, the address mapping relationship representing a mapping relationship between the first target addresses and the original addresses, the first target addresses in each of the address regions being continuous, and the first target addresses in adjacent two of the address regions being continuous.

2. The method of claim 1, wherein, After obtaining the first target addresses and the address mapping relationship, the method further includes: receiving a first to-be-processed address, a first instruction, and a second instruction; in a case where the second instruction is a mapping instruction, determining a second to-be-processed address corresponding to the first to-be-processed address according to the first to-be-processed address and the address mapping relationship; executing the first instruction to process a memory cell corresponding to the second to-be-processed address.

3. The method of claim 2, wherein, The first instruction includes any one of a set operation, a reset operation, and a read operation.

4. The method of claim 2, wherein, After determining the second to-be-processed address corresponding to the first to-be-processed address according to the first to-be-processed address and the address mapping relationship, the method further includes: performing position compensation on the second to-be-processed address; executing the first instruction to process a memory cell corresponding to the second to-be-processed address after the position compensation.

5. The method of claim 2, wherein, The method further includes: in a case where the second instruction is a rejection mapping instruction, executing the first instruction to process a memory cell corresponding to the first to-be-processed address.

6. The method of claim 1, wherein, The driver includes a word line driver and a bit line driver; determining target distances from the plurality of memory cells to the driver includes: determining first distances from each of the memory cells to the word line driver; determining second distances from each of the memory cells to the bit line driver; determining the target distances according to the first distances and the second distances.

7. The method of claim 1, wherein, Dividing the original addresses into a plurality of address regions according to the target distances includes: determining a value range of the target distances; dividing the value range into a plurality of subintervals and determining original addresses included in each of the subintervals; dividing a plurality of original addresses in a same one of the subintervals into an address region, and obtaining region information of the address region according to an interval attribute value of the subinterval.

8. A memory chip, characterized by The method includes: a plurality of stacked memory arrays, each of the memory arrays including a plurality of memory cells; a driver configured to drive the memory arrays; an address mapping module configured to: obtain original addresses of the plurality of memory cells; determine target distances from each of the memory cells to the driver; divide the original addresses into a plurality of address regions according to the target distances, each of the address regions having region information; According to the region information, a plurality of address regions are sorted, and a first target address and an address mapping relationship are obtained by reassigning original addresses in each of the sorted address regions, the address mapping relationship representing a mapping relationship between the first target address and the original address, the first target addresses in each of the address regions being continuous, and the first target addresses in two adjacent address regions being continuous.

9. The memory chip of claim 8, wherein, Also includes: A storage controller, and the address mapping module is electrically connected, is configured to receive the first to be processed address and the first instruction; A judgment module, respectively and the address mapping module, the processing module, the storage controller are electrically connected, are configured to receive the second instruction; The address mapping module is further configured to: in the case of the second instruction being a mapping instruction, according to the first to be processed address and the address mapping relationship, determine the second to be processed address corresponding to the first to be processed address; The storage chip further includes a processing module, respectively and the address mapping module, the storage array are electrically connected, are configured to execute the first instruction, process the storage unit corresponding to the second to be processed address.

10. The memory chip of claim 9, wherein, The processing module is further configured to execute the first instruction in the case of the second instruction being a rejection mapping instruction, to process the storage unit corresponding to the first to be processed address.

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