Provide validation for the system power management interface

Abstract

A system, method, and apparatus are configured to enable a receiver to provide feedback. In one example, a method performed at a device coupled to a serial bus includes: receiving a write command from the serial bus in a datagram; writing data bytes received in a first data frame of the datagram to a register address identified by the datagram; and using a second data frame of the datagram to provide feedback about the datagram. Feedback can be provided by driving data lines of the serial bus during the second data frame to provide a negative acknowledgment when a transmission error is detected in the datagram; and by stopping driving data lines of the serial bus during the second data frame to provide feedback when no transmission error is detected in the datagram, thereby providing acknowledgment of the datagram.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to patent application No. 202041023318 filed on June 3, 2020, with the Indian Patent Office, the entire contents of which are incorporated herein by reference, as if their entire contents were fully set forth below, and for all applicable purposes. Technical Field

[0003] Generally, this disclosure relates to serial communication via a shared serial bus, and more particularly, to providing feedback via a shared bus. Background Technology

[0004] Mobile communication devices may include a variety of components, including circuit boards, integrated circuit (IC) devices, and / or system-on-a-chip (SoC) devices. These components may include processing devices, user interface components, storage devices, and other peripheral components that communicate via a shared data communication bus, which may include a multi-point serial bus or a parallel bus. Commonly known serial interfaces in the industry include inter-integrated circuit (I2C) or inter-system (I2C) interfaces. 2 C) Serial interfaces and their derivative and alternative schemes.

[0005] The Mobile Industry Processor Interface (MIPI) Alliance defines standards for improved inter-integrated circuit (I3C) serial interfaces, radio frequency front-end (RFFE) interfaces, system power management interfaces (SPMI), and other interfaces. These interfaces can be used, for example, to connect processors, sensors, and other peripheral devices via multipoint serial buses. In some interfaces, multiple bus masters are coupled to the serial bus, allowing two or more devices to act as bus masters for different types of messages transmitted on the serial bus. The SPMI protocol defines the hardware interface that can be implemented between the baseband or application processor and peripheral components. In some cases, the SPMI protocol is implemented to support power management operations within the device.

[0006] Multipoint serial buses can support a large number of devices implementing increasingly faster and more complex applications, and new protocols are being developed to support such advanced applications. When implementing new protocols, it is necessary to support legacy devices. Summary of the Invention

[0007] Certain aspects of this disclosure relate to systems, apparatuses, methods, and techniques that enable devices coupled to a serial bus to provide feedback, including acknowledgments of transmissions via the serial bus. According to some aspects, the feedback mechanism can be implemented using existing bus protocols, while providing coexistence with conventional slave devices. The bus can be operated according to the SPMI protocol or another protocol available on the serial bus.

[0008] In several aspects of this disclosure, a method performed at a device coupled to a serial bus includes: receiving a write command from the serial bus, wherein the write command is received in a datagram and configured according to the SPMI protocol; writing data bytes received in a first data frame of the datagram to a register address identified by the datagram; and using a second data frame of the datagram to provide feedback about the datagram. Feedback can be provided by driving a data line of the serial bus during the second data frame to provide a negative acknowledgment when a transmission error is detected in the datagram; and by preventing the driving of the data line of the serial bus during the second data frame when no transmission error is detected in the datagram, thereby providing acknowledgment of the datagram.

[0009] In several aspects of this disclosure, an apparatus includes interface circuitry adapted to couple the apparatus to a serial bus and a processor. The processor can be configured to: receive a write command from the serial bus, wherein the write command is received in a datagram and configured according to the SPMI protocol; write data bytes received in a first data frame of the datagram to a register address identified by the datagram; and provide feedback on the datagram using a second data frame of the datagram by: driving data lines of the serial bus during the second data frame to provide a negative acknowledgment when a transmission error is detected in the datagram; and preventing the driving of data lines of the serial bus during the second data frame when no transmission error is detected in the datagram, thereby providing acknowledgment of the datagram.

[0010] In several aspects of this disclosure, a processor-readable storage medium stores code for: receiving a write command from a serial bus, wherein the write command is received in a datagram and configured according to the SPMI protocol; writing data bytes received in a first data frame of the datagram to a register address identified by the datagram; and using a second data frame of the datagram to provide feedback about the datagram. Feedback can be provided by: driving the data lines of the serial bus during the second data frame to provide a negative acknowledgment when a transmission error is detected in the datagram; and by preventing the driving of the data lines of the serial bus during the second data frame when no transmission error is detected in the datagram, thereby providing acknowledgment of the datagram.

[0011] In several aspects of this disclosure, an apparatus includes: components for receiving a write command from a serial bus, wherein the write command is received in a datagram and configured according to the SPMI protocol; components for writing data bytes received in a first data frame of the datagram to a register address identified by the datagram; and components for providing feedback about the datagram using a second data frame of the datagram. Feedback can be provided by driving data lines of the serial bus during the second data frame to provide a negative acknowledgment when a transmission error is detected in the datagram; and by preventing the driving of data lines of the serial bus during the second data frame when no transmission error is detected in the datagram, thereby providing acknowledgment of the datagram.

[0012] In several aspects of this disclosure, a method performed at a transmission device coupled to a serial bus includes: transmitting a write command configured according to the SPMI protocol in a datagram via the serial bus; transmitting data bytes in a first data frame of the datagram; providing a bus docking sequence on the serial bus in a second data frame of the datagram; and receiving feedback regarding the datagram during the second data frame and after providing the bus docking sequence. The feedback may include feedback bits in the second data frame, the feedback bits indicating a negative acknowledgment when received as a first value, and indicating acknowledgment of the datagram when received as a second value.

[0013] In several aspects of this disclosure, an apparatus includes interface circuitry adapted to couple the apparatus to a serial bus and a processor. The processor can be configured to: transmit a write command configured according to the SPMI protocol via the serial bus in a datagram; transmit data bytes in a first data frame of the datagram; provide a bus docking sequence on the serial bus in a second data frame of the datagram; and receive feedback regarding the datagram during the second data frame and after providing the bus docking sequence. The feedback may include a feedback bit in the second data frame that indicates a negative acknowledgment when received as a first value and indicates an acknowledgment of the datagram when received as a second value.

[0014] In several aspects of this disclosure, a processor-readable storage medium stores code for: transmitting a write command configured according to the SPMI protocol in a datagram via a serial bus; transmitting data bytes in a first data frame of the datagram; providing a bus docking sequence on the serial bus in a second data frame of the datagram; and receiving feedback about the datagram during the second data frame and after providing the bus docking sequence. The feedback may include a feedback bit in the second data frame that indicates a negative acknowledgment when received as a first value, and may indicate acknowledgment of the datagram when received as a second value.

[0015] In several aspects of the invention, an apparatus includes: components for transmitting a write command configured according to the SPMI protocol in a datagram via a serial bus; components for transmitting data bytes in a first data frame of the datagram; components for providing a bus docking sequence on the serial bus in a second data frame of the datagram; and components for receiving feedback regarding the datagram during the second data frame and after providing the bus docking sequence. The feedback may include a feedback bit in the second data frame that indicates a negative acknowledgment when received as a first value, and may indicate acknowledgment of the datagram when received as a second value. Attached Figure Description

[0016] Figure 1 The illustration shows a device that uses a data link between IC devices that operates selectively according to one of several available standards.

[0017] Figure 2 The diagram illustrates the system architecture of a device that uses data links between IC devices.

[0018] Figure 3 The diagram illustrates an apparatus for coupling multiple devices using an SPMI bus, according to certain aspects disclosed herein.

[0019] Figure 4 The diagram illustrates the datagram structure and timing for the SPMI extended register write command.

[0020] Figure 5 The diagram illustrates the datagram structure and timing for writing long commands to the SPMI extended register.

[0021] Figure 6 The illustration shows the use of SPMI extended register write commands configured according to certain aspects disclosed herein to support the confirmation of the first transaction.

[0022] Figure 7 The illustration shows how to support a confirmed second transaction by writing a long command using the SPMI extended register, which has been configured according to certain aspects disclosed herein.

[0023] Figure 8 The illustration shows how to support confirmed third transactions using SPMI extended register write commands that have been configured according to certain aspects disclosed herein.

[0024] Figure 9 The illustration shows how to support a confirmed fourth transaction by writing long commands using the SPMI extended register, which has been configured according to certain aspects disclosed herein.

[0025] Figure 10The diagram illustrates the datagram structure of the SPMI register-0 write command according to certain aspects disclosed herein.

[0026] Figure 11 An example of a device employing processing circuitry that can be adapted to certain aspects disclosed herein is illustrated.

[0027] Figure 12 This is a first flowchart illustrating some aspects disclosed in this article.

[0028] Figure 13 The illustration shows a first example of a hardware implementation of a device adapted to certain aspects disclosed herein.

[0029] Figure 14 This is a second flowchart illustrating some aspects disclosed in this article.

[0030] Figure 15 The illustration shows a second example of a hardware implementation of a device adapted to certain aspects of the disclosure herein. Detailed Implementation

[0031] The detailed description below, taken in conjunction with the accompanying drawings, is intended to describe a variety of configurations and not to represent only the configurations in which the concepts described herein can be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some cases, well-known structures and components are illustrated in block diagram form to avoid obscuring such concepts.

[0032] Several aspects of the invention will now be presented with reference to various devices and methods. These devices and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively, “elements”). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends on the specific application and design constraints imposed on the entire system.

[0033] Overview

[0034] Devices, including SoCs and other IC devices, typically employ a shared communication interface, which may include a serial bus or other data communication links to connect different devices. In one example, a multi-point serial bus can be implemented to interconnect the processor with modems and other peripherals. Serial buses and other data communication links can operate according to several defined standards or protocols. For example, a serial bus can operate according to I2C, I3C, SPMI, and / or RFFE protocols, or other protocols that can be configured for half-duplex operation. The increased operational functionality and complexity of devices coupled to serial buses, along with the use of a greater number of peripherals, RF front-end devices, and / or sensor devices to support complex applications, necessitates updates to existing bus protocols, including new features not defined in earlier versions of the bus protocol.

[0035] Some aspects of this disclosure relate to providing feedback capability for a device when it is configured to provide feedback according to a version of the SPMI specification and coupled to a serial bus that operates according to a different version of the SPMI specification that does not support feedback.

[0036] In one example, the device includes interface circuitry adapted to couple the device to a serial bus and a processor. The processor can be configured to: receive a write command from the serial bus, wherein the write command is received in a datagram and configured according to the SPMI protocol; write data bytes received in a first data frame of the datagram to a register address identified by the datagram; and provide feedback on the datagram using a second data frame of the datagram by: driving the data lines of the serial bus during the second data frame to provide a negative acknowledgment when a transmission error is detected in the datagram; and stopping the driving of the data lines of the serial bus during the second data frame to provide acknowledgment of the datagram when no transmission error is detected in the datagram.

[0037] Some aspects disclosed herein are described with reference to serial buses operating according to the SPMI protocol. However, some concepts can be equally applied to the RFFE protocol, I3C protocol, I2C protocol, and / or other bus protocols. Some aspects apply to serial buses operating in half-duplex or full-duplex mode. Some aspects apply to multi-point interfaces and / or interfaces operating in point-to-point mode.

[0038] Example of a device using a serial data link

[0039] According to certain aspects, serial data links can be used to interconnect electronic devices that are sub-components of devices, such as cellular phones, smartphones, Session Initiation Protocol (SIP) phones, laptops, notebooks, netbooks, smartbooks, personal digital assistants (PDAs), satellite radios, Global Positioning System (GPS) devices, smart home devices, smart lighting, multimedia devices, video devices, digital audio players (e.g., MP3 players), cameras, game consoles, entertainment devices, vehicle components, wearable computing devices (e.g., smartwatches, health or fitness trackers, goggles, etc.), facilities, sensors, security devices, vending machines, smart meters, or any other similar functional devices.

[0040] Figure 1 The illustration shows an example of a device 100 that may employ a data communication bus. Device 100 may include processing circuitry 102 having multiple circuits or devices 104, 106, and / or 108, which may be implemented in one or more ASIC devices or in a system-on-a-chip (SoC) device. In one example, device 100 may be configured to function as a communication device, and processing circuitry 102 may include processing devices provided in ASIC 104, one or more peripheral devices 106, and a transceiver 108 enabling the device to communicate with a radio access network, a core access network, the Internet, and / or other networks via antenna 124.

[0041] ASIC 104 may have one or more processors 112, one or more modems 110, on-board memory 114, bus interface circuitry 116, and / or other logic circuitry or functions. Processing circuitry 102 may be controlled by an operating system providing an application programming interface (API) layer, which enables one or more processors 112 to execute software modules residing in on-board memory 114 or other processor-readable storage devices 122 provided on processing circuitry 102. Software modules may include instructions and data stored in on-board memory 114 or processor-readable storage devices 122. ASIC 104 may access storage devices external to its on-board memory 114, processor-readable storage devices 122, and / or processing circuitry 102. On-board memory 114 and processor-readable storage devices 122 may include read-only memory (ROM) or random access memory (RAM), electrically erasable programmable ROM (EEPROM), flash cards, or any memory device that can be used in processing systems and computing platforms. Processing circuitry 102 may include, implement, or have access to a local database or other parameter storage device, which may store operating parameters and other information used for configuring and operating device 100 and / or processing circuitry 102. The local database may be implemented using registers, database modules, flash memory, magnetic media, EEPROM, floppy disks, or hard disks. Processing circuitry 102 may also be operatively coupled to external devices such as antenna 124, display 126, operator controllers (such as switches or buttons 128, 130 and / or an integrated or external keypad 132), and other components. The user interface module may be configured to operate with display 126, external keypad 132, etc., via a dedicated communication link or via one or more serial data interconnects.

[0042] Processing circuitry 102 may include or be coupled to one or more buses 118a, 118b, 120 that enable certain devices 104, 106, and / or 108 to exchange messages and other information. In one example, ASIC 104 may have bus interface circuitry 116, which includes a combination of circuitry, counters, timers, control logic, and other configurable circuitry or modules. In one example, bus interface circuitry 116 may be configured to operate according to a communication specification or protocol. Processing circuitry 102 may include or control power management functions that configure and manage the operation of device 100.

[0043] Figure 2 The diagram includes multiple devices 202 and 2220-222 coupled to serial bus 220. N Certain aspects of device 200. Devices 202 and 2220-222 can be implemented in one or more semiconductor IC devices such as application processors, SoCs, or ASICs.N In various implementations, devices 202 and 2220-222... N It may include, support, a modem, a signal processing device, a display driver, a camera, a user interface, a sensor, a sensor controller, a media player, a transceiver, an RFFE device, and / or other such components or devices, or operate as, a modem, a signal processing device, a display driver, a camera, a user interface, a sensor, a sensor controller, a media player, a transceiver, an RFFE device, and / or other such components or devices. In some examples, from devices 2220-222... N One or more slave devices can be used to control, manage, or monitor sensor devices. Devices 202 and 2220-222 N Communication between them via serial bus 220 is controlled by bus master 202. Some types of buses can support multiple bus masters 202.

[0044] In one example, master device 202 may include interface controller 204, which manages access to the serial bus and configures slave devices 2220-222. N The dynamic address and / or clock signal 228 are transmitted on clock line 218 of serial bus 220. Master device 202 may include configuration register 206 or other storage device 224 and other control logic 212 configured to control protocols and / or higher-level functions. Control logic 212 may include processing circuitry such as a state machine, sequencer, signal processor, or general-purpose processor. Master device 202 includes transceiver 210 and line drivers / receivers 214a and 214b. Transceiver 210 may include a receiver, transmitter, and common circuitry, wherein the common circuitry may include timing, logic, and storage circuitry and / or devices. In one example, the transmitter encodes and transmits data based on timing in clock signal 228 provided by clock generation circuitry 208. Other timing clocks 226 may be used by control logic 212 and other functions, circuitry, or modules.

[0045] At least one device 2220-222 NIt can be configured to operate as a slave device on serial bus 220 and may include circuitry and modules supporting and communicating with a display, an image sensor, and / or one or more sensors controlling and measuring environmental conditions. In one example, slave device 2220 configured to operate as a slave device may provide control functions, modules, or circuitry 232, including circuitry and modules supporting and communicating with a display, an image sensor, and / or one or more sensors controlling and measuring environmental conditions. Slave device 2220 may include configuration register 234 or other storage device 236, control logic 242, transceiver 240, and line drivers / receivers 244a and 244b. Control logic 242 may include processing circuitry such as a state machine, sequencer, signal processor, or general-purpose processor. Transceiver 210 may include a receiver, a transmitter, and common circuitry, wherein the common circuitry may include timing, logic, and storage circuitry and / or devices. In one example, the transmitter encodes and transmits data based on timing in clock signal 248 provided by clock generation and / or recovery circuitry 246. The clock signal 248 can be derived from the signal received from clock line 218. Other timing clock signals 238 can be used by control logic 242 and other functions, circuits, or modules.

[0046] The serial bus 220 can be operated according to I2C, I3C, RFFE, SPMI, C-PHY, D-PHY protocols, or other suitable protocols. At least one device 202, 2220-222 N It can be configured to selectively operate as a master or slave device on serial bus 220. Two or more devices 202, 2220-222 N It can be configured to operate as a master device on serial bus 220.

[0047] In one example, the serial bus 220 can be operated according to the I3C protocol. Devices communicating using the I3C protocol can coexist on the same serial bus 220 as devices communicating using the I2C protocol. The I3C protocol can support different communication modes, including a Single Data Rate (SDR) mode compatible with the I2C protocol. High Data Rate (HDR) mode can provide data transfer rates between 6 megabits per second (Mbps) and 16 Mbps, and some HDR modes can provide even higher data transfer rates. The I2C protocol can conform to the de facto I2C standard, thus providing data rates ranging from 100 kilobits per second (kbps) to 3.2 Mbps. In addition to aspects of bus control and data format, the I2C and I3C protocols can also define the electrical and timing aspects of the signals transmitted on the 2-wire serial bus 220. In some aspects, the I2C and I3C protocols can define the DC characteristics affecting certain signal levels associated with the serial bus 220, and / or the AC characteristics affecting certain timing aspects of the signals transmitted on the serial bus 220. In some examples, the 2-wire serial bus 220 transmits data on data line 216 and clock signals on clock line 218. In some cases, data can be encoded during signaling states or transitions between signaling states on data line 216 and clock line 218.

[0048] In some traditional systems, multiple serial buses are provided to support the demands for high data throughput, low latency, high bus availability, and / or for other reasons. In some cases, multiple serial buses are used to mitigate problems caused by the limited addressing capabilities of serial bus protocols. For example, Figure 3 and 4 The diagram illustrates a system in which multiple serial buses can be used to interconnect master and slave devices.

[0049] Figure 3 The illustration includes an example of a system 300 that operates a serial bus according to SPMI or other bus protocols. In some implementations, the SPMI protocol is used for power management control, and the bus can be configured to support the transmission of commands for resetting, hibernating, powering off, waking up, etc., of circuits or functional components. In some implementations, the SPMI bus protocol can be used to implement a general communication link. In the illustrated example, the two-wire serial bus includes a first wire (SCLK 302) carrying a clock signal and a second wire (SDATA 304) carrying a data signal transmitted according to timing provided by the clock signal. The serial bus can connect multiple slave devices that can be configured to act as master devices, including application processors, modems, sensors, controllers, etc. For example, a power management integrated circuit (PMIC 310) can be coupled to a serial bus operating according to the SPMI protocol.

[0050] Devices can be coupled to the serial bus as either slave or master devices. In an example of a serial bus operating according to the SPMI protocol, one to four master devices 306, 308 and up to 16 slave devices 312, 314, 316, 318 can be coupled to the serial bus. The SPMI protocol supports bus contention arbitration, request arbitration, and group addressing. Slave devices 312, 314, 316, 318 coupled to the serial bus devices may need to acknowledge certain commands. When multiple devices are requesting access to the serial bus to send a sequence of commands, a bus arbitration sequence is performed before the transaction to assign control of the serial bus to a master or a slave device. When the bus is idle, access to the serial bus can be requested by driving SDATA304 to a high signaling state while SCLK 302 is in a low signaling state. Some slave devices are capable of requesting access to the serial bus.

[0051] During certain operations, SCLK 302 and / or SDATA 304 may be undriven and may be held in a signaling state by a hold circuit 320 or by a pull-down circuit 322. In one example, the hold circuit 320 may be configured as a positive feedback circuit that drives SDATA 304 through a high-impedance output and receives feedback from SDATA 304 through a low-impedance input. The hold circuit 320 may be configured to maintain the last asserted voltage on SDATA 304. The hold circuit 320 may be easily overcome by a line driver in master devices 306, 308 or slave devices 312, 314, 316, 318. In some examples, a pull-down circuit 322 (or a pull-up circuit) may be used to hold SCLK 302 and / or SDATA 304 in the desired signaling state. The illustrated pull-down circuit 322 may be activated to couple a pull-down resistor to a line of the serial bus.

[0052] Protocols supporting communication over multi-station serial buses can define datagram structures for transmitting command, control, and data payloads within application-defined delay tolerances. Different protocols define certain common features in their datagram structures, including addressing for selecting devices to receive or transmit data, clock generation and management, interrupt handling, and device prioritization. In this disclosure, an example using the SPMI protocol is used to illustrate certain aspects of this disclosure. However, the concepts disclosed herein are applicable to other serial bus protocols and standards.

[0053] Figure 4The diagram illustrates a datagram 400 for an Extended Register Write (ERW) command that can be transmitted via a serial bus, and its corresponding timing diagram 420. Datagram 400 can be transmitted by the device that wins bus arbitration during arbitration sequence 402. Datagram 400 begins with a two-bit sequence start condition (SSC 404, 422), followed by a four-bit slave address 406, 424, or other device identifier. Eight-bit command codes 408, 426 are set with a parity bit. Command codes 408, 426 include a byte count (BC[3:0]) indicating the number of bytes to be written. Command codes 408, 426 are followed by eight-bit register addresses 410, 428, and data 412 between frames 1 and 16. The data may include at least a first data frame 430. After the final data frame 432 is transmitted, bus docking signals 414, 434 are provided. Bus docking signals 414 and 434 are provided when the device initially drives SDATA low and then releases SDATA to an undriven state 436 (where SDATA is held low by a retainer circuit (pull-down circuit / resistor)).

[0054] Figure 5 The diagram illustrates a datagram 500 that can transmit an Extended Register Write Long (ERWL) command via a serial bus and its corresponding timing diagram 520. Datagram 500 can be transmitted by the device that wins bus arbitration during arbitration sequence 502. Datagram 500 begins with the transmission of a two-bit sequence start condition (SSC 504, 522), followed by a four-bit slave address 506, 524, or other device identifier. Eight-bit command codes 508, 526 are set with a parity bit. Command codes 508, 526 include a byte count (BC[2:0]) indicating the number of bytes to be written. Command codes 508, 526 are followed by a 16-bit register address 510. The 16-bit register address 510 may include a high-order address byte 528 and a low-order address byte 530. Data 512 between one and eight frames can be transmitted in datagram 500. Data 512 may include at least a first data frame 532. After transmitting the final data frame 534, bus docking signals 514 and 536 are transmitted.

[0055] Some versions of the SPMI specification (which may be identified herein as SPMI 1.x) do not include all features defined for later versions of the SPMI specification (which may be identified herein as SPMI 2.x). In one example, the acknowledgment feature defined for SPMI 2.x is not available for use on devices operating according to SPMI 1.x. In some SPMI 2.x implementations, ACK / NACK bits may be transmitted at the end of the datagram after a first bus docking signaling 414, 434, 514, 536, and a second bus docking signaling may follow the ACK / NACK bits. When a sequence of commands supplying ACK / NACK bits is addressed to a single device using a unique slave identifier (USID) or master identifier (MID), the addressed device may be configured to respond with an ACK / NACK bit value 'b1' if the command sequence is received correctly. If the command sequence is received correctly, the addressed device may be configured to respond with an ACK / NACK bit value 'b0'. When a command sequence supplying the ACK / NACK bits is addressed to a group of slave devices using the Group Slave Identifier (GSID), if the command sequence is received correctly, the addressed device can be configured to maintain its line driver for SDATA in a high-impedance state, and the slave device can be configured to respond with the ACK / NACK value 'b1 only if an error is detected in the command sequence. On a serial bus operating according to the SPMI protocol, SDATA is typically pulled low when all devices are in a high-impedance state.

[0056] Certain aspects of this disclosure relate to techniques for extending the ability of a device to provide and receive feedback on data transmitted via a serial bus by utilizing existing bus protocols. In some examples, feedback includes an acknowledgment (ACK) that a sequence of commands comprising one or more data bytes has been received without apparent error. In some examples, feedback includes a negative acknowledgment (NACK) indicating an error associated with the reception of the command sequence. In some implementations, when the existing bus protocol does not provide a feedback mechanism, feedback can be enabled and supported by providing pseudo-data bytes and manipulating the byte count in the command sequence to ensure a sufficient number of clock pulses are provided to accommodate the transmission of the pseudo-data bytes.

[0057] Some aspects of this disclosure relate to feedback mechanisms that can be used when an SPMI 2.x compliant device is configured for use on a serial line operating according to SPMI 1.x. In one aspect, the feedback mechanism does not affect devices such as the SPMI 1.x-enabled PMIC310 (see...). Figure 3The functionality of conventional devices such as SPMI 2.x and configured according to certain aspects of this disclosure. In one example, a device conforming to SPMI 2.x and configured according to certain aspects of this disclosure can support a feedback mechanism implemented using pseudo-data bytes and ERW and ERWL command sequences when operating on a serial bus according to SPMI 1.x bus (where ACK / NACK cycles are not available).

[0058] Figure 6 The illustration depicts a first transaction supported by certain aspects disclosed herein. In this example, the ERW command is used to support the acknowledgment. A first timing diagram 600 illustrates portions of a conventional datagram of an ERW command frame 608 transmitted using SCLK 602 and SDATA 604, and a second timing diagram 620 illustrates portions of a datagram of an ERW command frame 628 configured according to certain aspects disclosed herein.

[0059] According to certain aspects of this disclosure, a pseudo-data byte provided after the last valid data byte is used to provide feedback in the datagram. Conventional devices can be configured to ignore the pseudo-data byte. In both timing diagrams 600, 620, bus arbitration 606, 626 precedes the transmission of ERW command frames 608, 628. The device that wins bus arbitration 606, 626 transmits ERW command frames 608, 628 along with ERW command codes, which contain a target slave identifier. In the first timing diagram 600, the ERW command code includes a byte count 612 (BC[3:0]) set to "0" indicating that one byte is to be written. ERW command frame 608 is followed by an 8-bit register address (shown as compressed period 614), followed by a single data byte 610. Bus docking signaling 616 indicates the end of the datagram.

[0060] In the second timing diagram 620, the ERW command code includes a byte count 634 (BC[3:0]) set to "1" indicating to the transmitter that two data bytes are being transmitted, thereby providing the transmitter with sufficient clock pulses to transmit the two bytes. Conventional receiving devices can be configured to ignore the last data byte. Devices configured to provide feedback can also be configured, according to certain aspects of this disclosure, to provide feedback within a data frame corresponding to pseudo-data byte 632.

[0061] Continuing with the second timing diagram 620, an 8-bit register address (shown as compressed segment 636) is transmitted after the ERW command frame 628, followed by the data byte 630 for writing to the identified register address. The transmitter drives SDATA 624 to a low signaling state until the seventh clock pulse for pseudo-data byte 632 is transmitted on SCLK 622, at which point the transmitter provides bus docking signaling 638, thereby releasing SDATA 624 and putting its SDATA line driver into a high-impedance state. The receiving device can then provide feedback in the form of ACK / NACK bit 640 during the eighth clock pulse for pseudo-data byte 632 transmitted on SCLK 622. When the ERW command frame 628 is addressed to MID or USID, the receiving device can drive SDATA 624 to a high signaling state to acknowledge successful datagram reception, and can hold SDATA 624 in a low signaling state if an error has been detected in the previous data. When the ERW command frame 628 is addressed to the GSID, the receiving device can maintain its SDATA line driver in a high-impedance state when the datagram is successfully received, and can drive SDATA 624 to a high signaling state to indicate that an error has been detected in the datagram. SDATA 624 can return to a low signaling state during the ninth pulse transmitted on SCLK 622 for the pseudo-data byte 632, where the ninth pulse corresponds to the pseudo-parity bit. Bus docking signaling 638 is then provided by releasing SDATA 624 and bringing the SDATA line driver to a high-impedance state.

[0062] In the second timing diagram 620, the device that wins bus arbitration 606, 626 drives SDATA 624 for the duration of the transaction (from -1Slave-1 644), which begins with the transmission of ERW command frame 628 and continues until the first bus docking signal 638. The winning device can relinquish control of SDATA 624 by providing the first bus docking signal 638. One or more devices to which ERW command frame 628 is addressed can actively drive SDATA 624 during period 646, which begins during or after the first bus docking signal 638 and ends with the second bus docking signal 642 upon completion of the transmission of pseudo-data byte 632.

[0063] Figure 7 The illustration depicts a second transaction supported by acknowledgment according to certain aspects disclosed herein. In this example, the ERWL command is used to support acknowledgment. A first timing diagram 700 illustrates portions of a conventional datagram of an ERWL command frame 708 transmitted using SCLK 702 and SDATA 704, and a second timing diagram 720 illustrates portions of a datagram of an ERWL command frame 728 configured according to certain aspects disclosed herein.

[0064] According to certain aspects of this disclosure, a pseudo-data byte transmitted after the last valid data byte provides feedback in the datagram. Conventional devices can be configured to ignore the pseudo-data byte. In both timing diagrams 700 and 720, bus arbitration 706 and 726 precede the transmission of ERWL command frames 708 and 728. The device that wins bus arbitration 706 and 726 transmits ERWL command frames 708 and 728 along with ERWL command codes, which contain a target slave identifier. In the first timing diagram 700, the ERWL command code includes a byte count 712 (BC[2:0]) set to "0" indicating that one byte is to be written. ERWL command frame 708 is followed by an 8-bit register address (shown as compressed period 714), followed by a single data byte 710. Bus docking signaling 716 indicates the end of the datagram.

[0065] In the second timing diagram 720, the ERWL command code includes a byte count 734 (BC[2:0]) set to "1" indicating to the transmitter that two data bytes are being transmitted, thereby providing the transmitter with sufficient clock pulses to transmit the two bytes. Conventional receiving devices can be configured to ignore the last data byte. Devices configured to provide feedback can also be configured, according to certain aspects of this disclosure, to provide feedback within a data frame corresponding to pseudo-data byte 732.

[0066] Continuing with the second timing diagram 720, after the ERWL command frame 728, an 8-bit register address (shown as compressed period 736) is transmitted, followed by the data byte 730 for writing to the identified register address. The transmitter drives SDATA 724 to a low signaling state until the seventh clock pulse for pseudo-data byte 732 is transmitted on SCLK 722, at which point the transmitter provides bus docking signaling 738 by releasing SDATA 724 and putting its SDATA line driver into a high-impedance state. The receiving device can then provide feedback in the form of ACK / NACK bits 740 during the eighth clock pulse for pseudo-data byte 732 transmitted on SCLK 722.

[0067] When the ERWL command frame 728 is addressed to MID or USID, the receiving device can drive SDATA 724 to a high signaling state to acknowledge successful datagram reception, and can hold SDATA 724 in a low signaling state if an error has been detected in previous data. When the ERWL command frame 728 is addressed to GSID, the receiving device can hold its SDATA line driver in a high-impedance state when the datagram is successfully received, and can drive SDATA 724 to a high signaling state to indicate that an error has been detected in the datagram. SDATA 724 can return to a low signaling state during the ninth pulse of the pseudo-data byte 732 transmitted on SCLK 722, where the ninth pulse corresponds to the pseudo-parity bit. Bus docking signaling 738 is then provided by releasing SDATA 724 and putting the SDATA line driver into a high-impedance state.

[0068] In the second timing diagram 720, the device that wins bus arbitration 706, 726 drives SDATA 724 for the duration of the transaction (Slave-1 744), which begins with the transmission of ERWL command frame 728 and continues until the first bus docking signal 738. The winning device can relinquish control of SDATA 724 by providing the first bus docking signal 738. Furthermore, when a negative acknowledgment needs to be transmitted, one or more devices targeted by ERWL command frame 728 can actively drive SDATA 724 during period 746, which begins during or after the first bus docking signal 738 and ends with the second bus docking signal 742 after the transmission of pseudo-data byte 732 is complete.

[0069] Figure 8 The illustrations depict a third transaction supported by certain aspects disclosed herein. In this example, the ERW command is used to support the acknowledgment. A first timing diagram 800 illustrates a portion of a datagram of ERW command frame 808 transmitted using SCLK 802 and SDATA 804, and a second timing diagram 820 illustrates a portion of a datagram of ERW command frame 828 configured according to certain aspects disclosed herein.

[0070] According to certain aspects of this disclosure, a pseudo-data byte provided after the last valid data byte is used to provide feedback in the datagram. Conventional devices can be configured to ignore the pseudo-data byte. In both timing diagrams 800, 820, bus arbitration 806, 826 precedes the transmission of ERW command frames 808, 828. The device that wins bus arbitration 806, 826 transmits ERW command frames 808, 828 along with ERW command codes, which include a target slave identifier. In the first timing diagram 800, the ERW command code includes a byte count 812 (BC[3:0]) set to “0”, indicating that one byte is to be written. ERW command frame 808 is followed by an 8-bit register address (shown as compressed period 814), followed by a single data byte 810. Bus docking signaling 816 indicates the end of the datagram.

[0071] In the second timing diagram 820, the ERW command code includes a byte count 834 (BC[3:0]) set to "1" to indicate to the transmitter that two data bytes are being transmitted, thereby providing the transmitter with sufficient clock pulses to transmit the two bytes. Conventional receiving devices can be configured to ignore the last data byte. Devices configured to provide feedback can also be configured, according to certain aspects of this disclosure, to provide feedback within a data frame corresponding to pseudo-data byte 832.

[0072] Continuing with the second timing diagram 820, an 8-bit register address (shown as compressed segment 836) is transmitted after the ERW command frame 828, followed by the data byte 830 for writing to the identified register address. In this example, an early bus docking signaling 838 is provided. During the first clock pulse for the pseudo-data byte 832 transmitted on SCLK 822, after the last bit of the parity bit of data byte 830 has been transmitted, the transmitter drives SDATA 824 to a low signaling state. The transmitter provides bus docking signaling 838 by releasing SDATA 824 and putting its SDATA line driver into a high-impedance state. SDATA 824 can be held in a non-driven state 846, held low by a hold circuit or a pull-down circuit. The receiving device can provide feedback in the form of an ACK / NACK bit 840 during the eighth clock pulse for the pseudo-data byte 832 transmitted on SCLK 82.

[0073] The receiving device can activate its driver at any time after bus parking signal 838. In one example, a receiving device expecting a slow line turn can activate its driver during the sixth clock pulse for pseudo data byte 832 transmitted on SCLK 822. In another example, a receiving device expecting a fast line turn can activate its driver during the seventh clock pulse for pseudo data byte 832 transmitted on SCLK 822.

[0074] When the ERW command frame 828 is addressed to MID or USID, the receiving device can drive SDATA 824 to a high signaling state to acknowledge successful datagram reception, and can hold SDATA 824 in a low signaling state if an error has been detected in previous data. When the ERW command frame 828 is addressed to GSID, the receiving device can maintain its SDATA line driver in a high-impedance state and drive SDATA 824 to a high signaling state to indicate that an error has been detected in the datagram when the datagram is successfully received. SDATA 824 can return to a low signaling state during the ninth pulse for pseudo-data byte 832 transmitted on SCLK 822, where the ninth pulse corresponds to the pseudo-parity bit. Bus docking signaling 838 is then provided by releasing SDATA 824 and putting the SDATA line driver into a high-impedance state.

[0075] In the second timing diagram 820, the device that wins bus arbitration 806, 826 drives SDATA 824 for the duration of the transaction (Slave-1 844), which begins with the transmission of ERW command frame 828 and continues until the first bus docking signal 838. The winning device can relinquish control of SDATA 824 by providing the first bus docking signal 838. One or more devices targeted by ERW command frame 828 can actively drive SDATA 824 during period 848, which begins during or after the first bus docking signal 838 and can end with the second bus docking signal 842 after the transmission of pseudo-data byte 832 is completed.

[0076] Figure 9 The illustration depicts a fourth transaction supported by acknowledgment according to certain aspects disclosed herein. In this example, the ERWL command is used to support acknowledgment. A first timing diagram 900 illustrates a portion of a conventional datagram of an ERWL command frame 908 transmitted using SCLK 902 and SDATA 904, and a second timing diagram 920 illustrates a portion of a datagram of an ERWL command frame 928 configured according to certain aspects disclosed herein.

[0077] According to certain aspects of this disclosure, a pseudo-data byte transmitted after the last valid data byte provides feedback in the datagram. Conventional devices can be configured to ignore the pseudo-data byte. In both timing diagrams 900, 920, bus arbitration 906, 926 precedes the transmission of ERWL command frames 908, 928. The device that wins bus arbitration 906, 926 transmits ERWL command frames 908, 928 (including the target slave identifier) ​​and ERWL command code. In the first timing diagram 900, the ERWL command code includes a byte count 912 (BC[2:0]) set to "0" indicating that one byte is to be written. ERWL command frame 908 is followed by an 8-bit register address (shown as compressed period 914), followed by a single data byte 910. Bus docking signaling 916 indicates the end of the datagram.

[0078] In the second timing diagram 920, the ERWL command code includes a byte count 934 (BC[2:0]) set to "1" to indicate to the transmitter that two data bytes are being transmitted, thereby providing the transmitter with sufficient clock pulses to transmit the two bytes. Conventional receiving devices can be configured to ignore the last data byte. Devices configured to provide feedback can also be configured, according to certain aspects of this disclosure, to provide feedback within a data frame corresponding to pseudo-data byte 932.

[0079] Continuing with the second timing diagram 920, after the ERWL command frame 928, an 8-bit register address (shown as compressed period 936) is transmitted, followed by the data byte 930 for writing to the identified register address. During the first clock pulse for the pseudo-data byte 932 transmitted on SCLK 922, after the last bit of the parity bit of the already transmitted data byte 930, the transmitter drives SDATA 924 to a low signaling state. The transmitter provides bus docking signaling 938 by releasing SDATA 924 and putting its SDATA line driver into a high-impedance state. SDATA 924 can be held in a non-driven state 946, held low by a hold circuit or a pull-down circuit. The receiving device can provide feedback in the form of ACK / NACK bits 940 during the eighth clock pulse for the pseudo-data byte 932 transmitted on SCLK 922.

[0080] The receiving device can activate its driver at any time after bus parking signal 938. In one example, a receiving device expecting a slow line turn can activate its driver during the sixth clock pulse for pseudo data byte 932 transmitted on SCLK 922. In another example, a receiving device expecting a fast line turn can activate its driver during the seventh clock pulse for pseudo data byte 932 transmitted on SCLK 922.

[0081] When the ERWL command frame 928 is addressed to MID or USID, the receiving device can drive SDATA 924 to a high signaling state to acknowledge successful datagram reception, and can hold SDATA 924 in a low signaling state if an error is detected in previous data. When the ERWL command frame 928 is addressed to GSID, the receiving device can maintain its SDATA line driver in a high-impedance state when the datagram is successfully received, and can drive SDATA 924 to a high signaling state to indicate that an error has been detected in the datagram. SDATA 924 can return to a low signaling state during the ninth pulse for pseudo-data byte 932 transmitted on SCLK 922, where the ninth pulse corresponds to the pseudo-parity bit. Bus docking signaling 938 is then provided by releasing SDATA 924 and putting the SDATA line driver into a high-impedance state.

[0082] In the second timing diagram 920, the device that wins bus arbitration 906, 926 drives SDATA 924 for the duration of the transaction (Slave-1 944), which begins with the transmission of ERWL command frame 928 and continues until the first bus docking signal 938. The winning device can relinquish control of SDATA 924 by providing the first bus docking signal 938. One or more devices to which ERWL command frame 928 is addressed can actively drive SDATA 924 during or after the first bus docking signal 938, and when a negative acknowledgment is to be transmitted, it ends with the second bus docking signal 942 after the transmission of pseudo-data byte 932.

[0083] Certain aspects of this disclosure provide a component by which a device conforming to or compatible with the recently published SPMI protocol and / or specification can provide feedback in pseudo-data bytes. A write command to register -0 of the receiving device can be used to configure the receiving device to manipulate the pseudo-data bytes for feedback purposes. Figure 10 The diagram illustrates a datagram structure 1000 for a register-0 write command according to the SPMI protocol. The register-0 write command is transmitted in the shortest datagram defined by the SPMI protocol. Datagram structure 1000 begins with a two-bit sequence start condition (SSC 1002), followed by a four-bit slave address 1004 or other device identifier. Next, an 8-bit command code 1006 is transmitted. The 8-bit command code 1006 is uniquely defined and has its most significant bit (MSB 1012) set to 1. Following command code 1006 are a parity bit 1008 and a bus docking signaling 1010.

[0084] Based on certain aspects disclosed herein, the register-0 write command in the SPMI and RFFE protocols can be adapted to configure slave devices to support the pseudo-data byte feedback technique disclosed herein. In one example, register-0 1020 can be adapted to enable up to four slave devices to use pseudo-data byte feedback. In the illustrated example, each of the four least significant bits 1022 in register-0 1020 defines a state for pseudo-data byte feedback support. Pseudo-data byte feedback is enabled when one of the four least significant bits 1022 is set to a first logical state, and disabled when set to a second logical state.

[0085] The response of the transmitting device to pseudo-data byte feedback can be determined at a higher layer. For example, the application can determine the appropriate response. Pseudo-data byte feedback can be used when a group identifier is transmitted in a write command. When no device is actively driving the line, SDATA can be pulled and held in a low signaling state. Any device that wants to signal a negative acknowledgment can drive SDATA to a high signaling state.

[0086] Traditional devices are unaffected by pseudo-data byte feedback signaling because they can decode an appropriate number of clocks to monitor transactions.

[0087] Examples of processing circuits and methods

[0088] Figure 11 This is a simplified diagram illustrating an example of a hardware implementation of device 1100. In some examples, device 1100 may perform one or more functions disclosed herein. According to various aspects of the invention, processing circuitry 1102 may be used to implement any element or any part of the elements or any combination of elements disclosed herein. Processing circuitry 1102 may include one or more processors 1104 controlled by some combination of hardware modules and software modules. Examples of processors 1104 include microprocessors, microcontrollers, digital signal processors (DSPs), SoCs, ASICs, field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequencers, gating logic, discrete hardware circuitry, and other suitable hardware configured to perform the various functionalities described throughout this disclosure. One or more processors 1104 may include dedicated processors that perform specific functions and can be configured, extended, or controlled by one of the software modules 1116. One or more processors 1104 may be configured by a combination of software modules 1116 loaded during initialization and may be further configured by loading or unloading one or more software modules 1116 during operation.

[0089] In the illustrated example, processing circuitry 1102 can be implemented using a bus architecture generally represented by bus 1110. Depending on the specific application and overall design constraints of processing circuitry 1102, bus 1110 can include any number of interconnect buses and bridges. Bus 1110 links together various circuits including one or more processors 1104 and storage devices 1106. Storage devices 1106 can include memory devices and mass storage devices, and are referred to herein as computer-readable media and / or processor-readable media. Bus 1110 can also link various other circuits, such as timing sources, timers, peripheral devices, voltage regulators, and power management circuitry. Bus interface 1108 provides an interface between bus 1110 and one or more transceivers 1112a, 1112b. Transceivers 1112a, 1112b can be provided for each networking technology supported by the processing circuitry. In some cases, multiple networking technologies can share some or all of the circuitry or processing modules found in transceivers 1112a, 1112b. Each transceiver 1112a, 1112b provides components for communicating with a variety of other devices via a transmission medium. In one example, transceiver 1112a may be used to couple device 1100 to a multi-wire bus. In another example, transceiver 1112b may be used to connect device 1100 to a radio access network. Depending on the nature of device 1100, a user interface 1118 (e.g., keypad, display, speaker, microphone, joystick) may also be provided, and the user interface 1118 may be communicatively coupled to bus 1110, either directly or via bus interface 1108.

[0090] Processor 1104 may be responsible for managing bus 1110 and for general processing, including executing software stored in a computer-readable medium (which may include storage device 1106). In this regard, processing circuitry 1102, including processor 1104, may be used to implement any of the methods, functions, and techniques disclosed herein. Storage device 1106 may be used to store data manipulated by processor 1104 during software execution, and said software may be configured to implement any of the methods disclosed herein.

[0091] One or more processors 1104 in processing circuitry 1102 can execute software. Software should be interpreted broadly as instructions, instruction sets, code, code segments, program code, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, functions, algorithms, etc., regardless of whether it is referred to as software, firmware, middleware, microcode, hardware description languages, or otherwise. The software may reside in a computer-readable form in storage device 1106 or on an external computer-readable medium. External computer-readable media and / or storage device 1106 may include non-transitory computer-readable media. As examples, non-transitory computer-readable media include: magnetic storage devices (e.g., hard disks, floppy disks, magnetic stripes), optical discs (e.g., compact discs (CDs) or digital multifunction discs (DVDs)), smart cards, flash memory devices (e.g., "flash memory drives," card, stick, or key drives), RAM, ROM, programmable read-only memory (PROM), erasable PROMs including EEPROMs (EPROMs), registers, removable disks, and any suitable medium for storing software and / or instructions accessible and readable by a computer. As examples, computer-readable media and / or storage device 1106 may also include carrier waves, transmission lines, and any other suitable medium for transmitting software and / or instructions accessible and readable by a computer. Computer-readable media and / or storage device 1106 may reside in processing circuitry 1102, in processor 1104, external to processing circuitry 1102, or distributed across multiple entities including processing circuitry 1102. Computer-readable media and / or storage device 1106 may be embodied in a computer program product. As examples, a computer program product may include computer-readable media in packaging material. Those skilled in the art will recognize how the functionality described throughout this disclosure can be optimally achieved, depending on the specific application and the overall design constraints imposed on the system as a whole.

[0092] Storage device 1106 can maintain and / or organize software within loadable code segments, modules, applications, programs, etc. (which may herein be referred to as software module 1116). Each software module in software module 1116 may include instructions and data that, when installed or loaded onto processing circuitry 1102 and executed by one or more processors 1104, contribute to a runtime image 1114 that controls the operation of one or more processors 1104. When executed, certain instructions may cause processing circuitry 1102 to perform functions according to certain methods, algorithms, and procedures described herein.

[0093] Some software modules in software module 1116 may be loaded during the initialization of processing circuitry 1102, and these software modules 1116 may configure processing circuitry 1102 to allow the execution of various functions disclosed herein. For example, some software modules 1116 may configure the internal devices and / or logic circuitry 1122 of processor 1104, and may manage access to external devices such as transceivers 1112a, 1112b, bus interface 1108, user interface 1118, timers, math coprocessors, etc. Software modules 1116 may include control programs and / or operating systems that interact with interrupt handlers and device drivers and control access to various resources provided by processing circuitry 1102. Resources may include storage space, processing time, access to transceivers 1112a, 1112b, user interface 1118, etc.

[0094] One or more processors 1104 of the processing circuitry 1102 can be multifunctional, whereby some software modules in software module 1116 are loaded and configured to perform different functions or different instances of the same function. One or more processors 1104 may be additionally adapted to manage background tasks, for example, initiated in response to input from user interface 1118, transceivers 1112a, 1112b, and device drivers. To support the execution of multiple functions, one or more processors 1104 can be configured to provide a multitasking environment, whereby each of the multiple functions is implemented as a set of tasks to be served by one or more processors 1104 as needed or desired. In one example, the multitasking environment can be implemented using a time-sharing program 1120 that transfers control of the processors 1104 between different tasks, whereby each task returns control of one or more processors 1104 to the time-sharing program 1120 upon completion of any incomplete operation and / or in response to inputs such as interrupts. When a task has control over one or more processors 1104, the processing circuitry is efficiently dedicated to the purpose achieved by the functions associated with the control task. The time-sharing program 1120 may include an operating system, a main loop that passes control on a polling basis, a function that allocates control over one or more processors 1104 according to the priority of the function, and / or an interrupt-driven main loop that responds to external events by providing control over one or more processors 1104 to the manipulation function.

[0095] Figure 12Flowchart 1200 shows a method that can be performed by a device coupled to a serial bus. In one example, the serial bus can be operated according to the SPMI specification. In block 1202, the device can receive a write command from the serial bus. The write command is received in a datagram and configured according to the SPMI protocol. In block 1204, the device can write data bytes received in the first data frame of the datagram to the register address identified by the datagram.

[0096] In block 1206, the device may use a second data frame of the datagram to provide feedback about the datagram. In some implementations, the device may determine at block 1208 whether the data byte was received without error. In one example, an error may occur during the transmission of the data byte transmitted in the first data frame. In another example, the error may be attributed to one or more data bytes transmitted in association with a write command. If an error in the data byte is detected or determined at block 1208, the device may drive the serial bus data lines at block 1210 to provide a negative acknowledgment during the second data frame when a transmission error is detected in the datagram. If no error in the data byte is detected or determined at block 1208, the device may, at block 1212, prevent the driving of the serial bus data lines during the second data frame when no transmission error is detected in the datagram, thereby providing an acknowledgment of the datagram. In one example, the second data frame includes a 9-bit transmission interval and does not include the data for writing, and the second data frame may be referred to as a pseudo-data byte.

[0097] In some examples, when a negative acknowledgment is provided during the second data frame, the device can enable the line driver coupled to the data line of the serial bus to actively drive the data line to a high signaling state. In one example, the device can activate the line driver when a seventh pulse is detected on the clock line of the serial bus during the second data frame, and can drive the serial bus data line to a high signaling state simultaneously with the detection of an eighth pulse on the clock line of the serial bus during the second data frame. In another example, the device can activate the line driver after receiving a data byte in the first data frame of the datagram, and can drive the serial bus data line to a high signaling state simultaneously with the detection of an eighth pulse on the clock line of the serial bus during the second data frame.

[0098] In some examples, the device may maintain the line driver of the data line coupled to the serial bus in a high-impedance state during the second data frame while an acknowledgment of the datagram is being provided. During the eighth and ninth bit transmission interval of the second data frame, the data line may be undriven. In one example, when the data line is undriven, it is pulled to a low signaling state.

[0099] In one example, when the bits of the configuration byte received from the serial bus are set to the first value, the device can use the second data frame of the datagram to provide feedback, while when the bits of the configuration byte received from the serial bus are set to the second value, the device can ignore the second data frame of the datagram.

[0100] In some examples, the device may provide a bus docking sequence on the serial bus after the data lines driving the serial bus during the second data frame. The device may provide the bus docking sequence by causing the line drivers of the data lines coupled to the serial bus to enter a high-impedance state at the end of the second data frame.

[0101] Figure 13 This is a simplified example of a hardware implementation of a device 1300 employing processing circuitry 1302. The processing circuitry typically has a controller or processor 1316 that may include one or more microprocessors, microcontrollers, digital signal processors, sequencers, and / or state machines. Processing circuitry 1302 may be implemented using a bus architecture typically represented by bus 1320. Depending on the specific application and overall design constraints of processing circuitry 1302, bus 1320 may include any number of interconnect buses and bridges. Bus 1320 links together various circuits including one or more processors and / or hardware modules represented by controller or processor 1316, modules or circuits 1304, 1306, and 1308, and processor-readable storage medium 1318. One or more physical layer circuits and / or modules 1314 may be provided to support communication over communication links implemented using multi-wire bus 1312, via antennas or antenna arrays 1322, etc. (e.g., to a radio access network). Bus 1320 can also link a variety of other circuits known in the art (such as timing sources, peripheral devices, voltage regulators and power management circuits), and therefore these other circuits will not be described further.

[0102] Processor 1316 is responsible for general processing, which includes the execution of software, code, and / or instructions stored on processor-readable storage medium 1318. Processor-readable storage medium 1318 may include non-transitory storage media. When executed by processor 1316, the software causes processing circuitry 1302 to perform the various functions described above for any particular device. Processor-readable storage medium 1318 may be used to store data manipulated by processor 1316 while executing the software. Processing circuitry 1302 also includes at least one of modules 1304, 1306, and 1308. Modules 1304, 1306, and 1308 may be software modules running in processor 1316, software modules residing / stored in processor-readable storage medium 1318, one or more hardware modules coupled to processor 1316, or some combination thereof. Modules 1304, 1306, and 1308 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

[0103] In one configuration, device 1300 includes modules and / or circuitry 1308 adapted to detect or determine errors in received data, which includes parity bit conditions that can indicate the occurrence of a transmission error. Device 1300 may include modules and / or circuitry 1306 adapted to process pseudo-data bytes and modules and / or circuitry 1304 adapted to configure, perform, and / or participate in transactions via a multi-wire bus 1312 configured to operate according to SPMI specifications or protocols. Pseudo-data bytes may have been transmitted for feedback purposes.

[0104] In some implementations, device 1300 includes physical layer circuitry and / or module 1314, which implements interface circuitry suitable for coupling device 1300 to multi-line bus 1312. Device 1300 may have a processor 1316 configured to: receive a write command from the serial bus, wherein the write command is received in a datagram and configured according to the SPMI protocol; write data bytes received in a first data frame of the datagram to a register address identified by the datagram; and use a second data frame of the datagram to provide feedback about the datagram. Processor 1316 may be configured to: drive the data lines of the serial bus during the second data frame to provide a negative acknowledgment when a transmission error is detected in the datagram; and prevent driving the data lines of the serial bus during the second data frame when no transmission error is detected in the datagram, thereby providing acknowledgment of the datagram. In one example, the second data frame includes a 9-bit transmission interval and does not include data for writing.

[0105] Device 1300 may include a line driver for a data line coupled to a serial bus. In some implementations, processor 1316 is configured to enable the line driver to actively drive the data line to a high signaling state when a negative acknowledgment is provided during a second data frame. Processor 1316 may be configured to activate the line driver when a seventh pulse is detected on the clock line of the serial bus during a second data frame, and to drive the serial bus data line to a high signaling state simultaneously with the detection of an eighth pulse on the clock line of the serial bus during a second data frame. In some implementations, processor 1316 is configured to maintain the line driver in a high-impedance state during a second data frame while an acknowledgment of a datagram is being provided. During the eighth and ninth bit transmission interval of the second data frame, the data line may be undriven. When the data line is undriven, it may be pulled to a low signaling state.

[0106] In some implementations, processor 1316 is configured to: use the second data frame of the datagram to provide feedback when the bits of the configuration byte received from the serial bus are set to the first value; and ignore the second data frame of the datagram when the bits of the configuration byte received from the serial bus are set to the second value.

[0107] In some implementations, processor 1316 is configured to provide a bus docking sequence on the serial bus after driving the data lines of the serial bus during the second data frame. In some implementations, processor 1316 is configured to cause the line drivers of the data lines coupled to the serial bus to enter a high-impedance state at the end of the second data frame.

[0108] Processor-readable storage medium 1318 may include temporary or non-temporary storage means configured to store code, instructions, and / or parameters for implementing one or more methods or procedures disclosed herein. Processor-readable storage medium 1318 may include code for receiving write commands from a serial bus. Write commands may be received in a datagram and can be configured according to the SPMI protocol. Processor-readable storage medium 1318 may include code for writing data bytes received in a first data frame of the datagram to a register address identified by the datagram. Processor-readable storage medium 1318 may include code for providing feedback on the datagram using a second data frame of the datagram in such a way that: when a transmission error is detected in the datagram, the data lines of the serial bus are driven during the second data frame to provide a negative acknowledgment; and when no transmission error is detected in the datagram, the driving of the data lines of the serial bus is stopped during the second data frame, thereby providing acknowledgment of the datagram.

[0109] In one example, the second data frame includes a 9-bit transmission interval and does not include the data to be written.

[0110] In some examples, when a negative acknowledgment is provided during the second data frame, the line driver coupled to the data line of the serial bus can be enabled to actively drive the data line to a high signaling state. The line driver can be activated when a seventh pulse is detected on the serial bus clock line during the second data frame, and the serial bus data line can be driven to a high signaling state simultaneously with the detection of an eighth pulse on the serial bus clock line during the second data frame.

[0111] In some examples, the processor-readable storage medium 1318 may include code for maintaining the line drivers of the data lines coupled to the serial bus in a high-impedance state during a second data frame while acknowledgment of a datagram is being provided. During the eighth and ninth bit transmission intervals of the second data frame, the data lines may be undriven. In one example, when the data lines are undriven, they may be pulled to a low signaling state.

[0112] In one example, processor-readable storage medium 1318 may include code configured to: provide feedback using a second data frame of the datagram when a bit of a configuration byte received from the serial bus is set to a first value, and ignore the second data frame of the datagram when a bit of a configuration byte received from the serial bus is set to a second value.

[0113] In some examples, the processor-readable storage medium 1318 may contain code for providing a bus docking sequence on the serial bus after the data lines driving the serial bus during a second data frame. The processor-readable storage medium 1318 may contain code for providing the bus docking sequence by causing the line drivers of the data lines coupled to the serial bus to enter a high-impedance state at the end of the second data frame.

[0114] Figure 14 Flowchart 1400 shows a method that can be performed by a device coupled to a serial bus. In one example, the serial bus can be operated according to the SPMI specification. At block 1402, the device can transmit a write command configured according to the SPMI protocol over the serial bus in a datagram. At block 1404, the device can transmit data bytes in the first data frame of the datagram. At block 1406, the device can provide a bus docking sequence on the serial bus in the second data frame of the datagram. At block 1408, the device can receive feedback about the datagram during the second data frame and after providing the bus docking sequence. The feedback may include a feedback bit in the second data frame that indicates a negative acknowledgment when received as a first value, and may indicate an acknowledgment of the datagram when received as a second value.

[0115] In one example, the device can provide a bus docking sequence by putting the line driver of the data line coupled to the serial bus into a high-impedance state during the first bit transmission interval of the second data frame. In another example, the device can provide a bus docking sequence by putting the line driver of the data line coupled to the serial bus into a high-impedance state during the seventh bit transmission interval of the second data frame. When the data line is undriven during the eighth bit transmission interval of the second data frame, the data line can be pulled to a signaling state that allows the feedback bit of the second data frame to be received as a second value.

[0116] In some examples, write commands are addressed to multiple devices coupled to the serial bus. One or more devices can be configured to provide feedback in a second data frame before the write command is transmitted. At least one other device can be configured to ignore the second data frame. For example, a device can configure bit settings in a register located at address zero in one or more devices.

[0117] Figure 15 This is a simplified example illustration of a hardware implementation of a device 1500 employing processing circuitry 1502. The processing circuitry typically has a controller or processor 1516, which may include one or more microprocessors, microcontrollers, digital signal processors, sequencers, and / or state machines. Processing circuitry 1502 may be implemented using a bus architecture generally represented by bus 1520. Depending on the specific application and overall design constraints of processing circuitry 1502, bus 1520 may include any number of interconnect buses and bridges. Bus 1520 links together various circuits including controller or processor 1516, modules or circuits 1504, 1506, and 1508, and processor-readable storage medium 1518. One or more physical layer circuits and / or modules 1514 may be provided to support communication over a communication link implemented using multi-wire bus 1512, via an antenna or antenna array 1522, etc. (e.g., to a radio access network). Bus 1520 can also link a variety of other circuits known in the art, such as timing sources, peripheral devices, voltage regulators and power management circuits, and therefore will not be described further.

[0118] Processor 1516 is responsible for general processing, which includes the execution of software, code, and / or instructions stored on processor-readable storage medium 1518. Processor-readable storage medium 1518 may include non-transitory storage media. When executed by processor 1516, the software causes processing circuitry 1502 to perform the various functions described above for any particular device. Processor-readable storage medium 1518 may be used to store data manipulated by processor 1516 during software execution. Processing circuitry 1502 also includes at least one of modules 1504, 1506, and 1508. Modules 1504, 1506, and 1508 may be software modules running in processor 1516, software modules residing / stored in processor-readable storage medium 1518, one or more hardware modules coupled to processor 1516, or some combination thereof. Modules 1504, 1506, and 1508 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

[0119] In one configuration, device 1500 includes a module and / or circuitry 1508 adapted to configure the device coupled to a serial bus to report feedback regarding errors in received data, including parity bit conditions that can indicate the occurrence of a transmission error. Device 1500 may include a module and / or circuitry 1506 adapted to transmit pseudo-data bytes, and a module and / or circuitry 1504 adapted to configure, perform, and / or participate in transactions via a multi-wire bus 1512 configured to operate according to SPMI specifications or protocols. Pseudo-data bytes may be transmitted for feedback purposes.

[0120] In some implementations, device 1500 includes physical layer circuitry and / or module 1514, which implements interface circuitry suitable for coupling device 1500 to multi-wire bus 1512. Device 1500 may have processor 1516, configured to: transmit write commands in datagrams via a serial bus configured according to the SPMI protocol; transmit data bytes in a first data frame of a datagram; provide a bus docking sequence on the serial bus in a second data frame of a datagram; and receive feedback regarding the datagram during the second data frame and after providing the bus docking sequence. The feedback may include a feedback bit in the second data frame that indicates a negative acknowledgment when received as a first value, and may indicate acknowledgment of the datagram when received as a second value.

[0121] In some implementations, processor 1516 is configured to put the line driver of the data line coupled to the serial bus into a high-impedance state during the seventh bit transmission interval in the second data frame when a bus docking sequence is provided. When the data line is undriven during the eighth bit transmission interval in the second data frame, the data line can be pulled into a signaling state that allows the feedback bit of the second data frame to be received as a second value.

[0122] In some cases, write commands are addressed to multiple devices coupled to the serial bus. In some implementations, processor 1516 configures one or more devices to provide feedback in a second data frame before transmitting the write command. At least one other device can be configured to ignore the second data frame.

[0123] Processor-readable storage medium 1518 may include temporary or non-temporary storage means configured to store code, instructions, and / or parameters for implementing one or more methods or procedures disclosed herein. Processor-readable storage medium 1518 may include code configured to: transmit a write command in a datagram via a serial bus configured according to the SPMI protocol; transmit data bytes in a first data frame of the datagram; provide a bus docking sequence on the serial bus in a second data frame of the datagram; and receive feedback regarding the datagram during the second data frame and after providing the bus docking sequence. The feedback may include a feedback bit in the second data frame that indicates a negative acknowledgment when received as a first value and indicates an acknowledgment of the datagram when received as a second value.

[0124] The processor-readable storage medium 1518 may contain code for causing the line driver of the data line coupled to the serial bus to enter a high-impedance state during the seventh bit transmission interval of the second data frame when a bus docking sequence is provided. When the data line is not driven during the eighth bit transmission interval of the second data frame, the data line can be pulled to a signaling state that causes the feedback bit of the second data frame to be received as a second value.

[0125] In some cases, write commands are addressed to multiple devices coupled to the serial bus. The processor-readable storage medium 1518 may contain code for configuring one or more devices before transmitting the write command and providing feedback in a second data frame. At least one other device may be configured to ignore the second data frame.

[0126] Some implementation examples are described in the following numbered clauses:

[0127] 1. A method for data communication at a device coupled to a serial bus, the method comprising: receiving a write command from the serial bus, the write command being received in a datagram and configured according to a System Power Management Interface (SPMI) protocol; writing data bytes received in a first data frame of the datagram to a register address identified by the datagram; and using a second data frame of the datagram to provide feedback on the datagram, the step comprising: driving a data line of the serial bus during the second data frame to provide a negative acknowledgment when a transmission error is detected in the datagram; and stopping driving the data line of the serial bus during the second data frame when no transmission error is detected in the datagram, thereby providing an acknowledgment of the datagram.

[0128] 2. The method according to Clause 1 further includes: when a negative acknowledgment is provided during the second data frame, enabling the line driver of the data line coupled to the serial bus to actively drive the data line to a high signaling state.

[0129] 3. The method according to Clause 2 further includes: activating the line driver when a seventh pulse is detected on the clock line of the serial bus during the second data frame; and driving the data line of the serial bus to a high signaling state while an eighth pulse is detected on the clock line of the serial bus during the second data frame.

[0130] 4. The method according to Clause 2 further includes: activating the line driver after receiving a data byte in the first data frame of the datagram; and driving the data line of the serial bus to a high signaling state while an eighth pulse is detected on the clock line of the serial bus during the second data frame, wherein the data line is in a high impedance state after receiving the data byte in the first data frame of the datagram.

[0131] 5. The method according to Clause 1 further includes: maintaining the line driver of the data line coupled to the serial bus in a high impedance state during the second data frame while an acknowledgment of the data packet is being provided.

[0132] 6. The method according to Clause 5, wherein the data line is not driven during the transmission interval of the eighth and ninth bits of the second data frame, and wherein when the data line is not driven, the data line is pulled to a low signaling state.

[0133] 7. The method pursuant to any one of Clauses 1-6 further includes: providing feedback using a second data frame of the datagram when a bit of the configuration byte received from the serial bus is set to a first value; and ignoring the second data frame of the datagram when a bit of the configuration byte received from the serial bus is set to a second value.

[0134] 8. The method according to any one of the clauses 1-7 further includes: providing a bus docking sequence on the serial bus after driving the data lines of the serial bus during the second data frame.

[0135] 9. The method according to Clause 8, wherein providing the bus docking sequence includes: after the completion of the second data frame, causing the line driver of the data line coupled to the serial bus to enter a high-impedance state.

[0136] 10. An apparatus for data communication, the apparatus comprising: interface circuitry adapted to couple the apparatus to a serial bus; and a processor configured to: receive a write command from the serial bus, the write command being received in a datagram and configured according to a System Power Management Interface (SPMI) protocol; write data bytes received in a first data frame of the datagram to a register address identified by the datagram; and provide feedback on the datagram using a second data frame of the datagram by: driving a data line of the serial bus during the second data frame to provide a negative acknowledgment when a transmission error is detected in the datagram; and preventing the driving of the data line of the serial bus during the second data frame when no transmission error is detected in the datagram, thereby providing acknowledgment of the datagram.

[0137] 11. The device according to Clause 10 further includes: a line driver coupled to a data line of a serial bus, wherein the processor is further configured to: enable the line driver to actively drive the data line to a high signaling state when a negative acknowledgment is provided during a second data frame.

[0138] 12. The device according to Clause 11, wherein the processor is further configured to: activate the line driver when a seventh pulse is detected on the clock line of the serial bus during the second data frame; and drive the data line of the serial bus to a high signaling state while an eighth pulse is detected on the clock line of the serial bus during the second data frame.

[0139] 13. The device according to Clause 11, wherein the processor is further configured to: activate the line driver after receiving a data byte in the first data frame of the datagram; and drive the data lines of the serial bus to a high signaling state while an eighth pulse is detected on the clock line of the serial bus during the second data frame, wherein the data lines are in a high impedance state after receiving the data byte in the first data frame of the datagram.

[0140] 14. The device according to Clause 10 further includes: a line driver coupled to a data line of a serial bus, wherein the processor is further configured to: maintain the line driver in a high-impedance state during a second data frame while an acknowledgment of a datagram is being provided.

[0141] 15. The device according to Clause 14, wherein the data line is not driven during the transmission interval of the eighth and ninth bits of the second data frame, and wherein when the data line is not driven, the data line is pulled to a low signaling state.

[0142] 16. The device pursuant to any one of clauses 10-15, wherein the processor is further configured to: provide feedback using a second data frame of the datagram when a bit of a configuration byte received from the serial bus is set to a first value; and ignore the second data frame of the datagram when a bit of a configuration byte received from the serial bus is set to a second value.

[0143] 17. The device according to clauses 10-16 further includes: a line driver coupled to a data line of a serial bus, wherein the processor is further configured to:

[0144] After the data lines driving the serial bus are driven during the second data frame, a bus docking sequence is provided on the serial bus.

[0145] 18. The device pursuant to Clause 17, wherein providing the bus docking sequence includes: after the completion of the second data frame, causing the line driver of the data line coupled to the serial bus to enter a high-impedance state.

[0146] 19. A method of data communication at a device coupled to a serial bus, the method comprising: transmitting a write command in a datagram via the serial bus, the write command being configured according to a System Power Management Interface (SPMI) protocol; transmitting data bytes in a first data frame of the datagram; providing a bus docking sequence on the serial bus in a second data frame of the datagram; and receiving feedback on the datagram during the second data frame, the feedback including a feedback bit of the second data frame indicating a negative acknowledgment when received as a first value, and indicating an acknowledgment of the datagram when received as a second value.

[0147] 20. The method according to Clause 19, wherein providing the bus docking sequence comprises: during the first transmission interval of the second data frame, causing the line driver of the data line coupled to the serial bus to enter a high-impedance state, wherein during the eighth transmission interval of the second data frame, the data line is pulled to a signaling state that causes the feedback bit of the second data frame to be received as a second value.

[0148] 21. The method according to Clause 19, wherein providing the bus docking sequence comprises: during the seventh bit transmission interval in the second data frame, causing the line driver of the data line coupled to the serial bus to enter a high impedance state, wherein during the eighth bit transmission interval in the second data frame, the data line is pulled to a signaling state that causes the feedback bit of the second data frame to be received as a second value.

[0149] 22. The method according to any one of the clauses 19-21, wherein a write command is addressed to a plurality of devices coupled to a serial bus.

[0150] 23. The method pursuant to any of the provisions 19-22 further comprises: configuring one or more means to provide feedback in a second data frame prior to transmitting the write command, wherein at least one other means is configured to ignore the second data frame.

[0151] 24. The method according to Clause 23, wherein configuring one or more devices to provide feedback includes: configuring bit settings of registers located at address zero in one or more devices.

[0152] 25. An apparatus for data communication, the apparatus comprising: interface circuitry adapted to couple the apparatus to a serial bus; and a processor configured to: transmit a write command in a datagram via the serial bus, the write command being configured according to a System Power Management Interface (SPMI) protocol; transmit data bytes in a first data frame of the datagram; provide a bus docking sequence on the serial bus in a second data frame of the datagram; and receive feedback regarding the datagram during the second data frame, the feedback including a feedback bit of the second data frame indicating a negative acknowledgment when received as a first value, and indicating an acknowledgment of the datagram when received as a second value.

[0153] 26. The device according to Clause 25, wherein the processor is further configured to: during the first transmission interval of the second data frame, cause the line driver of the data line coupled to the serial bus to enter a high-impedance state, wherein during the eighth transmission interval of the second data frame, the data line is pulled to a signaling state that causes the feedback bit of the second data frame to be received as a second value.

[0154] 27. The device according to Clause 25, wherein the processor is further configured to: during the seventh bit transmission interval in the second data frame, cause the line driver of the data line coupled to the serial bus to enter a high impedance state, wherein during the eighth bit transmission interval in the second data frame, the data line is pulled to a signaling state that causes the feedback bit of the second data frame to be received as a second value.

[0155] 28. A device pursuant to Clauses 25-27, wherein write commands are addressed to a plurality of devices coupled to a serial bus.

[0156] 29. The device pursuant to Clauses 25-28, wherein the processor is further configured to: configure one or more means to provide feedback in a second data frame prior to the transmission of a write command, wherein at least one other means is configured to ignore the second data frame.

[0157] 30. The device pursuant to Clause 29, wherein the processor is further configured to: configure bit settings of registers located at address zero in one or more devices.

[0158] It should be understood that the specific order or hierarchy of steps in the disclosed process is an illustration of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process can be rearranged. Furthermore, some steps can be combined or omitted. The appended method clauses present the elements of each step in a sample order and are not intended to limit us to the specific order or hierarchy presented.

[0159] The preceding description is provided to enable those skilled in the art to practice the various aspects described herein. Various modifications to these aspects will readily be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects shown herein, but rather to conform to the full scope consistent with the language of the claims, wherein, unless expressly stated otherwise, reference to an element in the singular is not intended to mean “one and only one,” but rather “one or more.” Unless expressly stated otherwise, the term “some” means one or more. All structural and functional equivalents of the elements of the various aspects described throughout this disclosure (which are known to or subsequently become known to those skilled in the art) are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended to be offered to the public, regardless of whether such disclosure is expressly stated in the claims. Unless an element of a claim is clearly stated using the phrase “for…component,” it should not be construed as a component plus a function.

Claims

1. A method of data communication at a device coupled to a serial bus, the method comprising: receiving a write command from the serial bus, the write command being received in a datagram and configured according to a system power management interface (SPMI) protocol; writing data bytes received in a first data frame of the datagram to a register address identified by the datagram; and providing feedback regarding the datagram using a second data frame of the datagram, the step comprising: when a transfer error is detected in the datagram, driving a data line of the serial bus during the second data frame to provide a negative acknowledgement, wherein driving the data line to provide the negative acknowledgement comprises: enabling a line driver coupled to the data line of the serial bus to actively drive the data line to a high signaling state when the negative acknowledgement is provided during the second data frame, activating the line driver when a seventh pulse is detected on a clock line of the serial bus during the second data frame, and driving the data line of the serial bus to the high signaling state while a eighth pulse is detected on the clock line of the serial bus during the second data frame; and when no transfer error is detected in the datagram, refraining from driving the data line of the serial bus during the second data frame, thereby providing an acknowledgement of the datagram.

2. The method of claim 1, further comprising: when an acknowledgement of the datagram is being provided, maintaining the line driver coupled to the data line of the serial bus in a high impedance state during the second data frame.

3. The method of claim 2, wherein the data line is un-driven during eighth and ninth bit transfer intervals of the second data frame, and wherein the data line is pulled to a low signaling state when the data line is un-driven.

4. The method of claim 1, further comprising: when a bit of a configuration byte received from the serial bus is set to a first value, providing feedback using the second data frame of the datagram; and when the bit of the configuration byte received from the serial bus is set to a second value, ignoring the second data frame of the datagram.

5. The method of claim 1, further comprising: after driving the data line of the serial bus during the second data frame, providing a bus parking sequence on the serial bus.

6. The method of claim 5, wherein providing the bus parking sequence comprises: after completing the second data frame, entering the line driver coupled to the data line of the serial bus into a high impedance state.

7. An apparatus for data communication, the apparatus comprising: an interface circuit adapted to couple the apparatus to a serial bus; a line driver coupled to a data line of the serial bus; and a processor configured to: receive a write command from the serial bus, the write command being received in a datagram and configured according to a system power management interface (SPMI) protocol; ​ ​ ​ writing data bytes received in a first data frame of the datagram to a register address identified by the datagram; and providing feedback regarding the datagram using a second data frame of the datagram by driving the data line of the serial bus during the second data frame to provide a negative acknowledgement when a transfer error is detected in the datagram, and refraining from driving the data line of the serial bus during the second data frame to thereby provide an acknowledgement of the datagram when no transfer error is detected in the datagram, wherein to drive the data line to provide the negative acknowledgement, the processor is configured to: enable the line driver to actively drive the data line to a high signaling state when the negative acknowledgement is being provided during the second data frame, activate the line driver when a seventh pulse is detected on a clock line of the serial bus during the second data frame, and drive the data line of the serial bus to the high signaling state while a eighth pulse is detected on the clock line of the serial bus during the second data frame.

8. The device of claim 7, wherein the processor is further configured to: maintain the line driver in a high impedance state during the second data frame when the acknowledgement of the datagram is being provided.

9. The device of claim 8, wherein the data line is un-driven during an eighth bit and a ninth bit transfer interval of the second data frame, and wherein the data line is pulled to a low signaling state when the data line is un-driven.

10. The apparatus of claim 7, wherein, the processor is further configured to: provide feedback using the second data frame of the datagram when a bit of a configuration byte received from the serial bus is set to a first value; and ignore the second data frame of the datagram when the bit of the configuration byte received from the serial bus is set to a second value.

11. The device of claim 7, wherein the processor is further configured to: provide a bus park sequence on the serial bus after driving the data line of the serial bus during the second data frame.

12. The device of claim 11, wherein providing the bus park sequence comprises: entering the line driver coupled to the data line of the serial bus into a high impedance state after completing the second data frame.

13. A method of data communication at a device coupled to a serial bus, the method comprising: receiving a write command from the serial bus, the write command being received in a datagram and configured according to a system power management interface (SPMI) protocol; writing data bytes received in a first data frame of the datagram to a register address identified by the datagram; and providing feedback regarding the datagram using a second data frame of the datagram, the step comprising: when a transmission error is detected in the datagram, driving a data line of the serial bus during the second data frame to provide a negative acknowledgement, wherein driving the data line to provide the negative acknowledgement comprises: when the negative acknowledgement is provided during the second data frame, enabling a line driver coupled to the data line of the serial bus to actively drive the data line to a high signaling state, activating the line driver after the data byte is received in the first data frame of the datagram, and driving the data line of the serial bus to the high signaling state while an eighth pulse is detected on a clock line of the serial bus during the second data frame, wherein the data line is in a high impedance state after the data byte is received in the first data frame of the datagram; and when no transmission error is detected in the datagram, refraining from driving the data line of the serial bus during the second data frame, thereby providing an acknowledgement of the datagram.

14. The method of claim 13, further comprising: when an acknowledgement of the datagram is being provided, maintaining the line driver coupled to the data line of the serial bus in a high impedance state during the second data frame.

15. The method of claim 14, wherein the data line is un-driven during eighth and ninth bit transmit intervals of the second data frame, and wherein the data line is pulled to a low signaling state when the data line is un-driven.

16. The method of claim 13, further comprising: when a bit of a configuration byte received from the serial bus is set to a first value, using the second data frame of the datagram to provide feedback; and when the bit of the configuration byte received from the serial bus is set to a second value, ignoring the second data frame of the datagram.

17. The method of claim 13, further comprising: after driving the data line of the serial bus during the second data frame, providing a bus park sequence on the serial bus.

18. The method of claim 17, wherein providing the bus park sequence comprises: after completion of the second data frame, entering the line driver coupled to the data line of the serial bus into a high impedance state.

19. An apparatus for data communication, the apparatus comprising: an interface circuit adapted to couple the apparatus to a serial bus; a line driver coupled to a data line of the serial bus; and a processor configured to: receive a write command from the serial bus, the write command received in a datagram and configured according to a system power management interface (SPMI) protocol; write a data byte received in a first data frame of the datagram to a register address identified by the datagram; and ​ to provide feedback on the data packet by driving the data line of the serial bus during the second data frame to provide a negative acknowledgement when a transmission error is detected in the data packet; and refraining from driving the data line of the serial bus during the second data frame when no transmission error is detected in the data packet, thereby providing an acknowledgement of the data packet, wherein to drive the data line to provide the negative acknowledgement, the processor is configured to: enable the line driver to actively drive the data line to a high signaling state when the negative acknowledgement is provided during the second data frame, activate the line driver after the data byte is received in the first data frame of the data packet; and when a eighth pulse is detected on a clock line of the serial bus during the second data frame, drive the data line of the serial bus to the high signaling state, wherein the data line is in a high impedance state after the data byte is received in the first data frame of the data packet.

20. The device of claim 19, wherein the processor is further configured to: maintain the line driver in a high impedance state during the second data frame when the acknowledgement of the data packet is being provided.

21. The device of claim 20, wherein the data line is un-driven during eighth and ninth bit transmit intervals of the second data frame, and wherein the data line is pulled to a low signaling state when the data line is un-driven.

22. The device of claim 19, wherein the processor is further configured to: provide feedback using the second data frame of the data packet when a bit of a configuration byte received from the serial bus is set to a first value; and ignore the second data frame of the data packet when the bit of the configuration byte received from the serial bus is set to a second value.

23. The device of claim 19, wherein the processor is further configured to: provide a bus parking sequence on the serial bus after driving the data line of the serial bus during the second data frame.

24. The device of claim 23, wherein providing the bus parking sequence comprises: entering the line driver coupled to the data line of the serial bus into a high impedance state after completion of the second data frame. ​

Images